Semiconductor device, manufacturing method thereof, and electronic equipment

Abstract

A semiconductor device, a manufacturing method thereof, and an electronic device, the semiconductor device comprising a plurality of stacked transistors, a first through-hole and a second through-hole extending through the different layers, a semiconductor layer and a back-gate electrode disposed within the first through-hole and extending in a direction perpendicular to the substrate and extending through the different layers, the semiconductor layer comprising a plurality of spaced-apart first semiconductor sublayers and a second semiconductor sublayer located between adjacent first semiconductor sublayers; a word line disposed within the second through-hole and extending through the different layers in a direction perpendicular to the substrate, the distance between the word line and the first semiconductor sublayer in a direction parallel to the substrate being less than the distance between the word line and the second semiconductor sublayer in a direction parallel to the substrate. The solution provided by the embodiments of the present disclosure provides a gate electrode for the parasitic transistor, which is used to turn off the parasitic transistor, eliminating the need for etching to remove the parasitic semiconductor layer, thereby avoiding affecting the transistor and improving device performance.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] An embodiment of the present disclosure provides a semiconductor device, including:

[0006] Multiple transistors are distributed in different layers and stacked along a direction perpendicular to the substrate;

[0007] a first through hole and a second through hole penetrating the different layers, the second through hole being connected to the first through hole, and a semiconductor layer and a back gate electrode being arranged in the first through hole and extending in a direction perpendicular to the substrate and penetrating the different layers, wherein the semiconductor layer surrounds the sidewall of the back gate electrode, the semiconductor layer includes a plurality of first semiconductor sublayers spaced apart and a second semiconductor sublayer located between adjacent first semiconductor sublayers, and the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure;

[0008] a word line disposed in the second through hole and extending through the different layers in a direction perpendicular to the substrate, wherein a distance between the word line and the first semiconductor sublayer in a direction parallel to the substrate is smaller than a distance between the word line and the second semiconductor sublayer in a direction parallel to the substrate;

[0009] The transistor includes the first semiconductor sublayer and a first gate electrode, and the first gate electrode of the transistor is part of the word line.

[0010] In some embodiments, the semiconductor device further comprises:

[0011] Insulating layers and conductive layers are alternately distributed from top to bottom in a direction perpendicular to the substrate; the first through hole and the second through hole penetrate the insulating layer and the conductive layer;

[0012] The semiconductor layer, the second gate insulating layer surrounding the sidewall of the back gate electrode, and the back gate electrode are sequentially distributed in the first through hole from outside to inside;

[0013] A first gate insulating layer surrounding the sidewall of the word line and the word line are sequentially distributed in the second through hole from outside to inside.

[0014] In some embodiments, a first sub-hole of the first through hole located in the insulating layer has a smaller aperture than a second sub-hole of the first through hole located in the conductive layer.

[0015] In some embodiments, the aperture of the third sub-hole of the second through hole located in the insulating layer is smaller than the aperture of the fourth sub-hole of the second through hole located in the conductive layer.

[0016] In some embodiments, a sidewall of the first semiconductor sublayer is connected to a sidewall of the first gate insulating layer, and an insulating layer is disposed between a sidewall of the second semiconductor sublayer and a sidewall of the first gate insulating layer.

[0017] In some embodiments, the transistor further includes a first electrode and a second electrode; the first electrode and the second electrode are distributed on the outer wall of the first semiconductor sublayer and are spaced apart along a first direction parallel to the substrate, and the word line is distributed in the area between the first electrode and the second electrode on the outer wall of the first semiconductor sublayer.

[0018] In some embodiments, the semiconductor device further includes: a memory cell array distributed along a direction perpendicular to the substrate, each layer of the memory cell array including multiple rows and columns of memory cells distributed along the first direction and the second direction respectively, the memory cells including the transistors, the multiple transistors being multiple transistors at the same position in different layers, the second electrodes of the transistors in the same column distributed along the second direction being connected to form a bit line extending along the second direction.

[0019] In some embodiments, transistors adjacent along the first direction are connected to different bit lines.

[0020] In some embodiments, the semiconductor device further comprises:

[0021] Insulating layers and conductive layers are alternately distributed from top to bottom along a direction perpendicular to the substrate, the first electrode and the second electrode are located in the conductive layer, and grooves with openings facing away from the word line, the back gate electrode and the second electrode are provided between adjacent insulating layers, the bottom walls of the grooves expose the first gate insulating layer and the first semiconductor sublayer, and the first electrode extends along the bottom wall and side walls of the grooves.

[0022] In some embodiments, the semiconductor device further includes: a capacitor, the capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the first electrode share the same electrode, the second capacitor electrode is insulated from the first electrode by a dielectric layer and fills the groove where the first electrode is located.

[0023] In some embodiments, an arrangement direction of the first through holes and the second through holes is perpendicular to an arrangement direction of the first electrodes and the second electrodes.

[0024] In some embodiments, the back gate electrode is configured to apply a first turn-off voltage during the turn-on phase of the transistor to turn off the parasitic transistor between adjacent transistors; and to apply a second turn-off voltage during the turn-off phase of the transistor to turn off the transistor together with the word line.

[0025] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0026] Providing a substrate, and alternately depositing a first insulating film and a sacrificial layer film on the substrate to form a stacked structure including alternately arranged insulating layers and sacrificial layers;

[0027] Patterning the stacked structure to form first trenches penetrating each layer, wherein the first trenches extend along a first direction; transistor regions are located between the first trenches;

[0028] forming second through holes penetrating the stacked structure in a direction perpendicular to the substrate in the transistor region between adjacent first trenches, laterally etching a sacrificial layer in each second through hole so that the aperture of the second through hole in the sacrificial layer is larger than the aperture in the insulating layer; and sequentially forming a first gate insulating layer and a word line on the sidewalls of the second through hole;

[0029] forming first through holes penetrating the stacked structure in a direction perpendicular to the substrate in the transistor region between adjacent first trenches, and laterally etching the sacrificial layer in each of the first through holes so that the aperture of the first through hole in the sacrificial layer is larger than the aperture in the insulating layer, and exposing each first gate insulating layer between any sacrificial layers in the second through holes;

[0030] A semiconductor layer connected to each of the first gate insulating layers, a second gate insulating layer, and back gate electrodes corresponding to transistors in different layers are sequentially formed in the first through hole. The semiconductor layer includes a plurality of first semiconductor sublayers arranged at intervals and a second semiconductor sublayer located between adjacent first semiconductor sublayers. The first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure. The distance between the word line and the first semiconductor sublayer along a direction parallel to the substrate is less than the distance between the word line and the second semiconductor sublayer along a direction parallel to the substrate.

[0031] In some embodiments, a capacitor region is further included between the adjacent first trenches, and before forming the second through hole, the method further includes:

[0032] A third through hole is formed in the capacitor region and passes through the stacked structure in a direction perpendicular to the substrate. A sacrificial layer is laterally etched in each of the third through holes to the transistor region. A first electrode of the transistor and a first capacitor electrode of the capacitor, a dielectric layer, and a second capacitor electrode are formed in the third through holes. The first electrode and the first capacitor electrode share the same electrode and are distributed in the third through hole on the sidewall of the sacrificial layer. The dielectric layer is distributed on the sidewall of the third through hole. The second capacitor electrode fills the third through hole, and the third through hole is connected to the first through hole and the second through hole.

[0033] In some embodiments, it further includes:

[0034] A second trench penetrating each layer is formed between transistor areas adjacent to each other along the first direction, and the second trench extends along the second direction; the sacrificial layer is laterally etched in the second trench to two adjacent transistor areas to form two lateral grooves, and two bit lines are formed in the two lateral grooves to fill the two lateral grooves respectively, and the lateral grooves are connected to the first through hole and the second through hole.

[0035] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments, or a semiconductor device manufactured according to the semiconductor device manufacturing method described in any of the above embodiments.

[0036] Embodiments of the present disclosure include a semiconductor device, a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; a first through-hole and a second through-hole penetrating the different layers, a semiconductor layer and a back-gate electrode arranged in the first through-hole extending along a direction perpendicular to the substrate and penetrating the different layers, wherein the semiconductor layer surrounds the sidewall of the back-gate electrode, the semiconductor layer includes a plurality of first semiconductor sublayers arranged at intervals and a second semiconductor sublayer located between adjacent first semiconductor sublayers, the first semiconductor sublayer and the second semiconductor sublayer being connected to form an integrated structure; a word line arranged in the second through-hole and penetrating the different layers and extending along a direction perpendicular to the substrate, wherein a distance between the word line and the first semiconductor sublayer along a direction parallel to the substrate is less than a distance between the word line and the second semiconductor sublayer along a direction parallel to the substrate; the transistor includes a first semiconductor sublayer and a first gate electrode, and the first gate electrode of the transistor at the same position in different layers stacked along a direction perpendicular to the substrate is part of the word line. The solution provided by the embodiment of the present disclosure, by setting a back gate electrode and controlling the distance between the word line and the second semiconductor sublayer and the first semiconductor sublayer, makes the word line have weaker control over the second semiconductor sublayer than over the first semiconductor sublayer. This can achieve turning off the parasitic transistor while turning on the transistor, avoiding leakage caused by the parasitic transistor, and does not require etching to remove the parasitic semiconductor layer, thereby avoiding affecting the channel area of ​​the transistor, simplifying the process, and improving device performance.

[0037] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0038] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation to the technical solution.

[0040] Figure 1A A top view of a semiconductor device provided for an exemplary embodiment;

[0041] Figure 1B For the Figure 1A Cross-section view in the AA direction;

[0042] Figure 1C For the Figure 1A Cross-section along the mid-BB direction;

[0043] Figure 1D For the Figure 1A Cross-section view in the mid-CC direction;

[0044] Figure 1E For the Figure 1A Cross-section along the mid-DD direction;

[0045] Figure 2A A top view of a stacked structure provided by an exemplary embodiment;

[0046] Figure 2B For the Figure 2A Cross-section view in the AA direction;

[0047] Figure 3A A top view after forming a first trench is provided for an exemplary embodiment;

[0048] Figure 3B For the Figure 3A Cross-section view in the AA direction;

[0049] Figure 3C For the Figure 3A Cross-section along the mid-BB direction;

[0050] Figure 4A A top view of an exemplary embodiment after lateral etching of a sacrificial layer;

[0051] Figure 4B For the Figure 4A Cross-section view in the AA direction;

[0052] Figure 4C For the Figure 4A Cross-section along the mid-BB direction;

[0053] Figure 5A A top view of an exemplary embodiment after lateral etching of a sacrificial layer;

[0054] Figure 5B For the Figure 5A Cross-section view in the AA direction;

[0055] Figure 5C For the Figure 5A Cross-section along the mid-BB direction;

[0056] Figure 6A A top view after etching the third through hole provided in an exemplary embodiment;

[0057] Figure 6B For the Figure 6A Cross-section view in the AA direction;

[0058] Figure 6C For the Figure 6A Cross-section along the mid-BB direction;

[0059] Figure 7A A top view of an exemplary embodiment after forming a dielectric layer and a second capacitor electrode;

[0060] Figure 7B For the Figure 7A Cross-section view in the AA direction;

[0061] Figure 7C For the Figure 7A Cross-section along the mid-BB direction;

[0062] Figure 8A A top view after forming a second trench and a first through hole is provided for an exemplary embodiment;

[0063] Figure 8B For the Figure 8A Cross-section view in the AA direction;

[0064] Figure 8C For the Figure 8A Cross-section along the mid-BB direction;

[0065] Figure 9A A top view after forming a second protective layer is provided for an exemplary embodiment;

[0066] Figure 9B For the Figure 9A Cross-section view in the AA direction;

[0067] Figure 9C For the Figure 9A Cross-section along the mid-BB direction;

[0068] Figure 10A A top view after exposing the second groove is provided for an exemplary embodiment;

[0069] Figure 10B For the Figure 10A Cross-section view in the AA direction;

[0070] Figure 10C For the Figure 10A Cross-sectional view along the BB direction.

[0071] Figure 11A A top view after forming a bit line is provided for an exemplary embodiment;

[0072] Figure 11B For the Figure 11A Cross-section view in the AA direction;

[0073] Figure 11C For the Figure 11A Cross-section along the mid-BB direction;

[0074] Figure 12AA top view after forming a first gate insulating layer and a word line is provided for an exemplary embodiment;

[0075] Figure 12B For the Figure 12A Cross-section view in the AA direction;

[0076] Figure 12C For the Figure 12A Cross-section along the mid-BB direction;

[0077] Figure 13A A top view after forming a second through hole is provided for an exemplary embodiment;

[0078] Figure 13B For the Figure 13A Cross-section view in the AA direction;

[0079] Figure 13C For the Figure 13A Cross-section along the mid-BB direction;

[0080] Figure 13D For the Figure 13A Cross-section view in the mid-CC direction;

[0081] Figure 14A A top view after forming the semiconductor layer, the second gate insulating layer and the back gate electrode;

[0082] Figure 14B For the Figure 14A Cross-section view in the AA direction;

[0083] Figure 14C For the Figure 14A Cross-section along the mid-BB direction;

[0084] Figure 14D For the Figure 14A Cross-section view in the mid-CC direction;

[0085] Figure 14E For the Figure 14A Cross-sectional view along the DD direction. DETAILED DESCRIPTION

[0086] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is any conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0087] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0088] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0089] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0090] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0091] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0092] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0093] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0094] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0095] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0096] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0097] In the embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0098] For metal oxide semiconductors as the channel of transistors, some semiconductor materials are very sensitive to the surrounding environment, especially hydrogen and oxygen. Therefore, when manufacturing semiconductor devices, the effects of dry and wet etching on semiconductor materials should be avoided as much as possible. In 3D stacked semiconductor devices, the semiconductor layer is located in the through-hole that penetrates the transistors in each layer, and the semiconductor layer is distributed in various areas of the through-hole sidewall. There are effective channels located in the transistor layer and parasitic channels located between adjacent transistor layers. The parasitic transistors corresponding to the parasitic channels affect the power consumption of the device. One way to remove parasitic MOS is to remove the parasitic channel by etching, but the effective channel is easily affected during the etching process, affecting the performance of the device.

[0099] In an exemplary embodiment of the present disclosure, a parasitic semiconductor layer is retained, and after the semiconductor layer is deposited on the inner sidewall of the hole, the process step of removing the parasitic channel is not performed. Instead, a gate electrode for controlling the parasitic transistor is added and the method timing of the gate electrode is controlled to achieve the purpose of removing the parasitic MOS. Specifically, two gate electrodes are set in the semiconductor device, the first gate electrode controls the turning on and off of the transistor, and the second gate electrode controls the turning off of the parasitic transistor between the transistors. The off voltage of the transistor (for example, a negative voltage for an n-type transistor) is applied to the second gate electrode to turn off the parasitic transistor. When data is accessed (written or read), a turn-on voltage (for example, a positive voltage greater than the transistor turn-on threshold for an n-type transistor) is applied to the first gate electrode to turn on the transistor without turning on the parasitic transistor (the first gate electrode is far away from the parasitic channel of the parasitic transistor and cannot control the parasitic transistor); in the non-working state (stand-by state) of the transistor, such as the off state, an off voltage (for example, a negative voltage for an n-type transistor) is applied to both the first gate electrode and the second gate electrode, thereby turning off the transistor and the parasitic transistor. This solution does not remove the parasitic semiconductor layer, and there is no impact on the channel of the transistor due to the removal of the parasitic semiconductor layer. It can also avoid leakage caused by the parasitic transistor, thereby improving device performance.

[0100] Figure 1A A schematic diagram of a semiconductor device provided as an exemplary embodiment is shown. Figure 1B For the Figure 1A Cross-section view in the AA direction; Figure 1C For the Figure 1A Cross-section along the mid-BB direction; Figure 1D For the Figure 1A Cross-section view in the mid-CC direction; Figure 1E For the Figure 1A Cross-sectional view in the DD direction. Figures 1A to 1E As shown, an embodiment of the present disclosure provides a semiconductor device including a three-dimensional stacked memory cell array. The memory cell array may include a plurality of memory cell arrays vertically stacked on a substrate 1. The plurality of memory cell arrays may be distributed along a third direction Z. The third direction Z may be perpendicular to the substrate 1.

[0101] The memory cell array may include a plurality of bit lines 30, a plurality of word lines 40, and a plurality of memory cells. The plurality of memory cells of the memory cell array may be arranged in an array along a first direction X and a second direction Y. The bit lines 30 may be conductive lines extending along the second direction Y parallel to the substrate 1. The plurality of bit lines 30 in the same memory cell array may be spaced apart from each other and may be distributed along the first direction X. The bit lines 30 of different memory cell arrays may be stacked on the substrate 1, with the bit lines 30 in the same position in different layers spaced apart from each other.

[0102] The word line 40 may extend along a third direction Z. Memory cells stacked vertically at the same position in the two-dimensional memory cell array share the word line 40 . Each memory cell in the two-dimensional memory cell array corresponds to one word line 40 .

[0103] The memory cell can be applicable to a 1T or 2T memory cell, or other multi-transistor memory cell. The role of the transistor within the memory cell is not limited. The transistor has the following characteristics: each memory cell stacked vertically at the same position in a two-dimensional memory cell array shares a word line and a semiconductor layer continuously distributed along the inner sidewall of a through-hole, and a parasitic semiconductor layer exists between memory cells in different layers.

[0104] Taking a 1T1C memory cell as an example, the memory cell includes a transistor and a capacitor connected to the transistor. The transistor may include a first gate electrode 26, a first electrode 51, and a second electrode 52. The first gate electrode 26 may be part of a word line 40. The first gate electrodes 26 of transistors at the same position on different layers may also be part of the same word line 40. The capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42. The first electrode 51 may be connected to the first capacitor electrode 41 of the capacitor, and the second electrode 52 may be connected to the bit line 30. The second electrode 52 may be part of the bit line 30.

[0105] The second electrodes 52 of the transistors in the same column of the same memory cell array may be connected to the same bit line 30. That is, the second electrodes 52 of the transistors in the same column distributed along the second direction Y are connected to form a bit line 30 extending along the second direction Y.

[0106] The transistor and the capacitor of the same memory cell may be distributed along a first direction X.

[0107] The following description is made by taking a semiconductor device including a plurality of vertically stacked transistors at the same position as an example, and taking a 1T1C memory cell as an example.

[0108] like Figures 1A to 1E As shown, an embodiment of the present disclosure provides a semiconductor device, which may include:

[0109] Multiple transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1. The transistors may include a first electrode 51, a second electrode 52, a first semiconductor sublayer 231, and a first gate electrode 26. The first semiconductor sublayer 231 is respectively connected to the first electrode 51 and the second electrode 52 of the transistor;

[0110] A first through hole K1 and a second through hole K2 passing through the different layers, wherein the second through hole K2 is connected to the first through hole K1; a semiconductor layer 23 and a back gate electrode 45 are arranged in the first through hole K1 and extend in a direction perpendicular to the substrate 1 and pass through the different layers, wherein the semiconductor layer surrounds the sidewall of the back gate electrode 45, the semiconductor layer 23 includes a plurality of first semiconductor sublayers 231 arranged at intervals and second semiconductor sublayers 232 located between adjacent first semiconductor sublayers 231, and the first semiconductor sublayers 231 and the second semiconductor sublayers 232 are connected to form an integrated structure; the first semiconductor sublayer 231 is the channel region of the transistor, and the second semiconductor sublayer 232 conducts the adjacent transistor to form a parasitic transistor, that is, the second semiconductor layer sublayer 232 is the channel region of the parasitic transistor;

[0111] The word line 40 is arranged in the second through hole K2 and extends through the different layers in a direction perpendicular to the substrate 1. The first gate electrode 26 of each transistor is part of the word line 40, wherein the distance between the word line 40 and the first semiconductor sublayer 231 in a direction parallel to the substrate 1 is smaller than the distance between the word line 40 and the second semiconductor sublayer 232 in a direction parallel to the substrate 1.

[0112] The semiconductor device provided in this embodiment, by setting a back gate electrode and making the word line 40 have weaker control over the second semiconductor sublayer 232 than over the first semiconductor sublayer 231, can achieve turning off the parasitic transistor while turning on the transistor, avoiding leakage caused by the parasitic transistor, and there is no need to etch and remove the parasitic semiconductor layer, avoiding affecting the channel area of ​​the transistor, simplifying the process, and improving device performance.

[0113] Among them, the first gate electrode 26 of the transistors in different layers can be part of the word line 40, that is, there is no need to make the first gate electrode 26 separately before and after the word line 40 is formed. After the word line 40 is made, part of the word line 40 plays the role of the first gate electrode 26.

[0114] The back gate electrode 45 can extend through the different layers in a direction perpendicular to the substrate 1 and is located within the region enclosed by the semiconductor layers of each stacked transistor and parasitic transistor. The back gate electrode 45 includes a plurality of second gate electrodes 28. That is, the second gate electrode 28 is part of the back gate electrode 45. Before and after the back gate electrode 45 is formed, there is no need to separately fabricate the second gate electrode 28. After the back gate electrode 45 is fabricated, a portion of the back gate electrode 45 functions as the second gate electrode 28. The second gate electrode 28, the second semiconductor sublayer 232, and the two adjacent first semiconductor sublayers 231 form a parasitic transistor. The second gate electrode 28 can control the shutdown of the second semiconductor sublayer 232, thereby disconnecting the signal between the two adjacent first semiconductor sublayers 231.

[0115] In some embodiments, the back gate electrode 45 is configured to apply a first turn-off voltage during the working phase of the transistor, such as the turn-on phase, so that the parasitic transistor between adjacent transistors is turned off; and to apply a second turn-off voltage during the non-working phase of the transistor, such as the turn-off state, to turn off the transistor together with the word line 40.

[0116] In some embodiments, the semiconductor layer 23 can extend on the side wall of the back gate electrode 45 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate 1. The semiconductor layer 23 can extend only in a direction perpendicular to the substrate 1 (there may be a protruding area in the horizontal direction during the extension process), or the main body of the semiconductor layer 23 extends in a direction perpendicular to the substrate 1, and there may be an extension in a horizontal direction (parallel to the substrate 1) at the end.

[0117] In the present disclosure, surrounding can be understood as partial or full surrounding. For example, the semiconductor layer 23 surrounding the back gate electrode 45 can be partially or fully surrounding the back gate electrode 45. In some embodiments, the surrounding can be a full surrounding as a whole, and the cross-section of the semiconductor layer 23 after surrounding is a closed ring. The interception direction of the cross-section is intercepted along a direction parallel to the substrate. In some embodiments, the surrounding can be a partial surrounding, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with an opening can be understood as a U-shaped cross-section, etc., wherein the interception direction of the cross-section is a direction parallel to the substrate.

[0118] The semiconductor device may further include a first gate insulating layer 24 surrounding the sidewall of the word line 40 and extending in a direction perpendicular to the substrate 1 . The word line 40 is insulated from the semiconductor layer 23 by the first gate insulating layer 24 .

[0119] It can be understood that the word line 40 and the back gate electrode 45 (or control line) are respectively located on both sides of the semiconductor layer 23, and are respectively connected to the semiconductor layer 23 through the first gate insulating layer 24. They can simultaneously control the channel area corresponding to the effective transistor of the semiconductor layer 23, and can also simultaneously control the parasitic semiconductor layer between the effective transistors.

[0120] The semiconductor device may further include a second gate insulating layer 27 surrounding the side wall of the back gate electrode 45 and extending in a direction perpendicular to the substrate 1 . The second gate insulating layer 27 is arranged between the side wall of the back gate electrode 45 and the side wall of the semiconductor layer 23 . The back gate electrode 45 is insulated from the semiconductor layer 23 by the second gate insulating layer 27 .

[0121] In some embodiments, the semiconductor device may further include:

[0122] Insulating layers and conductive layers are alternately distributed from top to bottom in a direction perpendicular to the substrate 1; the first through hole K1 and the second through hole K2 penetrate each of the insulating layers and each of the conductive layers;

[0123] The first gate insulating layer 24 surrounding the sidewall of the word line 40 and the word line 40 are sequentially distributed in the second through hole K2 from the outside to the inside;

[0124] The semiconductor layer 23 , the second gate insulating layer 27 surrounding the sidewall of the back gate electrode 45 , and the back gate electrode 45 are sequentially distributed in the first through hole K1 from outside to inside;

[0125] The first electrode 51 and the second electrode 52 are disposed on the conductive layer.

[0126] The solution provided in this embodiment can form the word line 40 , the first gate insulating layer 24 , the back gate electrode 45 , the second gate insulating layer 27 , and the semiconductor layer 23 at one time, thus simplifying the process.

[0127] In some embodiments, the orthographic projection of the third sub-hole of the second through hole K2 located in the insulating layer on the substrate 1 may fall within the orthographic projection of the fourth sub-hole of the second through hole K2 located in the conductive layer on the substrate 1, i.e., the aperture of the third sub-hole of the second through hole K2 located in the insulating layer is smaller than the aperture of the fourth sub-hole of the second through hole K2 located in the conductive layer. The solution provided in this embodiment, by providing third and fourth sub-holes of different apertures, can ensure that the distances between the word line 40 and the first semiconductor sublayer 231 and the second semiconductor sublayer 232 are different (the first semiconductor sublayer 231 is located in the region where the conductive layer is located, and the word line 40 protrudes relative to the fourth sub-hole in the third sub-hole (located in the conductive layer). Therefore, the word line 40 is closer to the first semiconductor sublayer 231 and farther from the second semiconductor sublayer 232). This ensures that the word line 40 has weaker control over the second semiconductor sublayer 232 than over the first semiconductor sublayer 231, thereby preventing the word line 40 from turning on a parasitic transistor when the transistor is turned on.

[0128] In some embodiments, the orthographic projection of the first sub-hole of the first through hole K1 located in the insulating layer on the substrate 1 can fall within the orthographic projection of the second sub-hole of the first through hole K1 located in the conductive layer on the substrate, that is, the aperture of the first sub-hole of the first through hole K1 located in the insulating layer is smaller than the aperture of the second sub-hole of the first through hole K1 located in the conductive layer. The solution provided in this embodiment, by providing first and second sub-holes of different apertures, can make the distances between the word line 40 and the first semiconductor sublayer 231 and the second semiconductor sublayer 232 different (the first semiconductor sublayer 231 is located in the second sub-hole, and the second semiconductor sublayer 232 is located in the first sub-hole, and the first semiconductor sublayer 231 is further outward from the second semiconductor sublayer 232 in the first through hole K1, so that the first semiconductor sublayer 231 is closer to the word line 40 than the second semiconductor sublayer 232). As a result, the control of the word line 40 over the second semiconductor sublayer 232 is weaker than that over the first semiconductor sublayer 231, thereby preventing the word line 40 from turning on a parasitic transistor when the transistor is turned on.

[0129] In some embodiments, the orthographic projection of the third sub-hole of the second through hole K2 in the insulating layer on the substrate 1 can fall within the orthographic projection of the fourth sub-hole of the second through hole K2 in the conductive layer on the substrate 1, and the orthographic projection of the first sub-hole of the first through hole K1 in the insulating layer on the substrate 1 can fall within the orthographic projection of the second sub-hole of the first through hole K1 in the conductive layer on the substrate. Compared to the previous two solutions, the solution provided in this embodiment can further increase the distance between the word line 40 and the second semiconductor layer 232, reduce the impact of the word line 40 on the parasitic transistor, and be more conducive to shutting down the parasitic transistor.

[0130] In some embodiments, the arrangement direction of the first through hole K1 and the second through hole K2 may be perpendicular to the arrangement direction of the first electrode 51 and the second electrode 52. The arrangement direction of the first electrode 51 and the second electrode 52 is, for example, the first direction X, and the arrangement direction of the first through hole K1 and the second through hole K2 is, for example, the second direction Y. That is, on a plane parallel to the substrate 1, the first through hole K1 and the second through hole K2 may be arranged along the second direction Y, and the arrangement order of the first through hole K1 and the second through hole K2 along the second direction Y is not limited to Figure 1A As shown in FIG, the positions of the first through hole K1 and the second through hole K2 can be interchanged.

[0131] In some embodiments, the first through hole K1 and the second through hole K2 may be located between the first electrode 51 and the second electrode 52 .

[0132] In some embodiments, the size of the second sub-aperture along the arrangement direction of the first electrode 51 and the second electrode 52 may be the same as the size of the fourth sub-aperture along the arrangement direction of the first electrode 51 and the second electrode 52. That is, the size of the second sub-aperture along the first direction X may be the same as the size of the fourth sub-aperture in the first direction X.

[0133] In some embodiments, the sidewall of the first semiconductor sublayer 231 may be connected to the sidewall of the first gate insulating layer 24 , and the insulating layer may be provided between the sidewall of the second semiconductor sublayer 232 and the sidewall of the first gate insulating layer 24 .

[0134] In some embodiments, the first electrode 51 and the second electrode 52 are distributed on the outer wall of the first semiconductor sublayer 231 and are spaced apart along a first direction X parallel to the substrate 1 , and the word line 40 is distributed in the area between the first electrode 51 and the second electrode 52 on the outer wall of the first semiconductor sublayer 231 .

[0135] In some embodiments, the first electrode 51 may be connected to the first gate insulating layer 24, and the second electrode 52 may be connected to the first gate insulating layer 24. The first electrode 51 may be located on a first side of the first gate insulating layer 24, and the second electrode 52 may be located on a second side of the first gate insulating layer 24, wherein the first side and the second side of the first gate insulating layer 24 are opposite sides, and the third side of the first gate insulating layer 24 is connected to the semiconductor layer 23, and the third side of the first gate insulating layer 24 is adjacent to the first side and the second side.

[0136] In some embodiments, a groove with an opening facing away from the word line 40, the back gate electrode 45 and the second electrode 52 is provided between adjacent insulating layers, the bottom wall of the groove exposes the first gate insulating layer 24 and the first semiconductor sublayer 231, and the first electrode 51 extends along the bottom wall and side wall of the groove. That is, a transverse groove is formed between adjacent insulating layers, and the first electrode 51 only covers the bottom wall and side wall of the groove, and does not completely fill the groove. However, the embodiments of the present disclosure are not limited to this, and the first electrode 51 can fill the groove. The first electrode 51 also serves as the first capacitor electrode 41 of the capacitor. When the first electrode 51 serves as an electrode of the capacitor, the first electrode 51 extends along the bottom wall and side wall of the groove, which can increase the area of ​​the first electrode 51, thereby increasing the capacitance.

[0137] In some embodiments, the second capacitor electrode 42 fills the groove in which the first electrode 51 is formed. A dielectric layer 43 is disposed between the first capacitor electrode 41 and the second capacitor electrode 42. In some embodiments, the second capacitor electrodes 42 of capacitors at the same location on different layers can be connected to form an integrated structure, forming a vertical portion extending in a direction perpendicular to the substrate 1 and multiple horizontal portions extending from the vertical portion to the groove where the first electrode 51 of a different layer is located.

[0138] In some embodiments, the second capacitor electrodes 42 of every two adjacent memory cells along the first direction X are connected to form an integrated structure.

[0139] In some embodiments, the second capacitor electrode 42 of the integrated structure includes a vertical portion extending in a direction perpendicular to the substrate and a horizontal portion extending from the vertical portion to the grooves where the first electrodes 51 of adjacent memory cells are located.

[0140] In some embodiments, the second electrode 52 of the transistor may be a portion of the bit line 30 to which the second electrode 52 is connected. For example, the bit line 30 is a straight line (eg, Figure 1A As shown), the side wall of the straight line is connected to the semiconductor layer 23, or the bit line 30 has a branch of an integral design, which is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as approximately perpendicular.

[0141] The branches may be multiple branches on one sidewall of the bit line, or multiple branches on both sidewalls at the same time, and each branch may form a transistor or a memory cell. Figure 1A In the embodiment, the bit line 30 is a straight line, and the sidewall of the straight line is connected only to the semiconductor layer 23 located on one side of the bit line 30. In this embodiment, the transistors in two adjacent columns are connected to different bit lines 30, and the bit lines 30 connected to the two adjacent columns of transistors are separated by an insulating film layer. However, the embodiments of the present disclosure are not limited to this. In some embodiments, the bit line 30 can be connected to the semiconductor layer 23 on both sides of the bit line 30, that is, a single bit line 30 can connect the semiconductor layers 23 of two adjacent columns of transistors.

[0142] Figures 1A to 1E The semiconductor device structure described is only an example, and the embodiments of the present disclosure are not limited thereto. For structures in which there are semiconductor layers extending through multiple layers in a direction perpendicular to the substrate 1, resulting in the presence of parasitic transistors between adjacent transistors, the parasitic transistors can be turned off by setting a corresponding second gate electrode for controlling the parasitic transistors. The embodiments of the present disclosure do not limit the position and shape of the second gate electrode, and parasitic transistors in different layers can be manufactured separately.

[0143] The technical solution of this embodiment will be further illustrated below using the manufacturing process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film of a certain material formed on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, the "thin film" before patterning is referred to as a "thin film" and the "layer" after patterning is referred to as a "layer." The "layer" after patterning or photolithography contains at least one "pattern."

[0144] In an exemplary embodiment, a process for manufacturing the semiconductor device may include:

[0145] 1) providing a substrate 1, depositing a sacrificial layer film and a first insulating film alternately on the substrate 1 to form a stacked structure, and depositing a hard mask film on the stacked structure to form a hard mask layer 9, such as Figure 2A and Figure 2B As shown, Figure 2A A top view of a stacked structure is provided for an exemplary embodiment. Figure 2B For the Figure 2A Cross-section view in the AA direction. Figure 2B As shown, the stack structure may include a stack of sacrificial layers 11 and first insulating layers 10 that are alternately arranged.

[0146] In some embodiments, substrate 1 may be a semiconductor substrate having one or more layers, structures, or regions formed thereon. Substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0147] In some embodiments, the first insulating film and the sacrificial layer film may be deposited using a chemical vapor deposition method.

[0148] In some embodiments, the first insulating film may be a low-K dielectric layer, ie, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0149] In some embodiments, the sacrificial layer film can be a conductive material or a non-conductive material different from the first insulating film. The sacrificial layer film can be, for example, the following conductive materials:

[0150] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0151] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0152] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0153] In some embodiments, the hard mask layer 9 includes but is not limited to at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0154] Figure 2B The stacked structure shown in the figure includes three first insulating layers 10 and three sacrificial layers 11, which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 10 and sacrificial layers 11 that are alternately arranged.

[0155] 2) etching the stacked structure to form a first trench T1;

[0156] The etching the stack structure to form the first trench T1 may include:

[0157] The stacked structure is etched to form a plurality of first trenches T1 penetrating the stacked structure; the first trenches T1 extend along a first direction X, and adjacent first trenches T1 include transistor regions 100 and capacitor regions 200, and adjacent transistor regions 100 along the first direction X include bit line regions 300. The sacrificial layer 11 forms a predetermined pattern. The predetermined pattern of the sacrificial layer 11 may include a plurality of first sub-portions and second sub-portions connecting the first sub-portions. The first sub-portions may extend along the first direction X, and the second sub-portions may extend along the second direction Y. Figure 3A The preset pattern of the hard mask layer 9 is shown, and the preset patterns of the other film layers are consistent with the preset pattern of the hard mask layer 9.

[0158] A second insulating film is deposited and polished to form a second insulating layer 13 filling the first trench T1; the second insulating layer 13 can be flush with the hard mask layer 9. Figure 3A 、 Figure 3B and Figure 3C As shown, Figure 3A This is a top view after forming the first trench T1. Figure 3B For the Figure 3A Cross-section view in the AA direction, Figure 3C For the Figure 3A The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0159] In some embodiments, the second insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0160] 3) forming a third through hole K3 and laterally etching the sacrificial layer 11;

[0161] The forming of the third through hole K3 and the transverse etching of the sacrificial layer 11 may include: etching the stacked structure from the top layer to the bottom layer in the capacitor region 200 by dry etching (the etching stops on the substrate 1) to form the third through hole K3, and transversely etching the sacrificial layer 11 in the third through hole K3 to remove the sacrificial layer 11 in the capacitor region 200 until the etching reaches the transistor region 100, thereby forming a first transverse groove K31 and a second transverse groove K32. Figure 4A 、 Figure 4B and Figure 4C As shown, Figure 4A This is a top view after the sacrificial layer 11 is laterally etched. Figure 4B For the Figure 4A Cross-section view in the AA direction, Figure 4C For the Figure 4A A cross-sectional view taken along the BB direction is shown. Subsequently, a second capacitor electrode 42 of the capacitor can be formed in the third through hole K3 , and first capacitor electrodes 41 of two capacitors can be formed in the first transverse groove K31 and the second transverse groove K32 .

[0162] 4) forming a first capacitor electrode 41 and a first protective layer 8;

[0163] The forming of the first capacitor electrode 41 and the first protective layer 8 may include: depositing a first conductive film and a first protective layer film in sequence on the substrate 1 having the aforementioned structure to form the first capacitor electrode 41 and the first protective layer 8, wherein the first protective layer 8 fills the third through hole K3 and the first transverse groove K31 and the second transverse groove K32, as shown in FIG. Figure 5A 、 Figure 5B and Figure 5C As shown, Figure 5A This is a top view after the sacrificial layer 11 is laterally etched. Figure 5B For the Figure 5A Cross-section view in the AA direction, Figure 5C For the Figure 5A In this embodiment, the first capacitor electrode 41 and the first electrode 51 are shared.

[0164] In some embodiments, the first conductive film includes but is not limited to at least one of the following or a combination thereof:

[0165] Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

[0166] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0167] In some embodiments, the first protective layer film can be an insulating material, including but not limited to SiN.

[0168] 5) Etching and removing the first capacitor electrode 41 and the first protective layer 8 in the third through hole K3;

[0169] The etching and removing of the first capacitor electrode 41 and the first protective layer 8 in the third through hole K3 may include: etching and removing the first capacitor electrode 41 and the first protective layer 8 in the third through hole K3 from the top layer to the bottom layer by dry etching, such as Figure 6A 、 Figure 6B and Figure 6C As shown, Figure 6A This is a top view after etching the third through hole K3. Figure 6B For the Figure 6A Cross-section view in the AA direction, Figure 6C For the Figure 6ACross-sectional view along the BB direction. It can be seen that the first capacitor electrode 41 and the first protective layer 8 in the third through hole K3 are completely removed, and the second capacitor electrode 42 is subsequently formed in the third through hole K3. Therefore, the first capacitor electrode 41 in the third through hole K3 is etched away to prevent conduction between the first capacitor electrode 41 and the second capacitor electrode 42, and to prevent conduction between the first capacitor electrodes 41 of capacitors in different layers. The first capacitor electrode 41 of one capacitor is distributed on the bottom wall and side walls of the first transverse groove K31, and the first capacitor electrode 41 of the other capacitor is distributed on the bottom wall and side walls of the second transverse groove K32.

[0170] 6) Forming a dielectric layer 43 and a second capacitor electrode 42;

[0171] The forming of the dielectric layer 43 and the second capacitor electrode 42 may include:

[0172] The first protective layer 8 in the first transverse groove K31 and the second transverse groove K32 is removed by transverse etching to expose the first capacitor electrode 41 ; the first protective layer 8 in the first transverse groove K31 and the second transverse groove K32 can be removed by wet etching.

[0173] A dielectric film and a conductor material are sequentially deposited on the substrate 1 forming the above structure to form a dielectric layer 43 and a second capacitor electrode 42 respectively. The second capacitor electrode 42 is insulated from the first capacitor electrode 41 by the dielectric layer 43. Figure 7A 、 Figure 7B and Figure 7C As shown, Figure 7A This is a top view after the dielectric layer 43 and the second capacitor electrode 42 are formed. Figure 7B For the Figure 7A Cross-section view in the AA direction, Figure 7C For the Figure 7A The second capacitor electrode 42 may fill the third through hole K3 , the first transverse groove K31 , and the second transverse groove K32 .

[0174] In some embodiments, the second capacitor electrodes 42 of capacitors at the same position in different layers may be connected to form an integrated structure, for example, by being connected via a vertical portion disposed in the third through hole K3 . Figure 7A and Figure 7B The shape of the capacitor shown is only an example, and the embodiments of the present disclosure are not limited thereto. It can be seen that the second capacitor electrodes 43 of the capacitors of adjacent memory cells along the first direction X can be connected to form an integrated structure, for example, through the vertical portion provided in the third through hole K3.

[0175] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, the dielectric film may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like. Exemplary materials include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0176] In some embodiments, the conductor material includes but is not limited to at least one of the following or a combination thereof:

[0177] Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

[0178] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0179] 7) Forming a second trench T2 and a second through hole K2;

[0180] The forming of the second trench T2 and the second through hole K2 may include: dry etching the stack structure, forming a second trench T2 in the bit line area 300 that penetrates the stack structure in a direction perpendicular to the substrate 1, and forming a second through hole K2 that penetrates the stack structure in the transistor area 100, wherein the second through hole K2 includes a third sub-hole located in the first insulating layer 10 and a fourth sub-hole located in the sacrificial layer 11, and the apertures of the third sub-hole and the fourth sub-hole are consistent; the second trench T2 includes a first sub-trench located in the first insulating layer 10 and a second sub-trench located in the sacrificial layer 11, and the width of the first sub-trench along the first direction X is consistent with the width of the second sub-trench along the first direction X; the second trench T2 may penetrate the stack structure along the second direction Y.

[0181] The sacrificial layer 11 is laterally etched to enlarge the aperture of the fourth sub-hole of the second through hole K2 located in the sacrificial layer 11, and to enlarge the width of the second sub-groove of the second trench T2 located in the sacrificial layer 11 along the first direction X, as shown in FIG. Figure 8A 、 Figure 8B and Figure 8C As shown, Figure 8AThis is a top view after the second trench T2 and the second through hole K2 are formed. Figure 8B For the Figure 8A Cross-section view in the AA direction, Figure 8C For the Figure 8A Cross-sectional view along the BB direction. At this point, the second through hole K2 forms multiple holes of two different sizes. The aperture of the third sub-hole of the second through hole K2 located in the first insulating layer 10 is smaller than the aperture of the fourth sub-hole located in the sacrificial layer 11. The orthographic projection of the third sub-hole of the second through hole K2 located in the first insulating layer 10 on the substrate 1 falls within the orthographic projection of the fourth sub-hole located in the sacrificial layer 11 on the substrate 1. The second trench T2 forms two different grooves of different sizes. The width of the first sub-trench of the second trench T2 located in the first insulating layer 10 along the first direction X is smaller than the width of the second sub-trench located in the sacrificial layer 11 along the first direction X. The orthographic projection of the first sub-trench of the second trench T2 located in the first insulating layer 10 on the substrate 1 is smaller than the width of the second sub-trench located in the sacrificial layer 11. The second through hole K2 and the second trench T2 are connected. At this time, in addition to the longitudinal trench T20 extending through the stacked structure in a direction perpendicular to the substrate, the second trench T2 also includes two transverse grooves: a third transverse groove T21 and a fourth transverse groove T22. Bit lines 30 are subsequently formed in the third transverse groove T21 and the fourth transverse groove T22, respectively. Transistors in the same layer and column are connected to the same bit line 30. Therefore, the third transverse groove T21 and the fourth transverse groove T22 extend along the second direction Y to the region where the transistors in the same layer and column are located. By providing third and fourth sub-holes of different apertures, the distances between the subsequently formed word lines 40 and the first semiconductor sub-layer 231 and the second semiconductor sub-layer 232 in the semiconductor layer 23 can be varied.

[0182] 8) forming a second protective layer 7;

[0183] The forming of the second protective layer 7 may include: depositing a second protective layer thin film on the substrate 1 forming the aforementioned structure to form the second protective layer 7, wherein the second protective layer 7 fills the second through hole K2 and the second trench T2, as shown in FIG. Figure 9A 、 Figure 9B and Figure 9C As shown, Figure 9A This is a top view after the second protective layer 7 is formed. Figure 9B For the Figure 9A Cross-section view in the AA direction, Figure 9C For the Figure 9A Cross-sectional view along the BB direction.

[0184] In some embodiments, the second protection layer film may be made of an insulating material different from that of the first insulating film, such as SiN.

[0185] 9) exposing the second trench T2;

[0186] Exposing the second trench T2 may include: etching away the second protection layer 7 in the second trench T2 to expose the second trench T2, that is, the second protection layer 7 in the second trench T2 is completely etched away, so as to subsequently form the bit line 30 in the second trench T2. Figure 10A 、 Figure 10B and Figure 10C As shown, Figure 10A is a top view after the second trench T2 is exposed, Figure 10B For the Figure 10A Cross-section view in the AA direction, Figure 10C For the Figure 10A Cross-sectional view along the BB direction.

[0187] In some embodiments, the second protection layer 7 in the longitudinal trench T20 may be removed by dry etching first, and then the second protection layer 7 in the third and fourth transverse grooves T21 and T22 may be removed by wet etching.

[0188] 10) forming a bit line 30;

[0189] Forming the bit lines 30 may include: depositing a second conductive film on the substrate 1 having the above structure; removing the second conductive film in the longitudinal trenches T20 from the top layer to the bottom layer by dry etching to form the bit lines 30; removing the second conductive film in the longitudinal trenches T20 may disconnect bit lines 30 in different layers and may disconnect adjacent bit lines 30 in the same layer. Two adjacent bit lines 30 are located in the third transverse trench T21 and the fourth transverse trench T22, respectively.

[0190] A third insulating film is deposited on the substrate 1 having the above structure to form a third insulating layer 14. The third insulating layer 14 fills the longitudinal trench T20. Figure 11A 、 Figure 11B and Figure 11C As shown, Figure 11A This is a top view after the bit line 30 is formed. Figure 11B For the Figure 11A Cross-section view in the AA direction, Figure 11C For the Figure 11A Cross-sectional view along the BB direction.

[0191] The bit lines 30 at the same position in different layers are separated by the first insulating layer 10 , and the adjacent bit lines 30 in the same layer are separated by the third insulating layer 14 .

[0192] In some embodiments, the third insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0193] In some embodiments, the second conductive film may be one or more of the following different types of materials:

[0194] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0195] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0196] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0197] 11) Forming a first gate insulating layer 24 and a word line 40;

[0198] The forming of the first gate insulating layer 24 and the word line 40 may include: depositing a first gate insulating film and a first gate electrode film in sequence in the second through hole K2 to form the first gate insulating layer 24 and the word line 40; the word line 40 fills the second through hole K2, such as Figure 12A 、 Figure 12B and Figure 12C As shown, Figure 12A FIG. 4 is a top view after forming the first gate insulating layer 24 and the word line 40. Figure 12B For the Figure 12A Cross-section view in the AA direction, Figure 12C For the Figure 12A The first gate electrode 26 of the transistor at the same position in different layers is part of the word line 40. The first gate insulating layer 24 covers the bottom wall and side walls of the second through hole K2.

[0199] In some embodiments, the material of the first gate insulating layer 24 may include one or more layers of a high-k dielectric material. In some embodiments, the material may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like. For example, the material may include, but is not limited to, at least one of the following high-k materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like.

[0200] In some embodiments, the first gate electrode film may be made of one or more of the following different types of materials:

[0201] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0202] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0203] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0204] 12) forming a first through hole K1;

[0205] The forming of the first through hole K1 may include: dry etching the stack structure to form the first through hole K1 penetrating the stack structure in the transistor region 100 , wherein the first through hole K1 includes a first sub-hole located in the first insulating layer 10 and a second sub-hole located in the sacrificial layer 11 , and the first sub-hole and the second sub-hole have the same aperture;

[0206] The sacrificial layer 11 is laterally etched to enlarge the aperture of the second sub-hole of the first through hole K1 located in the sacrificial layer 11, as shown in FIG. Figure 13A 、 Figure 13B 、 Figure 13C and Figure 13D As shown, Figure 13A This is a top view after the first through hole K1 is formed. Figure 13B For the Figure 13A Cross-section view in the AA direction, Figure 13C For the Figure 13A Cross-section view in the BB direction, Figure 13D For the Figure 13ACross-sectional view taken along the CC direction. The CC direction is parallel to the AA direction. At this point, the first through hole K1 forms a plurality of two types of holes of different sizes. The aperture of the first sub-hole of the first through hole K1 located in the first insulating layer 10 is smaller than the aperture of the second sub-hole located in the sacrificial layer 11. That is, the orthographic projection of the first sub-hole of the first through hole K1 located in the first insulating layer 10 on the substrate 1 falls within the orthographic projection of the second sub-hole located in the sacrificial layer 11 on the substrate 1. In this step, the sacrificial layer 11 is completely removed. By providing first and second sub-holes of different apertures, the distances between the first semiconductor sublayer 231 and the second semiconductor sublayer 232 in the subsequently formed semiconductor layer 23 and the word line 40 can be different.

[0207] 13) forming a semiconductor layer 23, a second gate insulating layer 27 and a back gate electrode 45;

[0208] The formation of the semiconductor layer 23, the second gate insulating layer 27 and the back gate electrode 45 may include: depositing a semiconductor film, a second gate insulating film and a second gate electrode film in sequence in the first through hole K1 to form the semiconductor layer 23, the second gate insulating layer 27 and the back gate electrode 45, wherein the back gate electrode 45 fills the first through hole K1. Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D and Figure 14E As shown, Figure 14A FIG. 4 is a top view after the semiconductor layer 23, the second gate insulating layer 27 and the back gate electrode 45 are formed. Figure 14B For the Figure 14A Cross-section view in the AA direction, Figure 14C For the Figure 14A Cross-section view in the BB direction, Figure 14D For the Figure 14A Cross-section view in CC direction, Figure 14E For the Figure 14A The cross-sectional view along the DD direction is perpendicular to the AA direction.

[0209] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 1.65 eV, or a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0210] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0211] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0212] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0213] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0214] In an exemplary embodiment of the present disclosure, the material of the second gate insulating layer 27 may include one or more layers of a High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, the material may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0215] In some embodiments, the second gate electrode film may be one or more of the following different types of materials:

[0216] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0217] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0218] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0219] The present disclosure also provides an electronic device comprising the semiconductor device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0220] An embodiment of the present disclosure provides a driving method for a semiconductor device, which is applied to the semiconductor device described in any of the above embodiments. The driving method includes:

[0221] In the working phase of the transistor, such as the turned-on phase, a first turn-off voltage is applied to the second gate electrode to turn off the parasitic transistor.

[0222] The driving method provided by the embodiment of the present disclosure turns off the parasitic transistor through the second gate electrode, thereby avoiding leakage caused by the parasitic transistor, and does not require etching and removing the parasitic transistor when manufacturing the semiconductor device, thereby avoiding affecting the channel area of ​​the transistor and improving device performance.

[0223] In some embodiments, the transistor may be an N-type transistor, and the first off-voltage may be a negative voltage. However, the embodiments of the present disclosure are not limited thereto, and the transistor may be a P-type transistor.

[0224] In some embodiments, the method may further include: in an operation phase of the memory cell or the transistor, applying a turn-on voltage to the first gate electrode to turn on the transistor.

[0225] In some embodiments, the transistor may be an N-type transistor, and the turn-on voltage may be a positive voltage greater than or equal to a threshold voltage of the transistor.

[0226] In some embodiments, the method may further include: in a non-working phase of the memory cell or the transistor, for example, in a standby state of the memory cell, or a closed state of the transistor, loading a second turn-off voltage on the first gate electrode to turn off the transistor, loading a third turn-off voltage on the second gate electrode to turn off the parasitic transistor, and, assisting in turning off the transistor.

[0227] In some embodiments, the transistor may be an N-type transistor, and the second off-voltage and the third off-voltage may be negative voltages.

[0228] In some embodiments, the third turn-off voltage may be the same as or different from the first turn-off voltage.

[0229] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: Multiple transistors are distributed in different layers and stacked along a direction perpendicular to the substrate; a first through hole and a second through hole penetrating the different layers, the second through hole being connected to the first through hole, and a semiconductor layer and a back gate electrode being arranged in the first through hole and extending in a direction perpendicular to the substrate and penetrating the different layers, wherein the semiconductor layer surrounds the sidewall of the back gate electrode, the semiconductor layer includes a plurality of first semiconductor sublayers spaced apart and a second semiconductor sublayer located between adjacent first semiconductor sublayers, and the first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure; a word line disposed in the second through hole and extending through the different layers in a direction perpendicular to the substrate, wherein a distance between the word line and the first semiconductor sublayer in a direction parallel to the substrate is smaller than a distance between the word line and the second semiconductor sublayer in a direction parallel to the substrate; The transistor includes the first semiconductor sublayer and a first gate electrode, and the first gate electrode of the transistor is part of the word line.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes: Insulating layers and conductive layers are alternately distributed from top to bottom in a direction perpendicular to the substrate; the first through hole and the second through hole penetrate the insulating layer and the conductive layer; The semiconductor layer, the second gate insulating layer surrounding the sidewall of the back gate electrode, and the back gate electrode are sequentially distributed in the first through hole from outside to inside; A first gate insulating layer surrounding the sidewall of the word line and the word line are sequentially distributed in the second through hole from outside to inside.

3. The semiconductor device according to claim 2, wherein The aperture of a first sub-hole of the first through hole located in the insulating layer is smaller than the aperture of a second sub-hole of the first through hole located in the conductive layer.

4. The semiconductor device according to claim 2, wherein The aperture of the third sub-hole of the second through hole located in the insulating layer is smaller than the aperture of the fourth sub-hole of the second through hole located in the conductive layer.

5. The semiconductor device according to claim 2, wherein The sidewall of the first semiconductor sublayer is connected to the sidewall of the first gate insulating layer, and an insulating layer is provided between the sidewall of the second semiconductor sublayer and the sidewall of the first gate insulating layer.

6. The semiconductor device according to claim 5, wherein The transistor also includes a first electrode and a second electrode; the first electrode and the second electrode are distributed on the outer wall of the first semiconductor sublayer and are spaced apart along a first direction parallel to the substrate, and the word line is distributed in the area between the first electrode and the second electrode on the outer wall of the first semiconductor sublayer.

7. The semiconductor device according to claim 6, wherein: The semiconductor device also includes: a memory cell array distributed in a direction perpendicular to the substrate, each layer of the memory cell array includes multiple rows and columns of memory cells distributed along the first direction and the second direction respectively, the memory cells include the transistors, the multiple transistors are multiple transistors in the same position on different layers, and the second electrodes of the transistors in the same column distributed along the second direction are connected to form a bit line extending along the second direction.

8. The semiconductor device according to claim 7, wherein: Transistors adjacent to each other along the first direction are connected to different bit lines.

9. The semiconductor device according to claim 6, wherein: The semiconductor device further includes: Insulating layers and conductive layers are alternately distributed from top to bottom along a direction perpendicular to the substrate, the first electrode and the second electrode are located in the conductive layer, and grooves with openings facing away from the word line, the back gate electrode and the second electrode are provided between adjacent insulating layers, the bottom walls of the grooves expose the first gate insulating layer and the first semiconductor sublayer, and the first electrode extends along the bottom wall and side walls of the grooves.

10. The semiconductor device according to claim 9, wherein The semiconductor device further includes: a capacitor, the capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the first electrode share the same electrode, the second capacitor electrode is insulated from the first electrode by a dielectric layer and fills the groove where the first electrode is located.

11. The semiconductor device according to claim 6, wherein An arrangement direction of the first through holes and the second through holes is perpendicular to an arrangement direction of the first electrodes and the second electrodes.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that: The back gate electrode is configured to apply a first turn-off voltage during the transistor on phase to turn off the parasitic transistor between adjacent transistors; and to apply a second turn-off voltage during the transistor off phase to turn off the transistor together with the word line.

13. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, and alternately depositing a first insulating film and a sacrificial layer film on the substrate to form a stacked structure including alternately arranged insulating layers and sacrificial layers; Patterning the stacked structure to form first trenches penetrating each layer, wherein the first trenches extend along a first direction; The transistor region is included between the first trenches; forming second through holes penetrating the stacked structure in a direction perpendicular to the substrate in the transistor region between adjacent first trenches, laterally etching a sacrificial layer in each second through hole so that the aperture of the second through hole in the sacrificial layer is larger than the aperture in the insulating layer; and sequentially forming a first gate insulating layer and a word line on the sidewalls of the second through hole; forming first through holes penetrating the stacked structure in a direction perpendicular to the substrate in the transistor region between adjacent first trenches, and laterally etching the sacrificial layer in each of the first through holes so that the aperture of the first through hole in the sacrificial layer is larger than the aperture in the insulating layer, and exposing each first gate insulating layer between any sacrificial layers in the second through holes; A semiconductor layer connected to each of the first gate insulating layers, a second gate insulating layer, and back gate electrodes corresponding to transistors in different layers are sequentially formed in the first through hole. The semiconductor layer includes a plurality of first semiconductor sublayers arranged at intervals and a second semiconductor sublayer located between adjacent first semiconductor sublayers. The first semiconductor sublayer and the second semiconductor sublayer are connected to form an integrated structure. The distance between the word line and the first semiconductor sublayer along a direction parallel to the substrate is less than the distance between the word line and the second semiconductor sublayer along a direction parallel to the substrate.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: A capacitor region is further included between the adjacent first trenches, and before forming the second through hole, the method further includes: A third through hole is formed in the capacitor region and passes through the stacked structure in a direction perpendicular to the substrate. A sacrificial layer is laterally etched in each of the third through holes to the transistor region. A first electrode of the transistor and a first capacitor electrode of the capacitor, a dielectric layer, and a second capacitor electrode are formed in the third through holes. The first electrode and the first capacitor electrode share the same electrode and are distributed in the third through hole on the sidewall of the sacrificial layer. The dielectric layer is distributed on the sidewall of the third through hole. The second capacitor electrode fills the third through hole, and the third through hole is connected to the first through hole and the second through hole.

15. The method for manufacturing a semiconductor device according to claim 13 or 14, wherein: Also includes: forming a second trench penetrating each layer between transistor regions adjacent to each other along the first direction, wherein the second trench extends along the second direction; The sacrificial layer is laterally etched in the second trench to two adjacent transistor regions to form two lateral grooves, and two bit lines are formed in the two lateral grooves to fill the two lateral grooves respectively. The lateral grooves are connected to the first through hole and the second through hole.

16. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to any one of claims 1 to 12, or a semiconductor device manufactured by the semiconductor device manufacturing method according to any one of claims 13 to 15.

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