Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package has a central region and a peripheral region around the central region in a plan view. The semiconductor package includes: a package substrate; a first chip stack on the package substrate in the central region and the peripheral region, and electrically connected to the package substrate; a second chip stack on the first chip stack in the peripheral region and including a lower second chip and an upper second chip on the lower second chip, the upper second chip being farther from the central region than the lower second chip; an interposer on the first chip stack, at least in the central region, and including a conductive path electrically connected to the package substrate; an encapsulation layer covering the first chip stack and the second chip stack on the package substrate; and an external connection terminal under the package substrate and electrically connected to the package substrate, in which the second chip stack and the interposer are electrically connected to each other on a side close to the central region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a multi-stack structure. Background Art

[0002] With the development of the electronics industry, there is an increasing demand for semiconductor packages with higher integration. To this end, a semiconductor package with a multi-stack structure has been proposed. In a semiconductor package with a multi-stack structure, for example, a first chip stack including a plurality of first-type chips may be disposed on a package substrate, and a second chip stack including a plurality of second-type chips may be disposed on the first chip stack, so that the semiconductor package may include various chips for performing specific or predetermined functions with higher integration within a limited volume.

[0003] However, since the materials and / or sizes of various chips and / or the composition and / or construction of different stacks including different chips may be different, semiconductor packages with multi-stack structures may be susceptible to reliability issues caused by stress (such as internal stress or external stress). Summary of the invention

[0004] The present disclosure provides a semiconductor package with improved reliability.

[0005] According to one aspect of the present disclosure, a semiconductor package is provided, which has a central area and a peripheral area around the central area in a plan view, and the semiconductor package includes: a packaging substrate; a first chip stack located on the packaging substrate in the central area and the peripheral area and electrically connected to the packaging substrate; a second chip stack located on the first chip stack in the peripheral area, the second chip stack including a lower second chip and an upper second chip on the lower second chip, the upper second chip being farther away from the central area than the lower second chip; an interposer on the first chip stack and at least in the central area, the interposer including a conductive path electrically connected to the packaging substrate; an encapsulation layer covering the first chip stack and the second chip stack on the packaging substrate; and an external connection terminal below the packaging substrate and electrically connected to the packaging substrate, wherein the second chip stack and the interposer are electrically connected to each other on a side close to the central area.

[0006] In an embodiment, the lower second chip may have a passive surface facing the first chip stack and an active surface facing the upper second chip, a portion of the active surface of the lower second chip close to the center area may be exposed by the upper second chip, and a chip pad of the lower second chip may be arranged on the portion of the active surface of the lower second chip.

[0007] In an embodiment, the upper second chip may extend beyond the lower second chip in a direction away from the central region.

[0008] In an embodiment, the semiconductor package may further include an upper lead structure, the upper lead structure including an upper interconnection lead and an upper connecting lead, wherein the upper interconnection lead can electrically connect the chip pad of the upper second chip and the chip pad of the lower second chip, and the upper connecting lead can electrically connect the chip pad of the lower second chip to the conductive path of the interposer.

[0009] In an embodiment, the interposer may be located on the first chip stack in the central region and the peripheral region, and may be partially located between the second chip stack and the first chip stack.

[0010] In an embodiment, the interposer may include a base layer on the first chip stack and a redistribution layer on the base layer, the redistribution layer may include at least a portion of the conductive path of the interposer, and the base layer may include a semiconductor material.

[0011] In an embodiment, the semiconductor package may further include an external lead structure including at least one external connection lead, wherein the conductive path of the interposer may be electrically connected to the package substrate through the at least one external connection lead.

[0012] In an embodiment, the first chip stack may include a plurality of first chips stacked in a vertical direction, each of the plurality of first chips may have a passive surface facing the package substrate and an active surface opposite to the passive surface, and the semiconductor package may also include a lower lead structure including a plurality of lower connecting leads, which may electrically connect the plurality of first chips to the package substrate.

[0013] In an embodiment, the first chip stack may include a plurality of first chips stacked in a vertical direction and a plurality of first connection structures respectively between the plurality of first chips, each of the plurality of first chips may include a through via formed therein, the through vias of adjacent first chips among the plurality of first chips may be connected to each other through the first connection structures between the adjacent first chips, the through vias of the topmost first chip among the plurality of first chips may also be connected to the conductive path of the interposer, and the through vias of the bottommost first chip among the plurality of first chips may also be electrically connected to the packaging substrate.

[0014] In an embodiment, the semiconductor package may further include at least one third chip stack, the at least one third chip stack may be located on the first chip stack in the peripheral region, the at least one third chip stack may include a lower third chip and an upper third chip on the lower third chip, the upper third chip may be farther from the central region than the lower third chip. The at least one third chip stack and the second chip stack may be spaced apart from each other so that at least a portion of the central region may be between the at least one third chip stack and the second chip stack. The at least one third chip stack may be electrically connected to the interposer on a side close to the central region. The encapsulation layer may also cover the at least one third chip stack.

[0015] In an embodiment, when the semiconductor package undergoes a strength test, the force applied from outside the semiconductor package for the strength test may produce a stress concentration phenomenon in the central area of ​​the semiconductor package, and the strength test may include or may be a three-point bending test, a four-point bending test, or a ball-and-ring test.

[0016] In an embodiment, in the plan view, a geometric center of the semiconductor package may be located in the central region.

[0017] In an embodiment, in the plan view, the peripheral area may be at both sides of the central area or completely surround the central area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects and features will become more apparent from the following description of example embodiments with reference to the accompanying drawings.

[0019] Figure 1 is a schematic cross-sectional view showing a semiconductor package.

[0020] FIG. 2A to FIG. 2C is a schematic diagram illustrating a strength testing method for a semiconductor package according to example embodiments.

[0021] Figure 3 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0022] Figure 4 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0023] Figure 5 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0024] Figure 6 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0025] Fig. 7A and Figure 7B is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0026] Example embodiments will be described more fully with reference to the accompanying drawings showing example embodiments. The embodiments described herein are provided as examples, and therefore, the present disclosure is not limited thereto, but may be implemented in various forms. Each embodiment provided in the following description does not exclude association with another example or another embodiment that is also provided herein or not provided herein but is consistent with the present disclosure. In the accompanying drawings, for clarity, various elements, components, layers, regions, etc. may not be drawn to scale. In the accompanying drawings, the same or similar reference numerals represent the same or similar components.

[0027] For descriptive purposes, spatially relative terms such as "below", "lower", "bottom", "above", "upper", "top", etc. may be used herein to describe the relationship of one element to another (or other) elements as shown in the accompanying drawings. It will be understood that in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are also intended to include different orientations of the device in use, operation and / or manufacture. For example, if the device in the accompanying drawings is turned over, the element described as "below" other elements or features will subsequently be positioned as "above" the other elements or features. Therefore, the exemplary term "below" can include both above and below orientations. In addition, the device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0028] Figure 1 is a schematic cross-sectional view showing a semiconductor package. Specifically, Figure 1 A schematic cross-sectional view of a related art semiconductor package is shown.

[0029] Reference Figure 1 The semiconductor package 1000 may include a package substrate 1100 , a first chip stack 1200 , a support layer SPL, a second chip stack 1300 , an encapsulation layer 1700 , and external connection terminals 1800 . In addition, the semiconductor package 1000 may further include a lower lead structure 1400 and an upper lead structure 1500 .

[0030] The first chip stack 1200 may be on the package substrate 1100. The first chip stack 1200 may include a plurality of first chips 1200a, 1200b, 1200c, and 1200d stacked in a vertical direction. The plurality of first chips 1200a, 1200b, 1200c, and 1200d may be stacked on top of each other in the vertical direction. As used herein, the term "vertical direction" may be a direction perpendicular to the upper surface and / or lower surface of the package substrate 1100.

[0031] The first chip stack 1200 may be electrically connected to the package substrate 1100 through a lower lead structure 1400. Specifically, the lower lead structure 1400 may include a plurality of lower connection leads 1400a, 1400b, 1400c, and 1400d. The plurality of lower connection leads 1400a, 1400b, 1400c, and 1400d may electrically connect the plurality of first chips 1200a, 1200b, 1200c, and 1200d to the package substrate 1100, respectively.

[0032] The supporting layer SPL may be on the first chip stack 1200. For example, the supporting layer SPL may be disposed on the uppermost first chip 1200d. The supporting layer SPL may serve as a supporting layer.

[0033] The second chip stack 1300 may be on the support layer SPL. The second chip stack 1300 may include a plurality of second chips 1300a, 1300b, 1300c, and 1300d stacked in a vertical direction. Among the plurality of second chips 1300a, 1300b, 1300c, and 1300d, the lower second chip (also referred to as the "lower second chip") may be arranged to be closer to the center of the semiconductor package 1000 than the upper second chip (also referred to as the "upper second chip") in the horizontal direction. For example, among the plurality of second chips 1300a, 1300b, 1300c, and 1300d, the lower second chip and the upper second chip may be partially stacked in the vertical direction, so that a portion of the upper surface of the lower second chip away from the center of the semiconductor package 1000 is exposed by the upper second chip, and a portion of the lower surface of the upper second chip close to the center of the semiconductor package 1000 is exposed by the lower second chip. In other words, the plurality of second chips 1300a, 1300b, 1300c, and 1300d may be stacked obliquely toward the center of the semiconductor package 1000. In this case, a chip pad (not shown) of each of the plurality of second chips 1300a, 1300b, 1300c, and 1300d may be disposed on its exposed upper surface. As used herein, the term "horizontal direction" may refer to a direction parallel to the upper or lower surface of the package substrate 1100.

[0034] The second chip stack 1300 can be electrically connected to the package substrate 1100 through the upper lead structure 1500. Specifically, the upper lead structure 1500 may include an upper interconnection lead 1500a and an upper connection lead 1500b. The upper interconnection lead 1500a can electrically connect the upper second chip and the lower second chip among the plurality of second chips 1300a, 1300b, 1300c and 1300d to each other. The upper connection lead 1500b can electrically connect the second chip stack 1300 (for example, the lowermost second chip 1300d) to the package substrate 1100. That is, the second chip stack 1300 (including the plurality of second chips 1300a, 1300b, 1300c and 1300d) can be electrically connected to the package substrate 1100 using a wire bonding method.

[0035] Since the plurality of second chips 1300a, 1300b, 1300c, and 1300d are stacked obliquely toward the center of the semiconductor package 1000, chip pads of the plurality of second chips 1300a, 1300b, 1300c, and 1300d may be disposed in a region adjacent to an edge of the package substrate 1100. In this manner, the plurality of second chips 1300a, 1300b, 1300c, and 1300d may be electrically connected to the package substrate 1100 through the upper lead structure 1500 using a wire bonding method.

[0036] The encapsulation layer 1700 may cover the first chip stack 1200 and the second chip stack 1300 on the package substrate 1100. For example, the encapsulation layer 1700 may cover the exposed surface (e.g., upper surface, side surface, and / or lower surface) of each of the first chip stack 1200 (e.g., first chips 1200a, 1200b, 1200c, and 1200d) and the second chip stack 1300 (e.g., second chips 1300a, 1300b, 1300c, and 1300d), and cover the exposed upper surface of the package substrate 1100. In addition, the lower lead structure 1400 and the upper lead structure 1500 may be buried in the encapsulation layer 1700. The encapsulation layer 1700 may be used to protect components disposed on the package substrate 1100.

[0037] The external connection terminal 1800 may be below the package substrate 1100. For example, the external connection terminal 1800 may be disposed on the lower surface of the package substrate 1100. The external connection terminal 1800 may be electrically connected to the package substrate 1100. The external connection terminal 1800 may be electrically connected to a component (e.g., the first chip stack 1200 and / or the second chip stack 1300) disposed above the package substrate 1100 through a conductive path of the package substrate 1100. The external connection terminal 1800 may be a connection member for electrically connecting the semiconductor package 1000 to an external component (e.g., an external circuit board).

[0038] Generally, in order to ensure the reliability (e.g., mechanical reliability) of a semiconductor package in actual use, a strength test may be performed on the manufactured semiconductor package with a designed structure to determine whether the semiconductor package has a mechanical strength that meets the use requirements. When a test sample of a semiconductor package with a designed structure is determined to have a mechanical strength that meets the use requirements through a strength test, it can be determined that the reliability (e.g., mechanical reliability) of the semiconductor package with the designed structure can meet the requirements in actual use.

[0039] Hereinafter, an example of a method for testing the mechanical strength of a semiconductor package according to example embodiments will be described with reference to the accompanying drawings.

[0040] FIG. 2A to FIG. 2C is a schematic diagram showing a strength test of a semiconductor package according to an example embodiment. Specifically, Figure 2A The three-point bending test method for testing the mechanical strength of a semiconductor package is schematically shown. Figure 2B A Four-Point Bending Test method for testing the mechanical strength of a semiconductor package is schematically shown, and Figure 2CThe figure schematically shows a Ball on Ring Test method for testing the mechanical strength of a semiconductor package.

[0041] Reference Figure 2A , the three-point bending test method can be used to test the mechanical strength of the semiconductor package PKG. Figure 2A As shown in part (a) of FIG. 1 , the semiconductor package PKG can be placed flat on two supporting rollers SP extending parallel to each other and spaced a predetermined distance apart, and then a force-applying roller IP extending parallel to the supporting rollers SP applies a pressure F (i.e., a test force) to the semiconductor package PKG from above to test the mechanical strength (e.g., bending strength or deflection strength) of the semiconductor package PKG. Based on the test data, the mechanical strength (e.g., bending strength or deflection strength) of the semiconductor package PKG can be calculated by the following equation 1:

[0042] [Equation 1]

[0043]

[0044] In Equation 1, δ represents the bending strength or flexural strength (e.g., tensile stress) of the semiconductor package PKG, b represents the width of the semiconductor package PKG (unit: mm), h represents the thickness of the semiconductor package PKG (unit: mm), L represents the span between two supporting rollers SP (unit: mm), and F represents the test force applied to the semiconductor package PKG by the force roller IP (unit: gf); wherein the width of the semiconductor package PKG may be the width in a direction parallel to the supporting rollers SP and / or the force rollers IP.

[0045] When the force roller IP applies force to the semiconductor package PKG placed on the support roller SP, the semiconductor package PKG may have a stress concentration area (i.e., an external stress concentration area) caused by the external force. Due to the propagation characteristics of the force, the external stress concentration area of ​​the semiconductor package PKG may be distributed in the portion of the semiconductor package PKG that contacts the force roller IP and the portion adjacent to the force roller IP.

[0046] Figure 2A Part (b) in FIG. 1 shows a plan view of a semiconductor package PKG undergoing a strength test as viewed from above. Figure 2A As shown in part (b) of FIG. 1 , the external stress concentration area of ​​the semiconductor package PKG may be located at the center of the semiconductor package PKG and may therefore be referred to as a “central area”. Figure 2AAs shown in part (b) of FIG. 1 , the external stress concentration region of the semiconductor package PKG may have a substantially rectangular shape extending parallel to the force application roller IP, and the remaining area (i.e., “peripheral area”) of the semiconductor package PKG other than the external stress concentration region may be located around (e.g., on both sides) the external stress concentration region of the semiconductor package PKG. In addition, as Figure 2A As shown in part (b) of FIG. 1 , the force roller IP may pass through the external stress concentration area of ​​the semiconductor package PKG. When the semiconductor package PKG undergoes a three-point bending test, the force applied from the outside of the semiconductor package PKG for the three-point bending test may generate a stress concentration phenomenon in the central area of ​​the semiconductor package PKG.

[0047] Reference Figure 2B , the four-point bending test method can be used to test the mechanical strength of the semiconductor package PKG. Figure 2B As shown in part (a) of FIG. 1 , the semiconductor package PKG can be placed flat on two supporting rollers SP extending parallel to each other and spaced a predetermined distance apart, and then a pressure F (i.e., a test force) is applied to the semiconductor package PKG from above by two force-applying rollers IP extending parallel to each other and parallel to the supporting rollers SP to test the mechanical strength (e.g., bending strength or deflection strength) of the semiconductor package PKG. Based on the test data, the mechanical strength (e.g., bending strength or deflection strength) of the semiconductor package PKG can be calculated by the following equation 2:

[0048] [Equation 2]

[0049]

[0050] In Equation 2, δ represents the bending strength or flexural strength (e.g., tensile stress) of the semiconductor package PKG, b represents the width of the semiconductor package PKG (unit: mm), h represents the thickness of the semiconductor package PKG (unit: mm), L1 represents the span between two force rollers IP (unit: mm), L2 represents the span between two supporting rollers SP (unit: mm), and F represents the force jointly applied to the semiconductor package PKG by the two force rollers IP (unit: N); wherein the width of the semiconductor package PKG may be the width in a direction parallel to the supporting rollers SP and / or the force rollers IP.

[0051] When the force roller IP applies force to the semiconductor package PKG placed on the support roller SP, the semiconductor package PKG may have a stress concentration area (i.e., an external stress concentration area) caused by the external force. Due to the propagation characteristics of the force, the external stress concentration area of ​​the semiconductor package PKG may be distributed in the portion of the semiconductor package PKG that contacts the force roller IP and the portion adjacent to the force roller IP.

[0052] Figure 2B Part (b) in FIG. 1 shows a plan view of a semiconductor package PKG undergoing a strength test as viewed from above. Figure 2B As shown in part (b) of FIG. 1 , the external stress concentration area of ​​the semiconductor package PKG may be located at the center of the semiconductor package PKG and may therefore be referred to as a “central area”. Figure 2B As shown in part (b) of FIG. 1 , the external stress concentration region of the semiconductor package PKG may have a substantially rectangular shape extending parallel to the force application roller IP, and the remaining area (i.e., “peripheral area”) of the semiconductor package PKG other than the external stress concentration region may be located around (e.g., on both sides) the external stress concentration region of the semiconductor package PKG. In addition, as Figure 2B As shown in part (b) of FIG. 1 , each of the two force rollers IP may pass through the external stress concentration area of ​​the semiconductor package PKG. When the semiconductor package PKG undergoes a four-point bending test, the force applied from the outside of the semiconductor package PKG for the four-point bending test may generate a stress concentration phenomenon in the central area of ​​the semiconductor package PKG.

[0053] Reference Figure 2C , the ball ring test method can be used to test the mechanical strength of the semiconductor package PKG. Figure 2C As shown in part (a) of FIG. 1 , the semiconductor package PKG can be placed flat on the annular ring of the support ring SR, and then a pressure P (i.e., a test force) is applied to the semiconductor package PKG from above by a spherical indenter IB to test the mechanical strength (e.g., bending strength or deflection strength) of the semiconductor package PKG. Based on the test data, the mechanical strength (e.g., bending strength or deflection strength) of the semiconductor package PKG can be calculated by the following equation 3:

[0054] [Equation 3]

[0055]

[0056] In Equation 3, σ maxrepresents the bending strength or deflection strength (e.g., maximum compressive stress) of the semiconductor package PKG, R represents half of the size (e.g., width) of the semiconductor package PKG (unit: mm), t represents the thickness of the semiconductor package PKG (unit: mm), a represents the radius of the annular ring of the support ring SR (unit: mm), P represents the force applied to the semiconductor package PKG by the spherical indenter IB (unit: N), υ represents the Poisson's ratio of the semiconductor package PKG, and z represents the radius of the area where the spherical indenter IB contacts the semiconductor package PKG (unit: mm). In an embodiment, the Poisson's ratio υ of the semiconductor package PKG can be determined by any suitable method known for measuring the Poisson's ratio of a material or object. As used herein, the value (approximate value) of the Poisson's ratio of the semiconductor package PKG can be (e.g., approximately) taken as 0.3. In an embodiment, the radius z of the area where the spherical indenter IB contacts the semiconductor package PKG can be calculated by the following equation 3-1.

[0057] [Equation 3-1]

[0058]

[0059] In Equation 3-1, P and υ are the same as those defined in Equation 3 above, E represents the elastic modulus of the semiconductor package PKG (unit: GPa), r b Indicates the spherical curvature radius of the spherical indenter IB (unit: mm), υ b The Poisson's ratio of the spherical indenter IB, E b represents the elastic modulus of the spherical indenter IB (unit: GPa). In the embodiment, the elastic modulus E of the semiconductor package PKG and the elastic modulus E of the spherical indenter IB are b Each can be determined by any suitable method for measuring the elastic modulus of a material or object. In an embodiment, the Poisson's ratio v of the spherical indenter IB b The Poisson's ratio of a material or object may be determined by any suitable method known to measure the Poisson's ratio of the material or object. As used herein, the value of the Poisson's ratio of the spherical indenter IB may be (eg, approximately) taken as 0.3.

[0060] When the spherical indenter IB applies force to the semiconductor package PKG placed on the support ring SR, the semiconductor package PKG may have a stress concentration area (i.e., an external stress concentration area) caused by the external force. Due to the propagation characteristics of the force, the external stress concentration area of ​​the semiconductor package PKG may be distributed in the portion of the semiconductor package PKG that contacts the spherical indenter IB and the portion adjacent to the force-applying roller IP.

[0061] Figure 2C Part (b) in FIG. 1 shows a plan view of a semiconductor package PKG undergoing a strength test as viewed from above. Figure 2C As shown in part (b) of FIG. 1 , the external stress concentration area of ​​the semiconductor package PKG may be located at the center of the semiconductor package PKG and may therefore be referred to as a “central area”. Figure 2C As shown in part (b) of FIG. 1 , the external stress concentration region of the semiconductor package PKG may have a substantially circular or elliptical shape extending outward from the region in contact with the spherical indenter IB, and the remaining region of the semiconductor package PKG other than the external stress concentration region (i.e., the “peripheral region”) may be located around the external stress concentration region of the semiconductor package PKG (e.g., completely surrounding the external stress concentration region of the semiconductor package PKG). In addition, as Figure 2C As shown in part (b) of FIG. 1 , the spherical indenter IB can be positioned in the external stress concentration area of ​​the semiconductor package PKG and is completely surrounded by the external stress concentration area of ​​the semiconductor package PKG. When the semiconductor package PKG undergoes a ball ring test, the force applied from the outside of the semiconductor package PKG for the ball ring test can generate a stress concentration phenomenon in the central area of ​​the semiconductor package PKG.

[0062] In the present disclosure, since the three-point bending test method, the four-point bending test method and the ball-and-ring test method as described above are bending or deflection strength test methods known in the art, other details of these methods are omitted herein.

[0063] Optionally, since the semiconductor package PKG can generally have a regular planar shape, in the strength test of the semiconductor package PKG, when viewed from the perspective of the plan view of the semiconductor package PKG, the force-applying member (e.g., the force-applying roller or spherical indenter) and the supporting member (e.g., the supporting roller or supporting ring) used for the test can be arranged about the geometric center of the semiconductor package PKG (e.g., partially overlapping with the geometric center of the semiconductor package PKG, and / or symmetrical with respect to the geometric center of the semiconductor package PKG). With such an arrangement, the test efficiency can be improved while ensuring the test accuracy. In addition, under such an arrangement, in the plan view of the semiconductor package PKG, the geometric center of the semiconductor package PKG can be located in the external stress concentration area (i.e., the central area) of the semiconductor package PKG.

[0064] and FIG. 2A to FIG. 2C Let’s refer to it again Figure 1As described above, in the semiconductor package 1000, the plurality of second chips 1300a, 1300b, 1300c, and 1300d may be stacked obliquely toward the center of the semiconductor package 1000. That is, the plurality of second chips 1300a, 1300b, 1300c, and 1300d may be stacked obliquely toward the external stress concentration region (i.e., the central region) of the semiconductor package 1000. In this case, since the upper second chip among the plurality of second chips 1300a, 1300b, 1300c, and 1300d has a portion extending beyond the lower second chip toward the central region of the semiconductor package 1000, when stress concentration caused by an external force (e.g., a force applied for testing in a strength test) occurs in the external stress concentration region of the semiconductor package 1000, the portion of the upper second chip extending beyond the lower second chip may be affected by the stress and sag, thereby causing cracks to occur in the semiconductor package 1000. As a result, the semiconductor package 1000 may have degraded reliability.

[0065] Hereinafter, examples of a semiconductor package according to example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0066] Figure 3 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0067] Reference Figure 3 , the semiconductor package 100 according to example embodiments may have a central region CR and a peripheral region PR. The central region CR and the peripheral region PR of the semiconductor package 100 may correspond to the reference FIG. 2A to FIG. 2C The outer stress concentration area (ie, the central area) of the semiconductor package PKG described above and the remaining area (ie, the peripheral area) other than the outer stress concentration area. In other words, FIG. 2A to FIG. 2C Similar to the description, in the plan view of the semiconductor package 100, the semiconductor package 100 may have a central region CR and a peripheral region PR around the central region CR. For example, in the plan view of the semiconductor package 100, the central region CR of the semiconductor package 100 may be surrounded by the peripheral region PR of the semiconductor package 100 (with the central region CR and the peripheral region PR of the semiconductor package 100). Figure 2A and Figure 2B Refer to Figure 3 For another example, in a plan view of the semiconductor package 100, the central region CR of the semiconductor package 100 may be completely surrounded or surrounded by the peripheral region PR of the semiconductor package 100 (with Figure 2C Refer to Figure 3 ).

[0068] Reference Figure 3The semiconductor package 100 according to the embodiment may include a package substrate 110, a first chip stack 120, an interposer ICL, a second chip stack 130, an encapsulation layer 170, and external connection terminals 180. In addition, the semiconductor package 100 may further include a lower lead structure 140, an upper lead structure 150, and an outer lead structure 160.

[0069] The package substrate 110 can be used to electrically connect components disposed above it (e.g., the first chip stack 120, the interposer ICL, and / or the second chip stack 130) to components disposed below it (e.g., the external connection terminal 180). For example, the package substrate 110 can be a substrate in which a plurality of conductive paths are formed. The package substrate 110 can also be used to support components disposed above it. For example, the package substrate 110 can be a rigid substrate. The package substrate 110 can be a printed circuit board, a ceramic substrate, a glass substrate, or a semiconductor substrate, but is not limited thereto.

[0070] The package substrate 110 may include a substrate pad 110P. For example, the substrate pad 110P may be disposed on the upper surface of the package substrate 110, or exposed from the upper surface of the package substrate 110. The substrate pad 110P may be used to electrically connect to a component (e.g., the first chip stack 120, the second chip stack 130, and / or the interposer ICL) disposed above the package substrate 110. The substrate pad 110P may be electrically connected to a corresponding conductive path among a plurality of conductive paths in the package substrate 110. In an embodiment, the substrate pad 110P may include a conductive material such as a metal and / or a metal nitride.

[0071] The first chip stack 120 may be on the package substrate 110 and may be electrically connected to the package substrate 110. The first chip stack 120 may be arranged on the package substrate 110 in both the central region CR and the peripheral region PR of the semiconductor package 100. The first chip stack 120 may include a plurality of first chips 120a, 120b, 120c, and 120d stacked in a vertical direction. For example, each of the plurality of first chips 120a, 120b, 120c, and 120d may be arranged in both the central region CR and the peripheral region PR of the semiconductor package 100. For example, the plurality of first chips 120a, 120b, 120c, and 120d may be stacked on each other in a vertical direction. As used herein, the term "vertical direction" may be a direction perpendicular to the upper surface and / or lower surface of the package substrate 110.

[0072] In an embodiment, each of the plurality of first chips 120a, 120b, 120c, and 120d may be a volatile memory chip. For example, each of the plurality of first chips 120a, 120b, 120c, and 120d may be a dynamic random access memory (DRAM) chip, but is not limited thereto. Figure 3 1 and 2 show that the first chip stack 120 includes four first chips 120a, 120b, 120c, and 120d, but example embodiments are not limited thereto. For example, the first chip stack 120 may include two, three, or five or more first chips that are stacked.

[0073] like Figure 3 As shown in , a plurality of first adhesive members AM1 may be respectively disposed on the lower surfaces of the plurality of first chips 120a, 120b, 120c, and 120d to attach and fix the plurality of first chips 120a, 120b, 120c, and 120d, respectively. In an embodiment, the first adhesive member AM1 may be a die attach film, but is not limited thereto. For example, the first adhesive member AM1 may be any suitable adhesive member for attaching and fixing a semiconductor chip (e.g., a semiconductor die).

[0074] exist Figure 3 In the example shown in FIG. 1 , among the plurality of first chips 120 a, 120 b, 120 c, and 120 d, the lower first chip (also referred to as the lower first chip) may be partially exposed by the upper first chip (also referred to as the upper first chip). For example, each of the plurality of first chips 120 a, 120 b, 120 c, and 120 d may have an inactive surface (at the bottom) facing the package substrate 110. Figure 3 middle, lower surface) and the active surface opposite to the passive surface (in Figure 3 A portion of the active surface of each of the plurality of first chips 120a, 120b, 120c, and 120d may be exposed. A chip pad (not shown) of each of the plurality of first chips 120a, 120b, 120c, and 120d may be disposed at the exposed portion of the corresponding active surface for electrical connection with the outside.

[0075] The first chip stack 120 may be electrically connected to the package substrate 110 through a lower lead structure 140. The lower lead structure 140 may include a plurality of lower connection leads 140a, 140b, 140c, and 140d. The plurality of lower connection leads 140a, 140b, 140c, and 140d may electrically connect the plurality of first chips 120a, 120b, 120c, and 120d to the package substrate 110, respectively. For example, the plurality of lower connection leads 140a, 140b, 140c, and 140d may be connected between chip pads of the plurality of first chips 120a, 120b, 120c, and 120d and a substrate pad 110P of the package substrate 110, respectively.

[0076] In an embodiment, each of the plurality of lower connection leads 140a, 140b, 140c, and 140d may include a conductive material, such as a metal such as gold or aluminum. Although not shown, the lower lead structure 140 may further include an insulating layer or a passivation layer covering the exposed surfaces of the plurality of lower connection leads 140a, 140b, 140c, and 140d, but is not limited thereto. In addition, the number and configuration of the lower connection leads included in the lower lead structure 140 are not limited to Figure 3 The number and configuration are not shown in FIG. 1 , but may be variously changed according to the number of first chips included in the first chip stack 120 and connection requirements.

[0077] The interposer ICL may be on the first chip stack 120. For example, the interposer ICL may be disposed on the uppermost first chip 120d. For example, the interposer ICL may be attached and fixed to the first chip 120d by a second adhesive member AM2 disposed on its lower surface. In an embodiment, the second adhesive member AM2 may be a die attach film, but is not limited thereto. For example, the second adhesive member AM2 may be any suitable adhesive member.

[0078] exist Figure 3 In the semiconductor package 100 shown in FIG. 1 , an interposer ICL may be disposed on the first chip stack 120 (eg, the uppermost first chip 120 d ) in the central region CR and the peripheral region PR of the semiconductor package 100 . The interposer ICL may be used as a support layer and an interconnection layer. Figure 3 In the example shown in , the interposer ICL may include a rigid interposer substrate in which a conductive path is formed. For example, the interposer substrate may be a glass substrate, a ceramic substrate, and / or a lead frame.

[0079] The interposer ICL may be electrically connected to the package substrate 110 through an external lead structure 160. The external lead structure 160 may include at least one external lead. The external leads of the external lead structure 160 may be connected between a conductive path (not shown) of the interposer ICL and a corresponding base pad 110P among base pads of the package substrate 110 (for example, at an edge portion of the interposer ICL) to electrically connect the interposer ICL to the package substrate 110. In an embodiment, the external leads of the external lead structure 160 may include a conductive material, such as a metal such as gold or aluminum. Although not shown, the external lead structure 160 may also include an insulating layer or a passivation layer covering the exposed surface of the external lead, but is not limited thereto. In addition, the number and configuration of the external leads of the external lead structure 160 are not limited to Figure 3 The number and configuration are not shown in FIG. 1 , but may be variously changed according to electrical connection requirements of the second chip stack 130 to be described below.

[0080] The second chip stack 130 may be on the first chip stack 120 (eg, the uppermost first chip 120 d ). For example, the second chip stack 130 may be disposed on the first chip stack 120 in the peripheral region PR of the semiconductor package 100 .

[0081] exist Figure 3 In the example shown in , the second chip stack 130 may be on the interposer ICL. For example, the second chip stack 130 may be disposed on the interposer ICL in the peripheral region PR of the semiconductor package 100. The second chip stack 130 may not be disposed in the central region CR of the semiconductor package 100. The second chip stack 130 may include a plurality of second chips 130a, 130b, 130c, and 130d stacked in a vertical direction. For example, each of the plurality of second chips 130a, 130b, 130c, and 130d may be disposed in the peripheral region PR of the semiconductor package 100, but not in the central region CR of the semiconductor package 100. In an embodiment, each of the plurality of second chips 130a, 130b, 130c, and 130d may be a nonvolatile memory chip. For example, each of the plurality of second chips 130a, 130b, 130c, and 130d may be a NAND memory chip, but is not limited thereto. In addition, although in Figure 3 1 and 2. It is shown in FIG. 2 that the second chip stack 130 includes four second chips 130a, 130b, 130c, and 130d, but example embodiments are not limited thereto. For example, the second chip stack 130 may include two, three, or five or more second chips that are stacked.

[0082] Among the plurality of second chips 130a, 130b, 130c, and 130d, the lower second chip (also referred to as a "lower second chip") may be disposed (e.g., in the horizontal direction) farther from the center region CR of the semiconductor package 100 than the upper second chip (also referred to as an "upper second chip"). For example, among the plurality of second chips 130a, 130b, 130c, and 130d, the lower second chip and the upper second chip may be partially overlapped in the vertical direction, so that a portion of an upper surface (e.g., an active surface) of the lower second chip close to the center region CR of the semiconductor package 100 in the horizontal direction is exposed by the upper second chip, and a portion of a lower surface (e.g., an inactive surface) of the upper second chip away from the center region CR of the semiconductor package 100 in the horizontal direction is exposed by the lower second chip. In other words, the plurality of second chips 130a, 130b, 130c, and 130d may be stacked obliquely away from the center region CR of the semiconductor package 100. In this case, a chip pad (not shown) of each of the plurality of second chips 130a, 130b, 130c, and 130d may be disposed on a portion (e.g., an exposed portion) of an upper surface (e.g., an active surface) thereof adjacent to the center region CR of the semiconductor package 100 in the horizontal direction. Meanwhile, a portion of an upper second chip among the plurality of second chips 130a, 130b, 130c, and 130d extending beyond a lower second chip in the horizontal direction may be located at a side of the second chip stack 130 that is away from the center region CR of the semiconductor package 100 in the horizontal direction. As used herein, the term “horizontal direction” may refer to a direction parallel to an upper surface or a lower surface of the package substrate 110.

[0083] like Figure 3 As shown in , a plurality of third adhesive members AM3 may be respectively disposed on the lower surfaces of the plurality of second chips 130a, 130b, 130c, and 130d to attach and fix the plurality of second chips 130a, 130b, 130c, and 130d, respectively. In an embodiment, the third adhesive member AM3 may be a die attach film, but is not limited thereto. For example, the third adhesive member AM3 may be any suitable adhesive member for attaching and fixing a semiconductor chip (e.g., a semiconductor die).

[0084] In the semiconductor package 100, the second chip stack 130 may be electrically connected to the interposer ICL through the upper lead structure 150. Figure 3As shown in , the second chip stack 130 and the interposer ICL may be electrically connected to each other at a side close to the center region CR of the semiconductor package 100. For example, the upper lead structure 150 may be relatively closer to the center region CR of the semiconductor package 100 than the second chip stack 130. For example, the upper lead structure 150 may be electrically connected to the interposer ICL in the center region CR of the semiconductor package 100, and may be electrically connected to the second chip stack 130 in the peripheral region PR of the semiconductor package 100, but is not limited thereto.

[0085] The upper lead structure 150 may include an upper interconnection lead 150a and an upper connection lead 150b. Figure 3 As shown in , the upper interconnection lead 150a can electrically connect the upper second chip and the lower second chip among the plurality of second chips 130a, 130b, 130c, and 130d to each other. For example, the upper interconnection lead 150a can be connected between chip pads (not shown) of adjacent second chips among the plurality of second chips 130a, 130b, 130c, and 130d. Figure 3 As shown in , the upper connection lead 150b can electrically connect the second chip stack 130 (e.g., the lowermost second chip 130d) to the interposer ICL. For example, the upper connection lead 150b can be connected between the die pad (not shown) of the second chip 130d and the conductive path (not shown) of the interposer ICL. In this way, even if the chip pads of the plurality of second chips 130a, 130b, 130c, and 130d are arranged in an area adjacent to the center of the package substrate 110, the second chip stack 130 (including the second chips 130a, 130b, 130c, and 130d) can be electrically connected to the package substrate 110 via the upper lead structure 150 and the interposer ICL. That is, in the semiconductor package 100, the second chip stack 130 (including the plurality of second chips 130a, 130b, 130c, and 130d) can be electrically connected to the package substrate 110 using a wire bonding method without being restricted (e.g., design restrictions and / or manufacturing restrictions due to the structure).

[0086] In an embodiment, each of the upper interconnection leads 150a and the upper connection leads 150b of the upper lead structure 150 may include a conductive material, such as a metal such as gold or aluminum. Although not shown, the upper lead structure 150 may further include an insulating layer or a passivation layer covering the exposed surfaces of the upper interconnection leads 150a and the upper connection leads 150b, but is not limited thereto. In addition, the number and configuration of the upper interconnection leads and / or the upper connection leads included in the upper lead structure 150 are not limited to Figure 3The number and configuration shown in the figure may be variously changed according to the number and connection requirements of the second chips included in the second chip stack 130. For example, one or more second chips included in the second chip stack 130 may be electrically connected to the interposer ICL through the upper connection leads of the upper lead structure 150, and the remaining second chips may be electrically connected to the one or more second chips through the upper interconnection leads.

[0087] In the semiconductor package 100, the encapsulation layer 170 may be used to protect components disposed on the package substrate 110. In an embodiment, the encapsulation layer 170 may include a molding material, such as an epoxy molding compound. Figure 3 As shown in , the encapsulation layer 170 may cover the first chip stack 120 and the second chip stack 130 on the package substrate 110. For example, the encapsulation layer 170 may cover the exposed surface (e.g., upper surface, side surface and / or lower surface) of each of the first chip stack 120 (e.g., first chips 120a, 120b, 120c and 120d) and the second chip stack 130 (e.g., second chips 130a, 130b, 130c and 130d), and cover the exposed upper surface of the package substrate 110. In addition, the encapsulation layer 170 may also cover the exposed interposer ICL. In addition, the lower lead structure 140 and the upper lead structure 150 may be buried in the encapsulation layer 170. That is, the encapsulation layer 170 may provide the upper surface of the semiconductor package 100 and fill the empty space between the upper surface of the semiconductor package 100 and the upper surface of the package substrate 110.

[0088] In the semiconductor package 100, the external connection terminals 180 may be connection members for electrically connecting the semiconductor package 100 to an external component (eg, an external circuit board). Figure 3 As shown in , the external connection terminal 180 may be below the package substrate 110. For example, the external connection terminal 180 may be disposed on the lower surface of the package substrate 110. The external connection terminal 180 may be electrically connected to the package substrate 110. The external connection terminal 180 may be electrically connected to a component (e.g., the first chip stack 120 and / or the second chip stack 130) disposed above the package substrate 110 through a conductive path (not shown) of the package substrate 110. In addition, the external connection terminal 180 may be provided in plurality, and according to the communication / connection specification between the semiconductor package 100 and an external component (e.g., an external circuit board), a plurality of external connection terminals 180 may be provided in a suitable planar layout. In an embodiment, the external connection terminal 180 may be a conductive ball or a conductive bump. In an embodiment, the external connection terminal 180 may include a conductive material such as a metal or an alloy.

[0089] Alternatively, if Figure 3As shown in , an additional chipset 190 may be further disposed between the first chip stack 120 and the package substrate 110. In an embodiment, the additional chipset 190 may include a plurality of additional chips 190a and 190b spaced apart from each other in a horizontal direction. Figure 3 In the example shown in FIG. 1 , the plurality of additional chips 190a and 190b may include a first additional chip 190a and a second additional chip 190b. The first additional chip 190a and the second additional chip 190b may be attached to the package substrate 110 by a fourth adhesive member AM4. In an embodiment, the fourth adhesive member AM4 may be a pressure-sensitive adhesive film or a die attach film, but is not limited thereto.

[0090] In an embodiment, the first additional chip 190a may be a logic chip. For example, the first additional chip 190a may be a central processing unit (CPU), a graphics processing unit (GPU), an arithmetic logic unit (APU), an application processor (AP), or a neural network processor (NPU), but is not limited thereto.

[0091] like Figure 3 As shown in , the first additional chip 190a can be electrically connected to the package substrate 110 through the additional lead 191. For example, the additional lead 191 can be connected between a chip pad (not shown) of the first additional chip 190a and a corresponding substrate pad among the substrate pads 110P of the package substrate 110. In an embodiment, the additional lead 191 may include a conductive material, such as a metal such as gold or aluminum. Although not shown, an additional insulating layer or passivation layer may cover the exposed surface of the additional lead 191, but is not limited thereto. In addition, the number and configuration of the additional leads 191 are not limited to Figure 3 The number and configuration are not shown in FIG. 1 , but may be variously changed according to connection requirements included in the first additional chip 190 a.

[0092] In an embodiment, the second additional chip 190b may be a dummy chip that plays a supporting role. As used herein, a dummy chip may be a semiconductor die having a structure substantially the same as or similar to that of a functional chip (e.g., a logic chip or a memory chip) but not performing a function, or may be a bulk wafer formed of a semiconductor material (such as, for example, a semiconductor material used in the first chip, the second chip, and / or the first additional chip as described above). However, the example of the second additional chip 190b is not limited thereto. In some other embodiments, the second additional chip 190b may also be one of the logic chips as described above. In this case, additional additional leads may be provided between a chip pad of the second additional chip 190b and a corresponding substrate pad among the substrate pads 110P of the package substrate 110 to electrically connect the second additional chip 190b to the package substrate 110.

[0093] As described above, when the semiconductor package 100 undergoes a strength test (eg, referring to FIG. 2A to FIG. 2C In any of the three-point bending test, four-point bending test, and ball ring test described in the foregoing description), even if the force applied from the outside of the semiconductor package 100 for the strength test generates a stress concentration phenomenon in the center region CR of the semiconductor package 100. However, in the semiconductor package 100 according to the example embodiment, the stress concentration phenomenon is not generated in the center region CR of the semiconductor package 100. Figure 1 Compared with the semiconductor package 1000 described above, since the second chip stack 130 can be disposed in the peripheral region PR of the semiconductor package 100 instead of being disposed in the central region CR of the semiconductor package 100, and the plurality of second chips 130a, 130b, 130c, and 130d included in the second chip stack 130 can be stacked obliquely away from the central region CR of the semiconductor package 100, in the region affected by the stress wave, the upper second chip among the second chips 130a, 130b, 130c, and 130d can be supported by the lower second chip instead of the encapsulation layer 170. Therefore, the sagging of the upper second chip among the second chips 130a, 130b, 130c, and 130d due to the external stress concentration can be suppressed or eliminated. Therefore, the stress cracks occurring in the external stress concentration region (i.e., the central region CR) of the semiconductor package 100 can be suppressed or eliminated. Therefore, the semiconductor package 100 can have improved reliability.

[0094] Figure 4 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0095] Reference Figure 4 , except that the semiconductor package 200 includes the second chip stack 130A and the third chip stack 130B, the semiconductor package 200 according to example embodiments may be similar to the reference 100 . Figure 3 The semiconductor package 100 described above is substantially the same or similar. Therefore, the same or similar reference numerals may be used to represent the semiconductor package 100 described above. Figure 3 The components described are the same or similar components, and redundant descriptions of the same or similar components may be omitted.

[0096] Reference Figure 3 , the semiconductor package 200 may have a central region CR and a peripheral region PR around the central region CR. The semiconductor package 200 may include a second chip stack 130A and a third chip stack 130B. Each of the second chip stack 130A and the third chip stack 130B may be disposed on the first chip stack 120 in the peripheral region PR of the semiconductor package 200. Figure 3In the example shown in , each of the second chip stack 130A and the third chip stack 130B may be disposed on the interposer ICL on the first chip stack 120 in the peripheral region PR of the semiconductor package 200. Each of the second chip stack 130A and the third chip stack 130B may not be disposed in the central region CR of the semiconductor package 200. For example, the second chip stack 130A and the third chip stack 130B may be disposed side by side in the horizontal direction. For example, in a plan view of the semiconductor package 200, the second chip stack 130A and the third chip stack 130B may be spaced apart from each other so that at least a portion of the central region CR of the semiconductor package 200 is located between the second chip stack 130A and the third chip stack 130B.

[0097] The second chip stack 130A may include a plurality of second chips 130aA, 130bA, 130cA, and 130dA stacked in a vertical direction. The third chip stack 130B may include a plurality of third chips 130aB, 130bB, 130cB, and 130dB stacked in a vertical direction. The plurality of second chips 130a, 130bA, 130cA, and 130dA included in the second chip stack 130A may have the same Figure 3 The configurations of the plurality of second chips 130a, 130b, 130c, and 130d described above are substantially the same. In addition, the plurality of third chips 130aB, 130bB, 130cB, and 130d included in the third chip stack 130B may correspond to the reference 130B, respectively. Figure 3 The plurality of second chips 130a, 130b, 130c and 130d described above may have the same Figure 3 The configurations of the plurality of second chips 130a, 130b, 130c and 130d described above are similar in configuration. In addition, each of the second chip stack 130A and the third chip stack 130B can be electrically connected to the interposer ICL at a side close to the center region CR of the semiconductor package 200 through the upper lead structure 150, and electrically connected to the package substrate 110 via the interposer ICL.

[0098] like Figure 4 As shown in FIG. 1 , in the second chip stack 130A, the plurality of second chips 130aA, 130bA, 130cA, and 130dA may be stacked obliquely away from the center region CR of the semiconductor package 200, and in the third chip stack 130B, the plurality of third chips 130aB, 130bB, 130cB, and 130dB may be stacked obliquely away from the center region CR of the semiconductor package 200. For example, Figure 4As shown in FIG. 1 , the plurality of second chips 130 aA, 130 bA, 130 cA, and 130 dA and the plurality of third chips 130 aB, 130 bB, 130 cB, and 130 dB may form a substantially “V” shape as a whole.

[0099] In the semiconductor package 200, since the number of chip stacks disposed on the first chip stack 120 or the interposer ICL increases, the semiconductor package 200 may have an increased degree of integration. For example, when the third chips 130aB, 130bB, 130cB, and 130dB may be non-volatile memory chips similar to the second chips 130aA, 130bA, 130cA, and 130dA, the semiconductor package 200 may have an increased degree of capacity integration (e.g., storage density). For another example, when the third chips 130aB, 130bB, 130cB, and 130dB may be other types of chips, the semiconductor package 200 may have an increased degree of functional integration (e.g., multifunctionality).

[0100] Since each of the second chip stack 130A and the third chip stack 130B can be set in the peripheral region PR of the semiconductor package 100 instead of the central region CR of the semiconductor package 100, the multiple second chips 130aA, 130bA, 130cA and 130dA included in the second chip stack 130A can be stacked obliquely away from the central region CR of the semiconductor package 100, and the third chips 130aB, 130bB, 130cB and 130dB included in the third chip stack 130B can be stacked obliquely away from the central region CR of the semiconductor package 100, so in the area affected by stress, the upper second chip among the second chips 130aA, 130bA, 130cA and 130dA can be supported by the lower second chip instead of the encapsulation layer 170, and the upper third chip among the third chips 130aB, 130bB, 130cB and 130dB can be supported by the lower third chip instead of the encapsulation layer 170. Therefore, the sagging of the upper second chip among the second chips 130aA, 130bA, 130cA, and 130dA due to external stress concentration can be suppressed or eliminated, and the sagging of the upper third chip among the third chips 130aB, 130bB, 130cB, and 130dB due to external stress concentration can be suppressed or eliminated. Therefore, stress cracks occurring in the external stress concentration area (i.e., the central region CR) of the semiconductor package 200 can be suppressed or eliminated. Therefore, the semiconductor package 200 can have improved reliability.

[0101] Although not specifically shown and described, in an example embodiment according to the present disclosure, one or more chip stacks having a configuration corresponding to and similar to the above-described second chip stack 130A and third chip stack 130B may be further disposed on the first chip stack 120 or the interposer ICL in the peripheral region PR of the semiconductor package 300. In this case, all chip stacks disposed on the first chip stack 120 or the interposer ICL may not be disposed in the central region CR of the semiconductor package 200. In addition, all chip stacks disposed on the first chip stack 120 may each include the same number or different numbers of chips.

[0102] Figure 5 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0103] Reference Figure 4 , except that the first chip stack 120′ includes a plurality of first chips 120a, 120b, and 120c and the interposer ICL′ includes a base layer 120D and a redistribution layer RDL, the semiconductor package 300 according to example embodiments may be similar to the reference 100. Figure 4 The semiconductor package 200 described above is substantially the same or similar. Therefore, the same or similar reference numerals may be used to represent the semiconductor package 200 described above. Figure 4 The components described are the same or similar components, and redundant descriptions of the same or similar components may be omitted.

[0104] Reference Figure 4 In the semiconductor package 300, the first chip stack 120' includes a plurality of first chips 120a, 120b, and 120c. The first chip stack 120' and the first chips 120a, 120b, and 120c may correspond to the reference Figure 4 A first chip stack 120 and first chips 120 a , 120 b , and 120 c are depicted.

[0105] Furthermore, in the semiconductor package 300 , the interposer ICL′ may include a base layer 120D and a redistribution layer RDL on the base layer 120D.

[0106] The base layer 120D may have the same Figure 4 The size of the first chip 120d described above is substantially the same as the size of the first chip 120d. In an embodiment, the base layer 120D may be a dummy chip. Figure 5 In the embodiment shown in FIG. 1 , the base layer 120D may be exposed at its edge by the redistribution layer RDL. In this case, the base layer 120D may have a Figure 4The first chip 120d described above is a semiconductor die with a substantially same or similar structure but does not perform a function. In this case, the base layer 120D may have a portion of the conductive path of the interposer ICL' formed therein, and be used for the electrical connection of the interposer ICL' with the external lead structure 160. However, example embodiments are not limited thereto. In some example embodiments, for example, the base layer 120D may be a bulk wafer formed of a semiconductor material. In this case, the conductive path of the interposer ICL' may not be formed in the base layer 120D, but may extend entirely in the redistribution layer RDL to be described below.

[0107] The redistribution layer RDL may be disposed between the second chip stack 130A and the base layer 120D, and exposed from a side of the second chip stack 130A close to the center region CR of the semiconductor package 300 in the horizontal direction. The redistribution layer RDL may be disposed between the second chip stack 130A and the base layer 120D, and exposed from a side of the third chip stack 130B close to the center region CR of the semiconductor package 300 in the horizontal direction. Figure 5 In the example shown in FIG. 1 , the redistribution layer RDL may extend (e.g., continuously extend) between the base layer 120D and the second chip stack 130A and the third chip stack 130B, and be exposed between the second chip stack 130A and the third chip stack 130B. Each of the second chip stack 130A and the third chip stack 130B may be electrically connected to the redistribution layer RDL at a side close to the center region CR of the semiconductor package 300 through the upper lead structure 150. Figure 5 As shown in , the redistribution layer RDL may expose an edge portion of the base layer 120D. In this case, a portion of the conductive path of the interposer ICL' may be formed in the redistribution layer RDL and used for electrical connection with the upper lead structure 150, and at the same time, the conductive path formed in the redistribution layer RDL and the conductive path formed in the base layer 120D may be connected to each other correspondingly to constitute a conductive path of the interposer ICL'. However, example embodiments are not limited thereto. In some example embodiments, the redistribution layer RDL may cover the entire upper surface of the base layer 120D and be exposed at an edge portion of the interposer ICL', and the conductive path of the interposer ICL' may all extend in the redistribution layer RDL to electrically connect the upper lead structure 150 to the outer lead structure 160.

[0108] In an embodiment, the redistribution layer RDL may include a plurality of interconnects and a plurality of vias. The plurality of interconnects and the plurality of vias may be connected to each other correspondingly to form a plurality of conductive paths independent of each other. The plurality of interconnects and the plurality of vias may include conductive materials, such as metals and / or metal nitrides. In addition, the redistribution layer RDL may further include an insulating layer for electrically insulating the plurality of conductive paths from each other. The insulating layer may include insulating materials, such as oxides, nitrides and / or oxynitrides. In an embodiment, the redistribution layer RDL may have a single-layer or multi-layer structure.

[0109] In the semiconductor package 300, since the interposer ICL' includes the base layer 120D including the semiconductor material, the difference in thermal expansion coefficient between the interposer ICL' and other chips in the semiconductor package 300 can be reduced. Therefore, the warpage of the semiconductor package 300 caused by the difference in thermal expansion coefficient can be suppressed. Therefore, the semiconductor package 300 can have improved reliability.

[0110] Figure 6 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0111] Reference Figure 6 , a semiconductor package 400 according to an example embodiment may include a package substrate 110′, a first chip stack 420 on the package substrate 410, an interposer ICL on the first chip stack 420, a second chip stack 430A and a third chip stack 440B on the interposer ICL, an encapsulation layer 470 covering the second chip stack 430A and the third chip stack 440B on the package substrate 410, and external connection terminals 480 under the package substrate 410.

[0112] The package substrate 410 may include a plurality of substrate pads 410P. The plurality of substrate pads 410P may be disposed on the upper surface of the package substrate 410. The plurality of substrate pads 410P may be disposed on the upper surface of the package substrate 410 in a region of the package substrate 410 overlapping with the first chip stack 420 to be described below. In addition, the plurality of substrate pads 410P may be exposed on the upper surface of the package substrate 410. In addition to the aforementioned configuration, the package substrate 410 may be configured as described in reference to Figures 3 to 5 The package substrates 110 are described to have substantially the same or similar configuration.

[0113] like Figure 6As shown in , the first chip stack 420 may be disposed on the package substrate 410 in both the central region CR and the peripheral region PR of the semiconductor package 400. In addition, the first chip stack 420 may overlap with a portion of the package substrate 410 provided with the substrate pad 410P in a vertical direction. For example, the first chip stack 420 may be disposed on a portion of the upper surface of the package substrate 410 provided with the substrate pad 410P. As used herein, the term "vertical direction" may be a direction perpendicular to the upper surface and / or lower surface of the package substrate 410.

[0114] The first chip stack 420 may include a plurality of first chips 420a, 420b, 420c, 420d, and 420e stacked in a vertical direction. Figure 6 In the example shown in FIG. 1 , the plurality of first chips 420 a , 420 b , 420 c , 420 d , and 420 e may be aligned in the vertical direction. For example, side surfaces of the plurality of first chips 420 a , 420 b , 420 c , 420 d , and 420 e may be substantially coplanar in the vertical direction, but are not limited thereto.

[0115] Each of the plurality of first chips 420a, 420b, 420c, 420d, and 420e may have an active surface (in the Figure 6 middle and lower surfaces) and the passive surface opposite to the active surface (in Figure 6 Among the plurality of first chips 420a, 420b, 420c, 420d, and 420e, the upper first chip (also referred to as an "upper first chip") may be stacked on the lower first chip with its active surface facing the lower first chip (also referred to as a "lower first chip"). That is, in the first chip stack 420, the plurality of first chips 420a, 420b, 420c, 420d, and 420e may all be arranged in a flip-chip method.

[0116] Each of the plurality of first chips 420a, 420b, 420c, 420d, and 420e may include a chip pad (not shown) disposed on its active surface, and may also include a through-via (not shown) disposed inside thereof. In each of the first chips 420a, 420b, 420c, 420d, and 420e, the chip pad may be exposed from the active surface of the first chip, the through-via may extend from the active surface to the passive surface in the first chip, and one end of the through-via may be connected to the chip pad. The chip pads and the through-vias of the plurality of first chips 420a, 420b, 420c, 420d, and 420e may be aligned in the vertical direction.

[0117] In an embodiment, the chip pad may be a conductive bump and may include a conductive material (such as a metal, a metal nitride and / or a metal silicide). In an embodiment, the through via may be a conductive pillar and may include a semiconductor material such as silicon (Si). For example, the through via may be a through silicon via (TSV).

[0118] In an embodiment, a plurality of first chips 420a, 420b, 420c, 420d, and 420e may include a single or multiple types of functional chips. For example, a plurality of first chips 420a, 420b, 420c, 420d, and 420e may include at least one logic chip and / or at least one memory chip. For example, at least one logic chip may include a central processing unit (CPU), a graphics processing unit (GPU), an arithmetic logic unit (APU), an application processor (AP), a neural network processor (NPU), or any suitable combination thereof, but not limited thereto. For example, at least one memory chip may include a dynamic random access memory (DRAM) chip, a static random access memory (SRAM), or any suitable combination thereof, but not limited thereto. When a plurality of first chips 420a, 420b, 420c, 420d, and 420e include a logic chip and a memory chip, the logic chip may be disposed below the memory chip, but not limited thereto.

[0119] Reference Figure 6 , the first chip stack 420 may further include a first connection structure 440. The first connection structure 440 may be provided in plurality, and the plurality of first connection structures 440 may be respectively provided between the plurality of first chips 420a, 420b, 420c, 420d, and 420e. Among the plurality of first chips 420a, 420b, 420c, 420d, and 420e, the upper first chip and the lower first chip may be electrically connected to each other by the first connection structure 440 provided therebetween. The lowermost first chip 420a among the plurality of first chips 420a, 420b, 420c, 420d, and 420e may be electrically connected to the package substrate 410 (e.g., through its chip pad). For example, the first connection structure 440 may be connected between the chip pad of the upper first chip and the conductive via of the lower first chip. In an embodiment, the first connection structure 440 may include a conductive microball or a conductive microbump, and may include a conductive material such as a metal, a metal nitride, or an alloy.

[0120] Reference Figure 6, the semiconductor package 400 may further include a second connection structure 491. The second connection structure 491 may be disposed between the lowermost first chip 420a and the package substrate 410, and connected to a chip pad (not shown) of the lowermost first chip 420a and a substrate pad 410P of the package substrate 410. In this way, the first chip stack 420 (including the first chips 420a, 420b, 420c, 420d, and 420e) may be electrically connected to the package substrate 410. In an embodiment, the second connection structure 491 may be a conductive microball or a conductive microbump, and may include a conductive material such as a metal, a metal nitride, or an alloy.

[0121] The interposer ICL may be disposed on the first chip stack 420. For example, the interposer ICL may be disposed on the uppermost first chip 420e in the first chip stack 420. For example, the interposer ICL may cover at least a portion of the upper surface of the uppermost first chip 420e. For example, the interposer ICL may be in contact with the uppermost first chip 420e.

[0122] The interposer ICL may include a conductive path. The conductive path of the interposer ICL may be electrically connected to the through-via of the uppermost first chip 420e. The conductive path of the interposer ICL may be electrically connected to the package substrate 410 (e.g., the substrate pad 410P of the package substrate 410) via the through-vias electrically connected to each other in the vertical direction in the first chip stack 420 and the first connection structure 440 and the second connection structure 491.

[0123] exist Figure 6 In the embodiment shown in , the interposer ICL may include a redistribution layer or may be composed of a redistribution layer. In this case, each of the conductive paths of the interposer ICL may extend in the redistribution layer and may have two ends exposed from the upper surface and the lower surface of the redistribution layer, respectively. One end of the conductive path exposed from the lower surface of the redistribution layer may contact and be electrically connected to the through via of the topmost first chip 420e. In addition, the "redistribution layer" described herein may have features that are substantially the same or similar to the features of the redistribution layer RDL described above.

[0124] The second chip stack 430A and the third chip stack 440B may be disposed on the interposer ICL in the peripheral region PR of the semiconductor package 400 and spaced apart from each other in the horizontal direction. The second chip stack 430A and the third chip stack 440B may not be disposed in the central region CR of the semiconductor package 400. The second chip stack 430A may include a plurality of second chips 430aA, 430bA, 430cA, and 430dA stacked in a vertical direction, and the plurality of second chips 430aA, 430bA, 430cA, and 430dA may be stacked obliquely away from the central region CR of the semiconductor package 400. The third chip stack 430B may include a plurality of third chips 430aB, 430bB, 430cB, and 430dB stacked in a vertical direction, and the plurality of third chips 430aB, 430bB, 430cB, and 430dB may be stacked obliquely away from the central region CR of the semiconductor package 400. As used herein, the term “horizontal direction” may refer to a direction parallel to an upper surface or a lower surface of the package substrate 410 .

[0125] Each of the second chip stack 430A and the third chip stack 440B may be electrically connected to the interposer ICL at a side close to the center region CR of the semiconductor package 400 through an upper lead structure 450. The upper lead structure 450 may include an upper interconnection lead 450a and an upper connection lead 450b. The plurality of second chips 430aA, 430bA, 430cA, and 430dA of the second chip stack 430A may be electrically connected to each other through the upper interconnection lead 450a, and the lowermost second chip 430aA of the second chip stack 430A may be electrically connected to the interposer ICL (e.g., a conductive path of the interposer ICL) through the upper connection lead 450b. The plurality of third chips 430aB, 430bB, 430cB and 430dB of the third chip stack 430B may be electrically connected to each other through the upper interconnection leads 450a, and the lowermost third chip 430aB of the third chip stack 430B may be electrically connected to the interposer ICL (e.g., a conductive path of the interposer ICL) through the upper connection leads 450b.

[0126] In addition to the above, the second chip stack 430A (including the second chips 430aA, 430bA, 430cA, and 430dA), the third chip stack 440B (including the third chips 430aB, 430bB, 430cB, and 430dB), and the upper lead structure 450 (including the upper interconnection leads 450a and the upper connection leads 450b) described herein may have reference Figure 4 and Figure 5 The features of corresponding components described are substantially the same or similar features.

[0127] The encapsulation layer 470 may encapsulate the first chip stack 420, the second chip stack 430A, and the third chip stack 440B on the package substrate 410. The encapsulation layer 470 may also encapsulate the upper lead structure 450. The encapsulation layer 470 may also cover the exposed interposer ICL. In an embodiment, the encapsulation layer 470 may include a molding material such as an epoxy molding compound.

[0128] In addition, the encapsulation layer 470 may also surround the first connection structure 440 and fill the space between the plurality of first chips 420a, 420b, 420c, 420d and 420e. In addition, the encapsulation layer 470 may also surround the second connection structure 491 and fill the space between the bottom first chip 420a and the package substrate 410. However, the example embodiments are not limited thereto. In some example embodiments, the encapsulation layer 470 may not be arranged between the plurality of first chips 420a, 420b, 420c, 420d and 420e and / or between the bottom first chip 420a and the package substrate 410. In this case, an additional adhesive layer or a filling layer may fill the space between the plurality of first chips 420a, 420b, 420c, 420d and 420e and / or between the bottom first chip 420a and the package substrate 410. In an embodiment, the adhesive layer may be a pressure-sensitive adhesive film or a die attach film, but is not limited thereto. In an embodiment, the filling layer may be an under-fill material, but is not limited thereto.

[0129] The external connection terminal 480 may be disposed on the lower surface of the package substrate 410. The external connection terminal 480 may be connected to a conductive path (not shown) of the package substrate 410 and electrically connected to the substrate pad 410P through the conductive path of the package substrate 410. Figure 6 The external connection terminal 480 described above may have the same Figures 3 to 5 The features of the external connection terminals 180 described are substantially the same or similar features.

[0130] In the semiconductor package 400, the first chip stack 420 may include a plurality of first chips 420a, 420b, 420c, 420d, and 420e stacked in a flip chip method. Compared with the wire bonding method, the flip chip method may be advantageous in reducing the size of the chip stack and in improving the connection reliability between the stacked chips. Therefore, the semiconductor package 400 may have improved integration and improved reliability.

[0131] In the semiconductor package 400, the interposer ICL may have a relatively small size (e.g., thickness and / or area). As a result, the volume occupied by the interposer ICL in the semiconductor package 400 may be relatively reduced. Therefore, the difference in thermal expansion coefficients between components inside the semiconductor package 400 may be reduced. Therefore, the warpage of the semiconductor package 400 due to the difference in thermal expansion coefficients may be suppressed or eliminated. Therefore, the semiconductor package 400 may have improved reliability.

[0132] Fig. 7A and Figure 7B is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments.

[0133] Reference Fig. 7A , except that the interposer ICL1 is disposed only in a region between the second chip stack 430A and the third chip stack 440B, the semiconductor package 400A according to example embodiments may be similar to the reference numeral 400A. Figure 6 The semiconductor package 400 described above is substantially the same or similar. Therefore, the same or similar reference numerals may be used to represent the semiconductor package 400 described above. Figure 6 The components described are the same or similar components, and redundant descriptions of the same or similar components may be omitted.

[0134] In the semiconductor package 400A, the interposer ICL1 may be disposed on the first chip stack 420 (eg, the uppermost first chip 420e) between the second chip stack 430A and the third chip stack 440B. The interposer ICL1 may not overlap each of the second chip stack 430A and the third chip stack 440B in a vertical direction. Fig. 7A As shown in FIG. 4 , the interposer ICL1 may be disposed on the uppermost first chip 420e in the center region CR of the semiconductor package 400A, but is not limited thereto. For example, the interposer ICL1 disposed between the second chip stack 430A and the third chip stack 440B may also be partially located in a region adjacent to the center region CR of the semiconductor package 400A.

[0135] The interposer ICL1 may include a conductive path (not shown). The conductive path of the interposer ICL1 may be electrically connected to a through-via (not shown) of the uppermost first chip 420e. The conductive path of the interposer ICL1 may also be electrically connected to the upper lead structure 450 to be electrically connected to each of the second chip stack 430A and the third chip stack 440B. Fig. 7A In the example shown in , the interposer ICL1 may be a redistribution layer, and the conductive paths of the interposer ICL1 may extend in the redistribution layer.

[0136] In addition, if Fig. 7A As shown in FIG. 4 , the second chip stack 430A and the third chip stack 440B may be attached to the first chip stack 420 (eg, the uppermost first chip 420e) by an adhesive member AM. In an embodiment, the adhesive member AM may be a die attach film, but is not limited thereto.

[0137] In the semiconductor package 400A, since the size of the interposer ICL1 can be further reduced, the volume occupied by the interposer ICL1 in the semiconductor package 400A can be further reduced. Therefore, the difference in thermal expansion coefficients between components inside the semiconductor package 400A can be further reduced. Therefore, the warpage of the semiconductor package 400A due to the difference in thermal expansion coefficients can be further suppressed or eliminated. Therefore, the semiconductor package 400A can have further improved reliability.

[0138] Reference Figure 7B , except that the interposer ICL2 is provided in the form of a block or a mesh, and an adhesive member AM′ for attaching each of the second chip stack 430A and the third chip stack 440B to the first chip stack 420 overlaps the interposer ICL2 in a horizontal direction, the semiconductor package 400B according to the example embodiment may be similar to the one described with reference to FIG. Fig. 7A The semiconductor package 400A described above is substantially the same or similar. Therefore, the same or similar reference numerals may be used to represent the semiconductor package 400A described above. Fig. 7A The components described are the same or similar components, and redundant descriptions of the same or similar components may be omitted.

[0139] In the semiconductor package 400B, the interposer ICL2 may be disposed in the form of a block or a mesh on the first chip stack 420 (e.g., the topmost first chip 420e). In this case, the interposer ICL2 may include a greater number and / or more configured conductive paths without excessively increasing the size (e.g., thickness and / or area). In this way, the density of interconnections via the interposer ICL2 in the semiconductor package 400B may be increased. In addition, the design freedom or design margin of the interconnections via the interposer ICL2 in the semiconductor package 400B may also be increased.

[0140] like Fig. 7AAs shown in , each of the second chip stack 430A and the third chip stack 440B can be attached to the uppermost first chip 420e of the first chip stack 420 by an adhesive member AM'. The adhesive member AM' can be disposed (e.g., filled) in a space defined by the interposer ICL2 between each of the second chip stack 430A and the third chip stack 440B and the first chip 420e. In this way, the increase in the size (e.g., thickness) of the semiconductor package 400B caused by the provision of the adhesive member AM' can be reduced while the size (e.g., thickness and / or area) of the interposer ICL2 is appropriately increased.

[0141] According to an example embodiment of the present disclosure, a semiconductor package may include a lower chip stack and one or more upper chip stacks stacked on the lower chip stack in a vertical direction. The upper chip stack may be disposed in a peripheral area around a central area of ​​the semiconductor package and include a plurality of upper chips stacked obliquely away from the central area of ​​the semiconductor package. In this way, the stacked plurality of upper chips of the upper chip stack may avoid a central area of ​​the semiconductor package where stress concentration may occur due to application of an external force (e.g., a test force applied in a strength test of the semiconductor package). Therefore, stress cracks occurring in the central area of ​​the semiconductor package may be suppressed or eliminated. Therefore, a semiconductor package according to an example embodiment may have improved reliability.

[0142] Although specific details of some example embodiments are described in this specification, these specific details should not be interpreted as limitations on the scope of any claimed subject matter, but rather as descriptions of features for specific embodiments. Some features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. On the other hand, different features described in the context of a single embodiment in this specification may also be implemented separately in multiple embodiments or in any suitable subcombination.

[0143] While aspects of the example embodiments have been particularly shown and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package having a central region and a peripheral region around the central region in a plan view, the semiconductor package comprising: Package substrate; a first chip stack located on the package substrate in the central region and the peripheral region and electrically connected to the package substrate; a second chip stack located on the first chip stack in the peripheral region, the second chip stack comprising a lower second chip and an upper second chip on the lower second chip, the upper second chip being farther from the central region than the lower second chip; an interposer on the first chip stack and at least in the central region, the interposer comprising a conductive path electrically connected to the package substrate; an encapsulation layer covering the first chip stack and the second chip stack on the packaging substrate; as well as an external connection terminal under the package substrate and electrically connected to the package substrate, The second chip stack and the interposer are electrically connected to each other at a side close to the central area.

2. The semiconductor package according to claim 1, in, The lower second chip has an inactive surface facing the first chip stack and an active surface facing the upper second chip, and A portion of the active surface of the lower second chip close to the central area is exposed by the upper second chip, and a chip pad of the lower second chip is disposed on the portion of the active surface of the lower second chip.

3. The semiconductor package according to claim 1, further comprising: The upper lead structure includes an upper interconnection lead and an upper connection lead, The upper interconnection lead electrically connects the chip pad of the upper second chip and the chip pad of the lower second chip, and the upper connection lead electrically connects the chip pad of the lower second chip to the conductive path of the interposer.

4. The semiconductor package according to claim 1, in, The interposer is located on the first chip stack in the central region and the peripheral region and partially between the second chip stack and the first chip stack.

5. The semiconductor package according to claim 4, wherein: The interposer includes a base layer on the first chip stack and a redistribution layer on the base layer, The redistribution layer includes at least a portion of the conductive path of the interposer, and The base layer includes a semiconductor material.

6. The semiconductor package according to claim 1, further comprising: The external lead structure includes at least one external connecting lead, Wherein, the conductive path of the interposer is electrically connected to the package substrate through the at least one external connection lead.

7. The semiconductor package according to claim 1, wherein: The first chip stack includes a plurality of first chips stacked in a vertical direction and a plurality of first connection structures respectively between the plurality of first chips. Each of the plurality of first chips includes a through-via formed therein, and the through-vias of adjacent first chips among the plurality of first chips are connected to each other through the first connection structure between the adjacent first chips, The through via of the uppermost first chip of the plurality of first chips is also connected to the conductive path of the interposer, and The through-via of the lowermost first chip among the plurality of first chips is also electrically connected to the package substrate.

8. The semiconductor package according to claim 1, further comprising: at least one third chip stack located on the first chip stack in the peripheral region, the at least one third chip stack comprising a lower third chip and an upper third chip on the lower third chip, the upper third chip being farther from the central region than the lower third chip, wherein the at least one third chip stack and the second chip stack are spaced apart from each other such that at least a portion of the central region is between the at least one third chip stack and the second chip stack, wherein the at least one third chip stack and the interposer are electrically connected to each other at a side close to the central area, and Wherein, the encapsulation layer also covers the at least one third chip stack.

9. The semiconductor package according to claim 1, in, When the semiconductor package is subjected to a strength test, a force applied from outside the semiconductor package for the strength test generates a stress concentration phenomenon in the central region of the semiconductor package, and Wherein, the strength test includes a three-point bending test, a four-point bending test or a ball-and-ring test.

10. The semiconductor package according to claim 1, in, In the plan view, the peripheral areas are at both sides of the central area or completely surround the central area.

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