Semiconductor device with multi-step gate and multi-step field plate and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor substrate, a surface passivation layer over the semiconductor substrate, and a first interlayer dielectric over the surface passivation layer. A gate electrode includes a gate channel portion extending through the surface passivation layer to contact an upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom range overlying the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom range higher than the first horizontal bottom range. A conductive field plate includes a first field plate having a third horizontal bottom range overlying and contacting the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom range at least as high as the first horizontal bottom range of the first gate field plate.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to semiconductor devices having gate electrodes and field plates and methods for fabricating such devices. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic components and systems. High power, high frequency transistors are used in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly suitable for these RF power applications and power electronics applications due to its excellent electronic and thermal properties. Specifically, the high electron velocity and high breakdown field strength of GaN make devices made from this material ideal for RF power amplifiers and high power switching applications.

[0003] Some GaN transistors include a field plate, which is an electrically grounded region of metallization that extends above the gate electrode of the transistor. The field plate is used to modify the electric field distribution, especially at the drain-side gate edge. This can cause an increase in breakdown voltage and a reduction in high-field trapping effects. Accurate alignment of the gate channel with the field plate is critical to achieving the necessary device performance for a variety of RF and power applications. In addition, the gate resistance, R G It is an important factor in determining the maximum signal gain by affecting the input power. However, conventional methods of reducing gate resistance may result in gate-drain capacitance C GD Increase and gate-source capacitance C GS This may result in a reduction in gain or a decrease in cutoff frequency. Therefore, in order to meet the device performance requirements for a given application, there is a need for GaN devices and methods of manufacturing such devices that ensure accurate alignment of the gate channel with the field plate and relatively low gate resistance. Summary of the invention

[0004] According to a first aspect of the present invention, there is provided a semiconductor device, comprising:

[0005] a semiconductor substrate having an upper surface and a channel;

[0006] a source electrode and a drain electrode over the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode;

[0007] a surface passivation layer located above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode;

[0008] a first interlayer dielectric (ILD0) over an upper surface of the surface passivation layer;

[0009] a gate electrode located above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent; and

[0010] A conductive field plate is located above the upper surface of the semiconductor substrate and between the gate electrode and the drain electrode, wherein the conductive field plate includes a first field plate having a third horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent at least as high as the first horizontal bottom extent of the first gate field plate.

[0011] In one or more embodiments, the semiconductor device further includes:

[0012] A horizontal dielectric spacer portion is on an upper surface of the surface passivation layer, wherein the fourth horizontal bottom extent of the second field plate overlies and contacts an upper surface of the horizontal dielectric spacer portion.

[0013] In one or more embodiments, the conductive field plate further includes a third field plate having a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.

[0014] In one or more embodiments, the ILD0 includes a lower ILD0 sublayer on the upper surface of the surface passivation layer, and a middle ILD0 sublayer on the upper surface of the lower ILD0 sublayer;

[0015] The fifth horizontal bottom extent of the third field plate overlies and contacts the upper surface of the lower ILD0 sublayer; and

[0016] The second horizontal bottom extent of the second gate field plate overlies an upper surface of the middle ILD0 sub-layer.

[0017] In one or more embodiments, the ILD0 further includes an upper ILD0 sublayer on the upper surface of the middle ILD0 sublayer; and

[0018] The conductive field plate further includes a fourth field plate having a sixth horizontal bottom extent that is higher than the fifth horizontal bottom extent of the third field plate, and the sixth horizontal bottom extent of the fourth field plate overlies and contacts an upper surface of the upper ILD0 sublayer.

[0019] In one or more embodiments, the lower ILD0 sublayer is formed of a material selected from silicon nitride;

[0020] The middle ILD0 sublayer is formed of a material selected from silicon dioxide; and

[0021] The upper ILDO sublayer is formed of a material selected from silicon nitride.

[0022] In one or more embodiments, the first gate field plate and the second gate field plate protrude upward and outward from the gate channel portion; and

[0023] The second field plate and the third field plate protrude upward and outward from the first field plate.

[0024] In one or more embodiments, the first gate field plate and the second gate field plate are located on the drain side of the gate electrode;

[0025] The gate electrode further includes another first gate field plate and another second gate field plate located on a source side of the gate electrode;

[0026] The second field plate and the third field plate are located on a gate side of the conductive field plate; and

[0027] The conductive field plate further includes another second field plate and another third field plate on the drain side of the conductive field plate.

[0028] In one or more embodiments, the surface passivation layer consists of a single surface passivation layer formed on the upper surface of the semiconductor substrate;

[0029] The upper surface of the single surface passivation layer defines the upper surface of the surface passivation layer; and

[0030] The third horizontal bottom extent of the first field plate contacts the upper surface of the single surface passivation layer.

[0031] In one or more embodiments, the single surface passivation layer is formed of a material selected from the group consisting of aluminum oxide, aluminum nitride, silicon nitride, and hafnium oxide.

[0032] In one or more embodiments, the surface passivation layer includes a lower surface passivation sublayer formed on the upper surface of the semiconductor substrate and an upper surface passivation sublayer formed on the lower surface passivation sublayer, wherein the upper surface of the upper surface passivation sublayer defines the upper surface of the surface passivation layer; and

[0033] The third horizontal bottom extent of the first field plate contacts the upper surface of the single surface passivation layer.

[0034] In one or more embodiments, the lower surface passivation sublayer is formed of silicon nitride; and

[0035] The upper surface passivation sublayer is formed of a material selected from aluminum oxide, aluminum nitride and hafnium oxide.

[0036] In one or more embodiments, the first field plate and the second field plate are formed of a field plate metal; and

[0037] The semiconductor device also includes a source metallization extending from the field plate metal across the gate electrode to a source contact.

[0038] In one or more embodiments, the field plate metal includes one or more materials selected from titanium, titanium tungsten, titanium aluminum, titanium tungsten nitride, gold, aluminum, molybdenum, nickel, polysilicon, platinum, copper and tantalum; and

[0039] The source metallization includes one or more materials selected from titanium, titanium tungsten, titanium aluminum, titanium tungsten nitride, gold, titanium-aluminum-gold, aluminum, molybdenum, nickel, polysilicon, germanium, platinum, copper and tantalum.

[0040] In one or more embodiments, the first field plate and the second field plate are formed by a source metallization extending across the gate electrode to a source contact; and

[0041] The source metallization includes one or more materials selected from titanium, titanium tungsten, titanium aluminum, titanium tungsten nitride, gold, titanium-aluminum-gold, aluminum, molybdenum, nickel, polysilicon, germanium, platinum, copper and tantalum.

[0042] According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0043] Providing a semiconductor substrate having an upper surface and a channel;

[0044] forming a surface passivation layer over the upper surface of the semiconductor substrate;

[0045] forming a first interlayer dielectric (ILD0) over an upper surface of the surface passivation layer;

[0046] forming a source electrode and a drain electrode over the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode;

[0047] forming a gate electrode between the source electrode and the drain electrode over the upper surface of the semiconductor substrate, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent; and

[0048] A conductive field plate is formed above the upper surface of the semiconductor substrate between the gate electrode and the drain electrode, wherein the conductive field plate includes a first field plate having a third horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent at least as high as the first horizontal bottom extent of the first gate field plate.

[0049] In one or more embodiments, the method further comprises:

[0050] Simultaneously forming a gate electrode opening and a field plate opening through the ILD0;

[0051] forming a field plate dielectric spacer on a sidewall of the ILD0 in the field plate opening, wherein the field plate dielectric spacer includes a vertical spacer portion contacting the sidewall of the ILD0, a horizontal spacer portion contacting the upper surface of the surface passivation layer, and an upper dielectric spacer portion overlying and contacting the vertical spacer portion and the horizontal spacer portion; and

[0052] removing at least a portion of the upper dielectric spacer portion and the vertical spacer portion of the field plate dielectric spacer, and

[0053] Wherein forming the conductive field plate comprises forming the first field plate between the horizontal spacer portions, and forming the second field plate on the horizontal spacer portions.

[0054] In one or more embodiments, the method further comprises:

[0055] Simultaneously forming a gate electrode opening and a field plate opening through the ILD0;

[0056] forming a gate dielectric spacer on a sidewall of the ILD0 in the gate electrode opening, wherein the gate dielectric spacer includes a vertical spacer portion contacting the sidewall of the ILD0, a horizontal spacer portion contacting the upper surface of the surface passivation layer, and an upper dielectric spacer portion overlying and contacting the vertical spacer portion and the horizontal spacer portion; and

[0057] removing the surface passivation layer between the gate dielectric spacers to expose a portion of the upper surface of the semiconductor substrate,

[0058] wherein the gate electrode opening has a first horizontal bottom range exposing the portion of the upper surface of the semiconductor substrate, a second horizontal bottom range overlying the upper surface of the surface passivation layer, and a third horizontal bottom range at or below the upper surface of the ILD0, and

[0059] The formation of the gate electrode includes depositing a gate metal in the gate electrode opening to form the gate channel portion contacting the upper surface of the semiconductor substrate at the first horizontal bottom range of the gate electrode opening, the first gate field plate overlying the upper surface of the surface passivation layer at the second horizontal bottom range of the gate electrode opening, and the second gate field plate contacting the third horizontal bottom range of the gate electrode opening.

[0060] In one or more embodiments, the method further comprises:

[0061] The gate dielectric spacer is removed such that the second horizontal bottom extent is defined by the upper surface of the surface passivation layer.

[0062] In one or more embodiments, forming the conductive field plate includes:

[0063] The conductive field plates are formed to further include a third field plate having a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.

[0064] In one or more embodiments, forming the ILD0 includes:

[0065] forming a lower ILDO sublayer on the upper surface of the surface passivation layer;

[0066] forming a middle ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer; and forming an upper ILD0 sub-layer on an upper surface of the middle ILD0 sub-layer,

[0067] wherein the fifth horizontal bottom extent of the third field plate overlies and contacts the upper surface of the lower ILD0 sublayer, and

[0068] The second horizontal bottom extent of the second gate field plate overlies an upper surface of the middle ILD0 sub-layer.

[0069] In one or more embodiments, forming the conductive field plate includes:

[0070] The conductive field plates are formed to further include a fourth field plate having a sixth horizontal bottom extent overlying and contacting an upper surface of the upper ILD0 sub-layer.

[0071] In one or more embodiments, forming the surface passivation layer includes:

[0072] A single surface passivation layer is formed on the upper surface of the semiconductor substrate, wherein an upper surface of the single surface passivation layer defines the upper surface of the surface passivation layer.

[0073] In one or more embodiments, forming the surface passivation layer includes:

[0074] forming a lower surface passivation sublayer on the upper surface of the semiconductor substrate; and

[0075] An upper surface passivation sublayer is formed on the lower surface passivation sublayer, wherein an upper surface of the upper surface passivation layer defines the upper surface of the surface passivation layer.

[0076] In one or more embodiments, forming the conductive field plate includes forming the first field plate and the second field plate from a field plate metal; and

[0077] The method also includes forming a source metallization extending from the field plate metal across the gate electrode to a source contact.

[0078] In one or more embodiments, forming the conductive field plates includes forming the first field plate and the second field plate from a source metallization extending across the gate electrode to a source contact.

[0079] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] A more complete understanding of the subject matter may be derived by referring to the detailed description and claims considered in conjunction with the following drawings, wherein like reference numerals refer to like elements throughout the various figures.

[0081] Figure 1 is a cross-sectional side view of an exemplary heterojunction field effect transistor (HFET) according to an embodiment;

[0082] Figure 2 is used to describe the manufacturing Figure 1 , 17 and 31 , a process flow diagram of an embodiment of a method of various embodiments of a heterojunction field effect transistor (HFET) device;

[0083] Figure 3 , 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17 are cross-sectional side views of embodiments of HFET devices during a series of fabrication steps according to example embodiments; and

[0084] Fig.18 , 19 , 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 and 31 are cross-sectional side views of another embodiment of a HFET device during a series of fabrication steps according to another example embodiment. DETAILED DESCRIPTION

[0085] Embodiments disclosed herein include field effect transistors (FETs), and in particular heterojunction field effect transistors (HFETs) including high electron mobility transistors (HEMTs). The transistor embodiments each include a gate electrode and a field plate structure. According to one or more embodiments, both the gate electrode and the field plate structure have a stepped configuration that produces a gate electrode having at least one gate field plate (GFP) and a field plate structure having a plurality of source connection field plates (SFP). The field plate structure may cause a gate-drain capacitance C GD The advantageous reduction of. In addition, in the case of multiple SFPs, the field plate structure is configured to ensure dielectric reliability and high breakdown voltage. The manufacturing method disclosed herein allows at least one GFP in the GFP and at least one SFP in the SFP to be fully self-aligned with the gate channel. By self-aligning these device features, device-to-device performance variations (e.g., variations in capacitance, gain, cutoff frequency, output power, and capture) that may otherwise occur due to feature misalignment can be avoided. In addition, in at least one embodiment, the gate structure is designed to have a relatively low gate resistance R G , without causing the gate-drain capacitance C GD or gate-source capacitance C GS significant increase.

[0086] Figure 1 is a cross-sectional side view of an exemplary GaN heterojunction field effect transistor (HFET) device 100 according to an embodiment. Figure 1 The upper image in FIG. 1 shows an overall view of the GaN HFET device 100. In addition, to enhance understanding, an enlarged view of a portion 101 of the GaN HFET device 100 is shown below the overall view of the device 100. The portion 101 corresponds to an embodiment of a transistor structure, which is described below in conjunction with Figures 2 to 17 The manufacturing of the transistor structure is described in detail. Figures 18 to 31 As explained, Figure 1Various modifications may be made to the transistor structure depicted in portion 101 of the device 100, and those modified embodiments may be incorporated into the overall view of the device 100 (ie, Fig.31 The alternative embodiment shown in Figure 1 101). Nevertheless, the following Figure 1 The various details and embodiments discussed, and particularly those associated with semiconductor substrate 110 and other features located outside portion 101, are applicable to Figures 3 to 31 All embodiments described in .

[0087] GaN HFET device 100 includes semiconductor substrate 110, one or more isolation regions 120, and active region 125. The active region is defined as the portion of device 100 located between isolation regions 120. As will be described in detail below, various transistor structures are formed on and above upper surface 112 of semiconductor substrate 110, and variable conductive channel 107 below upper surface 112 of semiconductor substrate 110 enables current flow through device 100.

[0088] In an embodiment, the semiconductor substrate 110 may include a main substrate 102, a buffer layer 104 disposed over an upper surface 103 of the main substrate 102, a channel layer 106 disposed over the buffer layer 104, and a barrier layer 108 disposed over the channel layer 106. In some embodiments, a cap layer 109 is disposed over the channel layer 106, and the cap layer 109 defines an upper surface 112 of the substrate 110. In other embodiments, the cap layer 109 may not be included, and the barrier layer 108 may define the upper surface 112 of the substrate 110. In the drawings, the upper layers of the substrate 110 are colored to enhance distinguishability from the underlying depicted layers overlying the upper surface 112 of the substrate 110.

[0089] The main substrate 102 may include silicon carbide (SiC), or may include other materials, such as sapphire, silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), diamond, polycrystalline SiC, silicon on insulator, gallium arsenide (GaAs), indium phosphide (InP), or other substantially insulating or high resistivity materials. A nucleation layer (e.g., AlN, not shown) may be formed on the upper surface 103 of the main substrate 102 between the buffer layer 104 and the main substrate 102. Embodiments of the buffer layer 104, the channel layer 106, the barrier layer 108, and the cap layer 109 may include materials selected from Si, AlN, GaN, indium phosphide (InP), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium gallium nitride (InGaN), and / or other suitable materials. The layers 104, 106, 108, and 109 may be epitaxially grown on the main substrate 102. Some of the layers 104, 106, 108, and 109 may be intentionally doped with iron (Fe), chromium (Cr), carbon (C), magnesium (Mg), germanium (Ge), or other suitable dopant species.

[0090] In some embodiments, the barrier layer 108 has a larger band gap and a larger spontaneous polarization than the channel layer 106, and when the barrier layer 108 is in direct contact with the channel layer 106, the channel 107 is generated in the form of a two-dimensional electron gas (2-DEG) within the channel layer 106 near the interface between the channel layer 106 and the barrier layer 108. In addition, the strain between the barrier layer 108 and the channel layer 106 can cause additional piezoelectric charge to be introduced into the 2-DEG and the channel 107. In some embodiments, an additional AlN interlayer barrier layer (not shown) can be formed between the channel layer 106 and the barrier layer 108. The AlN interlayer barrier layer can increase the channel charge, reduce electron alloy scattering to produce increased mobility, and improve electron confinement of the resulting 2-DEG.

[0091] Without departing from the scope of the present subject matter, it should be understood that the material selection and layer arrangement forming the semiconductor substrate 110 are exemplary. It should be understood that including the main substrate 102, the buffer layer 104, the channel layer 106, the barrier layer 108 and the cap layer 109 in the semiconductor substrate 110 is exemplary, and the functions and operations of the various layers can be combined and can vary depending on the materials used in any specific embodiment.

[0092] In other embodiments using N-polar materials, the channel layer 106 may be disposed above the barrier layer 108 to create a 2-DEG and channel 107 directly below the cap layer 109 and the gate electrode 160. Other embodiments may include a semiconductor layer made of GaAs, gallium oxide (Ga 2 O 4), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs) and aluminum indium arsenide (AlInAs) are formed to form the semiconductor substrate 110.

[0093] The isolation regions 120 may be formed via an implantation process configured to damage the epitaxial layer and / or other semiconductor layers to produce high resistivity regions of the semiconductor substrate 110 (i.e., to render the semiconductor substrate 110 high resistivity or semi-insulating in those high resistivity regions), while leaving the crystal structure intact in the active regions 125. In other embodiments, the isolation regions 120 may be formed by removing one or more of the epitaxial layer and / or other semiconductor layers of the semiconductor substrate 110, rendering the remaining layers of the semiconductor substrate 110 semi-insulating, and leaving an active region "mesa" surrounded by high resistivity or semi-insulating isolation regions (not shown). In still other embodiments, the isolation regions 120 may be formed by removing one or more of the epitaxial layer and / or other semiconductor layers of the semiconductor substrate 110, followed by using ion implantation to damage and further enhance the semi-insulating properties of the remaining layers of the semiconductor substrate 110, and leaving an active region "mesa" (not shown) surrounded by the implanted high resistivity or semi-insulating isolation regions 120.

[0094] Within the active region 125, the HFET device 100 includes a source electrode 140 (also referred to herein as a "first current carrying electrode"), a source contact 141, a drain electrode 145 (also referred to herein as a "second current carrying electrode"), a drain contact 146, a gate electrode 160 (also referred to herein as a "control electrode"), a source-connected field plate (SFP) structure 190 (also referred to herein as a "field plate," "multi-step field plate," or "conductive field plate"), a source region 142, and a drain region 147. In an embodiment, the GaN HFET device 100 may be configured as a transistor finger, wherein the source electrode 140, the drain electrode 145, the gate electrode 160, and the SFP structure 190 may be configured as an elongated element forming a transistor "fingers." To construct a high power device, multiple instances of the GaN HFET device 100 may be implemented in parallel with multiple drain electrodes 145 all coupled together and with multiple gate electrodes 160 all coupled together.

[0095] The source region 142 and the drain region 147 extend from the upper surface 112 of the substrate 110 to a depth below the upper surface 112, and these regions 142, 147 are located at opposite ends of the channel 107 at the upper surface 112 of the semiconductor substrate 110. In some embodiments, ion implantation may be used to form the intentionally doped source region 142 and drain region 147, and thus, the source region 142 and the drain region 147 may be regions of the semiconductor substrate 110 into which source and drain dopants have been implanted. In other embodiments, rather than including the intentionally doped source region 142 and drain region 147, these regions of the substrate 110 may not be intentionally doped. In practice, after depositing the constituent layers of the Ohmic stack forming the source contact 141 and the drain contact 146, an annealing process may be performed to alloy the Ohmic stack, thereby creating Ohmic contacts with the source region 142 and the drain region 147 of the semiconductor substrate 110 (i.e., with the 2-DEG of the channel 107). In yet other embodiments, in addition to or instead of the source region 142 and the drain region 147 (not shown) and in the same location as the source region 142 and the drain region 147, a heavily doped (e.g., Si doping> 1e19 cm -3 ) may be formed above the semiconductor substrate 110 and in contact with the semiconductor substrate 110.

[0096] At the upper surface 112 of the substrate 110, the source contact 141 extends from its proximal end near the source side of the gate electrode 160 toward the source electrode 140. The source contact 141 overlies and contacts the cap layer 109 and the source region 142 along substantially the entire length of the source contact 141. In other embodiments, if the cap layer 109 is not included, the source contact 141 may contact the barrier layer 108. In yet other embodiments, the source contact 141 may be recessed into the semiconductor substrate 110. The source electrode 140 is disposed on or over a portion of the distal end of the source contact 141 and is electrically coupled to the SFP structure 190 through the source metallization 148.

[0097] Similarly, at the upper surface 112 of the substrate 110, the drain contact 146 extends from its proximal end near the drain side of the gate electrode 160 toward the drain electrode 145. The drain contact 146 overlies and contacts the cap layer 109 and the drain region 147 along substantially the entire length of the drain contact 146. In other embodiments, if the cap layer 109 is not included, the drain contact 146 may contact the barrier layer 108. In yet other embodiments, the drain contact 146 may be recessed into the semiconductor substrate 110. The drain electrode 145 is disposed on or over a portion of the distal end of the drain contact 146 and is electrically coupled to a drain manifold (not shown) through a drain metallization 149.

[0098] In one or more embodiments, the source contact 141 and the drain contact 146 are formed of a conductive layer (eg, Figure 8 The conductive layer 830 may include one or more layers of titanium (Ti), titanium tungsten (TiW), titanium aluminum (TiAl), titanium tungsten nitride (TiWN), or other materials suitable for forming ohmic contacts with the source region 142 and the drain region 147. The source electrode 140 and the drain electrode 145 formed by the source metallization 148 and the drain metallization 149 overlie and contact the source contact 141 and the drain contact 146. The source electrode 140 and the drain electrode 145 (and the metallizations 148, 149) may be formed by a stack of multiple conductive layers. In some embodiments, the multilayer stack used to form the source electrode 140 and the drain electrode 145 and the source metallization 148 and the drain metallization 149 may include, for example, one or more layers of Ti, TiW, TiAl, TiWN, gold (Au), titanium-aluminum-gold (TiAlAu), Al, molybdenum (Mo), nickel (Ni), polysilicon, Ge, platinum (Pt), copper (Cu), tantalum (Ta), combinations of these materials, or other suitable materials.

[0099] exist Figure 1 In the embodiment of the present invention, the source metallization 148 is shown as extending from the source contact 141 across the gate electrode 160 to the SFP structure 190. This extension of the source metallization 148 may be continuous over the length of the transistor finger (i.e., along the dimension into the page). In other embodiments, in order to reduce the capacitive coupling between the gate electrode 160 and the source metallization 148, the source metallization 148 may cross the gate electrode 160 to the SFP structure 190 only in discrete locations along the length of the transistor finger. In other words, the source metallization 148 may be implemented as one or more conductive "strips" that electrically couple the source contact 141 to the SFP structure 190 at one or more locations along the transistor finger, rather than a continuous structure along the entire length of the transistor finger. Therefore, most of the transistor fingers may lack source metallization that crosses the gate electrode 160. In yet other embodiments, the source metallization 148 may be positioned outside the active region 125, beyond the ends of the transistor fingers (not shown), so as to electrically couple the source contact 141 to the SFP structure 190. In both other embodiments and still other embodiments, the same metal layer may be used to form the SFP structure 190 and the source metallization 148. However, alternatively, separate metal layers may be used for the metal to form the SFP structure 190 and the source metallization 148, but are not limited thereto.

[0100] In an embodiment, a surface passivation layer 130 (including a first surface passivation sublayer 131 and a second surface passivation sublayer 133 of the device 100, and only including the first passivation layer 133 of the device 100') and a multi-layer lowermost interlayer dielectric (ILD0) 134 (including at least a first ILD0 sublayer 135, a second ILD0 sublayer 136, and a third ILD0 sublayer 137) are formed in the active area 125 above the upper surface 112 of the semiconductor substrate 110. Adjacent sublayers of these sublayers 131, 133, 135, 137 are formed of different dielectric materials. Therefore, adjacent sublayers 131, 133, 135 to 137 have different etching properties. For example, various materials that can form the surface passivation layer and the ILD0 sublayers 131, 133, 135 to 137 include, but are not limited to, silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 or other stoichiometries), silicon oxynitride (SiON in various stoichiometries), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN) and hafnium oxide (HfO 2 ), but other substantially insulating materials may also be used. Figure 1 In the embodiment shown in , the surface passivation layer 130 includes two sub-layers 131, 133. In other embodiments (e.g., Fig.31 ), the surface passivation layer may include only a single layer.

[0101] The gate electrode 160 extends through all of the surface passivation sublayers 131, 133 and the ILD0 sublayers 135 to 137. The gate electrode 160 is located above the upper surface 112 of the substrate 110, between the source contact 141 and the drain contact 146. During operation, the gate electrode 160 is used to adjust the conductivity of the channel 107 in response to a time-varying voltage applied to the gate electrode 160, thereby adjusting the current between the source contact 141 and the drain contact 146. The contact area between the gate electrode 160 and the upper surface 112 of the substrate 110 is referred to herein as a "gate channel".

[0102] As mentioned previously and as will be described in detail below, the gate electrode 160 has a stepped configuration. The stepped configuration of the gate electrode 160 includes a gate channel portion 162 and a plurality of gate field plates (GFPs) 164, 166. The gate channel portion 162 is located at the gate channel and has a level (relative to the gate electrode 160) that defines the lowermost portion (i.e., the portion that contacts or is closest to the upper substrate surface 112) of the gate electrode 160. Figure 1) bottom extent. The first GFP 164 (GFP1) is integrally formed with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extent of the gate channel portion 162. More specifically, GFP1 164 overlies and contacts a portion of the dielectric surface passivation layer (e.g., a portion of the surface passivation sublayer 133). The second GFP 166 (GFP2) is also integrally formed with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extent of both the gate channel portion 162 and GFP1 164. More specifically, GFP2 166 overlies and contacts a portion of the additional dielectric layer (e.g., a portion of layer 136). Figure 1 As shown in FIG. 1 , the horizontal bottom extents of GFP1 164 and GFP2 166 protrude upward and outward from the gate channel portion 162 on both sides of the gate channel portion 162 .

[0103] As used herein, when a horizontal bottom extent of a first feature (e.g., GFP2 164) is referred to as being “higher” than a horizontal bottom extent of a second feature (e.g., GFP1 162), this means that the first feature is farther from the upper surface 112 of the semiconductor substrate 110 than the second feature (i.e., there is a thicker dielectric between the first feature and the upper surface 112 of the substrate 110 than there is between the second feature and the upper surface 112 of the substrate 110). Similarly, as used herein, when a horizontal bottom extent of a first feature (e.g., GFP1 162) is referred to as being “lower” than a horizontal bottom extent of a second feature (e.g., GFP2 164), this means that the first feature is closer to the upper surface 112 of the semiconductor substrate 110 than the second feature (i.e., there is a thinner dielectric between the first feature and the upper surface 112 of the substrate 110 than there is between the second feature and the upper surface 112 of the substrate 110).

[0104] In at least one embodiment, the gate electrode 160 has a relatively large cross-sectional area, which can result in a relatively low gate resistance R G , without causing the gate-drain capacitance C GD or gate-source capacitance C GSA Schottky contact is formed in the gate trench. According to an embodiment, for low loss, a Schottky gate electrode 160, such as one or more Schottky materials such as nickel (Ni), palladium (Pd), platinum (Pt), iridium (Ir), or copper (Cu), may be combined with one or more low stress conductive materials such as gold (Au), aluminum (Al), Cu, polysilicon, or other suitable materials in a metal stack to form the gate electrode 160. In various embodiments, the gate electrode 160 may be characterized by a gate length where the gate electrode 160 contacts the substrate surface 112, and the gate length may be between about 0.05 microns and about 1 micron. In other embodiments, the gate length may be between about 0.01 microns and about 5 microns, but other suitable dimensions may be used.

[0105] Many other gate electrode embodiments may be implemented without departing from the scope of the present subject matter. Figure 1 The exemplary embodiments of the present invention depict gate electrode 160 as disposed over semiconductor substrate 110. In other embodiments (not shown), gate electrode 160 may be recessed through cap layer 109 and partially extend into barrier layer 108, thereby enhancing the electrical coupling of gate electrode 160 with channel 107 through barrier layer 108. In still other embodiments (not shown), cap layer 109 may be omitted, and gate electrode 160 may directly contact barrier layer 108. In still other embodiments, gate electrode 160 may be disposed over a gate insulator (not shown), which may be formed between gate electrode 160 and semiconductor substrate 110 to form a metal-insulator semiconductor field effect transistor (MISFET) device.

[0106] The SFP structure 190 extends through the ILD0 sublayers 135-137 but not through the surface passivation layer 130. The SFP structure 190 is located above the upper surface 112 of the substrate 110, between the gate structure 160 and the drain contact 146. The SFP structure 190 is used to modify the electric field distribution, especially the electric field distribution at the drain-side edge of the gate electrode 160, thereby potentially causing an increase in the breakdown voltage of the device 100 and a reduction in the high-field trapping effect.

[0107] As previously mentioned and as will be described in detail below, the SFP structure 190 (or SFP structure 190') also has a stepped configuration. The stepped configuration of the SFP structure 190 (or SFP structure 190') includes a plurality of source connection field plates (SFP) 192 (or 192'), 194, 196, 198, 199, wherein the horizontal bottom range of SFP1 192 (and 192') is at a first level, and the horizontal bottom ranges of SFP2 194, SFP3 196, SFP4 198, and SFP5 199 are at increasingly higher levels (i.e., SFP2 194, SFP3 196, SFP4 198, and SFP5 199 protrude upward and outward from SFP1 192 (or 192') on both sides of SFP1 192 (or 192')). In general, the SFP structure 190 (or 190 ′) may result in a gate-drain capacitance C , compared to conventional devices lacking a field plate. GD The plurality of SFPs include a first SFP 192 (SFP1) (or 192') comprising a horizontal bottom extent separated from the upper surface 112 of the substrate 110 by a relatively thin underlying dielectric material (e.g., portions of the dielectric layers 131, 133). In one or more embodiments, the bottom extent of SFP1 192 (or 192') may be at the same level as the bottom extent of GFP1 164 (i.e., SFP1 192 (or 192') and GFP1 164 have the same underlying dielectric thickness). Lower gate-drain capacitance C GD This in turn may result in an increase in the gain of the device 100. In addition, a plurality of additional SFPs (e.g., SFP2 194, SFP3 196, SFP4 198, SFP5 199, etc.) are provided, each having an increasingly thicker underlying dielectric material (i.e., an increasingly higher horizontal bottom range) to weaken the electric field at the edge of SFP1 192 (or 192') in order to ensure dielectric reliability and improve breakdown.

[0108] In various embodiments, the SFP structure 190 may be formed using one or more conductive layers. For example, the SFP structure 190 may be formed of titanium (Ti), Au, Al, molybdenum (Mo), Ni, Si, Ge, Pt, Cu, Ta, combinations of these materials, or other suitable materials. In other embodiments, the one or more conductive layers used to form the SFP structure 190 may include titanium tungsten (TiW), titanium aluminum (TiAl), or titanium tungsten nitride (TiWN). Fig.31 As another example discussed, the SFP structure 190 ′ may be formed of a multi-layer conductive stack including an adhesion layer (eg, TiW or another suitable material) and additional layers (eg, gold (Au) and / or other suitable metals).

[0109] As will be discussed in more detail below, embodiments of the method of manufacturing device 100 ensure that at least SFP1 192 (or 192') and SFP2 194 are fully self-aligned with gate channel portion 162. By self-aligning these device features, device-to-device performance variations (e.g., variations in capacitance, gain, cutoff frequency, output power, and capture) that might otherwise occur due to feature misalignment can be avoided. According to embodiments, self-aligned gate channel portion 162, SFP1 192 (or 192'), and SFP2 194 are partially achieved by simultaneously forming a gate opening and a field plate opening (e.g., Figure 4 This is possible by virtue of the openings 460, 490) as will be described in detail later.

[0110] According to various embodiments, one or more additional dielectric layers 150, 170, 180 are disposed over the surface passivation sublayers 131, 133 and the ILD0 sublayers 135 to 137, the gate electrode 160, and the SFP structure 190 (or 190'). For example, the additional dielectric layers 150, 170, 180 may be formed of one or more suitable materials, including silicon dioxide (SiO 2 ), organic silicate glass, porous silicon dioxide, silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN) and hafnium oxide (HfO 2 ), but other substantially insulating materials may also be used.

[0111] As used herein, the term "low-k dielectric material" refers to a dielectric material having a dielectric constant lower than about 5.0, and the term "high-k dielectric material" refers to a dielectric material having a dielectric constant higher than about 5.0. In embodiments, the additional dielectric layers 150, 170, 180 may be formed of a low-k dielectric material. In some embodiments, the relatively low dielectric constant of the dielectric layer 150 may reduce parasitic capacitance between the gate electrode 160 and the source metallization 148 and the SFP structure 190 (or 190'), and may also reduce parasitic capacitance between the drain electrode 145 and the field plate structure 190 (or 190').

[0112] The dielectric constants of the surface passivation sublayers 131, 133 and ILD0 sublayers 135-137 may exceed the dielectric constant of the additional dielectric layers 150, 170, 180. Additionally, the dielectric constants of the sublayers 131, 133, 135 may exceed the dielectric constant of the upper ILD0 sublayers 136, 137.

[0113] Figure 2 is used to describe the manufacturing Figure 1Embodiments of a method for manufacturing a GaN HFET device 100 and a GaN HFET device (eg, Fig.31 100 ') is an alternative embodiment of the method of the process flow diagram of the alternative embodiment. To enhance understanding, Figure 2 Should be combined Figures 3 to 31 View, where Figures 3 to 17 The fabrication of a first embodiment of a GaN HFET device 100 is shown in Figures 18 to 31 The fabrication of the second embodiment of the GaN HFET device 100' is shown in FIG. Figures 3 to 31 The portions 100, 100' of the GaN HFET device depicted in FIG. Figure 1 101 of the device 100 shown in FIG. Figures 3 to 31 Only portions of GaN HFET devices are depicted, but those GaN HFET devices will also include other adjacent device structures, such as Figure 1 Shown in the upper image in are those device structures to the left and right of portion 101 (e.g., other GaN HFET devices would include a main substrate 102, source and drain regions 142 and 147, source and drain electrodes 140 and 145, source and drain contacts 141 and 146, isolation regions 120, etc.).

[0114] Example 1 Figures 3 to 17 ):

[0115] Figure 2 It will first be used to describe Figure 1 The manufacturing steps of the embodiment of GaN HFET 100 shown in FIG. Figures 3 to 17 More specifically, Figures 3 to 17 Included is a cross-sectional side view of an embodiment of a portion of a GaN HFET device 100 during a series of fabrication steps.

[0116] First reference Figure 1 and 2In block 202, fabrication of GaN HFET device 100 begins by providing semiconductor substrate 110. As previously mentioned, in at least one embodiment, providing semiconductor substrate 110 may include providing host substrate 102 and forming a number of semiconductor layers on or over host substrate 102. For example, host substrate 102 may include SiC, or may include other materials such as sapphire, Si, GaN, AlN, diamond, polycrystalline SiC, silicon-on-insulator, GaAs, InP, or other substantially insulating or high-resistivity materials. Forming overlying semiconductor layers may include forming a nucleation layer (not shown) on or over upper surface 103 of host substrate 102, forming a buffer layer 104 on or over nucleation layer, forming a channel layer 106 on or over buffer layer 104, forming a barrier layer 108 on or over channel layer 106, and optionally forming a cap layer 109 on or over barrier layer 108. Embodiments of the buffer layer 104, the channel layer 106, the barrier layer 108, and the cap layer 109 may include materials selected from Si, AlN, GaN, InP, AlGaN, InAlN, InGaN, or other suitable materials. The semiconductor layers 104, 106, 108, and 109 may be epitaxially grown using one of metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination of these techniques, but alternatively, other suitable techniques may be used. Some of the layers 104, 106, 108, and 109 may be intentionally doped with Fe, Cr, C, Mg, Ge, or other suitable dopant species.

[0117] At this stage or later, source region 142 and drain region 147 may be formed through upper surface 112 of semiconductor substrate 110. Forming source region 142 and drain region 147 may include forming a sacrificial dielectric layer (e.g., selected from Si) on or above semiconductor substrate 110. 3 N 4 、Al 2 O 3 、SiO 2 , AlN and HfO 2 ). An implantation mask may then be formed on the sacrificial dielectric layer, and dopant species (e.g., one or more selected from Si, Ge, O, or other suitable n-type dopants) may be implanted into the semiconductor substrate 110 through the openings in the implantation mask to form source and drain implantation regions within the semiconductor substrate. The implantation mask may then be removed (e.g., using one or more conventional wet chemical and plasma ashing techniques). The implanted regions may then be activated (e.g., by annealing the semiconductor substrate 110) to form source and drain regions 142, 147. The sacrificial dielectric layer may then be removed (e.g., using wet or dry etching).

[0118] Reference Figure 2and 3 , at block 204 and manufacturing stage 300 ( Figure 3 ), a multi-layer surface passivation layer 130 (including at least a lower surface passivation sublayer 131 and an upper surface passivation sublayer 133) is formed on or above an upper surface 112 of a semiconductor substrate 110. In addition, a multi-layer lowermost interlayer dielectric (ILD0) 134 (including at least a first ILDO sublayer 135, a second ILDO sublayer 136, and a third ILDO sublayer 137) is formed on or above the multi-layer surface passivation layer 130. In order to enhance the ability to distinguish the various sublayers 131, 133, 135, 136, 137, sublayers 133 and 136 are filled with a stippled pattern in some of the figures. The patterning is not meant to imply that sublayers 131, 135, 137 are formed of the same material, or that sublayers 133 and 136 are formed of the same material, but in some embodiments, sublayers 131, 135, 137 may be formed of the same material, or that sublayers 133 and 136 may be formed of the same material.

[0119] According to an embodiment, adjacent pairs of sublayers are formed of different dielectric materials to achieve etching selectivity (e.g., adjacent sublayers may be etched using different etching chemistries to achieve self-alignment of gate channel 162, SFP1 192, and SFP2 194 and formation of a stepped configuration of gate electrode 160 and SFP structure 190). More specifically, sublayer 131 is formed of a different dielectric material than sublayer 133, sublayer 133 is formed of a different dielectric material than sublayer 135, sublayer 135 is formed of a different dielectric material than sublayer 136, and sublayer 136 is formed of a different dielectric material than sublayer 137.

[0120] Specifically, as described below in conjunction with various manufacturing stages, each underlying sublayer 131, 133, 135, 136 can act as an etch stop layer when etching through each overlying sublayer 133, 135 to 137 using any given etching chemistry. For example, as described later, the etching chemistry (or multiple chemistries) used to etch the upper surface passivation sublayer 133 has a high etch selectivity between the materials of the upper surface passivation sublayer 133 and the lower surface passivation sublayer 131. As understood by those skilled in the art, the etch selectivity is the ratio of the etch rates between materials. In the present case, the etch selectivity of the etchant used to etch the upper surface passivation sublayer 133 can be defined as the ratio of the etch rate of the material of the upper surface passivation sublayer 133 ("etch rate 133") to the etch rate of the material of the lower surface passivation sublayer 131 ("etch rate 131") (i.e., the etch selectivity of the etchant used to etch the upper surface passivation sublayer 133 is equal to etch rate 133 / etch rate 131). Additionally, an etchant having a "low selectivity" to a material is configured to etch that material at a relatively high rate, while an etchant having a "high selectivity" to a material is not configured to etch that material at a high rate (or at all).

[0121] The two layers of the surface passivation layer 130 are first formed on the upper surface 112 of the semiconductor substrate 110. The lower surface passivation sublayer 131 is formed directly on the upper surface 112 of the semiconductor substrate 110 (e.g., on the cap layer 109 if it is included, or on the barrier layer 108 if it is not included). According to various embodiments, the lower surface passivation sublayer 131 may have a thickness in the range of about 50 angstroms to about 1000 angstroms, but the layer 131 may also be thinner or thicker.

[0122] According to some embodiments, the lower surface passivation sublayer 131 may be made of silicon nitride (Si 3 N 4 , including silicon-rich or silicon-poor compositions thereof), but alternatively, layer 131 may be formed of another dielectric material. The lower surface passivation sublayer 131 may be formed using low pressure chemical vapor deposition (LPCVD), but alternatively, layer 131 may be formed using a different deposition method (e.g., atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), metal organic CVD (MOCVD), molecular beam epitaxy (MBE), inductively coupled plasma (ICP) deposition, electron cyclotron resonance (ECR) deposition, plasma enhanced ALD (PEALD) or other suitable techniques).

[0123] According to an embodiment, the upper surface passivation sublayer 133 is formed directly on the lower surface passivation sublayer 131. According to various embodiments, the upper surface passivation sublayer 133 can have a thickness in the range of about 50 angstroms to about 1000 angstroms, but layer 133 can also be thinner or thicker. Therefore, in one or more embodiments, the total thickness of the surface passivation layer 130 (including the thickness of sublayers 131 and 133) can be between about 100 angstroms and about 2000 angstroms, but other thicknesses can be used.

[0124] According to some embodiments, the upper surface passivation sublayer 133 may be made of aluminum oxide (Al 2 O 3 ) or aluminum nitride (AlN), but alternatively, layer 133 may be formed of another dielectric material (e.g., Si 3 N 4 or HfO 2 ) is formed. The upper surface passivation sublayer 133 can be formed using sputtering, ALD or PEALD and / or using different deposition methods (e.g., LPCVD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition or other suitable techniques). Forming the upper surface passivation layer 133 completes the formation of the surface passivation layer 130. According to various embodiments, the material of the layers 131, 133 is mainly a high-k dielectric material, which is configured to provide high dielectric withstand voltage capability for low equivalent oxide thickness.

[0125] The three layers of ILD0 134 are then formed on the surface passivation layer 130. According to an embodiment, a lower ILD0 sublayer 135 is formed directly on the upper surface passivation sublayer 133. According to various embodiments, the lower ILD0 sublayer 135 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, although the layer 135 may also be thinner or thicker.

[0126] According to an embodiment, and as indicated above, the lower ILD0 sublayer 135 is etched at a rate that is lower than the upper surface passivation sublayer 133 when exposed to an etch chemistry that will subsequently be used to etch the lower ILD0 sublayer 135 (e.g., as later described in conjunction with blocks 206 and Figure 4 For example, and in accordance with some embodiments, the lower ILD0 sublayer 135 may be formed of silicon nitride (Si 3 N 4 , including its silicon-rich or silicon-poor composition) or other suitable materials. The lower ILD0 sublayer 135 can be formed using LPCVD and / or using different deposition methods (e.g., sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition or other suitable techniques).

[0127] According to an embodiment, middle ILD0 sublayer 136 is formed directly on lower ILD0 sublayer 135. According to various embodiments, middle ILD0 sublayer 136 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, although layer 136 may also be thinner or thicker.

[0128] According to an embodiment, and as indicated above, the middle ILD0 sublayer 136 is etched at a rate compared to the lower ILD0 sublayer 135 when exposed to an etch chemistry that will subsequently be used to etch the middle ILD0 sublayer 136 (e.g., as later described in conjunction with blocks 216 and Fig.10 For example, and in accordance with some embodiments, the middle ILD0 sublayer 136 may be made of silicon dioxide (SiO 2 ) or other suitable materials. The intermediate ILD0 sublayer 136 may be formed using LPCVD and / or using different deposition methods (eg, sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition or other suitable techniques).

[0129] According to an embodiment, upper ILD0 sublayer 137 is formed directly on middle ILD0 sublayer 136. According to various embodiments, upper ILD0 sublayer 137 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, although layer 137 may also be thinner or thicker. Thus, in one or more embodiments, the total thickness of ILD0 134 (including the thickness of sublayers 135-137) may be between about 1500 angstroms and about 6000 angstroms, although other thicknesses may be used.

[0130] According to an embodiment, and as indicated above, the upper ILD0 sublayer 137 is etched at a rate compared to the middle ILD0 sublayer 136 when exposed to an etch chemistry that will subsequently be used to etch the upper ILD0 sublayer 137 (e.g., as later described in conjunction with blocks 220 and Fig.13 For example, and in accordance with some embodiments, the upper ILD0 sublayer 137 may be formed of a dielectric material having a very high etch rate. 3 N 4 , including silicon-rich or silicon-poor compositions thereof) or other suitable materials. The upper ILD0 sublayer 137 may be formed using LPCVD and / or using different deposition methods (e.g., sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition or other suitable techniques).

[0131] Reference Figure 1 , 2 and 4, at block 206 and manufacturing stage 400 ( Figure 4), for the source ohmic contact 141 and the drain ohmic contact 146 to be formed ( Figure 1 ) openings 440, 445, 460, 490, gate electrode 160 ( Figure 1 ) and SFP 190( Figure 1 ) are formed through ILD0 134 (but not through the surface passivation layer 130) over the source and drain regions 142, 147 and over the final locations of the gate electrode 160 and SFP 190 using a sequential or simultaneous etching process performed with appropriate selectivity to terminate on the surface passivation layer 130.

[0132] For example, to form openings 440, 445, 460, 490, photoresist layer 410 may be deposited over the upper surface of ILD0 134 (i.e., on the upper surface of ILD0 sublayer 137), and photoresist openings 420 may be formed over (and including) locations where openings 440, 445, 460, 490 in ILD0 134 are to be formed. Figure 1 The various sub-layers 137, 136, 135 of ILD0 134 may then be etched sequentially or simultaneously with appropriate selectivity through the resist openings to terminate on the upper surface passivation sub-layer 133.

[0133] A plurality of dry and / or wet etching techniques may be used to etch the openings 440, 445, 460, 490 through the sub-layers 137, 136, 135. For example, according to various embodiments, the openings 440, 445, 460, 490 may be formed using reactive ion etching (RIE), inductively coupled plasma (ICP) etching, electron cyclotron resonance (ECR) etching, atomic layer etching (ALE), and wet chemical etching. Dry etching may be advantageous over wet etching because dry etching etches substantially anisotropically (i.e., produces substantially vertical sidewalls).

[0134] In one or more embodiments, a single etchant (e.g., a fluorine-based chemistry) may be used to etch through all sub-layers 137, 136, 135 while terminating on the surface passivation sub-layer 133 (e.g., the etchant is present on the Si substrate). 3 N 4 With SiO 2 It has low selectivity among 2 O 3 In other embodiments, multiple etchants may be used to sequentially etch through all sub-layers 137, 136, 135. For example, to etch the upper ILD0 sub-layer 137 (eg, Si 3 N 4) can selectively etch through the upper ILD0 sub-layer 137 and then terminate on the middle ILD0 sub-layer 136. Therefore, the etchant should have high selectivity to the material of the underlying middle ILD0 sub-layer 136 (i.e., the etchant should not be designed to etch a large amount of the underlying middle ILD0 sub-layer 136). After etching through the ILD0 sub-layer 137, the etchant used to etch the middle ILD0 sub-layer 136 (e.g., SiO 2 ) can selectively etch through the middle ILD0 sublayer 136 and then terminate on the lower ILD0 sublayer 135. Therefore, the etchant should have high selectivity to the material of the underlying lower ILD0 sublayer 135 (i.e., the etchant should not be designed to etch a large amount of the underlying lower ILD0 sublayer 135). Finally, the etchant used to etch the lower ILD0 sublayer 135 (e.g., Si 3 N 4 ) can selectively etch through the lower ILD0 sublayer 135 and then terminate on the upper surface passivation sublayer 133. Therefore, the etchant should have high selectivity to the material of the underlying upper surface passivation sublayer 133 (i.e., the etchant should not be designed to etch a large amount of the underlying upper surface passivation sublayer 133).

[0135] According to various embodiments, to etch through the upper ILD0 sublayer 137, a suitable dry etching technique may use, for example but not limited to, a fluorine-based chemistry (e.g., sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ) or one or more of other suitable chemistries). Alternatively, a suitable wet etch chemistry may be used.

[0136] In various embodiments, the middle ILD0 sublayer 136 (eg, SiO 2 ) may then be dry etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a fluorine-based chemistry (e.g., the same as layer 137), a chlorine-based chemistry, or another suitable dry etch chemistry.

[0137] Finally, the lower ILD0 sublayer 135 (eg, Si 3 N 4 ) can then be dry etched using a suitable technique (e.g., RIE, ICP, or ECR) in conjunction with a fluorine-based chemistry (e.g., the same as layer 137) or other suitable dry etch chemistry. Alternatively, a suitable wet etch chemistry can be used. Once the etching process is completed, the patterned photoresist 410 is removed.

[0138] At this stage, if the various materials of the surface passivation layer 130 and ILD0 134 can be retained in the high temperature annealing, the ohmic source region 142 and the ohmic drain region 147 can be processed for self-alignment. Alternatively, in other embodiments, after the passivation layer is removed only in the area of ​​the ohmic source region 142 and the ohmic drain region 147 (e.g., in blocks 212 and Figure 7 In these other embodiments, the self-aligned ohmic doping may be provided by selective epitaxy rather than by ohmic source and drain implantation (ie, omitting source region 142 and drain region 147).

[0139] Reference Figure 1 , 2 and 5, at block 208 and manufacturing stage 500 ( Figure 5 ), and then forming a lower conformal dielectric spacer layer 510 and an upper conformal dielectric spacer layer 520. First, the lower conformal dielectric spacer layer 510 is deposited over the upper surface of the remaining portion of ILD0134, deposited over the portion of the surface passivation layer 130 exposed by the openings 440, 445, 460 and 490 (i.e., the portion of the upper surface passivation layer 133 exposed by the openings 440, 445, 460 and 490), and deposited on the sidewalls of the openings 440, 445, 460 and 490 (i.e., on the sidewalls of the sub-layers 135 to 137 that are etched through). According to various embodiments, the lower conformal dielectric spacer layer 510 may have a thickness in the range of about 50 angstroms to about 300 angstroms, but the layer 510 may also be thinner or thicker. According to some embodiments, the lower conformal dielectric spacer layer 510 may be made of silicon nitride (Si 3 N 4 , including silicon-rich or silicon-poor compositions thereof) or other suitable materials.

[0140] After forming the lower conformal dielectric spacer layer 510, an upper conformal dielectric spacer layer 520 is formed on or over the lower conformal dielectric spacer layer 510, including on all horizontal and vertical surfaces of the lower conformal dielectric spacer layer 510. According to various embodiments, the upper conformal dielectric spacer layer 520 may have a thickness in the range of about 500 angstroms to about 2000 angstroms, but the layer 520 may be thinner or thicker. The upper conformal dielectric spacer layer 520 is formed of a different material than the lower conformal dielectric spacer layer 510 to provide etching selectivity between the two layers 510, 520. According to some embodiments, the upper conformal dielectric spacer layer 520 may be made of silicon dioxide (SiO 2 ) or other suitable materials.

[0141] The lower conformal dielectric spacer layer 510 and the upper conformal dielectric spacer layer 520 can be formed using atomic layer deposition (ALD), which is well suited for forming thin conformal layers, and / or using different deposition methods (e.g., LPCVD, sputtering, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques).

[0142] Reference now Figure 1 , 2 and 6, at block 210 and manufacturing stage 600 ( Figure 6 ), a multi-step etching process is then performed to form multiple layers of dielectric spacers 640, 645, 660, 690 from portions of the lower conformal dielectric spacer layer 510 and the upper conformal dielectric spacer layer 520. For ease of description, and due to the proximity of the dielectric spacers to other features to be formed, dielectric spacer 640 may be referred to as a source dielectric spacer, dielectric spacer 645 may be referred to as a drain dielectric spacer, dielectric spacer 660 may be referred to as a gate dielectric spacer, and dielectric spacer 690 may be referred to as a field plate dielectric spacer 690.

[0143] First, the upper conformal dielectric spacer layer 520 (e.g., SiO 2 ) until the lower conformal dielectric spacer layer 520 is exposed. Figure 6 As shown in , this causes portions of the upper conformal dielectric spacer layer 520 to remain on the vertical sidewalls of the lower conformal dielectric spacer layer 510 , with those remaining portions extending a short distance from the vertical sidewalls above the horizontal surface of the lower conformal dielectric spacer layer 510 .

[0144] For example, the upper conformal dielectric spacer layer 520 may be formed using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a fluorine-based chemistry (e.g., HF or CF 4 +H 2 The etchant should be able to etch the material of the underlying lower conformal dielectric spacer layer 510 (e.g., Si 3 N 4 ) and also has high selectivity to the material of the upper ILD0 sub-layer 137 (e.g., Si 3 N 4 ) has high selectivity (ie, the etchant should not be designed to significantly etch the lower conformal dielectric spacer layer 510 or the upper ILD0 sublayer 137).

[0145] After etching the upper conformal dielectric spacer layer 520, the lower conformal dielectric spacer layer 510 (eg, Si 3 N 4) until the upper surface passivation sublayer 133 is exposed. Figure 6 As shown in , this allows removal of exposed portions of the lower conformal dielectric spacer layer 510 that are not covered by remaining portions of the upper conformal dielectric spacer layer 520 without removing portions of the lower conformal dielectric spacer layer 510 that are covered by remaining portions of the upper conformal dielectric spacer layer 520.

[0146] For example, according to various embodiments, a suitable dry etching technique for etching the lower conformal dielectric spacer layer 510 may use, for example, but not limited to, SF 6 +O 2 CF 4 +O 2 NF 3 +N 2 +O 2 +H 2 or one or more of other suitable chemistries. The etchant should have high selectivity to the material of the remaining portion of the upper conformal dielectric layer 520 and to the material of the upper surface passivation sublayer 133 (i.e., the etchant should not be designed to etch a large amount of the remaining portion of the upper conformal dielectric layer 520 or the upper surface passivation sublayer 133).

[0147] Once the etching process is completed, the multi-layer dielectric spacers 640, 645, 660, 690 remain adjacent to the sidewalls of the openings 440, 445, 460, 490. For example, the gate dielectric spacer 660 is formed on the sidewalls of the ILD0 134 exposed in the gate opening 460, and the field plate dielectric spacer 690 is formed on the sidewalls of the ILD0 134 exposed in the field plate opening 490. Each of the dielectric spacers 640, 645, 660, 690 includes an “L-shaped” portion of the lower conformal dielectric spacer layer 510 and an overlying portion of the upper conformal dielectric spacer layer 520. As shown in the enlarged view of the right field plate spacer 690, for each of the dielectric spacers 640, 645, 660, 690, the "L-shaped" portion of the lower conformal dielectric spacer layer 510 includes a vertical spacer portion 691 that contacts the sidewalls of the ILD0 sublayers 135 to 137 and a horizontal spacer portion 692 that contacts the upper surface passivation sublayer 133. In addition, an overlying portion of the upper conformal dielectric spacer layer 520 (referred to herein as an upper dielectric spacer portion 693) contacts both the vertical spacer portion 691 and the horizontal spacer portion 692. It should be noted here that the thickness of the horizontal spacer portion 692 is less than the thickness of the lower ILD0 sublayer 135 (e.g., the thickness of the portion 692 may be between about 10% and about 90% of the thickness of the lower ILD0 sublayer 135, or between about 30% and about 70% of the thickness of the lower ILD0 sublayer 135).

[0148] Reference Figure 1 , 2 and 7, at block 212 and manufacturing stage 700 ( Figure 7 ), a selective etching process is used to pattern and etch source contact openings 740 and drain contact openings 745 through the surface passivation layer 130 while terminating on the top surface 112 of the semiconductor substrate 110. More specifically, a photoresist layer 710 is applied over the exposed portions of the surface passivation layer 130, the remaining portions of the ILD0134, and the dielectric spacers 640, 645, 660, 690, and the photoresist layer 710 is processed and patterned to form resist openings 720 over the source region 142 and the drain region 147. According to one or more embodiments, the patterned photoresist layer 710 covers the structures between the dielectric spacers 640, 645.

[0149] The portions of the surface passivation sublayers 133, 131 sequentially exposed through the openings 720 are then sequentially etched through the openings 720 to remove the exposed portions of the sublayers 133, 131. At this point, portions of the upper surface 112 of the semiconductor substrate 110 above the source region 142 and the drain region 147 are exposed in the source contact opening 740 and the drain contact opening 745. A plurality of dry and / or wet etching techniques may be sequentially used to etch openings through the upper surface passivation sublayer 133 and the lower surface passivation sublayer 131.

[0150] In various embodiments, the etching method for etching the upper surface passivation sublayer 133 (eg, Al 2 O 3 ) can selectively etch through the upper passivation sublayer 133 and then terminate on the lower passivation sublayer 131. For example, in various embodiments, the upper passivation sublayer 133 can be etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a chlorine-based chemistry (e.g., Cl 2 , CCl 4 , BCl 3 ) or other suitable dry etching chemistry for dry etching. Alternatively, NbF 5 and CCl 4 or Sn(acac) 2 Thermal or plasma ALE can be employed using HF pyridine and HF pyridine. Alternatively, suitable wet etch chemistries for etching the upper passivation sublayer 133 include piranha etch, KOH, NH 4 OH+ or another suitable wet etch chemistry.

[0151] The lower passivation sublayer 131 (eg, Si) may be etched after the etching process for the upper passivation sublayer 133 has been completed. 3 N 4). The lower passivation sublayer 131 may be etched using an etching process and / or etching chemistry that is different from the etching process and / or etching chemistry used to etch the upper passivation sublayer 133. For example, according to various embodiments, a suitable dry etching technique may use, for example, but not limited to, SF 6 CF 4 Or one or more of other suitable chemistries. Alternatively, a suitable wet etching chemistry may be used. The patterned photoresist 710 is retained for the next manufacturing stage.

[0152] Reference Figure 1 , 2 and 8, at block 214 and manufacturing stage 800 ( Figure 8 ), the conductive source contact 141 and the conductive drain contact 146 are formed by the ohmic contact metal 830 above the source region 142 and the drain region 147. According to one or more embodiments, the ohmic contact metal 830 for the conductive source contact 141 and the conductive drain contact 146 can be deposited using a lift-off process. More specifically, the patterned photoresist layer 710 is used as a mask to prevent the ohmic contact metal 830 from being deposited in regions other than above the source region 142 and the drain region 147.

[0153] An ohmic contact metal 830 in the form of a conductive layer or conductive layer stack is deposited over the exposed portions of the source and drain regions 142, 147, the exposed source and drain dielectric spacers 640, 645, and the upper surface of the patterned photoresist layer 710. According to one or more embodiments, the ohmic contact metal 830 may include one or more layers of titanium (Ti), titanium aluminum (TiAl), titanium tungsten (TiW), titanium tungsten nitride (TiWN), and / or other suitable materials. In some embodiments, if etch selectivity is required during subsequent processing steps, a thin layer of gold may be deposited on top of the conductive layer to provide a desired etching selectivity during those subsequent processing steps (e.g., before performing blocks 226 and 230). Fig.16 The photoresist layer 710 is then removed, thereby stripping the portion of the ohmic contact metal 830 that overlies the photoresist layer 710. The portion of the ohmic contact metal 830 that is deposited on the source region 142 and the drain region 147 and the source dielectric spacer 640 and the drain dielectric spacer 645 remains, thereby forming the source contact 141 and the drain contact 146.

[0154] In an alternative embodiment, rather than using a lift-off process to form source contact 141 and drain contact 146, a subtractive process may be used. More specifically, during manufacturing stage 700 ( Figure 7), ohmic contact metal 830 may be deposited directly over the surface of the device, and a photoresist mask (not shown) may be applied over the ohmic contact metal 830 and patterned to cover only those portions of the ohmic contact metal 830 that correspond to the source contact 141 and the drain contact 146. The portions of the ohmic contact metal 830 not covered by the patterned photoresist mask may then be removed, and the patterned photoresist mask removed.

[0155] Reference Figure 1 , 2 , 9 and 10, at block 216 and manufacturing stage 900 ( Fig. 9 , 10 ), a multi-level field plate opening 990 is formed. Fig. 9 To form the field plate opening 990, a photoresist layer 910 may be deposited over the source and drain contacts 141, 146, the upper surface of the ILD0 134, and the dielectric spacers 640, 645, 660, 690. A photoresist opening 920 may then be formed over the location where the field plate opening 990 is to be formed. In accordance with one or more embodiments, the width of the photoresist opening 920 encompasses two field plate dielectric spacers 690 and extends over portions of the ILD0 134 beyond those spacers 690.

[0156] Reference Fig.10 , the upper sublayer 137 and the middle sublayer 136 of the ILD0 134 and the portion of the field plate dielectric spacer 690 may then be sequentially etched through the resist opening 920. A plurality of etching techniques may be used to etch the upper sublayer 137 and the middle sublayer 136 of the ILD0 134 and the portion of the field plate dielectric spacer 690 so as to form the field plate opening 990. For example, according to various embodiments, the field plate opening 990 may be formed using RIE, ICP etching, ECR etching, or other suitable etching techniques.

[0157] According to one or more embodiments, a first etching process is performed to etch the upper ILD0 sublayer 137, at least a portion of the middle ILD0 sublayer 136, the upper dielectric spacer portion 693 of the field plate dielectric spacer 690, and the dielectric spacer 694 of the field plate dielectric spacer 690. Figure 6 ) and at least a portion of the vertical spacer portion 691 ( Figure 6 ). According to one or more embodiments, the etchant used to etch these features is resistant to the material (eg, Si) of the upper ILD0 sublayer 137 and the vertical spacer portion 691. 3 N 4 ) and also the material of the upper dielectric spacer portion 693 (e.g., SiO 2) has low selectivity. Therefore, the etchant is used to etch the material of the upper ILD0 sublayer 137, the vertical spacer portion 691, the middle ILD0 sublayer 136, and the upper dielectric spacer portion 693. According to an embodiment, this etching process is terminated before all the upper dielectric spacer portions 693 have been removed and before all the middle ILD0 sublayer 136 have been removed.

[0158] According to various embodiments, in order to etch through the upper ILD0 sublayer 137, at least a portion of the middle ILD0 sublayer 136, the field plate dielectric spacer 690 ( Figure 6 ) and at least a portion of the upper dielectric spacer portion 693 of the field plate dielectric spacer 690 ( Figure 6 ) at least a portion of the vertical spacer portion 691, a suitable dry etching technique may be used, such as but not limited to SF 6 CF 4 or one or more of other suitable chemistries. In one or more embodiments, the process may include a timed etch designed to terminate before reaching the horizontal spacer portion 692 of the field plate dielectric spacer 690 .

[0159] After the first etching process is terminated, a second anisotropic etching process is performed to etch the middle ILD0 sub-layer 136 (eg, SiO 2 ) (terminating on the lower ILD0 sublayer 136), while also etching the upper dielectric spacer portion 693 (e.g., also SiO 2 ) (terminating at the horizontal spacer portion 692 of the field plate dielectric spacer 690 ( Figure 6 According to one or more embodiments, in various embodiments, the middle ILD0 sublayer 136 and the remaining portion of the upper dielectric spacer portion 693 may be formed using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a fluorine-based chemistry (e.g., HF, C 3 F 8 , C 2 F 6 +H 2 CF 4 +H 2 ) or other suitable dry etching chemistry for dry etching. Alternatively, suitable wet etching chemistry for etching the remaining portion of the middle ILD0 sublayer 136 and the upper dielectric spacer portion 693 includes HF, buffered HF, KOH, or another suitable wet etching chemistry. The patterned photoresist layer 910 can be retained for use in the next manufacturing stage (i.e., Fig.11 stage 1000).

[0160] Once formed, the field plate opening 990 has a first (lowest) horizontal bottom extent 992, left and right second (middle) horizontal bottom extents 994, and left and right third (higher) horizontal bottom extents 996. The first horizontal bottom extent 992 is defined by the exposed surface of the surface passivation sublayer 133, and the bottom extent 992 is separated from the upper surface 112 of the semiconductor substrate 110 by a first thickness of dielectric material (e.g., the thickness of the surface passivation layer 130). The second horizontal bottom extent 994 is defined by the upper surface of the horizontal spacer portion 692 of the field plate dielectric spacer 690, and is separated from the upper surface 112 by a thicker dielectric material (e.g., the thickness of the surface passivation layer 130 plus the thickness of the horizontal spacer portion 692). Finally, the third horizontal bottom extent 996 is defined by the upper surface of the lower ILD0 sublayer 135, and is separated from the upper surface 112 by a still thicker dielectric material (e.g., the thickness of the surface passivation layer 130 and the lower ILD0 sublayer 135). In other words, each of the bottom extents 992 , 994 , 996 of the field plate opening 990 has increasingly thicker underlying dielectric material (ie, the horizontal bottom extents 992 , 994 , 996 become increasingly farther from the upper surface 112 of the semiconductor substrate 110 ).

[0161] Reference Figure 1 , 2 and 11, at block 218 and manufacturing stage 1000 ( Fig.11 ), the multi-step field plate 190 is then formed by the field plate metal 1030 within the field plate opening 990. According to one or more embodiments, a lift-off process may be used to deposit the field plate metal 1030. More specifically, the patterned photoresist layer 910 is used as a mask to prevent the field plate metal 1030 from being deposited in areas other than the location of the field plate 190 to be formed during the lift-off process.

[0162] A field plate metal 1030 in the form of a conductive layer or conductive layer stack may then be deposited within the field plate opening 990 and on the upper surface of the remaining portion of the patterned photoresist layer 910. According to one or more embodiments, the field plate metal 1030 may include one or more layers of Ti, TiW, TiAl, TiWN, Au, Al, Mo, Ni, polysilicon, Pt, Ta, combinations of these materials, or other suitable materials. The bottommost conductive layer may serve as an adhesion layer. In some embodiments, if etch selectivity is required during subsequent processing steps, a thin layer of gold may be deposited on top of the conductive layer to provide a desired adhesion layer during those subsequent processing steps (e.g., before performing blocks 226 and 230). Fig.16 The photoresist layer 910 is then removed, thereby stripping the portion of the field plate metal 1030 that overlies the photoresist layer 910. The portion of the field plate metal 1030 that is deposited within the field plate opening remains, thereby forming a conductive field plate 190.

[0163] In an alternative embodiment, rather than using a lift-off process to form the conductive field plate 190, a subtractive process may be used. More specifically, during the manufacturing stage 900 ( Fig.10 ), a field plate metal 1030 can be deposited directly over the surface of the device, and a photoresist mask (not shown) can be applied over the field plate metal 1030 and patterned to cover only those portions of the field plate metal 1030 that correspond to the field plates 190. Portions of the field plate metal 1030 not covered by the patterned photoresist mask can then be removed, and the patterned photoresist mask can then be removed.

[0164] As previously discussed, the SFP structure 190 has a stepped configuration including a first SFP 192 (SFP1), a second SFP 194 (SFP2), and a third SFP 196 (SFP3). The second SFP 194 and the third SFP 196 may be arranged generally symmetrically (or asymmetrically) on both sides of the first SFP 192. In other words, one of the second SFPs 194 is located on the gate side of the SFP structure 190, and another of the second SFPs 194 is located on the drain side of the SFP structure 190. Similarly, one of the third SFPs 196 is located on the gate side of the SFP structure 190, and another of the third SFPs 196 is located on the drain side of the SFP structure 190. In other words, the second SFP 194 and the third SFP 196 protrude upward and outward from the SFP1 192 on both sides (ie, the gate side and the drain side) of the SFP1 192 .

[0165] The first SFP 192 has a bottom range (e.g., Fig. 9 The second SFP 194 has a bottom range (e.g., Fig. 9 The bottom extent of the second SFP 194 is separated from the upper surface 112 by a thicker dielectric material (e.g., the thickness of the surface passivation layer 130 plus the thickness of the horizontal spacer portion 692). More specifically, the horizontal bottom extent of the second SFP 194 overlies and contacts the upper surface of the horizontal spacer portion 692, while the first SFP 192 contacts the sidewalls of the horizontal spacer portion 692. Finally, the third SFP 196 has a bottom extent (e.g., Fig. 9The bottom range 996 of the SFP 192 is separated from the upper surface 112 by a still thicker dielectric material (e.g., the thickness of the surface passivation layer 130 and the lower ILD0 sublayer 135). In other words, each of the bottom ranges of the SFPs 192, 194, 196 has an increasingly thicker underlying dielectric material (i.e., the horizontal bottom ranges 992, 994, 996 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). As previously mentioned, the second SFP 194 and the third SFP 196, each having an increasingly thicker underlying dielectric material (i.e., increasingly higher horizontal bottom ranges), are provided to weaken the electric field at the edge of the first SFP 192 so as to ensure dielectric reliability and high breakdown voltage.

[0166] Reference Figure 1 , 2 , 12 and 13, at block 220 and manufacturing stage 1100 ( Fig.12 , 13 ), a multi-level gate electrode opening 1160 is formed. First, refer to Fig.12 To form the gate electrode opening 1160, a photoresist layer 1110 may be deposited over the source and drain contacts 141, 146, the upper surface of the ILD0 134, and the dielectric spacers 660, and a photoresist opening 1120 may be formed over the location where the gate electrode opening 1160 is to be formed. According to one or more embodiments, the width of the photoresist opening 1120 encompasses two gate dielectric spacers 660 and extends beyond those spacers 660 over a portion of the ILD0 134.

[0167] Reference Fig.13 In order to form the gate electrode opening 1160, various features and layers are removed through the resist opening 1120. More specifically, several etching processes may be performed to remove the gate dielectric spacers 660 and the portions of the surface passivation layer 130 exposed between the gate dielectric spacers 660. All or a portion of the upper sublayer 137 of the ILD0 134 exposed through the resist opening 1120 may also be removed in the process.

[0168] Various dry and / or wet etching techniques may be used to etch these features in order to form the gate electrode opening 1160. For example, according to various embodiments, the gate electrode opening 1160 may be formed using RIE, ICP etching, ECR etching, and wet chemical etching.

[0169] According to one or more embodiments, a first etching process is performed to etch the portion of the upper surface passivation sublayer 133 exposed between the gate dielectric spacers 660 while terminating on the lower surface passivation sublayer 131. According to an embodiment, the etchant used to etch the exposed portion of the upper surface passivation sublayer 133 is preferably applied to the upper dielectric spacer portion 693 (e.g., SiO2) of the gate dielectric spacer 660. 2 )( Figure 6 ) and the upper ILD0 layer 137, the vertical portion 691 and the horizontal portion 692 of the L-shaped spacer ( Figure 6 ) and the exposed material of the underlying lower surface passivation sublayer 131 are selectively etched to etch the upper surface passivation sublayer 133 (eg, Al 2 O 3 ) materials. The etching should be controlled to stop before etching all the way through the lower surface passivation sublayer 131. Some loss of these materials can be tolerated. After the etching process is completed, the remaining portion of the lower surface passivation sublayer 131 will be exposed between the remaining portions of the gate dielectric spacer 660, and the vertical spacer portion 691 and the horizontal spacer portion 692 ( Figure 6 ) remain generally intact.

[0170] To etch through the exposed upper surface passivation sublayer 133, RIE, ICP etching, ECR etching, and wet chemical etching may be used. According to various embodiments, suitable dry etching techniques may use, for example, but not limited to, fluorine-based chemistries (e.g., C 4 F 8 ), chlorine-based chemicals (e.g., BCl 3 ) or another suitable dry etch chemistry. Additionally or alternatively, a suitable wet etch chemistry may be used. After exposing the substrate surface 112 between the horizontal portions 692 of the spacer, the remaining portion of the upper dielectric spacer portion 693 ( Figure 6 ) can be used, for example, for SiO 2 The HF plasma etching or HF-based wet etching can be used to remove it.

[0171] Subsequently, a second etching process is performed to etch the portion of the lower surface passivation sublayer 131 exposed between the remaining portion of the gate dielectric spacer 660 and the underlying portion of the remaining upper surface passivation layer 133 acting as a hard mask for the gate channel, and also to etch the remaining portion of the gate dielectric spacer 660 and some or all of the upper ILD0 sublayer 137, thereby terminating on the middle ILD0 sublayer 136. Some portions of the upper ILD0 sublayer 137 may remain. In order to etch the lower surface passivation sublayer 131, the remaining portion of the gate dielectric spacer 660, and the upper ILD0 sublayer 137, RIE, ICP etching, ECR etching, and wet chemical etching may be used. According to an embodiment, a suitable dry etching technique may be used, such as, but not limited to, SF etching. 6 +O 2 CF 4 +O 2 NF 3 +N 2 +O 2 +H 2 Or one or more of other suitable chemistries. Alternatively, a suitable wet etch chemistry may be used.

[0172] Once formed, the gate electrode opening 1160 has a first (lowest) horizontal bottom extent 1162, left and right second (middle) horizontal bottom extents 1164, and left and right third (higher) horizontal bottom extents 1166. The first horizontal bottom extent 1162 is defined by an exposed portion of the upper surface 112 of the semiconductor substrate 110. The second horizontal bottom extent 1164 is defined by the surface of the upper surface passivation sublayer 133 and is separated from the upper surface 112 by a first thickness of dielectric material (e.g., the thickness of the surface passivation layer 130). Finally, the third horizontal bottom extent 1166 is defined by the surface of the middle ILD0 sublayer 136 and is separated from the upper surface 112 by a thicker dielectric material (e.g., the thickness of the surface passivation layer 130, the lower ILD0 sublayer 135, the middle ILD0 sublayer 136, and the possible remaining portion of the upper ILD0 sublayer 137). In other words, each of the bottom extents 1164, 1166 of the gate electrode opening 1160 has an increasingly thicker underlying dielectric material (i.e., the horizontal bottom extents 1164, 1166 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). The patterned photoresist layer 1110 may be retained for use in the next manufacturing stage (i.e., Fig.14 stage 1200).

[0173] Reference Figure 1 , 2 and 14, at block 222 and manufacturing stage 1200 ( Fig.14), and then forming a multi-step gate electrode 160. According to one or more embodiments, a stripping resist process may be used to form the gate electrode 160. A previously deposited and patterned photoresist layer 1110 may be utilized for this process. A gate metal layer 1210 is deposited over the photoresist layer 1110 and into the gate electrode opening 1160. In one or more embodiments, the various layers of the gate metal layer 1210 may be deposited by evaporation, sputtering, PVD, ALD, or other suitable deposition techniques.

[0174] The conductive layer of the gate metal layer 1210 may include Au, Ag, Al, Cu, Ti, Ni, Pt, and / or other substantially conductive materials. In essence, a Schottky contact is formed in the gate channel (i.e., the portion of the gate electrode 160 closest to the upper surface 112 of the semiconductor substrate 110). The thickness of the conductive layer of the gate metal layer 1210 may be between about 1000 angstroms and about 20,000 angstroms, but other thickness values ​​may be used. According to one or more embodiments, the thickness of the gate metal layer 1210 is greater than the cumulative thickness of the surface passivation layer 130 and the ILD0 134.

[0175] Once the gate metal layer 1210 is deposited, a stripping process is then performed to remove the photoresist layer 1110 and the portion of the gate metal layer 1210 deposited on the photoresist layer 1110 while leaving the portion of the gate metal layer 1210 deposited into the gate electrode opening 1160 intact.

[0176] In an alternative embodiment, rather than using a lift-off process to form gate electrode 160, a subtractive process may be used. More specifically, during manufacturing stage 1100 ( Fig.13 ), a gate metal layer 1210 may be deposited directly over the surface of the device, and a photoresist mask (not shown) may be applied over the gate metal layer 1210 and patterned to cover only those portions of the gate metal layer 1210 that correspond to the gate electrode 160. Portions of the gate metal layer 1210 not covered by the patterned photoresist mask may then be removed, and the patterned photoresist mask removed.

[0177] As previously discussed, the gate electrode 160 has a stepped configuration including the gate channel portion 162 and the first GFP 164 and the second GFP 166 that are generally symmetrically (or asymmetrically) arranged on both sides of the gate channel portion 162. In other words, one of the first GFPs 164 is located on the drain side of the gate electrode 160, and the other of the first GFPs 164 is located on the source side of the gate electrode 160. Similarly, one of the second GFPs 166 is located on the drain side of the gate electrode 160, and the other of the second GFPs 166 is located on the source side of the gate electrode 160. In other words, the first GFP 164 and the second GFP 166 protrude upward and outward from the gate channel portion 162 on both sides (i.e., the source side and the drain side) of the gate electrode 160.

[0178] The gate channel portion 162 is located at the gate channel and has a horizontal bottom extent that defines the lowermost portion of the gate electrode 160 (i.e., the portion that contacts or is closest to the upper substrate surface 112). The first GFP 164 (GFP1) is formed integrally with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extent of the gate channel portion 162. More specifically, GFP1 164 overlies and contacts the upper surface of the surface passivation sublayer 133. The second GFP 166 (GFP2) is also formed integrally with the gate channel portion 162 and has a horizontal bottom extent that is higher than the bottom extents of both the gate channel portion 162 and GFP1 164. More specifically, GFP2 166 overlies and contacts the upper surface of the intermediate ILD0 sublayer 136. As can be seen in FIG. Fig.14 As can be seen in FIG. 1 , the gate electrode 160 has a relatively large cross-sectional area, which can result in a relatively low gate resistance R G , without causing the gate-drain capacitance C GD or gate-source capacitance C GS significant increase.

[0179] It may be noted here that in one or more embodiments, the bottom extents of SFP1 192, SFP2 194, and SFP3 196 may all be recessed relative to the bottom extent of GFP2 166 (i.e., SFP1 192, SFP2 194, and SFP3 196 may all have an underlying dielectric that is thinner than the dielectric below GFP2 166). This may cause C GD The lower gate-drain capacitance C GD This in turn may result in an increase in the gain of the device 100 .

[0180] Reference Figure 1 , 2 and 15, at block 224 and manufacturing stage 1300 ( Fig.15), a second interlayer dielectric (ILD1) 150 is deposited over ILD0 134, gate electrode 160, and field plate 190. In various embodiments, the dielectric material for ILD1 150 may be the same as or different from the dielectric material for ILD0 134. Preferably, the dielectric material for ILD1 150 is a low-k dielectric material different from the material of ILD0 top sublayer 137 in order to provide etching selectivity. For example, the material for ILD1 150 may be selected from SiO 2 , organic silicate glass, porous SiO 2 、Si 3 N 4 、SiON、HfO 2 、Al 2 O 3 or AlN and other suitable materials. ILD1 150 may be formed using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. In various embodiments, ILD1 150 may have a thickness in the range of about 0.2 microns to about 2.0 microns, but ILD1 150 may also be thinner or thicker.

[0181] Reference Figure 1 , 2 and 16, at block 226 and manufacturing stage 1400 ( Fig.16 ), a selective etching process is used to form an opening 1490 through ILD1 150 to expose the field plate 190. At the same time, an opening is also formed through ILD1 150 to expose the source ohmic contact 141 and the drain ohmic contact 146, but Fig.16 Those openings are not shown in FIG. 1 because they are located at Fig.16 14. For the location of the openings through ILD1 150 to the source ohmic contact 141 and the drain ohmic contact 146, see Figure 1 .

[0182] To form field plate opening 1490, photoresist layer 1410 is applied over ILD1 150, and photoresist layer 1410 is processed and patterned to form photoresist opening 1420 having a first side 1421 aligned along the width of field plate 190, and a second side 1422 aligned over a point along ILD0 134 to the right of the rightmost edge of field plate 190. Additionally, source opening and drain opening (see Figure 1 ) is formed through the photoresist layer 1410 above the source contact 141 and the drain contact 146.

[0183] The portion of ILD1 150 exposed by opening 1420 is then etched through opening 1420 to remove the exposed portion of ILD1 150. The etching process continues until field plate 190 is fully exposed and reaches portion 1434 of the upper surface of ILD0 134 (i.e., the etching process terminates on the upper surface of ILD0 134). This process creates an unfilled field plate opening 1490 above field plate 190. The bottom extent of field plate opening 1490 is defined by the upper surface of field plate 190 and the exposed portion 1434 of ILD0 134.

[0184] A variety of dry and / or wet etching techniques may be used to etch the opening through the ILD1 150. For example, according to various embodiments, the ILD1 150 may be etched using RIE, ICP etching, ECR etching, and wet chemical etching.

[0185] Reference Figure 1 , 2 and 17, at block 228 and manufacturing stage 1500 ( Fig.17 ), remove the photoresist 1410 ( Fig.16 ), and depositing metallization over ILD1 150 (and into the source opening, drain opening, and field plate opening through ILD1 150) to form source electrode 140 ( Figure 1 )、Drain electrode 145( Figure 1 )、Source metallization 148( Figure 1 ) and drain metallization 149 ( Figure 1 ). In the field plate opening 1490 ( Fig.16 ), source metallization 148 contacts field plate 190 and extends over ILD1 150 to source contact 141 to provide a conductive field plate to source connection. In addition, source metallization 148 contacts portion 1434 of the upper surface of ILD0 134 ( Fig.16), which forms a fourth source connection field plate SFP4 198 having a horizontal bottom extent extending beyond the right edge of the field plate 190. According to one or more embodiments, SFP4 198 is separated from the upper surface 112 of the semiconductor substrate 110 by an even thicker dielectric (e.g., the cumulative thickness of the surface passivation layer 130 and the ILD0 134) than the dielectrics below the other field plates (SFP1 192, SFP2 194, SFP3 196). In addition, SFP4 198 is higher than GFP2 166 (i.e., SFP4 198 has a thicker underlying dielectric than GFP2 166). Further, the source metallization 148 contacts the upper surface of the ILD1 150, which forms a fifth source connection field plate SFP5 199 having a horizontal bottom extent extending beyond the right edge of the field plate 190. According to one or more embodiments, SFP5 199 is separated from the upper surface 112 of the semiconductor substrate 110 by an even thicker dielectric (eg, the cumulative thickness of the surface passivation layer 130, ILD0 134, and ILD1 150). This higher SFP5 199 may be particularly beneficial for high voltage devices.

[0186] For example, for forming the source electrode 140 ( Figure 1 )、Drain electrode 145( Figure 1 ) and source metallization 148 and drain metallization 149 ( Figure 1 ) may be blanket deposited and etched, or may be deposited using a lift-off process. More specifically, a patterned multilayer conductive stack may be formed over ILD1 150. According to various embodiments, the conductive stack may include one or more metal layers and / or other suitable materials. In some embodiments, the first layer within the multilayer stack may include an adhesion layer (e.g., TiW or another suitable material), and additional layers may include gold (Au) and other suitable metals.

[0187] Reference again Figure 1 In block 230, the final passivation layers 170 and 180 ( Figure 1 ) to complete the device 100. For example, the passivation layer 170 can be made of Si 3 N 4 The passivation layers 170, 180 may be formed of polybenzoxazole (PBO) or another suitable material. The passivation layers 170, 180 may be deposited, for example, using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. Additional patterned conductive layers and dielectric layers may be formed over the passivation layers 170, 180, openings may be formed through each of the dielectric layers, and one or more intervening patterned conductive layers may be formed to enable electrical connectivity with other device elements.

[0188] Example 2 Figures 18 to 31 ):

[0189] Figure 2 Will be used again to describe Figure 1 The manufacturing steps of the second embodiment of the GaN HFET 100 portion 101 are as follows. These manufacturing steps are Figures 18 to 31 More specifically, Figures 18 to 31 Included are cross-sectional side views of embodiments of portions of additional embodiments identified as GaN HFET devices 100 ′ during various sequences of fabrication steps.

[0190] Device 100( Figure 1 , 17 ) and device 100'( Fig.31 ) is that for device 100', the surface passivation layer comprises only one layer 133 (rather than two sub-layers 131, 133 as in device 100). The surface passivation layer 133 in device 100' enables the lowermost extent of SFP structure 190' to be recessed at least below GFP2 166, but using a simpler and less expensive process than the above-described embodiments.

[0191] Another difference between the device 100' and the previously discussed device 100 is that the SFP structure 190' ( Fig.31 ) is formed from source metallization 148, rather than including a separate field plate metal (e.g., Fig.11 The field plate 190 is formed of a metal 1030 of the source metal. Using the source metallization 148 to form the SFP structure 190' results in a simpler and cheaper process than the above-described embodiment.

[0192] First reference Figure 1 and 2 In block 202, fabrication of an alternative embodiment of the GaN HFET device 100' begins by providing a semiconductor substrate 110 in which ohmic source and drain implants (e.g., source region 142 and drain region 147) have been formed. The description above in conjunction with forming the first embodiment of the device 100 (i.e., Figure 3The details associated with providing the semiconductor substrate 110 and forming the ohmic source and drain implants are discussed in detail in the description of manufacturing stage 300 of ) described above. For the sake of brevity, those details are not repeated here, but instead, those details are intended to be incorporated into the description of forming the device 100' and this second embodiment. Briefly, providing the semiconductor substrate 110 includes providing a main substrate 102 and forming various semiconductor layers (e.g., a nucleation layer (not shown), a buffer layer 104, a channel layer 106, a barrier layer 108, and optionally, a cap layer 109) on or above an upper surface 104 of the main substrate 102. Embodiments of the method may optionally include forming doped (e.g., ion implanted) source regions 142 and drain regions 147 ( Figure 1 ), as also described above in conjunction with the manufacturing stage 300 and Figure 3 Discussed.

[0193] Reference Figure 2 and 18 , at block 204 and manufacturing stage 300'( Fig.18 ), a single surface passivation layer including surface passivation layer 133 is formed on or over upper surface 112 of semiconductor substrate 110. In addition, a multi-layer lowermost interlayer dielectric (ILD0) 134 (including at least first ILD0 sublayer 135, second ILD0 sublayer 136, and third ILD0 sublayer 137) is formed on or over surface passivation layer 133. According to an embodiment, adjacent pairs of layers 133, 135 to 137 are formed of different dielectric materials to achieve etching selectivity.

[0194] The surface passivation layer 133 is first formed directly on the upper surface 112 of the semiconductor substrate 110 (e.g., on the cap layer 109 if the cap layer 109 is included, or on the barrier layer 108 if the cap layer 109 is not included). The thickness of the surface passivation layer 133 can be in the range of about 50 angstroms to about 1000 angstroms, but the layer 133 can be thinner or thicker. According to some embodiments, the surface passivation layer 133 can be made of aluminum oxide (Al 2 O 3 ) or aluminum nitride (AlN), but alternatively, layer 133 may be formed of another dielectric material (eg, HfO 2 ) is formed. Figure 3 The description of the manufacturing stage 300 of discusses in detail the details associated with forming the surface passivation layer 133 (e.g., the surface passivation sublayer 133), and those details are intended to be incorporated herein. According to various embodiments, the material of the surface passivation layer 133 is a high-k dielectric material that is configured to provide high dielectric withstand voltage capability for low equivalent oxide thickness.

[0195] The three sub-layers of ILD0 134 are then formed on the surface passivation layer 133. Figure 3 The description of the manufacturing stage 300 of 134 discusses in detail the details associated with the materials, material properties, thicknesses and methods of forming the three sub-layers of ILD0 134, and those details are intended to be incorporated herein. Briefly, the lower ILD0 sub-layer 135 may be made of silicon nitride (Si 3 N 4 , including its silicon-rich or silicon-poor composition), the middle ILD0 sublayer 136 may be made of silicon dioxide (SiO 2 ) is formed, and the upper ILD0 sub-layer 137 can be made of silicon nitride (Si 3 N 4 , including silicon-rich or silicon-poor compositions thereof), but any of these sub-layers 135 to 137 may be formed of other suitable materials. Each of the ILD0 sub-layers 135 to 137 may be formed using LPCVD, sputtering, ALD, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. In addition, each of the ILD0 sub-layers 135 to 137 may have a thickness in the range of about 500 angstroms to about 2000 angstroms, such that the ILD0 134 has a thickness in the range of about 150 angstroms to about 6000 angstroms.

[0196] Reference Figure 1 , 2 and 19, at block 206 and manufacturing stage 400'( Fig.19 ), for the source ohmic contact 141 and the drain ohmic contact 146 to be formed ( Figure 1 ) of the openings 440, 445, 460, 490, the gate electrode 160' ( Fig.28 ) and SFP190'( Fig.31 ) is formed using a sequential selective etching process to pass through ILD0 134 (but not through the surface passivation layer 133) over the source and drain regions 142, 147 and over the final locations of the gate electrode 160' and SFP 190'.

[0197] Combination of the above Figure 4 The description of the manufacturing stage 400 of 134 discusses in detail the details associated with the method of forming the openings 440, 445, 460, 490 through the ILD0 134, and those details are intended to be incorporated herein. Briefly, a plurality of dry and / or wet etching techniques may be used to etch the openings 440, 445, 460, 490 through the opening 420 in the patterned photoresist layer 410 deposited above the upper surface of the ILD0 134.

[0198] At this stage, if the various materials of the surface passivation layer 133 and ILD0 134 can be retained in the high temperature annealing, the ohmic source region 142 and the ohmic drain region 147 can be processed for self-alignment. Alternatively, after the passivation layer is removed only in the area of ​​the ohmic source region 142 and the ohmic drain region 147 (e.g., in blocks 212 and Fig. 22 After the manufacturing stage 700') self-aligned ohmic doping is provided by selective epitaxy.

[0199] Reference Figure 1 , 2 and 20, at block 208 and manufacturing stage 500'( Fig. 20 ), then forming a lower conformal dielectric spacer layer 510 and an upper conformal dielectric spacer layer 520. Figure 5 The description of the manufacturing stage 500 of the embodiment discussed in detail the details associated with the materials, material properties, thicknesses and methods of forming the lower conformal dielectric spacer layer 510 and the upper conformal dielectric spacer layer 520, and those details are intended to be incorporated herein. Briefly, the lower conformal dielectric spacer layer 510 can be made of silicon nitride (Si 3 N 4 , including silicon-rich or silicon-poor compositions thereof), and the upper conformal dielectric spacer layer 520 may be made of silicon dioxide (SiO 2 ), but other suitable materials may be used to form either of the layers 510, 520. Each of the conformal dielectric spacer layers 510, 520 may be formed using ALD, LPCVD, sputtering, PEALD, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. Additionally, the lower conformal dielectric spacer layer 510 may have a thickness in a range of about 50 angstroms to about 300 angstroms, and the upper conformal dielectric spacer layer 520 may have a thickness in a range of about 500 angstroms to about 2000 angstroms, but other thicknesses may be used.

[0200] Reference Figure 1 , 2 and 21, at block 210 and manufacturing stage 600'( Fig.21 ), a multi-step etching process is then performed to form multi-layer dielectric spacers 640, 645, 660, 690 from portions of the lower conformal dielectric spacer layer 510 and the upper conformal dielectric spacer layer 520. Figure 6The description of the manufacturing stage 600 of the present invention discusses in detail the details associated with the method of forming the spacers 640, 645, 660 and 690, and those details are intended to be incorporated herein. Briefly, a plurality of dry and / or wet etching techniques may be used to form the multi-layer dielectric spacers 640, 645, 660, 690 adjacent to the sidewalls of the openings 440, 445, 460, 490. As previously discussed, each of the dielectric spacers 640, 645, 660, 690 includes an "L-shaped" portion of a lower conformal dielectric spacer layer 510 and an overlying portion of an upper conformal dielectric spacer layer 520.

[0201] Reference Figure 1 , 2 and 22, at block 212 and manufacturing stage 700'( Fig. 22 ), a selective etching process is used to pattern and etch source contact openings 740' and drain contact openings 745' through the surface passivation layer 130' while terminating on the top surface 112 of the semiconductor substrate 110. More specifically, a photoresist layer 710 is applied over the exposed portions of the surface passivation layer 133, the remaining portions of the ILD0 134, and the dielectric spacers 640, 645, 660, 690, and the photoresist layer 710 is processed and patterned to form resist openings 720 over the source region 142 and the drain region 147. According to one or more embodiments, the patterned photoresist layer 710 covers the structures between the dielectric spacers 640, 645.

[0202] The portions of the surface passivation layer 133 exposed through the openings 720 are then etched through the openings 720 to remove the exposed portions of the layer 133. At this point, portions of the upper surface 112 of the semiconductor substrate 110 above the source and drain regions 142, 147 are exposed in the source contact openings 740' and the drain contact openings 745'. Dry and / or wet etching techniques may be used to etch the openings through the surface passivation layer 133.

[0203] In various embodiments, the surface passivation layer 133 (eg, Al 2 O 3 The etchant of AlN (or AlN) can selectively etch through the surface passivation layer 133 and then stop on the upper surface 112 of the semiconductor substrate 110. For example, in various embodiments, the surface passivation layer 133 can be etched using a suitable technique (e.g., RIE, ICP, or ECR) in combination with a chlorine-based chemistry (e.g., Cl 2 , CCl 4 , BCl 3 ) or other suitable dry etching chemistry for dry etching. Alternatively, NbF 5 and CCl 4or Sn(acac) 2 Thermal or plasma ALE can be employed using HF pyridine and HF pyridine. Alternatively, suitable wet etch chemistries for etching the upper passivation sublayer 133 include piranha etch, KOH, NH 4 OH+ or another suitable wet etch chemistry. The patterned photoresist 710 is retained for the next manufacturing stage.

[0204] Reference Figure 1 , 2 and 23, at block 214 and manufacturing stage 800'( Fig.23 ), the conductive source contact 141 and the conductive drain contact 146 are formed by the ohmic contact metal 830 above the source region 142 and the drain region 147. Figure 8 The description of manufacturing stage 800 of discusses in detail the details associated with the method of forming the conductive source contact 141 and the conductive drain contact 146, and those details are intended to be incorporated herein. Briefly, using a lift-off process, the ohmic contact metal 830 for the conductive source contact 141 and the conductive drain contact 146 may be deposited on the surface of the patterned photoresist layer 710 and through the opening 720 in the photoresist layer 710, and then the photoresist layer 710 may be removed. Alternatively, rather than using a lift-off process to form the source contact 141 and the drain contact 146, a subtractive process may be used. Either way, the ohmic contact metal 830 may include one or more layers of Ti, TiAl, TiW, TiWN, and / or other suitable materials. In some embodiments, if etching selectivity is required during subsequent processing steps, a thin layer of gold may be deposited on top of the conductive layer to provide a desired etching selectivity during those subsequent processing steps (e.g., before executing blocks 226 and Fig.30 1400') acts as an etch stop layer.

[0205] Reference Figure 1 , 2 , 24 and 25, according to an embodiment, at block 216 and manufacturing stage 900' ( Fig.24 , 25 ), a multi-level field plate opening 990' is formed. Fig.24 To form the field plate opening 990', a photoresist layer 910 may be deposited over the source and drain contacts 141, 146, the upper surface of the ILD0 134, and the dielectric spacers 640, 645, 660, 690. A photoresist opening 920 may then be formed over the location where the field plate opening 990' is to be formed. According to one or more embodiments, the width of the photoresist opening 920 encompasses the two field plate dielectric spacers 690 and extends over portions of the ILD0 134 beyond those spacers 690.

[0206] Reference Fig.25 , the upper sublayer 137 and the middle sublayer 136 of the ILD0 134 and the portion of the field plate dielectric spacer 690 can then be sequentially etched through the resist opening 920, while terminating on the lower ILD0 sublayer 135 and the surface passivation layer 133. Fig. 9 and 10 The description of the manufacturing stage 900 of 134 discussed in detail the details associated with the method of etching through the sub-layers 137 and 136 of the ILD0 134 and removing the portion of the dielectric spacer 690, and those details are intended to be incorporated herein. In short, a plurality of dry and / or wet etching techniques can be used to etch the sub-layers 137 and 136 and the portion of the dielectric spacer 690 through the resist opening 920.

[0207] Once formed, the field plate opening 990' has a first (lowest) horizontal bottom extent 992', left and right second (middle) horizontal bottom extents 994, and left and right third (higher) horizontal bottom extents 996. The first horizontal bottom extent 992' is defined by the exposed surface of the surface passivation layer 133, and the bottom extent 992' is separated from the upper surface 112 of the semiconductor substrate 110 by a first thickness of dielectric material (e.g., the thickness of the surface passivation layer 133). The second horizontal bottom extent 994 is defined by the upper surface of the horizontal spacer portion 692 of the field plate dielectric spacer 690, and is separated from the upper surface 112 by a thicker dielectric material (e.g., the thickness of the surface passivation layer 133 plus the thickness of the horizontal spacer portion 692). Finally, a third horizontal bottom extent 996 is defined by the upper surface of the lower ILD0 sublayer 135 and is separated from the upper surface 112 by still thicker dielectric material (e.g., the thickness of the surface passivation layer 133 and the lower ILD0 sublayer 135). In other words, each of the bottom extents 992', 994, 996 of the field plate opening 990' has increasingly thicker underlying dielectric material (i.e., the horizontal bottom extents 992', 994, 996 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110).

[0208] Reference Figure 1 , 2 , 26 and 27, at block 220 and manufacturing stage 1100' ( Fig.26 , 27 ), a multi-level gate electrode opening 1160' is formed. First, refer to Fig.26To form a gate electrode opening 1160', a photoresist layer 1110 may be deposited over the source and drain contacts 141, 146, the upper surface of ILD0 134, and the dielectric spacers 660, and a photoresist opening 1120 may be formed over the location where the gate electrode opening 1160' is to be formed. According to one or more embodiments, the width of the photoresist opening 1120 encompasses two gate dielectric spacers 660 and extends beyond those spacers 660 over a portion of ILD0 134.

[0209] Reference Fig. 27 , various features and layers are removed through the resist opening 1120 to form the gate electrode opening 1160'. More specifically, several etching processes may be performed to remove portions of the surface passivation layer 133 exposed between the gate dielectric spacers 660, at least some of the gate dielectric spacers 660, and a portion of the upper sublayer 137 of the ILD0 134 exposed through the resist opening 1120. Due to the limited etching selectivity, only a small portion of the upper ILD0 sublayer 137 may be lost. In contrast to the previously described embodiments, in this embodiment, at least portions of the vertical spacer portions 691 and the horizontal spacer portions 692 may remain intact.

[0210] According to one or more embodiments, one or more first etching processes are performed to remove the upper surface passivation sublayer 133 (eg, Al 2 O 3 ) exposed between the gate dielectric spacers 660, and it is also possible to remove the upper spacer portion 693 ( Fig.21 )(For example, SiO 2 ). A plurality of dry and / or wet etching techniques may be used to etch these features. For example, according to various embodiments, RIE, ICP etching, ECR etching, and wet chemical etching may be used to etch these features.

[0211] According to one or more embodiments, the plasma etch may first etch the material of the surface passivation layer 133 with selectivity to the material of the upper dielectric spacer portion 693 and to the material of the upper ILD0 sublayer 137 and the vertical spacer portions 691 and the horizontal spacer portions 692. According to various embodiments, a suitable dry etching technique may use, for example, but not limited to, fluorine-based chemistries (e.g., C 4 F 8 ) or chlorine-based chemicals (e.g., BCl 3) or another suitable dry etching chemistry. Desirably, the etchant can completely remove the exposed portion of the surface passivation layer 133 until the surface of the substrate 110 is exposed between the gate dielectric spacers 660, so the etching process can be stopped. For good etch thickness control, niobium pentafluoride (NbF 5 ) and carbon tetrachloride (CCl 4 ) or acetylacetonate Sn(acac) 2 According to various embodiments, alternatively, possible wet etching chemistries may be used to remove the exposed portion of the surface passivation layer 133, such as, but not limited to, piranha etching, KOH, NH 4 OH+ or other suitable wet etchants.

[0212] After exposing the surface of the substrate 110 between the gate dielectric spacers 660 using a suitable etching process, a wet or dry etching process may be used to remove the remaining portion of the upper spacer portion 693. According to various embodiments, suitable wet etching chemistries include, for example, but are not limited to, HF or buffered HF or other suitable wet etchants.

[0213] The first etching process causes the upper dielectric spacer portion 693 of the gate dielectric spacer 660 to be completely removed, so that the vertical spacer portion 691 and the horizontal spacer portion 692 ( Fig.21 In addition, the first etching process causes the portion of the surface passivation layer 133 exposed between the gate dielectric spacers 660 to be completely removed, so that the upper surface 112 of the semiconductor substrate 110 is exposed between the horizontal spacer portions 692.

[0214] like Fig. 27 As shown in the following figures, the vertical spacer portion 691 and the horizontal spacer portion 692 may remain in the device 100, which may increase the dielectric thickness under the first gate field plate 164' to be formed. In other embodiments, an additional selective etching process may be performed to remove the vertical spacer portion 691 and the horizontal spacer portion 692 (e.g., Si 3 N 4 ), which will also remove the 3 N 4 ) to expose the upper ILD0 sublayer 137 while terminating on the middle ILD0 sublayer 136. RIE, ICP etching, ECR etching and / or wet chemical etching may be used. Suitable dry etching techniques may be used, for example, but not limited to SF 6 +O 2 CF 4 +O 2or one or more of other suitable chemicals.

[0215] Once formed, the gate electrode opening 1160' has a first (lowest) horizontal bottom extent 1162, left and right second (middle) horizontal bottom extents 1164', and left and right third (higher) horizontal bottom extents 1166. The first horizontal bottom extent 1162 is defined by the exposed upper surface 112 of the semiconductor substrate 110. The second horizontal bottom extent 1164' is defined by the surface of the horizontal spacer portion 692 (or by the surface of the surface passivation layer 133 if the spacer portions 691, 692 are removed) and is separated from the upper surface 112 by a first thickness of dielectric material (e.g., the thickness of the surface passivation layer 133 and, in some embodiments, the horizontal spacer portion 692). Finally, a third horizontal bottom extent 1166 is defined by the surface of the middle ILD0 sublayer 136 and, in some embodiments, by the surface of the top ILD0 sublayer 137, and is separated from the upper surface 112 by thicker dielectric material (e.g., the thickness of the surface passivation layer 133, the lower ILD0 sublayer 135, the middle ILD0 sublayer 136, and, in some embodiments, the top ILD0 sublayer 137). In other words, each of the bottom extents 1164', 1166 of the gate electrode opening 1160' has increasingly thicker underlying dielectric material (i.e., the horizontal bottom extents 1164', 1166 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). The gate electrode opening 1160' ( Fig. 27 ) and the gate electrode opening 1160 ( Fig.13 ) is that the gate electrode opening 1160' extends through the single-layer surface passivation layer 133, while the gate electrode opening 1160 extends through the double-layer surface passivation layer 130. In addition, when the horizontal spacer portion 692 is retained, the dielectric thickness under the first gate field plate 164' to be formed is larger. After forming the gate electrode opening 1160', the patterned photoresist layer 1110 can be retained for the next manufacturing stage (i.e., Fig.28 stage 1200').

[0216] Reference Figure 1 , 2 and 28, at block 222 and manufacturing stage 1200'( Fig.28 ), the gate metal layer 1210 then forms a multi-step gate electrode 160' in the gate electrode opening 1160'. The previously deposited and patterned photoresist layer 1110 may be used for this process. Fig.14The description of the manufacturing stage 1200 of the present invention discusses in detail the details associated with the composition of the gate metal layer 1210 and the method of depositing the gate metal layer 1210, and those details are intended to be incorporated herein. In short, using a stripping process, the gate metal layer 1210 of the gate electrode 160' can be deposited (e.g., using evaporation, sputtering, PVD, ALD or other suitable deposition techniques) on the surface of the patterned photoresist layer 1110 and through the opening 1120 in the photoresist layer 1110, and the photoresist layer 1110 can be subsequently removed. The portion of the gate metal layer 1210 deposited within the gate electrode opening 1160' is retained, thereby forming a conductive gate electrode 160'. Alternatively, rather than using a stripping process to form the gate electrode 160', a subtractive process can be used. In either case, the gate metal layer 1210 may include one or more layers of Au, Ag, Al, Cu, Ti, Ni, Pt and / or other substantially conductive materials.

[0217] As previously discussed, the gate electrode 160' has a stepped configuration including a gate channel portion 162 and a first GFP 164' and a second GFP 166 that are substantially symmetrically arranged on both sides of the gate channel portion 162. The gate channel portion 162 is located at the gate channel and has a horizontal bottom extent that defines the lowest portion of the gate electrode 160'. In embodiments where the L-shaped gate spacer portions 691 and 692 are retained (e.g., Embodiment 2), GFP1 164' overlies and contacts the horizontal spacer portion 692, and thus overlies the upper surface of the upper surface passivation layer 133. GFP2 166 overlies the upper surface of the intermediate ILD0 sublayer 136. In other embodiments where the L-shaped gate spacer portions 691 and 692 are removed (e.g., Embodiment 2 discussed above and in Figure 1 and 17 In the embodiment 1 shown in FIG. 1 , GFP1 164 overlies and contacts the upper surface of the upper surface passivation layer 133, and GFP2 166 overlies the upper surface of the middle ILD0 sublayer 136. For both the first and second embodiments ( Fig.17 , 31 ), in some embodiments, GFP2166 may contact the upper surface of the middle ILD0 sublayer 136 (eg, as Fig.17 ), while in other embodiments, a portion of the upper ILDO sublayer 137 may exist between GFP2 166 and the middle ILDO sublayer 136 (eg, as shown in FIG. 1 ). Fig.31 ).

[0218] Reference Figure 1 , 2 and 29, at block 224 and manufacturing stage 1300'( Fig.29), a second interlayer dielectric (ILD1) 150 is deposited over ILD0 134 and gate electrode 160'. Fig.15 The description of the manufacturing stage 1300 of the embodiment discussed in detail the details associated with the composition of ILD1 150 and the method of depositing ILD1 150, and those details are intended to be incorporated herein. Briefly, the dielectric material used for ILD1 150 is a low-k dielectric material that is different from the material of ILD0 sublayers 137 and 135 and from the material of surface passivation layer 133 in order to provide etching selectivity. ILD1 150 may be selected from SiO 2 , organic silicate glass, porous SiO 2 、Si 3 N 4 、SiON、HfO 2 、Al 2 O 3 or AlN and other suitable materials. ILD1 150 may be formed using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. In various embodiments, ILD1 150 may have a thickness in the range of about 0.2 microns to about 2.0 microns, but ILD1 150 may also be thinner or thicker.

[0219] Reference now Figure 1 , 2 and 30, at block 226 and manufacturing stage 1400'( Fig.30 ), a selective etching process is used to form an opening 1490' through ILD1 150 to reproduce the previously formed field plate opening 990' ( Fig.25 ) and expose additional areas of the upper surface of ILD0 134 on either side of the reproduced field plate opening 990'. At the same time, an opening is also formed through ILD1 150 to expose the source ohmic contact 141 and the drain ohmic contact 146, but Fig.30 Those openings are not shown in FIG. 1 because they are located at Fig.30 14. For the location of the openings through ILD1 150 to the source ohmic contact 141 and the drain ohmic contact 146, see Figure 1 .

[0220] Combination of the above Fig.16The description of the manufacturing stage 1400 of the device 100 ′ discussed in detail the details associated with forming the opening 1490′ through the ILD1 150, and those details are intended to be incorporated herein. However, one difference to note is that the embodiment of the device 100 ′ described herein does not include the previously formed field plate 190. Briefly, source and drain openings (not shown) and field plate opening 1490′ are formed by etching the ILD1 150 through the opening 1420′ in the patterned photoresist layer 1410. The photoresist opening 1420′ for the field plate to be formed has a first side 1421′ aligned over a point along the ILD0 sublayer 137 to the left of the leftmost edge of the field plate to be formed and a second side 1422′ aligned over a point along the ILD0 sublayer 137 to the right of the rightmost edge of the field plate to be formed. To form the field plate opening 1490', an etching process is performed until portions 1437 and 1435 of the upper surfaces of the ILD0 sublayers 137 and 135 are reached, respectively (i.e., the etching process terminates on the upper surfaces of the ILD0 sublayers 137 and 135) and deeper until the horizontal spacer portions 692 and the portions of the surface passivation layer 133 between the horizontal spacer portions 692 are reached. This process results in an unfilled field plate opening 1490'. The bottom extent of the field plate opening 1490' is defined by the exposed portions 1437 and 1435 of the ILD0 sublayers 137 and 135, the horizontal spacer portions 692, and the portions of the surface passivation layer 133 exposed between the horizontal spacer portions 692.

[0221] Reference Figure 1 , 2 and 31, at block 228 and manufacturing stage 1500'( Fig.31 ), remove the photoresist 1410 ( Fig.30 ), and depositing metallization over ILD1 150 (and into the source opening, drain opening, and field plate opening through ILD1 150) to form SFP structure 190', source electrode 140 ( Figure 1 )、Drain electrode 145( Figure 1 )、Source metallization 148( Figure 1 ) and drain metallization 149 ( Figure 1 ).

[0222] In the field plate opening 1490'( Fig.30), source metallization 148 is deposited on the portion of the surface passivation layer 133 exposed between the horizontal spacer portions 692 (i.e., the lowermost extent 992' of the field plate opening 990'), on the horizontal spacer portions 692 (i.e., on the extent 994 of the field plate opening 990'), and on the exposed portions 1435 and 1437 of the lower ILD0 sublayer 135 and the upper ILD0 sublayer 137 (i.e., the extents 996 and 998 of the field plate opening 990'). In addition, the source metallization 148 extends across the ILD 1150 to the source contact 141. This provides a conductive field plate to source connection.

[0223] Combination of the above Fig.17 The description of the manufacturing stage 1500 of 1500 discusses in detail the details associated with the source metallization 148 and the drain metallization 149 and their deposition methods, and those details are intended to be incorporated herein. Briefly, the process for forming the SFP structure 190', the source electrode 140 ( Figure 1 )、Drain electrode 145( Figure 1 ) and source metallization 148 and drain metallization 149 ( Figure 1 ) can be blanket deposited and etched, or can be deposited using a lift-off process. In addition, the metallization can include a multi-layer conductive stack including an adhesion layer (e.g., TiW or another suitable material) and additional layers (e.g., Au and / or other suitable metals).

[0224] The SFP structure 190' has a stepped configuration including a first SFP 192' (SFP1), a second SFP 194 (SFP2), a third SFP 196 (SFP3), a fourth SFP 198 (SFP4), and a fifth SFP 199 (SFP5). The second SFP 194, the third SFP 196, and the fourth SFP 198 are generally symmetrically arranged on both sides of the SFP1 192'. The SFP1 192' has a bottom range (e.g., Fig.30 The second SFP 194 has a bottom range (e.g., Fig.30 The third SFP 196 has a bottom extent (e.g., Fig.30The fourth SFP 198 has a bottom range (e.g., a bottom range of 996) separated from the upper surface 112 by a still thicker dielectric material (e.g., the thickness of the surface passivation layer 133 and the lower ILD0 sublayer 135). Fig.30 134) is separated from the upper surface 112 by an even thicker dielectric material (e.g., the thickness of the surface passivation layer 133 and the ILD0 134). Finally, the fifth SFP 199 has a bottom range that is separated from the upper surface 112 by an even thicker dielectric material (e.g., the thickness of the surface passivation layer 133, the ILD0 134, and the ILD1 150). In other words, each of the bottom ranges of the SFPs 192', 194, 196, 198, and 199 has an increasingly thicker underlying dielectric material (i.e., the horizontal bottom ranges 992', 994, 996, 998, 999 become increasingly farther away from the upper surface 112 of the semiconductor substrate 110). As mentioned previously, second SFP 194, third SFP 196 and fourth SFP 198 are provided each with increasingly thicker underlying dielectric material (i.e., increasingly higher horizontal bottom extents) to weaken the electric field at the edge of SFP1 192' to ensure dielectric reliability and high breakdown voltage. Fifth SFP 199 may be particularly beneficial for high voltage devices.

[0225] It may be noted here that in one or more embodiments, the bottom extent of SFP1 192' may be at the same level as or below the bottom extent of GFP1 164' (i.e., SFP1 192' and GFP1 164' may have the same thickness as the underlying dielectric, or the dielectric below GFP1 164' may be thicker due to the inclusion of the horizontal spacer portion 692). In addition, the bottom extents of SFP1 192', SFP2 194, and SFP3 196 may all be recessed relative to the bottom extent of GFP2 166 (i.e., SFP1 192', SFP2 194, and SFP3 196 may all have an underlying dielectric that is thinner than the dielectric below GFP2 166). In addition, SFP4 198 is higher than GFP2 166 (i.e., SFP4 198 has an underlying dielectric that is thicker than GFP2 166). This overall structure may cause C GD The lower gate-drain capacitance C GD This in turn may result in an increase in the gain of the device 100 ′.

[0226] Reference again Figure 1 In block 230, the final passivation layers 170 and 180 ( Figure 1 ) to complete the device 100 ′. For example, the passivation layer 170 may be made of Si 3 N4 or another suitable material, and the passivation layer 180 may be formed of PBO or another suitable material. The passivation layers 170, 180 may be deposited, for example, using one or more of LPCVD, ALD, sputtering, PVD, PECVD, MOCVD, MBE, ICP deposition, ECR deposition, or other suitable techniques. Additional patterned conductive layers and dielectric layers may be formed over the passivation layers 170, 180, openings may be formed through each of the dielectric layers, and one or more intervening patterned conductive layers may be formed to enable electrical connectivity with other device elements.

[0227] An embodiment of a semiconductor device includes a semiconductor substrate having an upper surface and a channel, and a source electrode and a drain electrode above the upper surface of the semiconductor substrate. The source electrode and the drain electrode are electrically coupled to the channel, and the channel extends between the source electrode and the drain electrode. The device also includes a surface passivation layer above the upper surface of the semiconductor substrate, between the source electrode and the drain electrode, and a first interlayer dielectric (ILD0) above the upper surface of the surface passivation layer. A gate electrode is included above the upper surface of the semiconductor substrate, between the source electrode and the drain electrode. The gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom range overlying the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom range higher than the first horizontal bottom range. A conductive field plate is included above the upper surface of the semiconductor substrate, between the gate electrode and the drain electrode. The conductive field plate includes a first field plate having a third horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent at least as high as the first horizontal bottom extent of the first gate field plate.

[0228] According to another embodiment, the surface passivation layer includes a lower surface passivation sublayer formed on the upper surface of the semiconductor substrate, and an upper surface passivation sublayer formed on the intermediate surface passivation sublayer and defining the upper surface of the surface passivation layer. The third horizontal bottom range of the first field plate overlies and contacts the upper surface of the surface passivation layer.

[0229] According to yet another embodiment, the surface passivation layer comprises a single surface passivation layer formed on the upper surface of the semiconductor substrate, the single surface passivation layer defining an upper surface of the surface passivation layer. The third horizontal bottom extent of the first field plate overlies and contacts the upper surface of the single surface passivation layer.

[0230] According to yet another further embodiment, the first gate field plate and the second gate field plate protrude upward and outward from the gate channel portion, and the second field plate and the third field plate protrude upward and outward from the first field plate.

[0231] According to yet another further embodiment, the first gate field plate and the second gate field plate are located on the drain side of the gate electrode, and the gate electrode additionally comprises another first gate field plate and another second gate field plate located on the source side of the gate electrode. In addition, the second field plate and the third field plate are located on the gate side of the conductive field plate, and the conductive field plate additionally comprises another second field plate and another third field plate on the drain side of the conductive field plate.

[0232] An embodiment of a method for manufacturing a semiconductor device includes: providing a semiconductor substrate having an upper surface and a channel; forming a surface passivation layer above the upper surface of the semiconductor substrate; forming a first interlayer dielectric (ILD0) above the upper surface of the surface passivation layer; and forming a source electrode and a drain electrode above the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel, and the channel extends between the source electrode and the drain electrode. The method further includes forming a gate electrode between the source electrode and the drain electrode above the upper surface of the semiconductor substrate. The gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent. The method further includes forming a conductive field plate between the gate electrode and the drain electrode above the upper surface of the semiconductor substrate. The conductive field plate includes a first field plate having a third horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent at least as high as the first horizontal bottom extent of the first gate field plate.

[0233] According to another embodiment, forming the surface passivation layer includes forming a lower surface passivation sublayer on the upper surface of the semiconductor substrate and forming an upper surface passivation sublayer on the intermediate surface passivation sublayer, wherein the upper surface of the upper surface passivation sublayer defines the upper surface of the surface passivation layer.

[0234] According to another further embodiment, forming the surface passivation layer includes forming a single surface passivation layer on the upper surface of the semiconductor substrate, wherein an upper surface of the single surface passivation layer defines an upper surface of the surface passivation layer.

[0235] According to yet another additional embodiment, the method further comprises simultaneously forming a gate electrode opening and a field plate opening through the ILD0, and forming a field plate dielectric spacer on a sidewall of the ILD0 in the field plate opening. The field plate dielectric spacer comprises a vertical spacer portion contacting the sidewall of the ILD0, a horizontal spacer portion contacting the upper surface of the surface passivation layer, and an upper dielectric spacer portion overlying and contacting the vertical spacer portion and the horizontal spacer portion. The method further comprises removing the upper surface passivation sublayer between the field plate dielectric spacers to expose a portion of the upper surface of the surface passivation layer, and removing the upper dielectric spacer portion and the vertical spacer portion of the field plate dielectric spacer. Forming the conductive field plate comprises forming the first field plate on a portion of the upper surface of the surface passivation layer located between the vertical spacer portions and forming the second field plate on the vertical spacer portion.

[0236] The foregoing detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the words "exemplary" or "example" mean "serving as an example, instance, or illustration". Any embodiment described herein as exemplary or example is not necessarily to be construed as being preferred or superior to other embodiments. In addition, it is not intended to be bound by any explicit or implicit theory presented in the foregoing technical field, background technology, or specific embodiments.

[0237] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for implementing the described one or more embodiments to those skilled in the art. It should be understood that various changes may be made to the function and arrangement of elements without departing from the scope defined by the claims, which scope is included in known equivalents and foreseeable equivalents at the time of filing this patent application.

[0238] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference purposes only, and therefore these terms are not intended to be limiting, and unless the context clearly indicates, the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order.

[0239] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically joined. Likewise, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically joined. Thus, while the schematic diagrams shown in the drawings depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate having an upper surface and a channel; a source electrode and a drain electrode over the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode; a surface passivation layer located above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode; A first interlayer dielectric ILD0, which is above the upper surface of the surface passivation layer; a gate electrode located above the upper surface of the semiconductor substrate and between the source electrode and the drain electrode, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent; and A conductive field plate is located above the upper surface of the semiconductor substrate and between the gate electrode and the drain electrode, wherein the conductive field plate includes a first field plate having a third horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent at least as high as the first horizontal bottom extent of the first gate field plate.

2. The semiconductor device according to claim 1, wherein: Also includes: A horizontal dielectric spacer portion is on an upper surface of the surface passivation layer, wherein the fourth horizontal bottom extent of the second field plate overlies and contacts an upper surface of the horizontal dielectric spacer portion.

3. The semiconductor device according to claim 1, wherein: The conductive field plates also include a third field plate having a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.

4. The semiconductor device according to claim 3, wherein: The ILD0 includes a lower ILD0 sublayer on the upper surface of the surface passivation layer, and a middle ILD0 sublayer on the upper surface of the lower ILD0 sublayer; The fifth horizontal bottom extent of the third field plate overlies and contacts the upper surface of the lower ILD0 sublayer; and The second horizontal bottom extent of the second gate field plate overlies an upper surface of the middle ILD0 sub-layer.

5. The semiconductor device according to claim 4, wherein: The ILD0 also includes an upper ILD0 sublayer on the upper surface of the middle ILD0 sublayer; and The conductive field plate further includes a fourth field plate having a sixth horizontal bottom extent that is higher than the fifth horizontal bottom extent of the third field plate, and the sixth horizontal bottom extent of the fourth field plate overlies and contacts an upper surface of the upper ILD0 sublayer.

6. The semiconductor device according to claim 4, wherein: The first gate field plate and the second gate field plate protrude upward and outward from the gate channel portion; and The second field plate and the third field plate protrude upward and outward from the first field plate.

7. The semiconductor device according to claim 1, wherein: The surface passivation layer consists of a single surface passivation layer formed on the upper surface of the semiconductor substrate; The upper surface of the single surface passivation layer defines the upper surface of the surface passivation layer; and The third horizontal bottom extent of the first field plate contacts the upper surface of the single surface passivation layer.

8. The semiconductor device according to claim 1, wherein: The surface passivation layer comprises a lower surface passivation sublayer formed on the upper surface of the semiconductor substrate and an upper surface passivation sublayer formed on the lower surface passivation sublayer, wherein the upper surface of the upper surface passivation sublayer defines the upper surface of the surface passivation layer; and The third horizontal bottom extent of the first field plate contacts the upper surface of the single surface passivation layer.

9. The semiconductor device according to claim 1, wherein: The first field plate and the second field plate are formed of a field plate metal; and The semiconductor device also includes a source metallization extending from the field plate metal across the gate electrode to a source contact.

10. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a semiconductor substrate having an upper surface and a channel; forming a surface passivation layer over the upper surface of the semiconductor substrate; forming a first interlayer dielectric ILD0 over the upper surface of the surface passivation layer; forming a source electrode and a drain electrode over the upper surface of the semiconductor substrate, wherein the source electrode and the drain electrode are electrically coupled to the channel and the channel extends between the source electrode and the drain electrode; forming a gate electrode between the source electrode and the drain electrode over the upper surface of the semiconductor substrate, wherein the gate electrode includes a gate channel portion extending through the surface passivation layer to contact the upper surface of the semiconductor substrate, a first gate field plate having a first horizontal bottom extent overlying the upper surface of the surface passivation layer, and a second gate field plate having a second horizontal bottom extent higher than the first horizontal bottom extent; and A conductive field plate is formed above the upper surface of the semiconductor substrate between the gate electrode and the drain electrode, wherein the conductive field plate includes a first field plate having a third horizontal bottom extent overlying and contacting the upper surface of the surface passivation layer, and a second field plate having a fourth horizontal bottom extent at least as high as the first horizontal bottom extent of the first gate field plate.

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