A low-loss trench-gate silicon carbide mosfet device and method of manufacture

Abstract

The application provides a low-loss trench gate silicon carbide MOSFET device and a manufacturing method, and the device structure comprises an N+ substrate, an N- epitaxial layer, an N+ buffer layer, a P-type well region, an N+ source region, a P+ shielding region, a polysilicon gate, a source metal and a drain metal. The application is based on an asymmetric trench gate silicon carbide MOSFET device, which has a channel on one side of a silicon carbide trench and is wrapped by P+ on the other side. The integrated FinFET structure increases the channel density, and at the same time, the extremely narrow Fin-shaped mesa reduces the electric field intensity at the channel and the interface scattering, so that the mobility of the channel in the Fin-shaped mesa is increased. In addition, the P+ structure wrapping the gate trench reduces the gate oxide electric field at the trench corner, so that the gate oxide electric field intensity of the device after the introduction of the FinFET structure is in the safe working range.

Description

A low-loss trench-gate silicon carbide MOSFET device and its manufacturing method Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically a low-loss trench-gate silicon carbide MOSFET device and its manufacturing method. Background Technology

[0002] As more and more applications place higher demands on the voltage withstand capability and power consumption of power devices, the performance of these devices faces increasing challenges. Silicon carbide (SiC) materials possess advantages such as high thermal conductivity, wide bandgap, and high critical breakdown voltage, making SiC-based semiconductor devices increasingly advantageous in high-voltage, high-power applications. SiC MOSFETs exhibit high breakdown voltage, low specific on-resistance, and low switching losses, making them advantageous in various application scenarios, including new energy vehicles. However, due to limitations in gate oxide processes, SiC MOSFETs have numerous interface traps at their interface. These traps result in lower channel mobility and increased specific on-resistance.

[0003] To reduce the specific on-resistance of silicon carbide MOSFETs, trench-type silicon carbide MOSFETs have been proposed. The channel of a trench-type silicon carbide MOSFET is typically located at (11... _ 20) or (1) _ The 100) crystal plane has smaller interface traps and therefore higher channel mobility. However, to protect the gate oxide layer, trench silicon carbide MOSFETs often introduce a P-type shielding region, which introduces JFET region resistance and increases the cell size, thus not achieving a smaller specific on-resistance. The asymmetric trench silicon carbide MOSFET is a classic silicon carbide trench MOSFET structure, in which the channel is located at (112) crystal plane. _ 0) Crystal plane. One side of the gate trench is wrapped by a P-type shielding structure, which provides good gate oxide reliability. However, the P-type shielding region introduces JFET resistance and increases the cell size.

[0004] Japanese researchers proposed and fabricated silicon carbide FinFET devices. When the Fin width is sufficiently narrow, the device forms a "bulk inversion layer," resulting in a more uniform carrier distribution in the channel region and increased channel mobility—a phenomenon known as the "FinFET effect." Simultaneously, silicon carbide FinFETs have smaller cell sizes than trench-gate silicon carbide MOSFETs, leading to higher channel density. This mechanism results in silicon carbide FinFETs exhibiting significantly lower specific on-resistance than trench-type silicon carbide MOSFETs. However, these silicon carbide FinFETs exhibit high gate oxide electric fields under high voltage, exceeding the safe operating electric field strength of silicon dioxide (3 MV / cm).

[0005] This invention integrates a FinFET structure into the gate trench of an asymmetric trench-gate silicon carbide MOSFET device, with a Fin width of less than 300 nm. The integrated FinFET structure sacrifices the channel located on the trench sidewalls, increasing the channel width within the Fin-shaped mesa. Since the channel width within the Fin-shaped mesa is greater than the sacrificed channel width on the trench sidewalls, the overall channel density of the device increases. Simultaneously, the extremely narrow Fin-shaped mesa ensures a high carrier concentration even at locations far from the interface, and the channel carriers are less affected by interface scattering, thereby increasing the channel mobility of the FinFET structure. Therefore, the specific on-resistance of the asymmetric trench-gate silicon carbide MOSFET is significantly reduced after integrating the FinFET structure. The P-type shielding structure of the asymmetric trench-gate silicon carbide MOSFET protects the gate oxide layer of the integrated FinFET structure within the trench, thus the gate oxide reliability of the entire device is not compromised. Summary of the Invention

[0006] The purpose of this invention is to provide a low-loss trench-gate silicon carbide MOSFET device and its manufacturing method. The device structure is based on an asymmetric trench-gate silicon carbide MOSFET structure, with the channel located on one side of the gate trench, and the other side of the gate trench enclosed by a P-type shielding structure. This invention integrates a FinFET structure inside the gate trench to improve the specific on-resistance of the device, while the P-type shielding region protects the gate oxide layer of the FinFET structure. Therefore, the device exhibits both low specific on-resistance and good gate oxide layer reliability.

[0007] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0008] A low-loss trench-gate silicon carbide MOSFET device includes: an N+ substrate 3, with an N+ buffer layer 2 and an N- drift region 1 sequentially disposed on top of the N+ substrate 3; a gate trench disposed above the N- drift region 1, containing a gate oxide layer 8 and a polysilicon gate 9; a P-type well region 6 and an N+ source region 7 above the P-type well region 6 on one side of the gate trench, forming a channel located on the sidewall of the trench; a P-type shielding region A4 and a P-type shielding region B5 disposed on the N- drift region 1, with the P-type shielding region A4 enclosing the gate trench; a source metal A10 and a source metal B11 disposed above the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7, with the source metal B11 forming an ohmic contact with the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7; and a drain metal 12 disposed at the bottom of the device, forming an ohmic contact with the N+ substrate 3.

[0009] The gate trench integrates a FinFET structure, which includes the N-drift region 1, N+ buffer layer 2, N+ substrate 3, P-type well region 6, polysilicon gate 9, and N+ source region 7. The N+ buffer layer 2 is located on the N+ substrate 3, the N-drift region 1 is located on the N+ buffer layer 2, the P-type well region 6 is located on the N-drift region 1, and the N+ source region 7 is located above the P-type well region 6. The gate trench passes through the N+ source region 7, the P-type well region 6, and the N-drift region 1, and the trench contains the polysilicon gate 9.

[0010] As a preferred embodiment, the FinFET structure integrated within the gate trench has a Fin width of less than 300 nm.

[0011] As a preferred embodiment, the FinFET structure integrated within the gate trench is enclosed by a P-type shielding region A4.

[0012] The present invention also provides a method for manufacturing the low-loss trench-gate silicon carbide MOSFET, comprising the following steps:

[0013] Step 1: Select silicon carbide as the N+ substrate and epitaxially grow an N+ buffer layer on the N+ substrate;

[0014] Step 2: Epitaxially grow the N-drift region on the N+ buffer layer;

[0015] Step 3: Form a P-type trap region on the surface of the N-drift region by ion implantation of Al ions;

[0016] Step 4: Form an N-type source region on the surface of the P-type trap region by ion implantation of N ions;

[0017] Step 5: Form P-type shielding regions A and B on the surface of the N-drift region by ion implantation of Al;

[0018] Step 6: Form gate trenches in the N-drift region by etching;

[0019] Step 7: Grow the gate oxide layer within the gate trench;

[0020] Step 8: Deposit a polysilicon gate on the gate oxide layer;

[0021] Step 9: Deposit the oxide layer of the medium;

[0022] Step 10: Form ohmic contacts on the upper and lower surfaces of the device.

[0023] This invention integrates a FinFET structure into an asymmetric trench-gate silicon carbide MOSFET device structure. The integrated FinFET structure sacrifices the channel located on the trench sidewalls, increasing the channel within the Fin-shaped mesa. The width of the channel within the Fin-shaped mesa is greater than the width of the channel sacrificed on the trench sidewalls, thus increasing the overall channel density of the device. Simultaneously, the Fin-shaped mesa, with a width of less than 300 nm, ensures a high carrier concentration even at locations far from the interface, reducing the impact of interface scattering on channel carriers and increasing the channel mobility of the FinFET structure. Therefore, the specific on-resistance of the asymmetric trench-gate silicon carbide MOSFET is significantly reduced after integrating the FinFET structure. Furthermore, the P-type shielding region of the asymmetric trench-gate silicon carbide MOSFET structure protects the gate oxide layer, preventing premature breakdown of the oxide layer at the trench corners after the introduction of the FinFET structure. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the invention and are used together with the examples to explain the invention, but do not constitute a limitation thereof:

[0025] Figure 1 shows the structure of a trench-gate silicon carbide device with an integrated FinFET structure.

[0026] Figure 2 shows the structure of a trench gate silicon carbide device with integrated FinFET structure after removing polysilicon and metal.

[0027] Figure 3 is a top view of a low-loss trench-gate silicon carbide MOSFET ignoring the metal, polysilicon, and dielectric layers.

[0028] Figure 4 is a cross-sectional view along the dashed line AA' in Figure 3 after considering the metal, polysilicon, and dielectric. The dashed line AA' is the dashed line that points from the P-type shielding region B to the P-type shielding region A and passes through the N+ source region and the polysilicon gate.

[0029] Figure 5 is a cross-sectional view along the dashed line BB' in Figure 3 after considering the metal, polysilicon, and dielectric. The dashed line BB' is the dashed line pointing from one gate trench to another gate trench and passing through the N+ source region.

[0030] Figure 6 is a schematic diagram of a silicon carbide epitaxial wafer.

[0031] Figure 7 shows a schematic diagram of the pwell layer implanted on the epitaxial wafer.

[0032] Figure 8 is a schematic diagram of N+ region injection in the epitaxial layer.

[0033] Figure 9 is a schematic diagram of injecting a P-type shielding region into the epitaxial layer.

[0034] Figure 10 is a schematic diagram of the gate trench being dug in the epitaxial layer.

[0035] Figure 11 shows the formation of an oxide layer and polysilicon within the gate trench, with metal contacts formed on the upper and lower surfaces of the device.

[0036] Among them, 1-N-drift region, 2-N+ buffer layer, 3-N+ substrate, 4-P-type shielding region A, 5-P-type shielding region B, 6-P-type well region, 7-N+ source region, 8-gate oxide layer, 9-polysilicon gate, 10-source metal A, 11-source metal B, 12-drain metal. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] As shown in Figures 1 and 2, a low-loss trench-gate silicon carbide MOSFET device includes: an N+ substrate 3, with an N+ buffer layer 2 and an N- drift region 1 sequentially disposed on top of the N+ substrate 3; a gate trench disposed above the N- drift region 1, containing a gate oxide layer 8 and a polysilicon gate 9; a P-type well region 6 and an N+ source region 7 above the P-type well region 6 on one side of the gate trench, forming a channel located on the sidewall of the trench; a P-type shielding region A4 and a P-type shielding region B5 disposed on the N- drift region 1, with the P-type shielding region A4 enclosing the gate trench; a source metal A10 and a source metal B11 disposed above the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7, with the source metal B11 forming an ohmic contact with the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7; and a drain metal 12 disposed at the bottom of the device, forming an ohmic contact with the N+ substrate 3. The gate trench integrates a FinFET structure, which includes the N-drift region 1, N+ buffer layer 2, N+ substrate 3, P-type well region 6, polysilicon gate 9, and N+ source region 7. The N+ buffer layer 2 is located on the N+ substrate 3, the N-drift region 1 is located on the N+ buffer layer 2, the P-type well region 6 is located on the N-drift region 1, and the N+ source region 7 is located above the P-type well region 6. The gate trench passes through the N+ source region 7, the P-type well region 6, and the N-drift region 1, and the trench contains the polysilicon gate 9.

[0039] Figure 3 is a top view of a low-loss trench-gate silicon carbide MOSFET ignoring the metal, polysilicon, and dielectric layers, including a P-type shielded region A, a P-type shielded region B, an N+ source region, a gate trench, and a gate oxide layer. The gate trenches are arranged alternately, and adjacent gate trenches, together with the N+ source region, P-type well region, and N- drift region, form a FinFET structure.

[0040] Figure 4 is a cross-sectional view along the dashed line AA' in Figure 2, considering the metal, polysilicon, and dielectric. This cross-section represents an asymmetric trench-gate silicon carbide MOSFET device, including a gate trench with a channel located in the P-type well region on one side and a P-type shielding region A on the other side. P-type shielding regions A and B protect the gate oxide layer under high electric fields. The dashed line AA' points from P-type shielding region B to P-type shielding region A, passing through the N+ source region and the polysilicon gate.

[0041] Figure 5 shows a cross-sectional view along the dashed line BB' in Figure 2, considering the metal, polysilicon, and dielectric. This cross-section represents the FinFET structure integrated within the trench, consisting of adjacent gate trenches, N+ source regions, P-well regions, and N-drift regions. The FinFET structure has a Fin-type mesa smaller than 300 nm, forming a "bulk inversion layer" channel within the mesa. Channel carriers maintain a high concentration even far from the interface, thus reducing the impact of interface scattering and increasing the interface mobility of the FinFET structure, resulting in lower channel resistance. Furthermore, the channel density increases after integrating the FinFET structure. All these factors contribute to a significant reduction in the specific on-resistance of the low-loss trench-gate silicon carbide MOSFET. The dashed line BB' points from one gate trench to another, passing through the N+ source region.

[0042] This embodiment also provides a method for manufacturing a low-loss trench-gate silicon carbide MOSFET, including the following steps:

[0043] Step 1: Select silicon carbide as the N+ substrate and epitaxially grow an N+ buffer layer on the N+ substrate;

[0044] Step 2: Epitaxially grow the N-drift region on the N+ buffer layer, as shown in Figure 6;

[0045] Step 3: Form a P-type trap region on the surface of the N-drift region by implanting Al ions, as shown in Figure 7;

[0046] Step 4: An N-type source region is formed on the surface of the P-type trap region by ion implantation of N ions, as shown in Figure 8;

[0047] Step 5: P-type shielding region A and P-type shielding region B are formed on the surface of the N-drift region by ion implantation of Al, as shown in Figure 9;

[0048] Step 6: Form gate trenches in the N-drift region by etching, as shown in Figure 10;

[0049] Step 7: Grow the gate oxide layer within the gate trench;

[0050] Step 8: Deposit a polysilicon gate on the gate oxide layer;

[0051] Step 9: Deposit the oxide layer of the medium;

[0052] Step 10: Form ohmic contacts on the upper and lower surfaces of the device to obtain the device structure shown in Figure 11.

[0053] The specific concentration and thickness of the N-drift region 1 are determined based on the voltage level of the device.

[0054] The concentration and depth of P-type shielding zones A4 and B5 are determined based on the electric field strength of the gate oxide layer and the on-state voltage drop.

[0055] The working principle of this invention is as follows:

[0056] This invention proposes a low-loss trench-gate silicon carbide MOSFET device. When the width of the Fin-shaped mesa is less than 300 nm, the channel carriers still have a high concentration far from the interface, thus the channel carriers are less affected by interface scattering, thereby increasing the interface mobility of the FinFET structure. Furthermore, the integrated FinFET structure sacrifices the channel located on the trench sidewalls, increasing the channel within the Fin-shaped mesa. The channel width inside the Fin-shaped mesa is greater than the channel width of the sacrificed trench sidewalls. The integrated FinFET structure increases the channel density of the entire device. For these reasons, the low-loss trench-gate silicon carbide MOSFET has a lower specific on-resistance than the asymmetric trench-gate silicon carbide MOSFET. Secondly, the P-type shielding region surrounding the gate trench protects the gate oxide layer, ensuring that the gate oxide layer of the integrated FinFET structure device is still protected.

[0057] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A low-loss trench-gate silicon carbide MOSFET device, characterized in that, include: An N+ substrate (3) is provided with an N+ buffer layer (2) and an N- drift region (1) on top of the N+ substrate (3); a gate trench is provided above the N- drift region (1), and a gate oxide layer (8) and a polysilicon gate (9) are provided in the trench; a P-type well region (6) and an N+ source region (7) above the P-type well region (6) are provided on one side of the gate trench, and the two form a channel located on the sidewall of the trench; a P-type shielding region A (4) and a P-type shielding region B (5) are provided on the N- drift region (1), and the P-type shielding region A (4) wraps the gate trench; a source metal A (10) and a source metal B (11) are provided above the P-type shielding region A (4), the P-type shielding region B (5) and the N+ source region (7), and the source metal B (11) forms an ohmic contact with the P-type shielding region A (4), the P-type shielding region B (5) and the N+ source region (7); the bottom of the device is provided with A drain metal (12) is placed to form an ohmic contact with the N+ substrate (3); a FinFET structure is integrated in the gate trench, and the FinFET structure integrated in the gate trench has a width of less than 300 nm; the structure includes the N-drift region (1), N+ buffer layer (2), N+ substrate (3), P-type well region (6), polysilicon gate (9) and N+ source region (7); the N+ buffer layer (2) is located on the N+ substrate (3), the N-drift region (1) is located on the N+ buffer layer (2), the P-type well region (6) is located on the N-drift region (1), and the N+ source region (7) is located above the P-type well region (6). The gate trench passes through the N+ source region (7), the P-type well region (6) and the N-drift region (1). There is a polysilicon gate (9) in the trench, and the FinFET structure integrated in the gate trench is wrapped by the P-type shielding region A (4).

2. The method for manufacturing a low-loss trench-gate silicon carbide MOSFET device according to claim 1, characterized in that... Includes the following steps: Step 1: Select silicon carbide as the N+ substrate and epitaxially grow an N+ buffer layer on the N+ substrate; Step 2: Epitaxially grow N-drift regions on the N+ buffer layer; Step 3: Form P-type trap regions on the surface of N-drift regions by ion implantation of Al ions; Step 4: Form an N-type source region on the surface of the P-type trap region by ion implantation of N ions; Step 5: Form P-type shielding regions A and B on the surface of the N-drift region by ion implantation of Al; Step 6: Form gate trenches in the N-drift region by etching; forming a FinFET structure with a width of less than 300nm; Step 7: Grow a gate oxide layer within the gate trench; Step 8: Deposit a polysilicon gate on the gate oxide layer; Step 9: Deposit a dielectric oxide layer; Step 10: Form ohmic contacts on the upper and lower surfaces of the device.

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