A junction field effect transistor device, a manufacturing method therefor, and an electronic device

Abstract

This disclosure provides a junction field-effect transistor (JFET) device, its fabrication method, and an electronic device. The p-type gate region is formed by implantation ions on the side of the n-drift layer away from the n+ substrate. Therefore, it eliminates the need for high-energy p-type ion deep implantation to achieve the p-type gate region, thereby improving production efficiency. The n-type channel layer can be formed using homoepitaxial growth, which improves device design flexibility and channel mobility. Therefore, compared to Figure 1, this disclosure avoids using deep p-type ion implantation to form the bottom p-type gate region and deep n-type ion implantation to form the n-type channel layer, thus improving device design flexibility, production efficiency, and channel mobility.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a junction field-effect transistor device, its fabrication method, and an electronic device. Background Technology

[0002] Junction field-effect transistors (JFETs) are widely used as electrically controlled switching structures in electronic devices based on wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). A JFET is a unipolar electronic device, meaning that in the on-state, essentially only one type of carrier flows in the channel of this semiconductor device to form a conduction current between the source and drain. The gate of the JFET forms a pn junction with the channel. In normally-on JFETs, applying a voltage to the gate reverse-bias the pn junction to the channel pinch-off voltage, thereby turning off the device.

[0003] Existing JFET devices can be categorized into vertical and planar types based on the channel's position relative to the wafer. Planar JFETs, also known as lateral JFETs, have a channel horizontal to the wafer surface. The channel width is determined by two horizontal semiconductor gates (one above the other with opposite doping types to the channel). The variability in the spacing between these lateral semiconductor gates is determined by the difference in their doping depths. In semiconductor manufacturing, doping depth can be relatively easily and uniformly controlled between several nanometers and several micrometers by adjusting implantation energy or epitaxial time. Therefore, using a planar channel can effectively improve device fabrication capabilities.

[0004] Currently, the most common method for manufacturing planar JFETs is the implantation method, which involves multiple ion implantations to form the channel and the semiconductor gate sandwiching the channel. For example... Figure 1 As shown, Figure 1 The prior art, a planar triple-implanted JFET and its corresponding manufacturing method (application number: 201680061749.4), forms a top gate region 605a, a channel region 604, and a bottom gate region 605b by performing three ion implantations on the drift region, thus forming a pnp structure for the JFET and achieving a planar JFET channel. However, the lateral channel achieved by this method undergoes multiple high-energy ion implantations, resulting in poor channel crystal quality and low mobility. Furthermore, high-dose deep ion implantation is time-consuming, leading to high semiconductor gate resistivity and high gate resistance in the formed device. Additionally, there is a correlation between the ion implantation depth for forming the semiconductor gate and the device channel width and turn-off voltage; therefore, the on-resistance and turn-off voltage of the device are also limited by ion implantation.

[0005] like Figure 2 As shown, Figure 2The prior art (CJFET) describes a SiC JFET device with an integrated Schottky diode and its fabrication method (publication number: CN106783851B). This patent involves first implanting a p+ well layer onto the n-drift layer, then performing a secondary epitaxy to form an n-channel, followed by another implantation to form p+ and n+ / p+ source contacts. Finally, p-type implantation connects the bottom p+ well to the p+ source contact region. Because the bottom p+ well is connected to the source, the channel can only be unidirectionally cut off by the depletion region of the top gate / source pn junction when the device is turned off, resulting in a lower threshold voltage compared to... Figure 1 The more negative the on-resistance, the larger the device's turn-off voltage, making it very difficult to achieve a positive threshold voltage (i.e., normally-off device) with low on-resistance. Therefore, its Schottky junction design cannot achieve its desired reverse freewheeling effect. Figure 2 Integrating a Schottky junction is practically ineffective and wastes device area. Furthermore, Figure 2 The capacitance between the source and drain terminals of the device shown is much larger than Figure 1 The capacitance between the source and drain terminals of the device shown will increase the output capacitance if applied to a common cascode device, causing oscillation and increasing switching losses.

[0006] For the reasons mentioned above, existing JFET devices need to be improved. Summary of the Invention

[0007] This disclosure provides a junction field-effect transistor device, its fabrication method, and an electronic device. The n-type channel layer of the junction field-effect transistor device is formed by homoepitaxial growth, which improves the design flexibility and channel mobility of the device. Furthermore, it eliminates the need for high-energy p-type ion deep implantation to realize the p-type gate region, thereby improving production efficiency.

[0008] This disclosure provides a junction field-effect transistor device, its fabrication method, and an electronic device, the specific solutions of which are as follows:

[0009] On one hand, embodiments of this disclosure provide a junction field-effect transistor device, including an active region, wherein the cell structure of the active region includes:

[0010] n+ substrate;

[0011] An n-drift layer is located on one side of the n+ substrate;

[0012] The p-type gate region is located in the n-drift layer and is closer to the side of the n-drift layer away from the n+ substrate;

[0013] The n-type channel layer is located on the side of the p-type gate region away from the n+ substrate;

[0014] The p+ gate region is located in the n-type channel layer and is close to the side of the n-type channel layer away from the n+ substrate.

[0015] In some embodiments, in the junction field-effect transistor device provided in this disclosure, the cell structure of the active region further includes:

[0016] The p+ connection region is located in the p+ gate region on the side away from the n+ substrate, the middle part of the p+ connection region is located in the n-type channel layer, and the side of the p+ connection region closer to the n+ substrate is located in the p-type gate region.

[0017] The n+ source region is located in the n-type channel layer and is close to the side of the n-type channel layer away from the n+ substrate. The n+ source region is isolated from the p+ gate region through the n-type channel layer, and the n+ source region is spaced apart from the p+ connection region.

[0018] In some embodiments, in the junction field-effect transistor device provided in the present disclosure, the cell structure of the active region further includes a first n-type current diffusion layer and a second n-type current diffusion layer located in the n-drift layer and spaced apart. The first n-type current diffusion layer and the second n-type current diffusion layer are both close to the side of the n-drift layer away from the n+ substrate, and the first n-type current diffusion layer and the second n-type current diffusion layer are respectively located on both sides of the p-type gate region.

[0019] The p-type gate region includes: a first surface and a second surface disposed opposite to and parallel to the n+ substrate, and a first side surface and a second side surface connected to and disposed opposite to the first surface and the second surface; the first n-type current diffusion layer covers the first side surface, and the second n-type current diffusion layer covers the second side surface.

[0020] In some embodiments, in the junction field-effect transistor device provided in the present disclosure, the first surface of the p-type gate region is close to the n+ substrate, the first n-type current diffusion layer further covers a portion of the first surface, and the second n-type current diffusion layer further covers a portion of the first surface.

[0021] In some embodiments, in the junction field-effect transistor device provided in the present disclosure, the orthogonal projection of the p+ gate region on the n+ substrate completely covers the orthogonal projections of the first n-type current diffusion layer and the second n-type current diffusion layer on the n+ substrate.

[0022] In some embodiments, in the junction field-effect transistor device provided in this disclosure, the cell structure of the active region further includes:

[0023] A dielectric layer is located on the side of the p+ gate region away from the n+ substrate, and the dielectric layer has a first contact region corresponding to the p+ gate region and a second contact region corresponding to the n+ source region;

[0024] A gate ohmic contact layer is located on the side of the p+ gate region away from the n+ substrate and within the first contact region; the gate ohmic contact layer is electrically connected to the p+ gate region.

[0025] The source ohmic contact layer is located on the side of the n+ source region away from the n+ substrate, and is located within the second contact region;

[0026] The gate electrode is located on the side of the dielectric layer away from the n+ substrate and is electrically connected to the gate ohmic contact layer;

[0027] The source electrode is located on the side of the dielectric layer away from the n+ substrate and is electrically connected to the source ohmic contact layer;

[0028] The drain electrode is located on the side of the n+ substrate away from the n- drift layer.

[0029] In some embodiments, in the junction field-effect transistor device provided in the present disclosure, the orthogonal projection of the first contact region on the n+ substrate is located within the orthogonal projection range of the p+ connection region on the n+ substrate;

[0030] Alternatively, the orthographic projection of the first contact area on the n+ substrate does not overlap with the orthographic projection of the p+ connection area on the n+ substrate;

[0031] Alternatively, the orthographic projection of the first contact region on the n+ substrate overlaps with the orthographic projections of the p+ connection region and the p+ gate region on the n+ substrate.

[0032] In some embodiments, the junction field-effect transistor device provided in this disclosure further includes a terminal region located around the active region. The terminal region includes a plurality of spaced field-limiting ring structures. The field-limiting ring structure includes a first field-limiting ring and a second field-limiting ring that are stacked and contacted. The first field-limiting ring is disposed in the same layer and material as the p-type gate region, and the second field-limiting ring is disposed in the same layer and material as the p+ connection region.

[0033] In some embodiments, the junction field-effect transistor device provided in the present disclosure further includes a terminal region located around the active region. The terminal region includes a field-limiting ring structure, which includes a plurality of spaced-apart first field-limiting rings and a plurality of spaced-apart second field-limiting rings. The first field-limiting rings are disposed in the same layer and material as the p-type gate region, and the second field-limiting rings are disposed in the same layer and material as the p+ gate region. The orthogonal projection of the second field-limiting rings on the n+ substrate covers the orthogonal projection of two adjacent first field-limiting rings on the n+ substrate.

[0034] In some embodiments, the junction field-effect transistor device provided in this disclosure further includes a terminal region located around the active region. The terminal region includes a junction terminal extension structure, which includes a first junction terminal extension, a second junction terminal extension, and a third junction terminal extension stacked together. The first junction terminal extension is integral with the p-type gate region, the second junction terminal extension is integral with the p+ connection region, and the third junction terminal extension is disposed on the same layer and made of the same material as the p+ gate region.

[0035] On the other hand, this disclosure also provides a method for fabricating a junction field-effect transistor (JFET) device, used to fabricate the JFET device provided in this disclosure, the fabrication method comprising:

[0036] An n-drift layer is epitaxially formed on one side of the n+ substrate;

[0037] p-type ions are implanted on the side of the n-drift layer away from the n+ substrate to form a p-type gate region;

[0038] An n-type channel layer is epitaxially formed on the side of the p-type gate region away from the n+ substrate;

[0039] p-type ions are implanted on the side of the n-type channel layer away from the n+ substrate to form a p+ gate region.

[0040] In some embodiments, the preparation method provided in this disclosure further includes:

[0041] A p+ connection region is formed by implanting p-type ions on the side of the p+ gate region away from the n+ substrate. The side of the p+ connection region away from the n+ substrate is located within the p+ gate region. The middle portion of the p+ connection region is located in the n-type channel layer. The side of the p+ connection region closer to the n+ substrate is located within the p-type gate region.

[0042] An n-type ion is implanted on the side of the p+ gate region away from the n+ substrate to form an n+ source region. The n+ source region and the p+ gate region are provided with an n-type channel layer, and the n+ source region and the p+ connection region are spaced apart.

[0043] In some embodiments, in the above-described preparation method provided in this disclosure, before implanting p-type ions to form a p-type gate region on the side of the n-drift layer away from the n+ substrate, the method further includes: forming a first n-type current diffusion layer and a second n-type current diffusion layer at intervals on the side of the n-drift layer away from the n+ substrate by implanting n-type ions.

[0044] When p-type ions are implanted on the side of the n-drift layer away from the n+ substrate to form a p-type gate region, the first n-type current diffusion layer covers the first side surface and part of the first surface of the p-type gate region, and the second n-type current diffusion layer covers the second side surface and part of the first surface of the p-type gate region.

[0045] On the other hand, this disclosure also provides an electronic device, including the junction field-effect transistor device described above in this disclosure.

[0046] The beneficial effects of this disclosure are as follows:

[0047] This disclosure provides a junction field-effect transistor device, its fabrication method, and an electronic device. The p-type gate region is formed by implantation ions on the side of the n-drift layer away from the n+ substrate. Therefore, it eliminates the need for high-energy p-type ion deep implantation to achieve the p-type gate region, thereby improving production efficiency. The n-type channel layer can be formed using homoepitaxial growth, which improves device design flexibility and channel mobility. Therefore, this disclosure is related to... Figure 1 In contrast, this disclosure avoids using p-type deep ion implantation to form the bottom p-type gate region and using n-type deep ion implantation to form the n-type channel layer, thereby improving the device design flexibility, manufacturing efficiency and channel mobility. Attached Figure Description

[0048] Figure 1 A schematic diagram of a JFET structure provided in the prior art;

[0049] Figure 2 A schematic diagram of a JFET structure is provided for the second prior art;

[0050] Figure 3 A schematic diagram of a junction field-effect transistor device provided in an embodiment of this disclosure;

[0051] Figure 4 for Figure 3 A schematic diagram of the cross section along the AA' direction;

[0052] Figure 5 for Figure 3 A schematic diagram of the cross-section along the BB' direction;

[0053] Figure 6 for Figure 3 The top view of the structure shown, which has a dielectric layer, a gate ohmic contact layer, a source ohmic contact layer, a gate electrode, and a source electrode formed sequentially on top;

[0054] Figure 7 This is another schematic diagram of a junction field-effect transistor device provided in the embodiments of this disclosure;

[0055] Figure 8 This is another schematic diagram of a junction field-effect transistor device provided in the embodiments of this disclosure;

[0056] Figure 9 This is another schematic diagram of a junction field-effect transistor device provided in the embodiments of this disclosure;

[0057] Figure 10 For existing technology two Figure 2 With respect to this disclosure Figure 3 The corresponding simulated device transfer characteristic curves;

[0058] Figure 11 For existing technology one Figure 1 Existing technology two Figure 2 With respect to this disclosure Figure 3 Simulation schematic diagram of the specific on-resistance of the device with different doping concentrations of the n-drift layer;

[0059] Figure 12A Another structural schematic diagram provided for prior art;

[0060] Figure 12B For existing technology two Figure 2 A schematic diagram showing the high-field distribution area;

[0061] Figure 12C for Figure 12A and Figure 12B The corresponding drain withstand voltage electric field distribution diagram;

[0062] Figure 12D This is a diagram showing the withstand voltage electric field distribution of the drain electrode in this disclosure;

[0063] Figure 12E for Figure 12A , Figure 12B The electric field intensity distribution curve along the Y direction of the edge of the top p+ gate region of this disclosure;

[0064] Figure 13 A flowchart illustrating a method for fabricating a junction field-effect transistor device provided in this disclosure embodiment;

[0065] Figure 14 A flowchart illustrating yet another method for fabricating a junction field-effect transistor device provided in this disclosure embodiment;

[0066] Figure 15 A flowchart illustrating yet another method for fabricating a junction field-effect transistor device provided in this disclosure embodiment;

[0067] Figure 16A for Figure 3 The diagram shows a structural schematic of a junction field-effect transistor device during its fabrication process.

[0068] Figure 16B for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0069] Figure 16C for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0070] Figure 16D for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0071] Figure 16E for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0072] Figure 16F for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0073] Figure 16G for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0074] Figure 16H for Figure 16G A top view of the junction field-effect transistor device shown;

[0075] Figure 16I for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0076] Figure 16J for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0077] Figure 16K for Figure 3The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process.

[0078] Figure 16L for Figure 3 The diagram shows another structural schematic of a junction field-effect transistor device during its fabrication process. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0080] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0081] In the following description, when a component or layer is referred to as "on" or "connected to" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. When a component or layer is referred to as "located on one side of" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. However, when a component or layer is referred to as "directly on" or "directly connected to" another component or layer, there are no intermediate components or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0082] This disclosure provides a junction field-effect transistor device, such as... Figures 3-5 As shown, Figure 3 This is a three-dimensional schematic diagram of a junction field-effect transistor (JFET) device. Figure 4 for Figure 3 A schematic diagram of the cross-section along the AA' direction. Figure 5 for Figure 3 A schematic cross-sectional view along the BB' direction shows that this junction field-effect transistor device includes an active region, and the cell structure of the active region includes:

[0083] n+ substrate 1; optionally, n+ substrate 1 is a substrate such as silicon carbide (SiC) or gallium nitride (GaN);

[0084] The n-drift layer 2 is located on one side of the n+ substrate 1; optionally, the thickness of the n-drift layer 2 can be between 1 μm and 500 μm, such as 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, etc., and the doping concentration can be 1×10⁻⁶. 14 cm -3 Up to 1×10 17 cm -3 Between, for example, 1×10 14 cm -3 1×10 15 cm -3 1×10 16 cm -3 1×10 17 cm -3 wait;

[0085] The p-type gate region 3 is located in the n-drift layer 2, and is closer to the side of the n-drift layer 2 away from the n+ substrate 1. Specifically, the p-type gate region 3 is formed by implanting p-type ions on the side of the n-drift layer 2 away from the n+ substrate 1. Optionally, the p-type ions can be aluminum, boron, or other ions, and the thickness of the p-type gate region 3 can be between 100 nm and 1 μm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, etc., and the doping concentration can be 1 × 10⁻⁶. 16 cm -3 Up to 1×10 20 cm -3 Between, for example, 1×10 16 cm -3 1×10 17 cm -3 1×10 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 wait;

[0086] The n-type channel layer 4 is located on the side of the p-type gate region 3 away from the n+ substrate 1. Optionally, the thickness of the n-type channel layer 4 can be between 200 nm and 2 μm, such as 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, etc., and the doping concentration can be 1 × 10⁻⁶. 16 cm -3 Up to 1×10 20 cm -3 Between, for example, 1×10 16 cm -3 1×10 17 cm -3 1×10 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 wait;

[0087] The p+ gate region 5 is located in the n-type channel layer 4, and is closer to the side of the n-type channel layer 4 away from the n+ substrate 1. Specifically, the p+ gate region 5 is formed by implanting p-type ions on the side of the n-type channel layer 4 away from the n+ substrate 1. Optionally, the p-type ions can be aluminum, boron, magnesium, etc., and the thickness of the p+ gate region 5 can be between 100 nm and 1 μm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, etc., and the doping concentration can be 1 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 Between, for example, 1×10 17 cm -3 1×10 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 wait.

[0088] The junction field-effect transistor device provided in this disclosure has a p-type gate region formed by implanting p-type ions on the side of the n-drift layer away from the n+ substrate 1. Therefore, it eliminates the need for high-energy p-type ion deep implantation to achieve the p-type gate region, thereby improving production efficiency. The n-type channel layer can be formed using homoepitaxial growth, which improves the device design flexibility and channel mobility. Therefore, this disclosure is similar to... Figure 1 In contrast, this disclosure avoids using p-type deep ion implantation to form the bottom p-type gate region and using n-type deep ion implantation to form the n-type channel layer, thereby improving the device design flexibility, manufacturing efficiency and channel mobility.

[0089] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figures 3-5 As shown, the distance between the edge of the p-type gate region 3 and the edge of the cell structure can be between 0.5 μm and 5 μm.

[0090] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figures 3-5 As shown, the cell structure of the active region also includes:

[0091] The p+ connection region 6 has its side away from the n+ substrate 1 located within the p+ gate region 5, its middle portion located within the n-type channel layer 4, and its side closer to the n+ substrate 1 located within the p-type gate region 3. Thus, the p+ gate region 5 and the p-type gate region 3 are connected by periodically distributed p+ connection regions 6. The p+ connection regions 6 can be located inside or at the edge of the active region. This disclosure and... Figure 2 Compared to the structure shown, the p-type gate region 3 of this disclosure is electrically connected to the gate (described later) through the p+ connection region 6 and the p+ gate region 5. This allows the threshold voltage of the device to be corrected when the on-resistance is the same, which is beneficial for the device turn-off. Specifically, the p+ connection region 6 is formed by implanting p-type ions on the side of the p+ gate region 5 away from the n+ substrate 1. The specific location of the p+ connection region 6 is affected by the ion implantation process. Optionally, aluminum, boron, or other ions can be used as p-type ions. The thickness of the p+ connection region 6 can be between 100 nm and 3 μm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, 3 μm, etc., and the doping concentration can be 1 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 Between, for example, 1×10 17 cm -3 1×10 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 wait;

[0092] The n+ source region 7 is located in the n-type channel layer 4, closer to the side of the n-type channel layer 4 away from the n+ substrate 1. The n+ source region 7 is isolated from the p+ gate region 5 by the n-type channel layer 4, and the n+ source region 7 and the p+ connection region 6 are spaced apart. Specifically, the n+ source region 7 is formed by implanting n-type ions on the side of the n-type channel layer 4 away from the n+ substrate 1, and the n+ source region 7 and the p+ connection region 6 are arranged alternately. The n+ source region 7 of the device is surrounded by the p+ gate region 5, and there is a buffer zone of the n-type channel layer 4 between the n+ source region 7 and the p+ gate region 5. That is, when the p+ gate region 5 is formed by ion implantation, the n+ source region 7 to be formed and the buffer zone are blocked. This buffer zone can effectively improve the gate reverse breakdown voltage. Optionally, the n-type ions can be nitrogen, phosphorus, silicon, arsenic, or other ions; the thickness of the n+ source region 7 can be between 100 nm and 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm, and the doping concentration can be 1 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 Between, for example, 1×10 17 cm -3 1×10 18 cm -3 1×10 19 cm -31×10 20 cm -3 wait.

[0093] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figures 3-5 As shown, the orthogonal projection of the p+ connection region 6 on the n+ substrate 1 is located between the orthogonal projections of the bottom p-type gate region 3 and the p+ gate region 5 on the n+ substrate 1, thus enabling the p-type gate region 3 and the p+ gate region 5 to be connected through the p+ connection region 6.

[0094] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figures 3-5 As shown, the cell structure of the active region also includes a first n-type current diffusion layer 81 and a second n-type current diffusion layer 82 located in the n-drift layer 2 and spaced apart. The first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 are both close to the side of the n-drift layer 2 away from the n+ substrate 1, and the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 are located on both sides of the p-type gate region 3, respectively.

[0095] The p-type gate region 3 includes: a first surface 31 and a second surface 32 disposed opposite to and parallel to the n+ substrate 1, and a first side surface 33 and a second side surface 34 connected to and disposed opposite to the first surface 31 and the second surface 32; a first n-type current diffusion layer 81 covers the first side surface 33, and a second n-type current diffusion layer 82 covers the second side surface 34. This disclosure, by introducing the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82, can reduce the specific on-resistance of the device, making the specific on-resistance of the device relatively... Figure 1 and Figure 2 This significantly reduces costs, which helps lower device costs.

[0096] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figures 3-5 As shown, the first surface 31 of the p-type gate region 3 is close to the n+ substrate 1, and the first n-type current diffusion layer 81 further covers a portion of the first surface 31, and the second n-type current diffusion layer 82 further covers a portion of the first surface 31. This can further reduce the specific on-resistance of the device, which is relatively low compared to the present invention. Figure 1 and Figure 2 The reduction rate is approximately 25% to 40%.

[0097] Specifically, such as Figures 3-5As shown, the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 are formed by implanting n-type ions on the side of the n-drift layer 2 away from the n+ substrate 1 before the formation of the p-type gate region 3 by ion implantation; optionally, nitrogen, phosphorus, or other ions can be used as n-type ions; the thickness of the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 can be between 100 nm and 2 μm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, etc., and the doping concentration can be 1 × 10⁻⁶. 14 cm -3 Up to 1×10 20 cm -3 Between, for example, 1×10 14 cm -3 1×10 15 cm -3 1×10 16 cm -3 1×10 17 cm -3 1×10 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 wait.

[0098] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figures 3-5 As shown, the orthogonal projection of the p+ gate region 5 on the n+ substrate 1 completely covers the orthogonal projections of the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 on the n+ substrate 1.

[0099] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figures 3-5 As shown, the cell structure of the active region also includes:

[0100] The dielectric layer 9 is located on the side of the p+ gate region 5 away from the n+ substrate 1. The dielectric layer 9 has a first contact region V1 corresponding to the p+ gate region 5 and a second contact region V2 corresponding to the n+ source region 7. Optionally, the first contact region V1 and the second contact region V2 are through holes that penetrate the thickness of the dielectric layer 9 and are formed by an etching process. The thickness of the dielectric layer 9 can be between 20nm and 2μm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, etc. The material of the dielectric layer 9 can be a dielectric material such as silicon dioxide or silicon nitride.

[0101] The gate ohmic contact layer 10 is located on the side of the p+ gate region 5 away from the n+ substrate 1 and is located within the first contact region V1. The gate ohmic contact layer 10 is electrically connected to the p+ gate region 5. Optionally, the material of the gate ohmic contact layer 10 can be metals such as nickel, aluminum, titanium, and tungsten, or their alloys. The thickness of the gate ohmic contact layer 10 can be between 20nm and 200nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, and 200nm.

[0102] The source ohmic contact layer 11 is located on the side of the n+ source region 7 away from the n+ substrate 1 and is located within the second contact region V2. Optionally, the source ohmic contact layer 11 and the gate ohmic contact layer 10 can be formed by a single deposition process. The material of the source ohmic contact layer 11 can be metals such as nickel, aluminum, titanium, and tungsten and their alloys. The thickness of the source ohmic contact layer 11 can be between 20nm and 200nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, etc.

[0103] The gate electrode 12 is located on the side of the dielectric layer 9 away from the n+ substrate 1 and is electrically connected to the gate ohmic contact layer 10; thus, the p+ gate region 5 is electrically connected to the gate electrode 12 through the gate ohmic contact layer 10, that is, the gate electrode 12 is electrically connected to the p-type gate region 3, the p+ connection region 6, and the p+ gate region 5; optionally, the material of the gate electrode 12 can be metals such as titanium, aluminum, gold, silver, and copper and their alloys, or it can be conductive materials such as heavily doped polycrystalline silicon, titanium nitride, and indium tin oxide;

[0104] The source electrode 13 is located on the side of the dielectric layer 9 away from the n+ substrate 1 and is electrically connected to the source ohmic contact layer 11. Thus, the n+ source region 7 is electrically connected to the source electrode 13 through the source ohmic contact layer 11. The source electrode 13 and the gate electrode 12 are isolated from the underlying semiconductor structure through the dielectric layer 9, and different cell structures of the active region of the device are connected through the source electrode 13 and the gate electrode 12. Optionally, the source electrode 13 and the gate electrode 12 can be formed by a single etching process. The material of the source electrode 13 can be metals such as titanium, aluminum, gold, silver, and copper and their alloys, or conductive materials such as heavily doped polycrystalline silicon, titanium nitride, and indium tin oxide.

[0105] The drain electrode 14 is located on the side of the n+ substrate 1 away from the n- drift layer 2. Optionally, the material of the drain electrode 14 can be metals such as nickel, aluminum, titanium, and tungsten, or their alloys. The thickness of the drain electrode 14 can be between 20nm and 2μm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, etc.

[0106] Specifically, such as Figure 6 As shown, Figure 6 for Figure 3 The structure shown is a top view after the dielectric layer 9, gate ohmic contact layer 10, source ohmic contact layer 11, gate electrode 12 and source electrode 13 are formed in sequence. There is a dielectric layer 9 of a certain width between the source electrode 13 and the gate electrode 12 to prevent leakage between the source electrode 13 and the gate electrode 12.

[0107] Specifically, such as Figures 3-5 As shown, when the device is working, electrons first flow from the source electrode 13 through the n-type channel layer 4, then through the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 into the n-drift layer 2, and finally reach the drain electrode 14 to form a current.

[0108] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figure 4 As shown, the orthographic projection of the first contact area V1 on the n+ substrate 1 is within the range of the orthographic projection of the p+ connection area 6 on the n+ substrate 1. Alternatively, the orthographic projection of the first contact area V1 on the n+ substrate 1 may not overlap with the orthographic projection of the p+ connection area 6 on the n+ substrate 1; or the orthographic projection of the first contact area V1 on the n+ substrate 1 may overlap with the orthographic projections of both the p+ connection area 6 and the p+ gate region 5 on the n+ substrate 1. All of these methods can achieve electrical connection between the gate ohmic contact layer 10 and the p+ gate region 5, thereby achieving electrical connection between the gate electrode 12 and the p+ gate region 5.

[0109] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figure 7 As shown, it also includes a terminal region BB located around the active region AA. The terminal region BB includes multiple spaced field limiting ring structures 20. The field limiting ring structure 20 includes a first field limiting ring 21 and a second field limiting ring 22 stacked and contacted. The first field limiting ring 21 is disposed in the same layer and material as the p-type gate region 3. The second field limiting ring 22 is disposed in the same layer and material as the p+ connection region 6. That is, the bottom first field limiting ring 21 is formed by sharing a photolithography mask and implantation process steps with the aforementioned p-type gate region 3, and the top second field limiting ring 22 is formed by sharing a photolithography mask and implantation process steps with the aforementioned p+ connection region 6.

[0110] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figure 8 As shown, it also includes a terminal region BB located around the active region AA. The terminal region BB includes a field limiting ring structure 20. The field limiting ring structure 20 includes multiple spaced first field limiting rings 21 and multiple spaced second field limiting rings 22. The first field limiting rings 21 are disposed in the same layer and with the same material as the p-type gate region 3. The second field limiting rings 22 are disposed in the same layer and with the same material as the p+ gate region 5. The orthogonal projection of the second field limiting rings 22 on the n+ substrate 1 covers the orthogonal projection of two adjacent first field limiting rings 21 on the n+ substrate 1. That is, the bottom first field limiting rings 21 and the aforementioned p-type gate region 3 are formed by sharing a photolithography mask and implantation process steps. The top second field limiting rings 22 and the aforementioned p+ gate region 5 are formed by sharing a photolithography mask and implantation process steps.

[0111] In some embodiments, the junction field-effect transistor device provided in this disclosure, such as Figure 9 As shown, it also includes a terminal region BB located around the active region AA. The terminal region BB includes a junction terminal extension structure 30. The junction terminal extension structure 30 includes a first junction terminal extension 31, a second junction terminal extension 32, and a third junction terminal extension 33 stacked together. The first junction terminal extension 31 is an integral structure with the p-type gate region 3. The second junction terminal extension 32 is an integral structure with the p+ connection region 6. The third junction terminal extension 33 is set in the same layer and with the same material as the p+ gate region 5. That is, the bottom first junction terminal extension 31 and the aforementioned p-type gate region 3 are formed by sharing a photolithography mask and implantation process steps. The middle second junction terminal extension 32 and the aforementioned p+ connection region 6 are formed by sharing a photolithography mask and implantation process steps. The top third junction terminal extension 33 and the aforementioned p+ gate region 5 are formed by sharing a photolithography mask and implantation process steps.

[0112] Specifically, such as Figures 7-9As shown, the terminal region BB is located on the periphery of the active region AA. By setting a field limiting ring structure 20 or a junction termination extension structure 30 in the terminal region BB, the phenomenon of electric field concentration can be reduced. At the same time, the distribution of electric field in the terminal region BB can improve the overall breakdown voltage level of the junction field-effect transistor device.

[0113] In some embodiments, in the junction field-effect transistor device provided in the present disclosure, the planar structure of the cell structure can be strip, rectangular, or hexagonal, etc. After the gate electrode and source electrode are completed, the device can be constructed into a complete device by forming different cells such as strip cells, square cells, hexagonal cells, etc. This disclosure embodiment Figure 3 Taking the rectangular planar structure of the cell structure as an example, it can also be a hexagonal cell structure layout, which can make the layout of the p+ connection region more uniform and reduce the gate electrode resistance.

[0114] In some embodiments, the junction field-effect transistor devices provided in this disclosure can be fabricated from wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) through processes such as epitaxy and ion implantation.

[0115] The inventors of this disclosure have made a difference to prior art two. Figure 2 And this disclosure Figure 3 The corresponding threshold voltage was simulated, such as Figure 10 As shown, Figure 10 For existing technology two Figure 2 With respect to this disclosure Figure 3 The corresponding simulated device transfer characteristic curve, with the horizontal axis representing the threshold voltage (V) GS The vertical axis represents the drain electrode current (I). D As can be seen, compared with the prior art, since this disclosure uses a p-type gate region 3 electrically connected to the gate electrode 12, the threshold voltage of the device is corrected when the on-resistance is the same, which is beneficial to the turn-off of the device.

[0116] like Figure 11 As shown, Figure 11 For existing technology one Figure 1 Existing technology two Figure 2 With respect to this disclosure Figure 3 The simulation diagram of the specific on-resistance of the device under different doping concentrations of the n-drift layer shows that, due to the setting of the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82, the specific on-resistance of the device can be significantly reduced compared with the prior art 1 and prior art 2, with a reduction ratio of about 25% to 40%, which is beneficial to reducing the device cost.

[0117] like Figures 12A-12E As shown, Figure 12A This is another structural diagram in the prior art. Figure 12AThe high-field distribution area was marked. Figure 12B For existing technology two Figure 2 A schematic diagram showing the high-field distribution region. Figure 12C for Figure 12A and Figure 12B The corresponding drain withstand voltage electric field distribution diagram, Figure 12D This is a diagram showing the breakdown voltage electric field distribution of the drain electrode in this disclosure. Figure 12E for Figure 12A , Figure 12B As can be seen from the electric field intensity distribution curve along the Y direction of the top p+ gate region edge in this disclosure, Figure 12A and Figure 12B The corresponding top p-type gate corner and bottom p-type gate corner have high electric fields, while this disclosure effectively suppresses the electric field intensity at the corners of the top p+ gate region and the bottom p-type gate region, thus achieving a higher breakdown voltage. Compared with prior art 1 and prior art 2, the electric field intensity suppressed by this disclosure can reach 1MV / cm.

[0118] In summary, the junction field-effect transistor device provided in this disclosure does not require high-energy p-type ion deep implantation to realize the p-type gate region, thus improving production efficiency; the n-type channel layer is formed by epitaxial growth, ensuring the channel mobility; and the formation of the first n-type current diffusion layer and the second n-type current diffusion layer by n-type ion implantation can reduce the specific on-resistance of the device.

[0119] Based on the same inventive concept, this disclosure provides a method for fabricating the above-mentioned junction field-effect transistor device. Since the principle of this fabrication method in solving the problem is similar to that of the above-mentioned junction field-effect transistor device, the implementation of the fabrication method provided in this disclosure can refer to the implementation of the above-mentioned junction field-effect transistor device provided in this disclosure, and the repeated parts will not be described again.

[0120] In some embodiments, the fabrication method of the junction field-effect transistor device provided in this disclosure, such as... Figure 13 As shown, it may include:

[0121] S1301, An n- drift layer is epitaxially formed on one side of the n+ substrate;

[0122] S1302, p-type ions are implanted on the side of the n-drift layer away from the n+ substrate to form a p-type gate region;

[0123] S1303, An n-type channel layer is epitaxially formed on the side of the p-type gate region away from the n+ substrate;

[0124] S1304. P-type ions are implanted on the side of the n-type channel layer away from the n+ substrate to form a p+ gate region.

[0125] In some embodiments, in the preparation method provided in the present disclosure, such as Figure 14 As shown, it also includes:

[0126] S1401. P-type ions are implanted on the side of the p+ gate region away from the n+ substrate to form a p+ connection region. The side of the p+ connection region away from the n+ substrate is located in the p+ gate region. The middle part of the p+ connection region is located in the n-type channel layer. The side of the p+ connection region close to the n+ substrate is located in the p-type gate region.

[0127] S1402. An n-type ion is implanted on the side of the p+ gate region away from the n+ substrate to form an n+ source region. An n-type channel layer is provided between the n+ source region and the p+ gate region, and the n+ source region and the p+ connection region are spaced apart.

[0128] In some embodiments, in the above-described preparation method provided in this disclosure, before performing step S1302, which involves implanting p-type ions on the side of the n-drift layer away from the n+ substrate to form a p-type gate region, as follows: Figure 15 As shown, it also includes: S1501, forming a first n-type current diffusion layer and a second n-type current diffusion layer at intervals on the side of the n-drift layer away from the n+ substrate by implanting n-type ions;

[0129] When performing step S1302, p-type ions are implanted on the side of the n-drift layer away from the n+ substrate to form a p-type gate region, a first n-type current diffusion layer covers the first side surface and part of the first surface of the p-type gate region, and a second n-type current diffusion layer covers the second side surface and part of the first surface of the p-type gate region.

[0130] To better understand the preparation method provided in the embodiments of this disclosure, this disclosure uses... Figure 3 Taking the junction field-effect transistor (JFET) device shown as an example, the fabrication process of the JFET device will be explained in detail.

[0131] In some embodiments, Figure 3 The fabrication process of the junction field-effect transistor device shown may specifically include the following steps:

[0132] (1) As Figure 16A As shown, an n-drift layer 2 is epitaxially grown on one side of the n+ substrate 1.

[0133] (2) Figure 16B As shown, a photolithographic mask is applied to the side of the n-drift layer 2 away from the n+ substrate 1, leaving a mask 100. Then, ion implantation (as indicated by the arrow) is performed to form a first n-type current diffusion layer 81 and a second n-type current diffusion layer 82.

[0134] (3) Figure 16CAs shown, after removing mask 100, photolithography is performed again, leaving mask 200. Then, ion implantation (as indicated by the arrow) is performed to form p-type gate region 3.

[0135] (4) Figure 16D As shown, after removing the mask 200, the wafer surface is thoroughly cleaned, and then an n-type trench layer 4 is epitaxially grown on the formed structure.

[0136] (5) Figure 16E As shown, a photolithographic mask is applied to the side of the epitaxial n-type channel layer 4 away from the n+ substrate 1, leaving a mask 300. Then, ion implantation (as indicated by the arrow) is performed to form the p+ gate region 5. Optionally, the orthogonal projection of the mask 300 on the n+ substrate 1 is located inside the orthogonal projection of the p-type gate region 3 on the n+ substrate 1.

[0137] (6) Figure 16F As shown, after removing mask 300, photolithography is performed again, leaving mask 400. Then, ion implantation (as indicated by the arrow) is performed to form p+ connection region 6. Optionally, the orthogonal projection of p+ connection region 6 on n+ substrate 1 is located between the orthogonal projections of p-type gate region 3 and p+ gate region 5 on n+ substrate 1.

[0138] (7) Figure 16G As shown, after removing mask 400, photolithography is performed again, leaving mask 500. Ion implantation is then performed (as indicated by the arrow) to form the n+ source region 7. The top view of the device after epitaxy and ion implantation is shown below. Figure 16H As shown, the n+ source region 7 of the device is surrounded by the top p+ gate region 5, and there is a buffer of n-type channel layer 4 between them at a certain distance. This buffer can effectively improve the gate reverse breakdown voltage.

[0139] (8) Figure 16I and Figure 16J As shown, after removing mask 500, dielectric layer 9 is deposited, followed by photolithography. After leaving the mask, dielectric layer 9 is etched. The etched areas can be located above the p+ gate region 5 and the n+ source region 7, forming the first contact region V1 and the second contact region V2 (i.e., vias). After etching, dielectric layer 9 is left, followed by ohmic metal deposition. The deposition areas are located above the p+ gate region 5 and the n+ source region 7, respectively. High-temperature annealing is then performed to form the gate ohmic contact layer 10 and the source ohmic contact layer 11.

[0140] (9) such as Figure 16K and Figure 16L As shown, after forming the gate ohmic contact layer 10 and the source ohmic contact layer 11, a conductive interconnect layer is deposited to form the gate electrode 12 and the source electrode 13.

[0141] (10) After completing the interconnect deposition, the drain electrode 14 is deposited and ohmic contact annealed to form the drain electrode 14, such as... Figure 4 and Figure 5 As shown.

[0142] Through the above steps (1)-(10), a process was formed. Figure 3 The junction field-effect transistor device shown.

[0143] It should be noted that in the above-described fabrication method provided in the embodiments of this disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the desired pattern formed in the actual fabrication process, and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0144] Based on the same inventive concept, this disclosure provides an electronic device including the junction field-effect transistor (JFET) device described above. Since the principle by which this electronic device solves the problem is similar to that of the JFET device, the implementation of this electronic device can refer to the implementation of the JFET device described above, and repeated details will not be elaborated further.

[0145] In some embodiments, the electronic devices provided in this disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radar, satellites, power supplies, automotive electronics, energy-saving lamps, and home appliances. Of course, the electronic devices provided in this disclosure may include not only junction field-effect transistor devices, but also other structures. For example, when the electronic device is a radar, it may also include structures such as transmitters, antennas, and receivers; when the electronic device is a mixer, it may also include structures such as input ports and output ports.

[0146] This disclosure provides a junction field-effect transistor device, its fabrication method, and an electronic device. The p-type gate region is formed by implantation ions on the side of the n-drift layer away from the n+ substrate. Therefore, it eliminates the need for high-energy p-type ion deep implantation to achieve the p-type gate region, thereby improving production efficiency. The n-type channel layer can be formed using homoepitaxial growth, which improves device design flexibility and channel mobility. Therefore, this disclosure is related to... Figure 1 In contrast, this disclosure avoids using p-type deep ion implantation to form the bottom p-type gate region and using n-type deep ion implantation to form the n-type channel layer, thereby improving the device design flexibility, manufacturing efficiency and channel mobility.

[0147] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0148] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A junction field-effect transistor device, characterized in that, Includes an active region, the cell structure of which includes: n+ substrate; An n-drift layer is located on one side of the n+ substrate; The p-type gate region is located in the n-drift layer and is close to the side of the n-drift layer away from the n+ substrate; the p-type gate region is formed by implanting p-type ions on the side of the n-drift layer away from the n+ substrate. An n-type channel layer is located on the side of the p-type gate region away from the n+ substrate; the n-type channel layer is formed by homoepitaxial growth. The p+ gate region is located in the n-type channel layer and is close to the side of the n-type channel layer away from the n+ substrate; The p+ connection region is located in the p+ gate region on the side away from the n+ substrate, the middle part of the p+ connection region is located in the n-type channel layer, and the side of the p+ connection region closer to the n+ substrate is located in the p-type gate region. The n+ source region is located in the n-type channel layer and is close to the side of the n-type channel layer away from the n+ substrate. The n+ source region is isolated from the p+ gate region through the n-type channel layer, and the n+ source region is spaced apart from the p+ connection region.

2. The junction field-effect transistor device as described in claim 1, characterized in that, The cell structure of the active region further includes a first n-type current diffusion layer and a second n-type current diffusion layer located in the n-drift layer and spaced apart. The first n-type current diffusion layer and the second n-type current diffusion layer are both close to the side of the n-drift layer away from the n+ substrate, and the first n-type current diffusion layer and the second n-type current diffusion layer are respectively located on both sides of the p-type gate region. The p-type gate region includes: a first surface and a second surface disposed opposite to and parallel to the n+ substrate, and a first side surface and a second side surface connected to and disposed opposite to the first surface and the second surface; the first n-type current diffusion layer covers the first side surface, and the second n-type current diffusion layer covers the second side surface.

3. The junction field-effect transistor device as described in claim 2, characterized in that, The first surface of the p-type gate region is close to the n+ substrate, the first n-type current diffusion layer also covers a portion of the first surface, and the second n-type current diffusion layer also covers a portion of the first surface.

4. The junction field-effect transistor device as described in claim 3, characterized in that, The orthogonal projection of the p+ gate region onto the n+ substrate completely covers the orthogonal projections of the first n-type current diffusion layer and the second n-type current diffusion layer onto the n+ substrate.

5. The junction field-effect transistor device as described in claim 4, characterized in that, The cell structure of the active region also includes: A dielectric layer is located on the side of the p+ gate region away from the n+ substrate, and the dielectric layer has a first contact region corresponding to the p+ gate region and a second contact region corresponding to the n+ source region; A gate ohmic contact layer is located on the side of the p+ gate region away from the n+ substrate and within the first contact region; the gate ohmic contact layer is electrically connected to the p+ gate region. The source ohmic contact layer is located on the side of the n+ source region away from the n+ substrate, and is located within the second contact region; The gate electrode is located on the side of the dielectric layer away from the n+ substrate and is electrically connected to the gate ohmic contact layer; The source electrode is located on the side of the dielectric layer away from the n+ substrate and is electrically connected to the source ohmic contact layer; The drain electrode is located on the side of the n+ substrate away from the n- drift layer.

6. The junction field-effect transistor device as described in claim 5, characterized in that, The orthographic projection of the first contact area on the n+ substrate lies within the orthographic projection range of the p+ connection area on the n+ substrate; Alternatively, the orthographic projection of the first contact area on the n+ substrate does not overlap with the orthographic projection of the p+ connection area on the n+ substrate; Alternatively, the orthographic projection of the first contact region on the n+ substrate overlaps with the orthographic projections of the p+ connection region and the p+ gate region on the n+ substrate.

7. The junction field-effect transistor device according to any one of claims 1-6, characterized in that, It also includes a terminal region located around the active region. The terminal region includes multiple spaced field limiting ring structures. The field limiting ring structure includes a first field limiting ring and a second field limiting ring that are stacked and contacted. The first field limiting ring is disposed in the same layer and material as the p-type gate region, and the second field limiting ring is disposed in the same layer and material as the p+ connection region.

8. The junction field-effect transistor device according to any one of claims 1-6, characterized in that, It also includes a terminal region located around the active region. The terminal region includes a field limiting ring structure. The field limiting ring structure includes a plurality of spaced first field limiting rings and a plurality of spaced second field limiting rings. The first field limiting rings are disposed in the same layer and material as the p-type gate region. The second field limiting rings are disposed in the same layer and material as the p+ gate region. The orthogonal projection of the second field limiting rings on the n+ substrate covers the orthogonal projection of two adjacent first field limiting rings on the n+ substrate.

9. The junction field-effect transistor device according to any one of claims 1-6, characterized in that, It also includes a terminal region located around the active region. The terminal region includes a junction terminal extension structure. The junction terminal extension structure includes a first junction terminal extension, a second junction terminal extension, and a third junction terminal extension stacked together. The first junction terminal extension is integral with the p-type gate region. The second junction terminal extension is integral with the p+ connection region. The third junction terminal extension is disposed in the same layer and with the same material as the p+ gate region.

10. A method for fabricating a junction field-effect transistor device, characterized in that, The method for fabricating a junction field-effect transistor device as described in any one of claims 1-9 includes: An n-drift layer is epitaxially formed on one side of the n+ substrate; p-type ions are implanted on the side of the n-drift layer away from the n+ substrate to form a p-type gate region; An n-type channel layer is formed on the side of the p-type gate region away from the n+ substrate by homoepitaxial growth; p-type ions are implanted on the side of the n-type channel layer away from the n+ substrate to form a p+ gate region; A p+ connection region is formed by implanting p-type ions on the side of the p+ gate region away from the n+ substrate. The side of the p+ connection region away from the n+ substrate is located within the p+ gate region. The middle portion of the p+ connection region is located in the n-type channel layer. The side of the p+ connection region closer to the n+ substrate is located within the p-type gate region. An n-type ion is implanted on the side of the p+ gate region away from the n+ substrate to form an n+ source region. The n+ source region and the p+ gate region are provided with an n-type channel layer, and the n+ source region and the p+ connection region are spaced apart.

11. The preparation method according to claim 10, characterized in that, Before implanting p-type ions to form a p-type gate region on the side of the n-drift layer away from the n+ substrate, the method further includes: forming a first n-type current diffusion layer and a second n-type current diffusion layer at intervals on the side of the n-drift layer away from the n+ substrate by implanting n-type ions. When p-type ions are implanted on the side of the n-drift layer away from the n+ substrate to form a p-type gate region, the first n-type current diffusion layer covers the first side surface and part of the first surface of the p-type gate region, and the second n-type current diffusion layer covers the second side surface and part of the first surface of the p-type gate region.

12. An electronic device, characterized in that, Includes the junction field-effect transistor device as described in any one of claims 1-9.

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