A mosfet device of a sic material

Abstract

The application discloses a MOSFET device of SiC material, a drain is located at the bottom, a substrate is arranged above the drain, the substrate is a heavily doped N type SiC substrate, an ohmic contact is formed between the highly doped SiC of the substrate and metal tungsten of the drain, an epitaxial layer is arranged above the substrate, is made of N type doped SiC material, is lower than the doping concentration of the substrate, the epitaxial layer comprises a P region, the P region is formed by ion implanting a P type doped SiC strip in the N type doped epitaxial layer, so that a PN junction is formed between the P type doped SiC and the N type doped SiC of the epitaxial layer, the P type doped SiC strip in the epitaxial layer is arranged at 5 mu m above the substrate, two P type doped base regions are symmetrically arranged above the P region, two P + source regions and N + source regions, two polysilicon regions are symmetrically arranged between the two P type doped base regions, the application has the advantages of small size, high voltage resistance, high temperature resistance, fast switching, low on-resistance and low loss, and is mainly applied to high-performance and high-gate oxide reliability SiC MOSFET of new energy automobile specification.

Description

Technical Field

[0001] This invention relates to the field of new energy technology, and in particular to a MOSFET device made of SiC material. Background Technology

[0002] As a core component of power electronic devices, power semiconductor devices play a crucial role. Currently, silicon-based power devices are the mainstream, but with advancements in process technology, silicon-based power devices are approaching their physical limits, struggling to meet demands for high voltage, high conversion efficiency, and high power density. Therefore, there is an urgent need to develop a MOSFET device made of SiC material to address these technical challenges.

[0003] In view of this, the present invention is hereby proposed. Summary of the Invention

[0004] The purpose of this invention is to provide a MOSFET device made of SiC material, which has the advantages of small size, high voltage resistance, high temperature resistance, fast switching, low on-resistance and low loss. It is mainly used in high-performance, high gate oxide reliability SiC MOSFETs of the new energy vehicle grade, and has broad application prospects, which is conducive to its promotion and application.

[0005] To achieve the above objectives, the present invention provides a MOSFET device made of SiC material, comprising a drain, a substrate, and an epitaxial layer. The drain is located at the bottom and serves as the terminal for output current of the MOSFET device. The drain is made of tungsten metal. A substrate is disposed above the drain. The substrate is a heavily doped N-type SiC substrate with a thickness of 1 μm and a doping concentration of 5 × 10⁻⁶. 19 cm -3 The highly doped SiC substrate forms an ohmic contact with the tungsten drain electrode. The epitaxial layer, located above the substrate, is made of N-type doped SiC material with a lower doping concentration than the substrate, and its drift region doping concentration is 2 × 10⁻⁶. 15 cm -3 The epitaxial layer has a thickness of 18 μm and includes a P-region. The P-region is formed by ion implantation of a P-type doped SiC band into the N-type doped epitaxial layer, creating a PN junction between the P-type doped SiC band and the N-type doped SiC band in the epitaxial layer. The P-type doped SiC band in the epitaxial layer is located 5 μm above the substrate, has a thickness of 3 μm, and a doping concentration of 1 × 10⁻⁶. 16 cm -3 Two P-type doped base regions are symmetrically arranged above the P-region to form a conductive channel, with a thickness of 1.8 μm and a width of 5 μm. A P-type doped base region is symmetrically arranged above the two P-type doped base regions. + Source region and N + Source region, the N + The source region is located on the inside, and the P + The source region is located in N+ Outside the source region, the P + The source region has a thickness of 1 μm and a width of 2 μm, the N + The source region has a thickness of 1 μm and a width of 3 μm, with a portion forming an ohmic contact with the electrode metal. Two polysilicon regions are symmetrically positioned between the two P-type doped base regions. These polysilicon regions are deposited using heavily N-type doped polysilicon as the device gate. Each polysilicon region is cylindrical, 2.5 μm thick and 1 μm wide, with its lower part positioned below the P-type doped base regions. + A source electrode is located above the source region, and both the source electrode and the gate electrode are made of molybdenum metal.

[0006] Preferably, the ion implantation of the P region of the epitaxial layer is performed after the epitaxial layer growth and before other processes, and the ion implantation concentration is higher than the doping concentration of the epitaxial layer itself, so as to avoid process waste and reduce the difficulty of the ion implantation process.

[0007] Preferably, the drain electrode is manufactured using a sputtering process.

[0008] Preferably, the epitaxial layer is grown on a highly doped, low-resistivity substrate using an epitaxial growth process, and a homogeneous epitaxial growth process is used to reduce the difficulty of device fabrication.

[0009] Preferably, two P-type doped base regions are formed above the N-type doped epitaxial layer using an ion implantation process.

[0010] Preferably, the P + The source region is constructed using ion implantation technology in N + Ion implantation between the source region and the P-type doped base region + The source region realizes a P-type heavily doped SiC region.

[0011] Preferably, the N + The source region is an N-type heavily doped SiC region achieved by ion implantation.

[0012] Preferably, the source and gate are fabricated using sputtering or evaporation processes.

[0013] Preferably, the polycrystalline silicon region is fabricated using a chemical vapor deposition process.

[0014] The present invention provides a MOSFET device made of SiC material, which has the following beneficial effects.

[0015] 1. SiC materials have a wider bandgap, three times that of Si. A larger bandgap reduces the intrinsic carrier concentration (by about 20 orders of magnitude compared to Si at room temperature). A high intrinsic carrier concentration can negatively impact the normal operation of devices under high temperature and high radiation conditions. A larger bandgap means that valence band electrons need to absorb more energy to transition from the valence band to the conduction band, reducing intrinsic excitation and allowing for more stable device operation.

[0016] 2. SiC materials have higher electron saturation drift velocity, which allows them to perform better in high-power applications. Electron saturation drift velocity directly affects the frequency characteristics of the device. High electron saturation drift velocity helps the device's reverse recovery, which can improve the device's frequency characteristics and give the device an advantage in high-frequency applications.

[0017] 3. SiC materials have a higher critical breakdown electric field, which is about 10 times that of Si devices. The critical breakdown electric field is an important parameter for evaluating the withstand voltage level of a device. A higher critical breakdown electric field can improve the withstand voltage of the device, reduce the length of the device drift region under the same withstand voltage, thereby reducing the on-resistance of the device and reducing unnecessary energy loss. Therefore, compared with silicon-based devices, devices made of SiC materials have lower on-resistance at the same withstand voltage.

[0018] 4. SiC materials have higher thermal conductivity, which represents the heat dissipation performance of a material. The higher the thermal conductivity, the better the heat dissipation performance of the material. High thermal conductivity allows SiC to work in higher temperature environments, which can avoid the failure of SiC materials due to excessive temperature. At the same time, it can reduce the proportion of heat dissipation devices in power electronic systems, reduce costs, and facilitate system integration. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a MOSFET device made of SiC material provided by the present invention. Detailed Implementation

[0020] The present invention will be further described below with reference to specific embodiments and accompanying drawings to help understand the content of the present invention.

[0021] like Figure 1The diagram shows a schematic of a SiC MOSFET device provided by this invention. The SiC MOSFET device includes a drain, a substrate, and an epitaxial layer. The drain, located at the bottom, serves as the terminal for the MOSFET's output current. The drain material is tungsten, which has advantages such as a high melting point, good thermal stability, and high conductivity, making it well-suited for this device. The drain is produced using a tungsten metal sputtering process, facilitating the formation of good ohmic contacts. A substrate is positioned above the drain. This substrate is the most fundamental material for fabricating power devices, as all necessary epitaxial growth processes must be performed on it. The substrate is a heavily doped N-type SiC substrate with a thickness of 1 μm and a doping concentration of 5 × 10⁻⁶. 19 cm -3 The highly doped SiC substrate forms an ohmic contact with the tungsten drain electrode. The epitaxial layer, located above the substrate, is made of N-type doped SiC material with a lower doping concentration than the substrate. Because the epitaxial layer is the main voltage-bearing region of the MOSFET device, it needs to have high resistivity to ensure a high breakdown voltage. Its drift region doping concentration is 2 × 10⁻⁶. 15 cm -3 The epitaxial layer has a thickness of 18 μm and includes a P-region. The P-region is formed by ion implantation of a P-type doped SiC band into the N-type doped epitaxial layer, creating a PN junction between the P-type doped SiC and the N-type doped SiC in the epitaxial layer. This further enhances the device's breakdown voltage and withstand voltage capability. The P-type doped SiC band in the epitaxial layer is located 5 μm above the substrate, has a thickness of 3 μm, and a doping concentration of 1 × 10⁻⁶. 16 cm -3 Two P-type doped base regions are symmetrically arranged above the P-region to form a conductive channel, with a thickness of 1.8 μm and a width of 5 μm. A P-type doped base region is symmetrically arranged above the two P-type doped base regions. + Source region and N + Source region, the N + The source region is located on the inside, and the P + The source region is located in N + Outside the source region, the P + The source region has a thickness of 1 μm and a width of 2 μm to prevent parasitic BJTs within the MOSFET device and to prevent accidental turn-on. The N... +The source region has a thickness of 1 μm and a width of 3 μm, with a portion forming an ohmic contact with the electrode metal. Two polysilicon regions are symmetrically positioned between the two P-type doped base regions. These polysilicon regions are deposited using heavily N-type doped polysilicon as the device gate. Compared to other materials, polysilicon is easier to deposit using chemical vapor deposition (CVD) and can be fabricated in thinner layers, resulting in better performance. The polysilicon regions are columnar, fabricated using CVD, and have a thickness of 2.5 μm and a width of 1 μm. The lower part of these polysilicon regions is below the P-type doped base regions, increasing the JFET area within the device and improving overall device performance. + A source electrode is located above the source region, and both the source electrode and the gate electrode are made of molybdenum metal.

[0022] Ion implantation of the P-region of the epitaxial layer is performed after epitaxial layer growth and before other processes. The ion implantation concentration is higher than the doping concentration of the epitaxial layer itself to avoid process waste and reduce the difficulty of ion implantation. The drain is fabricated using a sputtering process. The epitaxial layer is grown on a highly doped, low-resistivity substrate using a homogeneous epitaxial growth process to reduce the difficulty of device fabrication. Two P-type doped base regions are formed above the N-type doped epitaxial layer using ion implantation. + The source region is constructed using ion implantation technology in N + Ion implantation between the source region and the P-type doped base region + The source region realizes a p-type heavily doped SiC region. The N... + The source region is an N-type heavily doped SiC region created using ion implantation. The source and gate electrodes are fabricated using sputtering or evaporation processes.

[0023] This invention focuses on the selection of key materials and structural optimization for SiC MOSFET devices. By employing tungsten as the drain, a heavily doped N-type SiC substrate, and an N-type doped SiC epitaxial layer, the device's breakdown voltage and on-resistance performance parameters were successfully improved. In the epitaxial layer, ion implantation of P-type doped SiC bands and P-type doped base regions formed a PN junction and conductive channel, further enhancing the device's breakdown voltage and preventing parasitic BJT false turn-on. Furthermore, the use of heavily doped N-type and P-type source regions, along with a heavily doped N-type polysilicon gate, optimized the device structure and improved overall performance. Finally, molybdenum was selected as the source and gate materials, fabricated using sputtering or evaporation processes, ensuring the device's stability and reliability. Overall, this invention achieves significant results in improving the performance of SiC MOSFET devices.

[0024] SiC materials have a wider bandgap, three times that of Si. This larger bandgap reduces the intrinsic carrier concentration (by about 20 orders of magnitude compared to Si at room temperature), which can negatively impact device operation under high temperature and radiation conditions. A wider bandgap also means valence band electrons need to absorb more energy to transition from the valence band to the conduction band, reducing intrinsic excitation and leading to more stable device operation. SiC also exhibits a higher electron saturation drift velocity, which allows it to perform better in high-power applications. The electron saturation drift velocity directly affects the device's frequency characteristics; a high velocity facilitates reverse recovery, further enhancing frequency performance and giving the device an advantage in high-frequency applications. SiC materials possess a higher critical breakdown electric field, approximately 10 times that of Si devices. The critical breakdown electric field is a crucial parameter for evaluating the voltage withstand capability of a device. A higher critical breakdown electric field allows for improved voltage withstand capability, reduces the length of the drift region at the same voltage withstand capability, and consequently lowers the on-resistance, minimizing unnecessary energy loss. Therefore, compared to silicon-based devices, SiC devices exhibit lower on-resistance at the same voltage withstand capability. SiC also boasts higher thermal conductivity, which reflects its heat dissipation performance. Higher thermal conductivity results in better heat dissipation, enabling SiC to operate at higher temperatures and preventing failure due to overheating. Furthermore, it reduces the proportion of heat dissipation devices in power electronic systems, lowering costs and facilitating system integration.

[0025] This article uses specific examples to illustrate the inventive concept in detail. The description of the above embodiments is only for the purpose of helping to understand the core idea of ​​the present invention. It should be noted that any obvious modifications, equivalent substitutions or other improvements made by those skilled in the art without departing from the inventive concept should be included within the protection scope of the present invention.

Claims

1. A MOSFET device made of SiC material, characterized in that, The device comprises a drain, a substrate, and an epitaxial layer. The drain, located at the bottom, serves as the terminal for the output current of the MOSFET device and is made of tungsten. Above the drain is a heavily doped N-type SiC substrate with a thickness of 1 μm and a doping concentration of 5 × 10⁻⁶. 19 cm -3 The highly doped SiC substrate forms an ohmic contact with the tungsten drain electrode. The epitaxial layer, located above the substrate, is made of N-type doped SiC material with a lower doping concentration than the substrate, and its drift region doping concentration is 2 × 10⁻⁶. 15 cm -3 The epitaxial layer has a thickness of 18 μm and includes a P-region. The P-region is formed by ion implantation of a P-type doped SiC band into the N-type doped epitaxial layer, creating a PN junction between the P-type doped SiC band and the N-type doped SiC band in the epitaxial layer. The P-type doped SiC band in the epitaxial layer is located 5 μm above the substrate, has a thickness of 3 μm, and a doping concentration of 1 × 10⁻⁶. 16 cm -3 Two P-type doped base regions are symmetrically arranged above the P-region to form a conductive channel, with a thickness of 1.8 μm and a width of 5 μm. A P-type doped base region is symmetrically arranged above the two P-type doped base regions. + Source region and N + Source region, the N + The source region is located on the inside, and the P + The source region is located in N + Outside the source region, the P + The source region has a thickness of 1 μm and a width of 2 μm, the N + The source region has a thickness of 1 μm and a width of 3 μm, with a portion forming an ohmic contact with the electrode metal. Two polysilicon regions are symmetrically positioned between the two P-type doped base regions. These polysilicon regions are deposited using heavily N-type doped polysilicon as the device gate. Each polysilicon region is cylindrical, 2.5 μm thick and 1 μm wide, with its lower part positioned below the P-type doped base regions. + A source electrode is located above the source region, and both the source electrode and the gate electrode are made of molybdenum metal.

2. A MOSFET device made of SiC material according to claim 1, characterized in that, Ion implantation in the P region of the epitaxial layer is performed after the epitaxial layer is grown, and the ion implantation concentration is higher than the doping concentration of the epitaxial layer itself.

3. A MOSFET device made of SiC material according to claim 2, characterized in that, The drain electrode is manufactured using a sputtering process.

4. A MOSFET device made of SiC material according to claim 3, characterized in that, The epitaxial layer is grown on a highly doped, low-resistivity substrate using an epitaxial growth process.

5. A MOSFET device made of SiC material according to claim 4, characterized in that, Two P-type doped base regions are formed above the N-type doped epitaxial layer using an ion implantation process.

6. A MOSFET device made of SiC material according to claim 5, characterized in that, The P + The source region is constructed using ion implantation technology in N + Ion implantation between the source region and the P-type doped base region + The source region realizes a P-type heavily doped SiC region.

7. A MOSFET device made of SiC material according to claim 6, characterized in that, The N + The source region is an N-type heavily doped SiC region achieved by ion implantation.

8. A MOSFET device made of SiC material according to claim 7, characterized in that, The source and gate are fabricated using sputtering or evaporation processes.

9. A MOSFET device made of SiC material according to claim 8, characterized in that, The polycrystalline silicon region was fabricated using a chemical vapor deposition process.

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