Array substrate and preparation method thereof, light-emitting substrate, display module and display device

Abstract

The embodiment of the invention provides an array substrate and a preparation method thereof, a light-emitting substrate, a display module and a display device, relates to the technical field of display, and aims to improve the resolution of the display device. The array substrate comprises a substrate, a binding electrode and a circuit layer. The substrate is provided with a first via hole. The binding electrode is arranged in the first via hole; the binding electrode is configured to be connected with a circuit board. The circuit layer is disposed on the substrate. The circuit layer comprises a plurality of pixel driving circuits, and the pixel driving circuits are connected with the binding electrodes. The pixel driving circuit comprises an oxide transistor, and the orthographic projection of at least one oxide transistor on the reference surface is located in the range of the orthographic projection of the opening, close to the line layer, of the first via hole on the reference surface. The reference surface is a plane where the surface of the substrate away from the circuit layer is located. The array substrate is used for preparing a light-emitting substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a light-emitting substrate, a display module, and a display device. Background Art

[0002] With the development of light emitting diode technology, sub-millimeter (Micro) or even micron (Mini) light emitting diode (LED) backlight sources have been widely used. As a result, not only can the screen contrast of products such as liquid crystal display (LCD) using this backlight source reach the level of organic light emitting diode (OLED) display products, but also the product can retain the technical advantages of liquid crystal display, thereby improving the display effect of the picture and providing users with a better visual experience.

[0003] In some related technologies, the pixel driving circuit in the display device is connected to the driving chip on the other side through a via hole penetrating the substrate to receive a driving signal. However, the pixel driving circuit and the via hole are staggered, and the via hole is large in size and needs to occupy a large space, which is not conducive to the space utilization of the array substrate and the improvement of the resolution of the display device. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide an array substrate and a preparation method thereof, a light-emitting substrate, a display module, and a display device, so as to reduce the total area occupied by the pixel driving circuit and the vias, and improve the space utilization of the array substrate and the resolution of the display device.

[0005] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0006] In one aspect, an array substrate is provided. The array substrate comprises a substrate, a binding electrode and a circuit layer. The substrate is provided with a first via hole. The binding electrode is arranged in the first via hole; the binding electrode is configured to connect a circuit board. The circuit layer is arranged on the substrate. The circuit layer comprises a plurality of pixel driving circuits, and the pixel driving circuits are connected to the binding electrode. The pixel driving circuit comprises an oxide transistor, and the orthographic projection of at least one of the oxide transistors on a reference plane is located within the range of the orthographic projection of an opening of the first via hole close to the circuit layer on the reference plane. The reference plane is a plane where the surface of the substrate away from the circuit layer is located.

[0007] In the array substrate provided by the embodiment of the present disclosure, the area occupied by the oxide transistor on the reference surface is within the range of the area occupied by the first via hole on the reference surface. That is, the oxide transistor in the pixel driving circuit occupies the same area with the first via hole, which can reduce the total area occupied by the pixel driving circuit and the first via hole compared to the staggered arrangement of the pixel driving circuit and the first via hole, thereby improving the space utilization of the array substrate and the resolution of the display device.

[0008] In some embodiments, the pixel driving circuit further includes a low-temperature polysilicon transistor. The circuit layer includes a first driving circuit layer and a second driving circuit layer. The first driving circuit layer is disposed on the substrate. The first driving circuit layer includes the low-temperature polysilicon transistor, and the low-temperature polysilicon transistor is staggered with the first via. The second driving circuit layer is disposed on a side of the first driving circuit layer away from the substrate. The second driving circuit layer includes the oxide transistor.

[0009] In some embodiments, the first driving circuit layer covers the first via hole, and a groove is formed at a portion located at the first via hole. The oxide transistor includes a second active portion. The second driving circuit layer includes a second semiconductor layer and a second conductive layer, and the second semiconductor layer includes the second active portion. The second active portion is disposed on a sidewall of the groove. The second conductive layer is disposed on a side of the second semiconductor layer away from the substrate. The second conductive layer includes a second gate line, and an orthographic projection of the second gate line on the sidewall of the groove overlaps with an orthographic projection of the second active portion on the sidewall of the groove.

[0010] In some embodiments, the first driving circuit layer includes a third gate line, and an orthographic projection of the third gate line on the sidewall of the groove overlaps with an orthographic projection of the second active portion on the sidewall of the groove.

[0011] In some embodiments, the circuit layer further comprises a source-drain conductive layer, the source-drain conductive layer is disposed on a side of the second driving circuit layer away from the substrate. The source-drain conductive layer comprises a first voltage signal line, and the first voltage signal line is connected to the third gate line.

[0012] In some embodiments, the second semiconductor layer further includes a second doped portion, the second doped portion is connected to the second active portion and extends to the bottom of the groove and / or extends outside the groove. And / or, the second gate line extends to the bottom of the groove and / or extends outside the groove. And / or, the third gate line extends to the bottom of the groove and / or extends outside the groove.

[0013] In some embodiments, the low-temperature polysilicon transistor includes a first active portion. The first driving circuit layer includes a first semiconductor layer, a first conductive layer, and a third conductive layer. The first semiconductor layer includes the first active portion. The first conductive layer is disposed on a side of the first semiconductor layer away from the substrate. The second conductive layer includes a first gate line, and the orthographic projection of the first gate line on the substrate overlaps with the orthographic projection of the first active portion on the substrate. The third conductive layer is disposed on a side of the first conductive layer away from the substrate. The third conductive layer includes a first electrode plate, and the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the first gate line on the substrate.

[0014] In some embodiments, the third gate line is located in the third conductive layer.

[0015] In some embodiments, the circuit layer further includes a light shielding layer, the light shielding layer is disposed between the substrate and the first semiconductor layer. The light shielding layer includes a light shielding portion, the orthographic projection of the light shielding portion on the substrate overlaps with the orthographic projection of the first active portion on the substrate, and the light shielding portion is connected to the first gate line.

[0016] In some embodiments, the pixel driving circuit includes a plurality of oxide transistors, and the orthographic projections of at least two of the oxide transistors on the reference plane are located within the range of the orthographic projections of the opening of the same first via hole close to the wiring layer on the reference plane.

[0017] In some embodiments, a radial dimension of the first via hole is 5 μm to 20 μm.

[0018] On the other hand, a light-emitting substrate is provided. The light-emitting substrate comprises an array substrate, a light-emitting device and a circuit board as described in any of the above embodiments. The light-emitting device is disposed on the array substrate and connected to a pixel driving circuit of the array substrate. The circuit board is disposed on a side of the array substrate away from the light-emitting device and connected to the binding electrode.

[0019] In another aspect, a display module is provided. The display module comprises a light-emitting substrate as described in any of the above embodiments and a plurality of optical films. The light-emitting substrate has a light-emitting side and a non-light-emitting side that are arranged opposite to each other, and the plurality of optical films are arranged on the light-emitting side of the light-emitting substrate.

[0020] In another aspect, a display device is provided, comprising the display module and a housing as described in the above embodiment, wherein the display module is disposed in the housing.

[0021] On the other hand, a method for preparing an array substrate is provided. The method for preparing an array substrate is used to prepare an array substrate as described in any of the above embodiments, comprising: forming a binding electrode on a substrate. Forming a substrate on the substrate, and opening a first via hole. The first via hole exposes at least a portion of the binding electrode. Forming a circuit layer on the substrate. The circuit layer includes a plurality of pixel driving circuits, and the pixel driving circuits are connected to the binding electrode. The pixel driving circuit includes an oxide transistor, and the orthographic projection of at least one of the oxide transistors on a reference plane is located within the range of the orthographic projection of an opening of the first via hole close to the circuit layer on the reference plane. The reference plane is a plane where the surface of the substrate away from the circuit layer is located. Removing the substrate.

[0022] The above-mentioned light-emitting substrate, display module, display device and method for manufacturing the array substrate have the same structure and beneficial technical effects as the array substrate provided in some of the above-mentioned embodiments, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0024] Figure 1 is a structural diagram of a display device according to some embodiments;

[0025] Figure 2 is a structural diagram of another display device according to some embodiments;

[0026] Figure 3 is a cross-sectional view of a display device according to some embodiments;

[0027] Figure 4 is a cross-sectional view of a display module according to some embodiments;

[0028] Figure 5 is a top view of a light emitting substrate according to some embodiments;

[0029] Figure 6 is a top view of an array substrate according to some embodiments;

[0030] Figure 7 is a circuit diagram of a pixel driving circuit according to some embodiments;

[0031] Figure 8 to Figure 12is a flow chart of a method for preparing an array substrate according to some embodiments;

[0032] Fig.13 and Fig.14 FIG. 1 is a diagram showing the preparation steps of a method for preparing an array substrate according to some embodiments. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0034] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0035] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0036] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0037] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0038] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0039] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0040] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0041] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0042] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0043] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0044] The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors (such as oxide thin film transistors) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples.

[0045] Herein, the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0046] In the circuits provided in the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram being equivalent.

[0047] like Figure 1 As shown, some embodiments of the present disclosure provide a display device 1000, which may be any device that displays images, whether in motion (eg, video) or fixed (eg, still image), and whether text or images.

[0048] For example, see Figure 1 The display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.

[0049] For example, Figure 1 As shown, the display device 1000 may be a portable display product; for example, the display device 1000 may be Figure 1 For another example, see Figure 2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be Figure 2 The watch shown in.

[0050] It should be noted that, depending on different application scenarios, the shape of the display surface of the display device 1000 is not unique, and the shape of the display surface of the display device 1000 can be any one of circular, elliptical or polygonal, which is not specifically limited in the embodiments of the present disclosure.

[0051] In some embodiments, see Figure 3 The display device 1000 includes a display module 100 and a housing 200 , and the display module 100 is disposed in the housing 200 .

[0052] For example, Figure 3 As shown, the display module 100 may include a light-emitting substrate 300, a cover plate 400 and a circuit board 500, and the circuit board 500 is connected to the light-emitting substrate 300 to provide a driving signal to the light-emitting substrate 300. The longitudinal section of the housing 200 may be, for example, U-shaped. The light-emitting substrate 300 and the circuit board 500 may be arranged in the housing 200, and the cover plate 400 is arranged on the light-emitting side of the light-emitting substrate 300 and is located at the opening of the housing 200.

[0053] It should be noted that the light emitting substrate 300 has a light emitting side and a non-light emitting side. The light emitting side refers to the side from which the light emitting substrate 300 emits light ( Figure 3 The non-light-emitting side refers to the other side opposite to the light-emitting side ( Figure 3 The lower side of the light emitting substrate 300).

[0054] In some embodiments, see Figure 4 The display module 100 further includes a plurality of optical films 600 , which are disposed on the light-emitting side of the light-emitting substrate 300 , that is, the light emitted from the light-emitting substrate 300 is emitted after passing through the optical films 600 .

[0055] The optical film 600 modulates the wavelength of light emitted from the light-emitting substrate 300 and / or modulates the propagation direction of light.

[0056] For example, Figure 4 As shown, the light-emitting substrate 300 can directly emit white light, and the propagation direction of the white light is modulated after passing through the multiple optical films 600 and then emitted to the outside. Alternatively, the light-emitting substrate 300 can also emit light of other colors (such as blue light), and then pass through the multiple optical films 600 to achieve modulation of the wavelength of the light and / or the modulation of the propagation direction and then emit to the outside.

[0057] For example, see Figure 4 The plurality of optical films 600 include a scattering layer 610, a color conversion layer 620, a diffuser 630 and a composite film 640. The scattering layer 610, the color conversion layer 620, the diffuser 630 and the composite film 640 can be sequentially arranged away from the light-emitting substrate 300, for example.

[0058] The scattering layer 610 can blur the light emitted by the light-emitting substrate 300 and provide support for the color conversion layer 620, the diffuser 630 and the composite film 640. The color conversion layer 620 can convert the light of a certain color emitted by the light-emitting substrate 300 into white light under the stimulation of the light, so as to improve the utilization rate of the light energy of the light-emitting substrate 300. The diffuser 630 can homogenize the light passing through the diffuser 630. The composite film 640 can improve the light extraction efficiency of the light-emitting substrate 300, thereby improving the display brightness of the display device 1000.

[0059] It should be noted that the composite film 640 may include a brightness enhancement film (BEF) and a dual brightness enhancement film (DBEF), which utilizes the principles of total reflection, refraction and polarization to increase the light flux within a certain angle range to improve the brightness of the display device 1000.

[0060] For example, see Figure 4 , the light-emitting substrate 300 emits blue light. The color conversion layer 620 may include a red quantum dot material, a green quantum dot material, and a transparent material. When the blue light emitted by the light-emitting substrate 300 passes through the red quantum dot material, it is converted into red light; when the blue light passes through the green quantum dot material, it is converted into green light; the blue light can directly pass through the transparent material; then, the blue light, the red light, and the green light are mixed and superimposed in a certain proportion to present white light. Finally, the scattering layer 610 and the diffuser 630 can modulate the incident light in different propagation directions and emit it in a more uniform state, so as to improve the light shadow produced by the light-emitting substrate 300 and improve the display quality of the display device 1000.

[0061] In some embodiments, see Figure 4 The light emitting substrate 300 includes an array substrate 10 and a plurality of light emitting devices 20 .

[0062] Among them, Figure 5 As shown, the array substrate 10 has a light-emitting area A and a peripheral area B located at least on one side of the light-emitting area A. The light-emitting area A can be configured to set a light-emitting device 20, for example, the light-emitting device 20 is set in the light-emitting area A. The peripheral area B can be configured to set a driving circuit and circuit wiring, for example, a gate driving circuit.

[0063] In addition, if Figure 4As shown, the light emitting device 20 may include one or more of a micro light emitting diode (Micro Light Emitting Diode, Micro LED for short) and / or a sub-millimeter light emitting diode (Mini Light Emitting Diode, Mini LED for short).

[0064] It should be noted that the size (eg, length) of Micro LED is less than 50 microns, for example, 10 to 50 microns. The size (eg, length) of Mini LED is 50 to 150 microns, for example, 80 to 120 microns.

[0065] In some embodiments, see Figure 6 The array substrate 10 includes a substrate 11 and a circuit layer 12 , and the circuit layer 12 is arranged on the substrate 11 .

[0066] like Figure 6 As shown, the substrate 11 can be a rigid substrate or a flexible substrate. The material of the rigid substrate includes at least one of glass, quartz, sapphire, ceramic and polymethyl methacrylate (PMMA). The material of the flexible substrate includes at least one of epoxy resin, triazine, silicone resin and polyimide. The material of the conductive layer 103 includes at least one of copper, molybdenum-niobium alloy, nickel and indium tin oxide.

[0067] The thickness of the substrate 11 is 5 μm to 20 μm. For example, the thickness of the substrate 11 is any one of 5 μm, 7 μm, 10 μm, 12 μm, 15 μm, 18 μm, and 20 μm.

[0068] like Figure 3 , Figure 6 and Figure 7 As shown, the circuit layer 12 includes a plurality of pixel driving circuits 121 , and the pixel driving circuits 121 are connected to the circuit board 500 and the light emitting device 20 to transmit driving signals to the light emitting device 20 .

[0069] In some examples, such as Figure 6 As shown, the array substrate 10 further includes a binding electrode P, the substrate 11 is provided with a first via hole 110, and the binding electrode P is disposed in the first via hole 110. The binding electrode P is configured to connect to the circuit board 500. The material of the binding electrode P includes a conductive metal, and illustratively, the material of the binding electrode P includes at least one of titanium, aluminum and molybdenum.

[0070] It should be noted that the radial dimension of the first via hole 110 is 5 μm to 20 μm. For example, the radial dimension of the first via hole 110 is any one of 5 μm, 7 μm, 10 μm, 12 μm, 15 μm, 18 μm and 20 μm. In addition, the thickness of the binding electrode P is For example, the thickness of the binding electrode P is and Any one of .

[0071] For example, see Figure 3 , Figure 4 and Figure 6 , the circuit board 500 is disposed on the side of the substrate 11 away from the circuit layer 12, and is connected to the binding electrode P on the side of the substrate 11 away from the circuit layer 12. The pixel driving circuit 121 is connected to the binding electrode P through the first via 110, thereby being electrically connected to the circuit board 500 to receive a fixed driving signal provided by the circuit board 500. In this case, the pixel driving circuit 121 is directly connected to the circuit board 500 on the other side of the substrate 11 through the first via 110, so that it can avoid winding wires from the edge of the substrate 11 to be bound and connected to the circuit board 500, and the frame of the array substrate 10 can be reduced, thereby facilitating the narrow frame design of the display device 1000.

[0072] It should be noted that the binding electrode P can block the end of the first via hole 110 away from the circuit layer 12 , and the surface of the binding electrode P away from the circuit layer 12 can be substantially flush with the surface of the substrate 11 away from the circuit layer 12 .

[0073] Among them, Figure 6 As shown, the circuit layer 12 may include a fourth conductive layer 70, and the fourth conductive layer 70 includes a fan-out routing 71. The fan-out routing 71 covers the binding electrode P exposed by the first via hole 110 and extends outside the first via hole 110, so that the pixel driving circuit 121 is outside the first via hole 110 and overlaps with the fan-out routing 71, thereby connecting with the binding electrode P.

[0074] The thickness of the fourth conductive layer 70 is For example, the thickness of the fourth conductive layer 70 is

[0075] and Any one of .

[0076] It should be noted that the circuit layer 12 may further include a passivation layer 81, which is disposed between the fourth conductive layer 70 and the substrate 11 to prevent oxidation of the fourth conductive layer 70. The passivation layer 81 may be partially located in the first via hole 110, covering the side wall of the first via hole 110 and exposing the binding electrode P; or the first via hole 110 may be completely avoided, that is, the passivation layer 81 is located on the upper side of the substrate 11, and the first via hole 110 is completely exposed. The specific selection may be based on the number of mask openings, and the embodiment of the present disclosure is not specifically limited here.

[0077] However, in the related art, the pixel driving circuit and the via hole are staggered, and the via hole is large in size and occupies a large space, which is not conducive to improving the space utilization of the array substrate and the resolution of the display device.

[0078] Based on this, see Figure 6 In some embodiments of the present disclosure, in the array substrate 10 , at least one pixel driving circuit 121 includes an oxide transistor T1 , for example, all pixel driving circuits 121 include an oxide transistor T1 .

[0079] The orthographic projection of at least one oxide transistor T1 on the reference plane is within the range of the orthographic projection of the opening of the first via 110 close to the circuit layer 12 on the reference plane. It should be noted that the reference plane is the plane where the surface of the substrate 11 away from the circuit layer 12 is located.

[0080] In this case, the area occupied by the oxide transistor T1 on the reference surface is within the range of the area occupied by the first via hole 110 on the reference surface. That is, the oxide transistor T1 in the pixel driving circuit 121 occupies the same area with the first via hole 110. Compared with the pixel driving circuit 121 and the first via hole 110 being staggered, the total area occupied by the pixel driving circuit 121 and the first via hole 110 can be reduced, thereby improving the space utilization of the array substrate 10 and the display device 1000 (see Figure 1 ) resolution.

[0081] On this basis, if Figure 6 As shown, in the array substrate 10 provided in some embodiments of the present disclosure, the pixel driving circuit 121 further includes a low-temperature polysilicon transistor T2.

[0082] It should be understood that the active layer of the low temperature polysilicon transistor T2 uses low temperature polysilicon (LTPS for short), and the low temperature polysilicon transistor T2 has the advantages of high mobility and fast charging, etc. The active layer of the oxide transistor T1 uses an oxide semiconductor (Oxide), such as indium gallium zinc oxide, indium gallium tin oxide, etc., and the oxide transistor T1 has the advantages of low leakage current, etc.

[0083] Based on this, the low-temperature polysilicon transistor T2 and the oxide transistor T1 are integrated on one array substrate 10, which can take advantage of both to reduce leakage current, lower power consumption, achieve low-frequency driving, and improve display quality.

[0084] It is understandable that the structure of the pixel driving circuit 121 includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit 121 may include "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C" structures. Among them, "T" represents a transistor, and the number in front of "T" represents the number of transistors, and "C" represents a storage capacitor, and the number in front of "C" represents the number of storage capacitors.

[0085] Below, some embodiments of the present disclosure are exemplarily described by taking the pixel driving circuit 121 structure of 7T1C as an example, that is, the pixel driving circuit 121 includes 7 transistors and 1 capacitor C, but the implementation of the present disclosure is not limited to this, and any other structure of the pixel driving circuit 121 can also be considered as long as the same technical concept is applied.

[0086] For example, see Figure 7 , the pixel driving circuit 121 includes 7 transistors and 1 capacitor C.

[0087] like Figure 7 As shown, a first electrode of the first transistor T1 ′ is coupled to the initial switching signal terminal VINIT, a second electrode of the first transistor T1 ′ is coupled to the second node N2 ′, and a control electrode of the first transistor T1 ′ is coupled to the first reset signal terminal RESET1 .

[0088] like Figure 7 As shown, a first electrode of the second transistor T2 ′ is coupled to the second node N2 ′, a second electrode of the second transistor T2 ′ is coupled to the fourth node N4 ′, and a control electrode of the second transistor T2 ′ is coupled to the first scan signal terminal GATE1 .

[0089] like Figure 7As shown, a first electrode of the third transistor T3' is coupled to the third node N3', a second electrode of the third transistor T3' is coupled to the fourth node N4', and a control electrode of the third transistor T3' is coupled to the second node N2'.

[0090] like Figure 7 As shown, a first electrode of the fourth transistor T4 ′ is coupled to the data signal terminal DATA, a second electrode of the fourth transistor T4 ′ is coupled to the third node N3 ′, and a control electrode of the third transistor T3 ′ is coupled to the second scan signal terminal GATE2 .

[0091] like Figure 7 As shown, a first electrode of the fifth transistor T5 ′ is coupled to the first voltage signal terminal VDD, a second electrode of the fifth transistor T5 ′ is coupled to the third node N3 ′, and a control electrode of the fifth transistor T5 ′ is coupled to the enable signal terminal EM.

[0092] like Figure 7 As shown, a first electrode of the sixth transistor T6 ′ is coupled to the fourth node N4 ′, a second electrode of the sixth transistor T6 ′ is coupled to the first node N1 ′, and a control electrode of the sixth transistor T6 ′ is coupled to the enable signal terminal EM.

[0093] like Figure 7 As shown, a first electrode of the seventh transistor T7 ′ is coupled to the initial switching signal terminal VINIT, a second electrode of the seventh transistor T7 ′ is coupled to the first node N1 ′, and a control electrode of the seventh transistor T7 ′ is coupled to the second reset signal terminal RESET2 .

[0094] like Figure 7 As shown, the first plate of the capacitor C is coupled to the first voltage signal terminal VDD, and the second plate of the capacitor C is coupled to the second node N2'.

[0095] The first transistor T1' and the second transistor T2' are both N-type oxide transistors, and the third transistor T3', the fourth transistor T4', the fifth transistor T5', the sixth transistor T6' and the seventh transistor T7' are all P-type low temperature polysilicon transistors.

[0096] That is to say, the above-mentioned oxide transistor T1 can be the first transistor T1' or the second transistor T2', and the above-mentioned low-temperature polysilicon transistor T2 can be any one of the third transistor T3', the fourth transistor T4', the fifth transistor T5', the sixth transistor T6' and the seventh transistor T7', which is not specifically limited in the embodiments of the present disclosure.

[0097] Below, some embodiments of the present disclosure are exemplarily described by taking the pixel driving circuit 121 structure as 7T1C, and the pixel driving circuit 121 includes a low-temperature polysilicon transistor and an oxide transistor as an example, but the implementation of the present disclosure is not limited to this, and any other structure of the pixel driving circuit 121 can also be considered as long as the same technical concept is applied.

[0098] In some embodiments, see Figure 6 The circuit layer 12 includes a first driving circuit layer 30 and a second driving circuit layer 40. The first driving circuit layer 30 is disposed on the substrate 11 and includes a low-temperature polysilicon transistor T2. The second driving circuit layer 40 is disposed on a side of the first driving circuit layer 30 away from the substrate 11 and includes an oxide transistor T1.

[0099] In some embodiments, Figure 6 As shown, the low-temperature polysilicon transistor T2 includes a first active portion 311. The low-temperature polysilicon transistor T2 is staggered with the first via 110 to avoid stacking of the low-temperature polysilicon transistor T2 and the oxide transistor T1, thereby reducing electromagnetic interference between the low-temperature polysilicon transistor T2 and the oxide transistor T1. Moreover, the first active portion 311 can be directly disposed in a relatively flat area outside the first via 110, which is conducive to forming the first active portion 311 using a low-temperature polysilicon process and reducing the process difficulty.

[0100] For example, Figure 6 As shown, the first driving circuit layer 30 includes a first semiconductor layer 31, a first conductive layer 32 and a third conductive layer 33. The first conductive layer 32 is disposed on a side of the first semiconductor layer 31 away from the substrate 11. The third conductive layer 33 is disposed on a side of the first conductive layer 32 away from the substrate 11.

[0101] Among them, see Figure 6 The first semiconductor layer 31 includes a first active portion 311, and the first conductive layer 32 includes a first gate line 321. The orthographic projection of the first gate line 321 on the substrate 11 overlaps with the orthographic projection of the first active portion 311 on the substrate 11 to form a low-temperature polysilicon transistor T2. For example, the orthographic projection of the first active portion 311 on the substrate 11 is located within the range of the orthographic projection of the first gate line 321 on the substrate 11.

[0102] It should be noted that the first conductive layer 32 may include a plurality of first gate lines 321. The scanning signals transmitted by the plurality of first gate lines 321 may be the same or different, which is not specifically limited in the embodiment of the present disclosure.

[0103] In addition, see Figure 6The third conductive layer 33 includes a first electrode plate 331, and the orthographic projection of the first electrode plate 331 on the substrate 11 overlaps with the orthographic projection of the first gate line 321 on the substrate 11. The overlapping portion of the first electrode plate 331 and the first gate line 321 forms a capacitor C.

[0104] On this basis, if Figure 6 As shown, the circuit layer 12 may further include a source-drain conductive layer 50, which is disposed on a side of the second driving circuit layer 40 away from the substrate 11. The source-drain conductive layer 50 includes a first voltage signal line 51, which is connected to the first electrode plate 331 to provide a first voltage signal to the pixel driving circuit 121.

[0105] It should be noted that the voltage transmitted by the first voltage signal line 51 is 0V-10V. For example, the voltage transmitted by the first voltage signal line 51 is 4.6V.

[0106] In addition, the source-drain conductive layer 50 may further include a data line 52, a switching line 53, and an initialization signal line 54. The data line 52 may be connected to the first active portion 311 of a low-temperature polysilicon transistor T2 to provide a data signal. One end of the switching line 53 may be connected to the first active portion 311 of a low-temperature polysilicon transistor T2, and the other end may be connected to the fan-out line 71 to transmit a driving signal. The initialization signal line 54 may provide an initialization signal to the pixel driving circuit 121.

[0107] It should be noted that different film layers can be overlapped by providing second vias and transfer pads, which is not specifically limited in the embodiments of the present disclosure.

[0108] In some embodiments, Figure 6 As shown, the circuit layer 12 further includes a light shielding layer 60 , and the light shielding layer 60 is disposed between the substrate 11 and the first semiconductor layer 31 .

[0109] The light shielding layer 60 includes a light shielding portion 61, and the orthographic projection of the light shielding portion 61 on the substrate 11 overlaps with the orthographic projection of the first active portion 311 on the substrate 11 to form the bottom gate of the low-temperature polysilicon transistor T2. Here, the light shielding portion 61 can be connected to the first gate line 321 on the upper side of the corresponding first active portion 311, so that the low-temperature polysilicon transistor T2 forms a dual-gate structure, reducing the risk of leakage current of the low-temperature polysilicon transistor T2.

[0110] It should be noted that the thickness of the light shielding layer 60 is For example, the thickness of the light shielding layer 60 is

[0111] and Any one of .

[0112] In addition, the orthographic projection of the first active portion 311 on the substrate 11 can be, for example, located within the range of the orthographic projection of the light shielding portion 61 on the substrate 11. In this way, the light shielding portion 61 can block the external ambient light from irradiating the first active portion 311, thereby reducing the risk of the threshold voltage shift of the second low-temperature polysilicon transistor T2 under the irradiation of the external ambient light.

[0113] It should be understood that see Figure 6 In the fourth conductive layer 70 , the light shielding layer 60 , the first semiconductor layer 31 , the first conductive layer 32 and the third conductive layer 33 , other insulating film layers may be provided between every two adjacent layers.

[0114] It should be noted that the materials of the fourth conductive layer 70 , the light shielding layer 60 , the first conductive layer 32 and the third conductive layer 33 include at least one of molybdenum, magnesium, aluminum, copper and titanium, which is not specifically limited in the embodiments of the present disclosure.

[0115] For example, Figure 6 As shown, the array substrate 10 further includes a barrier layer 91 , a buffer layer 92 , a first gate insulating layer 93 and a second gate insulating layer 94 .

[0116] The blocking layer 91 is located between the fourth conductive layer 70 and the light shielding layer 60. The buffer layer 92 is located between the light shielding layer 60 and the first semiconductor layer 31. The first gate insulating layer 93 is located between the first semiconductor layer 31 and the first conductive layer 32. The second gate insulating layer 94 is located between the first conductive layer 32 and the third conductive layer 33.

[0117] It should be noted that the materials of the blocking layer 91 , the buffer layer 92 , the first gate insulating layer 93 , and the second gate insulating layer 94 include at least one of inorganic insulating materials of silicon nitride, silicon oxynitride, and silicon oxide, which is not specifically limited in the embodiments of the present disclosure.

[0118] In some embodiments, Figure 6 As shown, the oxide transistor T1 includes a second active portion 411. The orthographic projection of the oxide transistor T1 on the reference plane is located within the range of the orthographic projection of the opening of the first via hole 110 close to the circuit layer 12 on the reference plane. That is, the orthographic projection of the second active portion 411 on the reference plane is located within the range of the orthographic projection of the opening of the first via hole 110 close to the circuit layer 12 on the reference plane.

[0119] For example, Figure 6 As shown, the second driving circuit layer 40 includes a second semiconductor layer 41 and a second conductive layer 42, and the second conductive layer 42 is disposed on a side of the second semiconductor layer 41 away from the substrate 11. Figure 6The second semiconductor layer 41 includes a second active portion 411. The second conductive layer 42 includes a second gate line 421, and the second gate line 421 is disposed opposite to the second active portion 411 to form an oxide transistor T1.

[0120] For example, Figure 6 , Fig.13 and Fig.14 As shown, the first driving circuit layer 30 covers the first via hole 110, and the portion located at the first via hole 110 forms a groove. The second active portion 411 is disposed on the side wall of the groove, and the orthographic projection of the second gate line 421 on the side wall of the groove overlaps with the orthographic projection of the second active portion 411 on the side wall of the groove to form a vertical oxide transistor T1. For example, the orthographic projection of the second active portion 411 on the side wall of the groove is located within the range of the orthographic projection of the second gate line 421 on the side wall of the groove.

[0121] At this time, while the occupied area on the horizontal plane remains unchanged, the second active portion 411 is arranged on the side wall of the groove, that is, the second active portion 411 is arranged on the inclined surface, which can increase the length of the second active portion 411 along the inclined surface, thereby increasing the channel length of the oxide transistor T1 and improving the stability of the oxide transistor T1.

[0122] In some embodiments, see Figure 6 , Fig.13 and Fig.14 , the first driving circuit layer 30 further includes a third gate line 332, and the orthographic projection of the third gate line 332 on the side wall of the groove overlaps with the orthographic projection of the second active portion 411 on the side wall of the groove. For example, the orthographic projection of the second active portion 411 on the side wall of the groove is located within the range of the orthographic projection of the third gate line 332 on the side wall of the groove to form the bottom gate of the oxide transistor T1, so that the oxide transistor T1 forms a dual-gate structure, thereby reducing the risk of leakage current of the oxide transistor T1. It should be noted that the third gate line 332 can be located in the third conductive layer 33, for example.

[0123] In addition, the third gate line 332 can be connected to a fixed voltage (such as a first voltage signal), for example, the third gate line 332 is connected to the first voltage signal line 51. In this way, the third gate line 332 will not cause the channel state of the oxide transistor T1 to jump when the oxide transistor T1 is working, and can play the role of electromagnetic shielding, reduce the interference of the low-temperature polysilicon transistor T2 on the oxide transistor T1, and improve the stability of the pixel driving circuit 121.

[0124] In some embodiments, see Figure 6 The second semiconductor layer 41 further includes a second doped portion, and the second doped portion may be a portion of the second semiconductor layer 41 other than the second active portion 411 .

[0125] Among them, multiple second active parts 411 in the same layer can be connected through the second doped part, that is, the second doped part is connected to the second active part 411. In addition, the second doped part extends to the bottom of the groove and / or extends outside the groove, that is, at least part of the second doped part is arranged in a relatively flat area, which is convenient for overlapping with other circuit structures (such as the adapter line 53), thereby connecting with other transistors or signal lines (such as the initialization signal line 54).

[0126] It should be noted that the first semiconductor layer 31 may also include a first doped portion, and the first doped portion may be a portion other than the first active portion 311 in the first semiconductor layer 31 . Multiple first active portions 311 in the same layer may be connected through the first doped portion, which is not specifically limited in the embodiments of the present disclosure.

[0127] In some embodiments, see Figure 6 The second gate line 421 extends to the bottom of the groove and / or extends outside the groove. That is, at least part of the second gate line 421 is arranged in a relatively flat area, which is convenient for overlapping with other circuit structures (such as the adapter line 53), thereby connecting with other transistors or signal lines.

[0128] In some embodiments, see Figure 6 , the third gate line 332 extends to the bottom of the groove and / or extends outside the groove. That is, at least part of the third gate line 332 is arranged in a relatively flat area, which is convenient for overlapping with other circuit structures (such as the adapter line 53), thereby connecting with other transistors or signal lines (such as the first voltage signal line 51).

[0129] It should be understood that see Figure 6 In the third conductive layer 33 , the second semiconductor layer 41 , the second conductive layer 42 and the source-drain conductive layer 50 , other insulating film layers may be provided between each two adjacent layers.

[0130] It should be noted that the material of the second conductive layer 42 and the source-drain conductive layer 50 includes at least one of molybdenum, magnesium, aluminum, copper and titanium, which is not specifically limited in the embodiment of the present disclosure.

[0131] For example, Figure 6 As shown, the array substrate 10 further includes a first interlayer insulating layer 95 , a third gate insulating layer 96 and a second interlayer insulating layer 97 .

[0132] The first interlayer insulating layer 95 is located between the third conductive layer 33 and the second semiconductor layer 41 . The third gate insulating layer 96 is located between the second semiconductor layer 41 and the second conductive layer 42 . The second interlayer insulating layer 97 is located between the second conductive layer 42 and the source-drain conductive layer 50 .

[0133] It should be noted that the materials of the first interlayer insulating layer 95, the third gate insulating layer 96 and the second interlayer insulating layer 97 include at least one of inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide, which are not specifically limited in the embodiments of the present disclosure. For example, the first interlayer insulating layer 95 may include a multilayer structure, such as the first interlayer insulating layer 95 includes a silicon nitride layer and a silicon oxide layer, and the silicon oxide layer is located on the side of the silicon nitride layer away from the substrate 11.

[0134] In some embodiments, Figure 6 As shown, the pixel driving circuit 121 includes multiple oxide transistors T1. In the same pixel driving circuit 121, the orthographic projections of at least two oxide transistors T1 on the reference plane are located within the range of the orthographic projections of the opening of the same first via 110 close to the circuit layer 12 on the reference plane. Figure 6 In the figure, the orthographic projections of two oxide transistors T1 on the reference plane are taken as an example, and are located within the range of the orthographic projection of the opening of the same first via hole 110 close to the circuit layer 12 on the reference plane.

[0135] In this case, the areas occupied by the two oxide transistors T1 in the pixel driving circuit 121 on the reference surface are both within the range of the area occupied by the same first via hole 110 on the reference surface. In other words, the two oxide transistors T1 in the pixel driving circuit 121 and the first via hole 110 occupy the same area, which can further reduce the total area occupied by the pixel driving circuit 121 and the first via hole 110, thereby improving the space utilization of the array substrate 10 and the resolution of the display device 1000.

[0136] Some embodiments of the present disclosure also provide a method for preparing an array substrate, which is used to prepare the array substrate 10 of any of the above embodiments. Figure 8 As shown, the preparation method includes S100 to S400.

[0137] S100: See Fig.13 , a binding electrode P is formed on the substrate 700 .

[0138] In the above steps, the binding electrode P can be formed by a thin film deposition process to form an electrode thin film, and then by a patterning process. The thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0139] It should be noted that the above-mentioned substrate 700 only provides support and serves as a working platform. After the array substrate 10 is formed, the array substrate 10 can be separated from the substrate 700 .

[0140] S200: See Fig.13 , a substrate 11 is formed on the substrate 700, and a first via hole 110 is opened.

[0141] In the above steps, the first via hole 110 exposes at least a portion of the binding electrode P. The first via hole 110 may be formed by a photolithography process.

[0142] S300: See Figure 6 , Fig.13 and Fig.14 , a circuit layer 12 is formed on the substrate 11.

[0143] In the above steps, the circuit layer 12 includes a plurality of pixel driving circuits 121, and the pixel driving circuits 121 are connected to the binding electrodes P. The pixel driving circuits 121 include oxide transistors T1, and the orthographic projection of at least one oxide transistor T1 on the reference plane is located within the range of the orthographic projection of the opening of the first via 110 close to the circuit layer 12 on the reference plane.

[0144] In some embodiments, see Fig. 9 , S300 includes S310~S320.

[0145] S310: See Figure 6 and Fig.13 , a first driving circuit layer 30 is formed on the substrate 11.

[0146] In the above steps, the first driving circuit layer 30 includes a first semiconductor layer 31, a first conductive layer 32 and a third conductive layer 33. The first conductive layer 32 is disposed on a side of the first semiconductor layer 31 away from the substrate 11. The third conductive layer 33 is disposed on a side of the first conductive layer 32 away from the substrate 11.

[0147] For some examples, see Fig.10 , S310 includes S311~S313.

[0148] S311: See Figure 6 and Fig.13 , a first semiconductor layer 31 is formed on the substrate 11.

[0149] In the above steps, the first semiconductor layer 31 includes a first active portion 311. The first semiconductor layer 31 can be formed by forming an amorphous silicon layer through a thin film deposition process, then crystallizing to form polysilicon through an excimer laser annealing process, and finally formed through a patterning process.

[0150] It should be noted that the first semiconductor layer 31 may further include a first doped portion, which may be a portion other than the first active portion 311 in the first semiconductor layer 31 . The first doped portion may be formed by an ion implantation process, which is not specifically limited in the embodiments of the present disclosure.

[0151] In some embodiments, Fig.13 As shown, before S311, a barrier layer 91 and a buffer layer 92 may be formed on the substrate 11 to play a role of buffering and preventing water oxygen corrosion.

[0152] S312: See Figure 6 and Fig.13 A first conductive layer 32 is formed on a side of the first semiconductor layer 31 away from the substrate 11 .

[0153] In the above steps, the first conductive layer 32 includes a first gate line 321, and the orthographic projection of the first gate line 321 on the substrate 11 overlaps with the orthographic projection of the first active portion 311 on the substrate 11 to form a low-temperature polysilicon transistor T2. The first conductive layer 32 can be formed into a conductive film by a thin film deposition process and then formed by a patterning process.

[0154] It should be understood that Fig.13 As shown, before S312, a first gate insulating layer 93 may be formed on a side of the first semiconductor layer 31 away from the substrate 11, that is, the first gate insulating layer 93 is located between the first semiconductor layer 31 and the first conductive layer 32 to play an insulating protection role, which is not specifically limited in the embodiments of the present disclosure.

[0155] S313: See Figure 6 and Fig.13 A third conductive layer 33 is formed on a side of the first conductive layer 32 away from the substrate 11 .

[0156] In the above steps, the third conductive layer 33 includes a first electrode 331, an orthographic projection of the first electrode 331 on the substrate 11 overlaps with an orthographic projection of the first gate line 321 on the substrate 11, and the overlapping portion of the first electrode 331 and the first gate line 321 forms a capacitor C. The third conductive layer 33 can be formed by a thin film deposition process to form a conductive film, and then formed by a patterning process.

[0157] It should be understood that Fig.13 As shown, before S313, a second gate insulating layer 94 may be formed on the side of the first conductive layer 32 away from the substrate 11, that is, the second gate insulating layer 94 is located between the first conductive layer 32 and the third conductive layer 33 to play an insulating protection role, which is not specifically limited in the embodiments of the present disclosure.

[0158] For some examples, see Fig.10, before S311, the above S300 also includes S314.

[0159] S314: See Figure 6 and Fig.13 , a light shielding layer 60 is formed on the substrate 11.

[0160] In the above steps, the light shielding layer 60 includes a light shielding portion 61, and the orthographic projection of the light shielding portion 61 on the substrate 11 overlaps with the orthographic projection of the first active portion 311 on the substrate 11 to form the bottom gate of the low-temperature polysilicon transistor T2. The light shielding layer 60 can be formed into a conductive film by a thin film deposition process and then formed by a patterning process.

[0161] It should be noted that the light shielding layer 60 is located between the first semiconductor layer 31 and the substrate 11 . For example, the light shielding layer 60 may be located between the barrier layer 91 and the buffer layer 92 . The barrier layer 91 and the buffer layer 92 provide insulation protection for the light shielding layer 60 .

[0162] S320: See Figure 6 and Fig.14 A second driving circuit layer 40 is formed on a side of the first driving circuit layer 30 away from the substrate 11 .

[0163] In the above steps, the second driving circuit layer 40 includes a second semiconductor layer 41 and a second conductive layer 42 , and the second conductive layer 42 is disposed on a side of the second semiconductor layer 41 away from the substrate 11 .

[0164] For some examples, see Fig.11 , S320 includes S321~S322.

[0165] S321: See Figure 6 and Fig.14 , a second semiconductor layer 41 is formed on a side of the first driving circuit layer 30 away from the substrate 11 .

[0166] In the above steps, the second semiconductor layer 41 includes a second active portion 411. The second semiconductor layer 41 can be formed by forming a metal oxide layer through a thin film deposition process and then through a patterning process.

[0167] It should be noted that the second semiconductor layer 41 also includes a second doped portion, which may be a portion other than the second active portion 411 in the second semiconductor layer 41 . The second doped portion may be formed by an ion implantation process, which is not specifically limited in the embodiments of the present disclosure.

[0168] It should be understood that Fig.14As shown, before S321, a first interlayer insulating layer 95 can also be formed on the side of the first driving circuit layer 30 away from the substrate 11, that is, the first interlayer insulating layer 95 is located between the third conductive layer 33 and the second semiconductor layer 41 to play an insulating protection role, which is not specifically limited in the embodiments of the present disclosure.

[0169] S322: See Figure 6 and Fig.14 A second conductive layer 42 is formed on a side of the second semiconductor layer 41 away from the substrate 11 .

[0170] In the above steps, the second conductive layer 42 includes a second gate line 421, which is arranged opposite to the second active portion 411 to form an oxide transistor T1. The second semiconductor layer 41 can be formed into a conductive film by a thin film deposition process and then formed by a patterning process.

[0171] It should be understood that Fig.14 As shown, before S322, a third gate insulating layer 96 may be formed on the side of the second semiconductor layer 41 away from the substrate 11, that is, the third gate insulating layer 96 is located between the second semiconductor layer 41 and the second conductive layer 42 to play an insulating protection role, which is not specifically limited in the embodiments of the present disclosure.

[0172] In some embodiments, Fig. 9 As shown, after S320, S300 further includes S330.

[0173] S330: See Figure 6 and Fig.14 A source-drain conductive layer 50 is formed on a side of the second driving circuit layer 40 away from the substrate 11 .

[0174] In the above steps, the source-drain conductive layer 50 includes a first voltage signal line 51, and the first voltage signal line 51 is connected to the first electrode 331 to provide a first voltage signal to the pixel driving circuit 121. The source-drain conductive layer 50 can be formed into a conductive film by a thin film deposition process and then formed by a patterning process.

[0175] It should be understood that Fig.14 As shown, before S330, a second interlayer insulating layer 97 can also be formed on the side of the second driving circuit layer 40 away from the substrate 11, that is, the second interlayer insulating layer 97 is located between the second conductive layer 42 and the source-drain conductive layer 50 to play an insulating protection role, which is not specifically limited in the embodiments of the present disclosure.

[0176] S400: removing the substrate 700.

[0177] In the above steps, at least one of laser stripping, mechanical stripping or chemical stripping may be used to remove the substrate 700 so that the surface of the binding electrode P away from the circuit layer 12 is exposed to facilitate connection with the circuit board 500 .

[0178] In some embodiments, between S200 and S300, refer to Fig.12 , the above preparation method also includes S500.

[0179] S500: See Figure 6 and Fig.13 , forming a fourth conductive layer 70.

[0180] In the above steps, the fourth conductive layer 70 includes a fan-out trace 71, which covers the binding electrode P exposed by the first via hole 110 and extends outside the first via hole 110, so that the pixel driving circuit 121 is overlapped with the fan-out trace 71 outside the first via hole 110, thereby connecting with the binding electrode P.

[0181] It should be noted that the fourth conductive layer 70 can be formed by forming a conductive film through a thin film deposition process and then through a patterning process.

[0182] It should be understood that Fig.13 As shown, between S500 and S200 , a passivation layer 81 may be formed between the fourth conductive layer 70 and the substrate 11 . The passivation layer 81 is disposed between the fourth conductive layer 70 and the substrate 11 to prevent the fourth conductive layer 70 from being oxidized.

[0183] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: A substrate having a first via hole; A binding electrode is disposed in the first via hole; The binding electrode is configured to be connected to a circuit board; A circuit layer is arranged on the substrate; the circuit layer includes a plurality of pixel driving circuits, and the pixel driving circuits are connected to the binding electrodes; the pixel driving circuits include oxide transistors, and the orthographic projection of at least one of the oxide transistors on the reference plane is located within the range of the orthographic projection of the opening of the first via hole close to the circuit layer on the reference plane; the reference plane is the plane where the surface of the substrate away from the circuit layer is located.

2. The array substrate according to claim 1, characterized in that: The pixel driving circuit further includes a low temperature polysilicon transistor, and the circuit layer includes: A first driving circuit layer is disposed on the substrate; the first driving circuit layer includes the low-temperature polysilicon transistor, and the low-temperature polysilicon transistor is staggered with the first via hole; The second driving circuit layer is arranged on a side of the first driving circuit layer away from the substrate; the second driving circuit layer includes the oxide transistor.

3. The array substrate according to claim 2, characterized in that: The first driving circuit layer covers the first via hole, and a groove is formed at a portion located at the first via hole; the oxide transistor includes a second active portion; The second driving circuit layer comprises: A second semiconductor layer, comprising the second active portion; the second active portion is disposed on a sidewall of the groove; The second conductive layer is arranged on a side of the second semiconductor layer away from the substrate; the second conductive layer includes a second gate line, and the orthographic projection of the second gate line on the side wall of the groove overlaps with the orthographic projection of the second active part on the side wall of the groove.

4. The array substrate according to claim 3, characterized in that: The first driving circuit layer includes a third gate line, and an orthographic projection of the third gate line on the sidewall of the groove overlaps with an orthographic projection of the second active portion on the sidewall of the groove.

5. The array substrate according to claim 4, characterized in that: The circuit layer also includes: The source-drain conductive layer is arranged on a side of the second driving circuit layer away from the substrate; the source-drain conductive layer comprises a first voltage signal line, and the first voltage signal line is connected to the third gate line.

6. The array substrate according to claim 4, characterized in that: The second semiconductor layer further includes a second doped portion, the second doped portion is connected to the second active portion and extends to the bottom of the groove and / or extends outside the groove; And / or, the second gate line extends to the bottom of the groove and / or extends outside the groove; And / or, the third gate line extends to the bottom of the groove and / or extends outside the groove.

7. The array substrate according to claim 4, characterized in that: The low temperature polysilicon transistor includes a first active portion; the first driving circuit layer includes: A first semiconductor layer including the first active portion; A first conductive layer is disposed on a side of the first semiconductor layer away from the substrate; the first conductive layer comprises a first gate line, and an orthographic projection of the first gate line on the substrate overlaps with an orthographic projection of the first active portion on the substrate; The third conductive layer is arranged on a side of the first conductive layer away from the substrate; the third conductive layer comprises a first electrode plate, and the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the first gate line on the substrate.

8. The array substrate according to claim 7, characterized in that: The third gate line is located in the third conductive layer.

9. The array substrate according to claim 7, characterized in that: The circuit layer also includes: A light shielding layer is arranged between the substrate and the first semiconductor layer; the light shielding layer includes a light shielding portion, the orthographic projection of the light shielding portion on the substrate overlaps with the orthographic projection of the first active portion on the substrate, and the light shielding portion is connected to the first gate line.

10. The array substrate according to any one of claims 1 to 9, characterized in that: The pixel driving circuit comprises a plurality of oxide transistors, and orthographic projections of at least two of the oxide transistors on the reference plane are located within the range of orthographic projections of an opening of the same first via hole close to the circuit layer on the reference plane.

11. The array substrate according to claim 1, characterized in that: The radial dimension of the first via hole is 5 μm to 20 μm.

12. A light-emitting substrate, characterized in that: include: The array substrate according to any one of claims 1 to 11; A light emitting device, disposed on the array substrate and connected to a pixel driving circuit of the array substrate; The circuit board is arranged on a side of the array substrate away from the light emitting device and is connected to the binding electrode.

13. A display module, characterized in that: include: The light-emitting substrate according to claim 12, wherein the light-emitting substrate has a light-emitting side and a non-light-emitting side that are arranged opposite to each other; A plurality of optical films are arranged on the light emitting side of the light emitting substrate.

14. A display device, characterized in that: include: The display module as claimed in claim 13; The display module is arranged in the housing.

15. A method for preparing an array substrate, characterized in that: For preparing an array substrate according to any one of claims 1 to 11, comprising: forming a binding electrode on a substrate; A substrate is formed on the substrate, and a first via hole is opened; the first via hole exposes at least a portion of the binding electrode; A circuit layer is formed on the substrate; the circuit layer includes a plurality of pixel driving circuits, and the pixel driving circuits are connected to the binding electrodes; the pixel driving circuits include oxide transistors, and an orthographic projection of at least one of the oxide transistors on a reference plane is located within the range of an orthographic projection of an opening of the first via hole close to the circuit layer on the reference plane; the reference plane is a plane where a surface of the substrate away from the circuit layer is located; The substrate is removed.

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