Image sensor and electronic system including the same

Abstract

An image sensor and an electronic system including the same are disclosed. The image sensor includes unit pixels each including a photodiode in a substrate having a front side surface and a rear side surface, a sensor array region including at least one isolation structure configured to isolate the unit pixels from each other and vertically penetrate the substrate, and a capacitor region including at least one capacitor disposed on the front side surface and the rear side surface. And a capacitor region disposed adjacent to the sensor array region in a horizontal direction parallel to the back side surface of the substrate, and including at least one capacitor on the front side surface of the substrate and at least one dummy isolation structure adjacent to the at least one capacitor to vertically penetrate the substrate, one end surface of each of the at least one isolation structure and the at least one dummy isolation structure is coplanar with a back side surface of the substrate, and the at least one isolation structure and the at least one dummy isolation structure include the same material.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0144171 filed on October 25, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosure relates to an image sensor and an electronic system including the image sensor, and more particularly, to an image sensor including a sensor array region and a capacitor region and an electronic system including the image sensor. Background Art

[0003] With the advancement of the computer industry and the communication industry, image sensors that capture images and convert them into electrical signals are used in various applications (such as digital cameras, video cameras, personal communication systems (PCS), game consoles, security cameras, and medical miniature cameras). With the high integration of image sensors and the miniaturization of pixel sizes, the width of the sensing area defined by the device isolation structure has gradually decreased to realize the image sensor. Therefore, although the density of the device isolation structure is high in the sensor array region including the device isolation structure, because there is no device isolation structure in the peripheral circuit region surrounding the sensor array region, when the back side surface of the substrate is planarized during the process of manufacturing the image sensor, there is a relatively large difference in polishing rate between the sensor array region and the peripheral circuit region, and therefore, process defects may be generated in the subsequent photolithography process. Summary of the invention

[0004] Provided is an image sensor having a structure that, when a rear side surface of a substrate is planarized during a process of manufacturing the image sensor, process defects caused by a step difference between a sensor array region and a capacitor region adjacent to the sensor array region outside a peripheral region around the sensor array region can be suppressed by minimizing a difference in polishing rate between the sensor array region and the capacitor region.

[0005] In addition, an electronic system including an image sensor having the following structure is provided: when the back side surface of the substrate is planarized during the process of manufacturing the image sensor, process defects caused by a step difference between the sensor array region and a capacitor region adjacent to the sensor array region outside a peripheral region around the sensor array region can be suppressed by minimizing the difference in polishing rate between the sensor array region and the capacitor region.

[0006] According to one disclosed aspect, an image sensor includes a sensor array region and a capacitor region, the sensor array region including: a plurality of unit pixels, each unit pixel including a photodiode located in a substrate, wherein the substrate includes a front side surface and a back side surface; and at least one isolation structure that passes through the substrate in a vertical direction from the front side surface to the back side surface, wherein the at least one isolation structure isolates the plurality of unit pixels from each other, and the capacitor region is adjacent to the sensor array region, wherein the capacitor region includes: at least one capacitor on the front side surface; and at least one dummy isolation structure that is adjacent to the at least one capacitor, wherein the at least one dummy isolation structure passes through the substrate in a vertical direction, wherein one end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends in the same plane as the back side surface, and wherein the at least one isolation structure and the at least one dummy isolation structure include the same material.

[0007] According to one disclosed aspect, an image sensor includes a sensor array region, a pad region, and a capacitor region, the sensor array region including: a plurality of unit pixels, each unit pixel including a photodiode located in a substrate, wherein the substrate includes a front side surface and a back side surface; and at least one isolation structure that passes through the substrate in a vertical direction from the front side surface to the back side surface, wherein the at least one isolation structure isolates the plurality of unit pixels from each other, the pad region surrounds the sensor array region and includes a plurality of conductive pads, the capacitor region is between the sensor array region and the pad region, the capacitor region includes: a plurality of capacitors on the front side surface; and at least one dummy isolation structure that passes through the substrate in a vertical direction between two adjacent capacitors among the plurality of capacitors, wherein one end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends in the same plane as the back side surface, and wherein the at least one isolation structure and the at least one dummy isolation structure include the same material.

[0008] According to one disclosed aspect, an image sensor includes a first semiconductor chip and a second semiconductor chip, the first semiconductor chip including a logic area and a peripheral circuit area, wherein the logic area includes a logic device and the peripheral circuit area includes a peripheral circuit, the second semiconductor chip is stacked on the first semiconductor chip, wherein the second semiconductor chip includes a substrate, a sensor array area and a capacitor area, the substrate includes a front side surface and a back side surface, the sensor array area includes: a plurality of unit pixels, each unit pixel includes a photodiode located in the substrate; and a plurality of isolation structures, which pass through the substrate from the front side surface to the back side surface in a vertical direction and isolate the plurality of unit pixels from each other, the capacitor area surrounds the sensor array area and includes: a plurality of capacitors, on the front side surface; and a plurality of dummy isolation structures, which are arranged to be adjacent to the plurality of capacitors, respectively, and pass through the substrate in the vertical direction, wherein one end surface of each of the plurality of isolation structures and the plurality of dummy isolation structures extends in the same plane as the back side surface, and wherein the plurality of isolation structures and the plurality of dummy isolation structures include the same material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic exploded perspective view of an image sensor according to one or more embodiments; Figure 2 is a block diagram illustrating some components of an image sensor according to one or more embodiments; Figure 3 is a block diagram illustrating some components of an image sensor according to one or more embodiments; Figure 4 It shows that Figure 3 When the area EX1 is rotated 180 degrees in the XY plane Figure 3 An enlarged cross-sectional view of a region EX1; Figure 5A is a plan view of a portion of a capacitor region of an image sensor according to one or more embodiments; Figure 5B It is along Figure 5A The line X2-X2' intercepts Figure 5A a cross-sectional view of a portion of an image sensor; Figure 6 is a plan view showing an image sensor according to one or more embodiments; Figure 7 is a plan view showing an image sensor according to one or more embodiments; Fig. 8A , Figure 8B and Figure 8C is a cross-sectional view showing a series of processes of a method of manufacturing an image sensor according to one or more embodiments; Fig. 9A is a block diagram of an electronic system according to one or more embodiments; and Fig. 9B yes Fig. 9A Detailed block diagram of the electronic system of the camera module. DETAILED DESCRIPTION

[0010] Hereinafter, the disclosed embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components are denoted by the same reference numerals, and repeated descriptions thereof are omitted.

[0011] Terms such as "unit", "module", "component" and "block" can be implemented as hardware or software. As used herein, multiple "units", "modules", "components" and "blocks" can be implemented as a single component, or a single "unit", "module", "component" and "block" can include multiple components.

[0012] It will be understood that when an element is referred to as being “connected with” or “connected to” another element, the element may be directly or indirectly connected to the other element.

[0013] Furthermore, when a component “includes” or “comprises” an element, unless there is a specific description contrary thereto, the component may further include other elements, rather than excluding other elements.

[0014] Throughout the specification, when a member is “on” another member, this includes not only a case where the member is in contact with the other member but also a case where another member is present between the two members.

[0015] Here, the expressions "at least one of a, b or c" and "at least one of a, b and c" mean "only a", "only b", "only c", "both a and b", "both a and c", "both b and c" and "all of a, b and c".

[0016] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, the disclosure should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0017] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0018] With respect to any method or process described herein, identification codes may be used to facilitate description, but are not intended to illustrate the order of each step or operation. Unless the context clearly indicates otherwise, each step or operation may be implemented in an order different from the order shown. Unless the disclosed context clearly indicates otherwise, one or more steps or operations may be omitted.

[0019] Figure 1 is a schematic exploded perspective view of an image sensor 100 according to one or more embodiments.

[0020] Reference Figure 1 , the image sensor 100 may include a plurality of Figure 1 The first semiconductor chip 110 and the second semiconductor chip 120 are stacked on each other in a Z direction (in a direction of a horizontal axis). The first semiconductor chip 110 may include a logic chip, and the second semiconductor chip 120 may include a sensor chip.

[0021] The first semiconductor chip 110 may include a logic area LA including a logic device and a peripheral circuit area PE including a peripheral circuit. The logic area LA may be surrounded by the peripheral circuit area PE.

[0022] The second semiconductor chip 120 may be stacked on the first semiconductor chip 110 to overlap the first semiconductor chip 110 in a vertical direction (Z direction). The second semiconductor chip 120 may include a sensor array area SA, a capacitor area CA surrounding the sensor array area SA, a pad area PA surrounding the sensor array area SA and the capacitor area CA, and a plurality of through-via areas TVA between the capacitor area CA and the pad area PA. In the second semiconductor chip 120, the capacitor area CA, the plurality of through-via areas TVA, and the pad area PA may constitute a peripheral circuit area of ​​the second semiconductor chip 120.

[0023] In the second semiconductor chip 120, the sensor array area SA may include an active pixel sensor area (or referred to as, active pixel area) APS including active pixels for generating active signals corresponding to the wavelength of light from outside the second semiconductor chip 120, and an optical black sensor area OBS including optical black pixels for generating optical black signals by blocking light from outside the second semiconductor chip 120. The dummy pixel sensor may be arranged in an edge portion of the active pixel sensor area APS adjacent to the optical black sensor area OBS.

[0024] Multiple capacitors (e.g. Figure 3The capacitor 158 of the second semiconductor chip 120 may be arranged in the capacitor area CA of the second semiconductor chip 120. The sensor array area SA may be arranged in an area defined by the capacitor area CA. In the second semiconductor chip 120, the capacitor area CA may be arranged closer to the sensor array area SA than to the pad area PA. That is, in the horizontal direction (e.g., Figure 1 In the X direction or the Y direction in FIG. 1 , a distance between the capacitor area CA and the sensor array area SA may be smaller than a distance between the capacitor area CA and the pad area PA.

[0025] The capacitor area CA may be disposed adjacent to the optical black sensor area OBS, and the capacitor area CA may be spaced apart from the active pixel sensor area APS with the optical black sensor area OBS located between the capacitor area CA and the active pixel sensor area APS to surround the active pixel sensor area APS and the optical black sensor area OBS. Figure 1 When viewed in the XY plane in FIG. 1 , the capacitor area CA may have a rectangular ring shape surrounding the sensor array area SA. However, according to the disclosure, the planar shape of the capacitor area CA is not limited to Figure 1 For example, the capacitor area CA may be locally or intermittently arranged along the periphery of the optical black sensor area OBS to be adjacent to the optical black sensor area OBS.

[0026] The plurality of pads 2 may be arranged in the pad area PA of the second semiconductor chip 120. In one or more embodiments, the plurality of pads 2 may exchange electrical signals with an external device. In one or more embodiments, the plurality of pads 2 may transmit driving power (such as a power supply voltage or a ground voltage) supplied from outside the second semiconductor chip 120 to a circuit in the second semiconductor chip 120.

[0027] A plurality of through vias 4 may be arranged in each of a plurality of through via areas TVA of the second semiconductor chip 120. Some of the plurality of through vias 4 may be respectively connected to unit pixels in the sensor array area SA through wirings of the second semiconductor chip 120. Other through vias of the plurality of through vias 4 may respectively connect wirings of the first semiconductor chip 110 with wirings of the second semiconductor chip 120. Still other through vias of the plurality of through vias 4 may respectively connect wirings of the first semiconductor chip 110 with logic devices included in the logic area LA of the second semiconductor chip 120.

[0028] Figure 2 It is shown Figure 1 A block diagram of some components of image sensor 100 is shown in FIG.

[0029] Reference Figure 1 and Figure 2 The image sensor 100 may include a pixel array 10 arranged in a sensor array area SA and a circuit for controlling the pixel array 10. In one or more embodiments, the circuit for controlling the pixel array 10 may include a column driver 20, a row driver 30, a timing controller 40, and a readout circuit 50.

[0030] The image sensor 100 may operate according to a control command received from the image processor 70, and may convert light transmitted from an external object into an electrical signal and output the electrical signal to the image processor 70. The image sensor 100 may include a complementary metal oxide semiconductor (CMOS) image sensor.

[0031] The pixel array 10 may include a plurality of unit pixels PX having a two-dimensional array structure and arranged in a matrix along a plurality of row lines and a plurality of column lines. As used herein, the term "unit pixel" may be simply referred to as a pixel.

[0032] Each of the plurality of unit pixels PX may include a photodiode. The photodiode may receive light transmitted from an object and thus generate a charge. The image sensor 100 may perform an autofocus function by using a phase difference between pixel signals respectively generated by a plurality of photodiodes in the plurality of unit pixels PX. Each of the plurality of unit pixels PX may include a pixel circuit for generating a pixel signal from the charge generated by the photodiode.

[0033] In one or more embodiments, the image sensor 100 may include an image sensor capable of performing a global shutter operation. For example, during operation of the image sensor 100, all unit pixels PX in the pixel array 10 may be simultaneously exposed to a light signal provided from outside the image sensor 100, and thus charges may be simultaneously stored in each of the plurality of unit pixels PX. In one or more embodiments, due to the charges stored in each of the plurality of unit pixels PX, pixel signals may be sequentially output row by row.

[0034] The column driver 20 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The CDS may be connected to the unit pixel PX included in the row selected by the row selection signal provided by the row driver 30 via the column line, and may detect the reset voltage and the pixel voltage by performing correlated double sampling. The ADC may convert the reset voltage and the pixel voltage detected by the CDS into digital signals and transmit the digital signals to the readout circuit 50.

[0035] The readout circuit 50 may include an amplification circuit, a latch or buffer circuit that can temporarily store a digital signal, etc., and may generate image data by temporarily storing or amplifying a digital signal received from the column driver 20. The operation timing of the column driver 20, the row driver 30, and the readout circuit 50 may be determined by the timing controller 40, and the timing controller 40 may be operated by a control command sent by the image processor 70.

[0036] The image processor 70 may perform signal processing on the image data output by the readout circuit 50, and output the processed image data to a display device or store the processed image data in a storage device such as a memory. When the image sensor 100 is mounted on an autonomous driving vehicle, the image processor 70 may perform signal processing on the image data and transmit the processed image data to a main controller or the like for controlling the autonomous driving vehicle.

[0037] Figure 3 It is shown Figure 1 A block diagram of some components of image sensor 100 is shown in FIG. Figure 4 It is shown Figure 3 When the area EX1 is rotated 180 degrees in the XY plane Figure 3 An enlarged cross-sectional view of area EX1.

[0038] Reference Figure 1 , Figure 3 and Figure 4 , the image sensor 100 may include a second semiconductor chip 120 bonded to the first semiconductor chip 110 by using a bonding layer BL. The second semiconductor chip 120 may include an active pixel region APS, an optical black sensor region OBS, and a capacitor region CA sequentially arranged in the order stated in the first horizontal direction (X direction). The active pixel region APS and the optical black sensor region OBS may constitute a sensor array region SA.

[0039] A plurality of unit pixels PX may be arranged in each of the active pixel region APS and the optical black sensor region OBS. Active pixels for generating active signals corresponding to the wavelength of light from outside the image sensor 100 may be arranged in the active pixel region APS. Optical black pixels that block light from outside the image sensor 100 and generate optical black signals may be arranged in the optical black sensor region OBS.

[0040] The optical black sensor region OBS may be formed along the periphery of the active pixel region APS. The active pixel region APS and the optical black sensor region OBS may constitute a sensor array region. In one or more embodiments, a dummy unit pixel may be arranged in the optical black sensor region OBS. The dummy unit pixel may be a pixel that does not generate an active signal.

[0041] The image sensor 100 may include a substrate 122. The substrate 122 may include a semiconductor layer. In one or more embodiments, the substrate 122 may include a semiconductor layer doped with P-type impurities. For example, the substrate 122 may include a semiconductor layer containing Si, Ge, SiGe, a II-VI compound semiconductor, a III-V compound semiconductor, or a combination thereof. In one or more embodiments, the substrate 122 may include a P-type epitaxial semiconductor layer epitaxially grown on a P-type bulk silicon substrate. The substrate 122 may have a front side surface 122F and a back side (or backside) surface 122B facing each other.

[0042] In the active pixel region APS and the optical black sensor region OBS, each of the plurality of unit pixels PX may include a photodiode PD, a floating diffusion region FD, and a transfer transistor TX. The photodiode PD and the floating diffusion region FD may be arranged in the substrate 122. The photodiode PD may generate a charge proportional to the amount of light incident from the outside of the image sensor 100. The charge generated in this way may be accumulated in the photodiode PD, and the charge accumulated in the photodiode PD may be transferred to the floating diffusion region FD. The charge transferred to the floating diffusion region FD may be applied to the source follower gate included in the unit pixel PX. One end of the transfer transistor TX may be connected to the photodiode PD, and the other end of the transfer transistor TX may be connected to the floating diffusion region FD. The transfer transistor TX may transfer the charge generated by the photodiode PD to the floating diffusion region FD. The transfer transistor TX may include a transfer gate, a gate insulating film, and a gate spacer. The transfer gate may include a portion buried in the substrate 122. The gate insulating film may be arranged between the transfer gate and the substrate 122. The gate spacer may cover both side walls of the transfer gate.

[0043] A plurality of isolation structures DSA configured to isolate a plurality of unit pixels PX from each other may be arranged in each of the active pixel region APS and the optical black sensor region OBS. Figure 3At least some of the plurality of isolation structures DSA shown in the active pixel region APS and the optical black sensor region OBS in FIG. 1 may have a structure connected to each other. The plurality of isolation structures DSA may pass through the substrate 122 in a vertical direction (Z direction). Here, the vertical direction (Z direction) may refer to a direction perpendicular to the rear side surface 122B of the substrate 122.

[0044] The capacitor area CA may be adjacent to the sensor array area SA in a horizontal direction (e.g., a first horizontal direction (X direction) and a second horizontal direction (Y direction)) parallel to the backside surface 122B of the substrate 122. In the capacitor area CA, a plurality of capacitors 158 and a plurality of dummy isolation structures DSB may be arranged. Each of the plurality of capacitors 158 may be arranged on the frontside surface 122F of the substrate 122 in the active area AC of the substrate 122. The plurality of dummy isolation structures DSB may be adjacent to the plurality of capacitors 158, respectively, to pass through the substrate 122 in a vertical direction (Z direction).

[0045] In the capacitor region CA, the insulating film 156 may be disposed between the front side surface 122F of the substrate 122 and the capacitor 158. In one or more embodiments, the capacitor 158 may include a doped polysilicon film. The insulating film 156 may include a silicon oxide film. However, the respective constituent materials of the capacitor 158 and the insulating film 156 are not limited to the above examples. The structure of each of the plurality of capacitors 158 is not limited to Figure 3 For example, each of the plurality of capacitors 158 in the capacitor region CA may include a capacitor having a metal-oxide-semiconductor (MOS) structure or a capacitor having a metal-insulator-metal (MIM) structure.

[0046] An end surface D1 of each of the plurality of isolation structures DSA in the sensor array area SA and an end surface D2 of each of the plurality of dummy isolation structures DSB in the capacitor area CA may extend in the same plane as the backside surface 122B of the substrate 122. The plurality of isolation structures DSA in the sensor array area SA and the plurality of dummy isolation structures DSB in the capacitor area CA may include the same material.

[0047] Each of the plurality of isolation structures DSA in the sensor array area SA may include a local device isolation film 152A and a main device isolation film 154A. The main device isolation film 154A may pass through the substrate 122 from the front side surface 122F to the back side surface 122B of the substrate 122 in the vertical direction (Z direction). The local device isolation film 152A may pass through only a portion of the substrate 122 from the front side surface 122F of the substrate 122 in the vertical direction (Z direction), and may cover a portion of the sidewall of the main device isolation film 154A adjacent to the front side surface 122F of the substrate 122.

[0048] Each of the plurality of dummy isolation structures DSB in the capacitor region CA may include a local device isolation film 152B and a main device isolation film 154B. The main device isolation film 154B may pass through the substrate 122 from the front side surface 122F to the back side surface 122B of the substrate 122 in the vertical direction (Z direction). The local device isolation film 152B may pass through only a portion of the substrate 122 from the front side surface 122F of the substrate 122 in the vertical direction (Z direction), and may cover a portion of the sidewall of the main device isolation film 154B adjacent to the front side surface 122F of the substrate 122.

[0049] In the plurality of isolation structures DSA in the sensor array area SA and the plurality of dummy isolation structures DSB in the capacitor area CA, the width of each of the main device isolation films 154A and 154B may gradually decrease from the front side surface 122F of the substrate 122 toward the back side surface 122B of the substrate 122 .

[0050] Each of the local device isolation films 152A and 152B and the main device isolation films 154A and 154B may include, but is not limited to, silicon oxide, silicon nitride, SiCN, SiON, SiOC, polysilicon, metal, metal nitride, metal oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PE-TEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), air, or a combination thereof. As used herein, the term "air" may refer to the atmosphere or other gases that may be present during the manufacturing process. When at least one of the local device isolation films 152A and 152B and the main device isolation films 154A and 154B includes a metal, the metal may include tungsten (W), copper (Cu), or a combination thereof. When at least one of the local device isolation films 152A and 152B and the main device isolation films 154A and 154B includes a metal nitride, the metal nitride may include TiN, TaN, or a combination thereof. When at least one of the local device isolation films 152A and 152B and the main device isolation films 154A and 154B includes a metal oxide, the metal oxide may include indium tin oxide (ITO), aluminum oxide (Al 2 O 3 ) or a combination thereof.

[0051] In one or more embodiments, at least one of the local device isolation films 152A and 152B and the main device isolation films 154A and 154B may further include a silicon region doped with P+ type impurities. The silicon region doped with P+ type impurities may reduce dark current in the unit pixel PX, thereby improving the quality of the image sensor 100.

[0052] In one or more embodiments, the density of the plurality of isolation structures DSA in the sensor array area SA may be equal to or similar to the density of the plurality of dummy isolation structures DSB in the capacitor area CA. In one or more embodiments, the density of the plurality of isolation structures DSA in the sensor array area SA may be different from the density of the plurality of dummy isolation structures DSB in the capacitor area CA. In one example, the density of the plurality of dummy isolation structures DSB in the capacitor area CA may be less than the density of the plurality of isolation structures DSA in the sensor array area SA. In another example, the density of the plurality of dummy isolation structures DSB in the capacitor area CA may be greater than the density of the plurality of isolation structures DSA in the sensor array area SA.

[0053] The image sensor 100 may include a backside insulating film 162 covering the backside surface 122B of the substrate 122, a plurality of grid patterns 164 arranged on the backside insulating film 162 in the active pixel sensor region APS, a plurality of color filters 170 arranged above the backside insulating film 162 in the active pixel sensor region APS, and a plurality of microlenses 180 arranged in the active pixel sensor region APS to respectively cover the plurality of color filters 170.

[0054] In one or more embodiments, the back side insulating film 162 may include, but is not limited to, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a hafnium oxide film, or a combination thereof. The back side insulating film 162 may be used as an anti-reflection film. The back side insulating film 162 may prevent reflection of light incident on the substrate 122 from outside the image sensor 100, thereby improving the light collection efficiency of the photodiode PD. In addition, the back side insulating film 162 may have a planarized surface. Because the plurality of color filters 170 and the plurality of micro lenses 180 are arranged on or above the planarized surface of the back side insulating film 162, the respective heights of the plurality of color filters 170 and the plurality of micro lenses 180 may be uniform.

[0055] Each of the plurality of color filters 170 may be arranged above the backside insulating film 162 to correspond to the corresponding unit pixel PX. The plurality of color filters 170 may include various color filters respectively according to the unit pixel PX. In one or more embodiments, the plurality of color filters 170 may be arranged in a Bayer pattern including a red filter, a green filter, and a blue filter. In one or more embodiments, the plurality of color filters 170 may include a yellow filter, a magenta filter, and a cyan filter, and may also include a white filter.

[0056] The grid pattern 164 may include a material having a refractive index lower than that of silicon (Si). In one or more embodiments, the grid pattern 164 may include, but is not limited to, a silicon oxide film, an aluminum oxide film, a tantalum oxide film, or a combination thereof.

[0057] In the active pixel sensor region APS, the first protective film 166 may be disposed between the backside insulating film 162 and the plurality of color filters 170 and between the plurality of grid patterns 164 and the plurality of color filters 170. The first protective film 166 may conformally cover the upper surface of the backside insulating film 162 and the side and upper surfaces of the grid patterns 164. The first protective film 166 may protect the backside insulating film 162 and the grid patterns 164 so that the backside insulating film 162 and the grid patterns 164 are not damaged. The first protective film 166 may include, but is not limited to, an aluminum oxide film.

[0058] The second protective film 182 may be formed on the microlens 180. The second protective film 182 may conformally cover the surface of the microlens 180. The second protective film 182 may protect the microlens 180 from external impacts and may improve the light focusing ability of the microlens 180. In one or more embodiments, the second protective film 182 may include, but is not limited to, a silicon oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, or a combination thereof.

[0059] The wiring structure may be arranged on the front side surface 122F of the substrate 122. The wiring structure may include a plurality of interlayer dielectrics 130, 132, 134, 136, and 138 covering the plurality of transfer transistors TX, and a plurality of via contacts 141 and 143 and a plurality of wiring layers 142, 144, 145, and 146 covered by the plurality of interlayer dielectrics 130, 132, 134, 136, and 138. Some of the plurality of via contacts 141 and 143 may electrically connect the floating diffusion region FD to the wiring layers 142, 144, 145, and 146. Some of the wiring layers 142, 144, 145, and 146 arranged in the capacitor region CA among the plurality of wiring layers 142, 144, 145, and 146 may be arranged to overlap with the capacitor 158 in the vertical direction (Z direction).

[0060] The plurality of interlayer dielectrics 130, 132, 134, 136, and 138 and the plurality of wiring layers 142, 144, 145, and 146 are not limited to Figure 3 The examples shown in the figure may be modified and changed as needed. A plurality of wiring layers 142, 144, 145, and 146 may include wires connected to a plurality of transistors, each of which is electrically connected to a photodiode PD. The electrical signal converted by the photodiode PD may undergo signal processing via a plurality of wiring layers 142, 144, 145, and 146. In one or more embodiments, each of the plurality of interlayer dielectrics 130, 132, 134, 136, and 138 may include, but is not limited to, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a low-K film having a dielectric constant lower than that of a silicon oxide film, or a combination thereof. In one or more embodiments, each of the plurality of via contacts 141 and 143 and the plurality of wiring layers 142, 144, 145, and 146 may include, but is not limited to, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0061] The first semiconductor chip 110 may include a logic substrate 112 and a plurality of transistors TR on the logic substrate 112. The plurality of transistors TR may constitute a logic circuit. In one or more embodiments, the plurality of transistors TR may constitute a circuit for controlling transistors of the second semiconductor chip 120.

[0062] An interlayer dielectric 114 covering a plurality of transistors TR and a plurality of via contacts 115 and a plurality of wiring layers 116 covered by the interlayer dielectric 114 may be arranged on or above the logic substrate 112. A plurality of transistors TR may be electrically connected to a plurality of wiring layers 116 via a plurality of via contacts 115, respectively. Some of the wiring layers 116 vertically overlapping the capacitor region CA among the plurality of wiring layers 116 may be arranged to overlap the capacitor 158 in the vertical direction (Z direction). The interlayer dielectric 114 may include, but is not limited to, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a low-K film having a dielectric constant lower than that of the silicon oxide film, or a combination thereof. Each of the plurality of via contacts 115 and the plurality of wiring layers 116 may include, but is not limited to, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0063] In the optical black sensor region OBS and the capacitor region CA, the backside metal layer BML may be disposed over the backside surface 122B of the substrate 122. The backside metal layer BML may be spaced apart from the backside surface 122B of the substrate 122 using a backside insulating film 162 located between the backside metal layer BML and the backside surface 122B of the substrate 122. The backside metal layer BML may block light incident on the optical black sensor region OBS. In one or more embodiments, the backside metal layer BML may include, but is not limited to, titanium (Ti), titanium nitride (TiN), tungsten (W), or a combination thereof.

[0064] In the optical black sensor region OBS and the capacitor region CA, the color filter 170B may be disposed on the backside metal layer BML. In one or more embodiments, the color filter 170B may include, but is not limited to, a blue color filter.

[0065] In the optical black sensor region OBS and the capacitor region CA, the color filter 170B may be covered by a third protective film 180B. The third protective film 180B may include a light-transmitting resin. In one or more embodiments, the third protective film 180B may include the same material as the constituent material of the microlens 180. The third protective film 180B may be covered by a fourth protective film 182B. The fourth protective film 182B may have a configuration substantially the same as the above-described second protective film 182 disposed in the active pixel sensor region APS.

[0066] Reference Figures 1 to 4The described image sensor 100 includes a capacitor region CA adjacent to a sensor array region SA to surround at least a portion of the sensor array region SA, and a plurality of dummy isolation structures DSB are arranged in the capacitor region CA, each of the plurality of dummy isolation structures DSB being adjacent to a capacitor 158 to pass through a substrate 122 in a vertical direction (Z direction). An end surface D1 of each of the plurality of isolation structures DSA in the sensor array region SA and an end surface D2 of each of the plurality of dummy isolation structures DSB in the capacitor region CA extend in the same plane as a rear side surface 122B of the substrate 122, and the isolation structures DSA in the sensor array region SA and the dummy isolation structures DSB in the capacitor region CA include the same material. Therefore, when the substrate 122 is planarized until the rear side surface 122B of the substrate 122 during a manufacturing process of the image sensor 100, by minimizing the difference in polishing rate between the sensor array region SA and the capacitor region CA surrounding it, process defects (e.g., defects such as a recess phenomenon generated in the capacitor region) caused by a step difference between the sensor array region SA and the capacitor region CA can be suppressed. In addition, during the manufacturing process of the image sensor 100, after the process of planarizing the substrate 122 until the backside surface 122B of the substrate 122, and when the photolithography process is performed, degradation of process efficiency due to degradation of depth of focus (DOF) can be prevented, productivity in the manufacturing process of the image sensor 100 can be improved, and product integrity can be improved by improving the sensitivity and resolution of the image sensor 100.

[0067] Figure 5A and Figure 5B is a diagram showing an image sensor 200 according to one or more embodiments, and specifically, Figure 5A is a plan view of a portion of the capacitor area CA, Figure 5B It is along Figure 5A 1 is a cross-sectional view of a portion of the capacitor area CA taken along line X2 - X2 ′. Figure 5B The image sensor 200 is shown Figure 3 The area EX1 corresponds to the area of ​​the components. Figure 5A and Figure 5B In, with Figures 1 to 4 The same reference numerals denote the same components, respectively, and repeated description thereof will be omitted here.

[0068] Reference Figure 5A and Figure 5B , the image sensor 200 has the same Figures 1 to 4The image sensor 100 described above has substantially the same configuration. However, the image sensor 200 includes a plurality of capacitors 158 arranged in the capacitor region CA and a plurality of dummy isolation structures DSB2 arranged in the capacitor region CA to be respectively adjacent to the capacitors 158. The dummy isolation structures DSB2 may be arranged to be spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0069] In the image sensor 200, a plurality of capacitors 158 may be arranged in rows in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction) parallel to the rear side surface 122B of the substrate 122 and orthogonal to each other, thereby forming a matrix. A plurality of capacitors 158 may be spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). In the image sensor 200, some of the plurality of capacitors 158 may be arranged in rows in the first horizontal direction (X direction). Here, the plurality of capacitors 158 arranged in rows in the first horizontal direction (X direction) among the plurality of capacitors 158 may each be referred to as a first capacitor. In the image sensor 200, some other capacitors in the plurality of capacitors 158 may be arranged in rows in the second horizontal direction (Y direction). Here, the plurality of capacitors 158 arranged in rows in the second horizontal direction (Y direction) among the plurality of capacitors 158 may each be referred to as a second capacitor.

[0070] Each of the plurality of dummy isolation structures DSB2 may have a Figure 3 and Figure 4 The dummy isolation structures DSB2 described above have substantially the same configuration. However, in the image sensor 200 , two dummy isolation structures DSB2 may be disposed between adjacent two capacitors 158 among the plurality of capacitors 158 .

[0071] Each of the multiple dummy isolation structures DSB2 can pass through a portion of the substrate 122 facing the separation space between two adjacent capacitors 158 among the multiple capacitors 158 in the vertical direction (Z direction), so that the multiple dummy isolation structures DSB2 do not overlap with the multiple capacitors 158 in the vertical direction (Z direction).

[0072] like Figure 5AAs shown in , a plurality of dummy isolation structures DSB2 arranged in a row in a first horizontal direction (X direction) among a plurality of dummy isolation structures DSB2 may be separated from each other in the first horizontal direction (X direction). Here, a plurality of dummy isolation structures DSB2 arranged in a row in the first horizontal direction (X direction) may each be referred to as a first dummy isolation structure. A plurality of dummy isolation structures DSB2 arranged in a row in a second horizontal direction (Y direction) among a plurality of dummy isolation structures DSB2 may be separated from each other in the second horizontal direction (Y direction). Here, a plurality of dummy isolation structures DSB2 arranged in a row in the second horizontal direction (Y direction) may each be referred to as a second dummy isolation structure.

[0073] When the plane parallel to the rear side surface 122B of the substrate 122 ( Figure 5A and Figure 5B When viewed in an XY plane in the first horizontal direction (X direction), each of the plurality of dummy isolation structures DSB2 may have a rectangular ring shape and may be arranged around the capacitor 158 to pass through the substrate 122 in the vertical direction (Z direction), the rectangular ring being horizontally spaced apart from the capacitor 158 to surround the capacitor 158. The plurality of dummy isolation structures DSB2 may be arranged in a row in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction) to form a matrix.

[0074] Each of the plurality of dummy isolation structures DSB2 may include a portion extending longitudinally in the second horizontal direction (Y direction) in a local region of the substrate 122, the local region of the substrate 122 facing a separation space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row in the first horizontal direction (X direction). Each of the plurality of dummy isolation structures DSB2 may include a portion extending longitudinally in the first horizontal direction (X direction) in a local region of the substrate 122, the local region of the substrate 122 facing a separation space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row in the second horizontal direction (Y direction).

[0075] Figure 6 is a plan view illustrating an image sensor 300 according to one or more embodiments. Figure 6 FIG. 2 shows a planar structure of a portion of the capacitor region CA of the image sensor 300. Figure 6 In, with Figures 1 to 5B The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0076] Reference Figure 6 , the image sensor 300 has a reference Figure 5A and Figure 5BThe image sensor 300 has substantially the same configuration as the image sensor 200 described above. However, the image sensor 300 includes a plurality of dummy isolation structures DSB3 in the capacitor area CA, each of which is arranged adjacent to the capacitor 158. The plurality of dummy isolation structures DSB3 may be spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0077] Each of the plurality of dummy isolation structures DSB3 may have a Figure 3 and Figure 4 The dummy isolation structures DSB3 described above have substantially the same configuration. However, in the image sensor 300 , two dummy isolation structures DSB3 may be disposed between adjacent two capacitors 158 among the plurality of capacitors 158 .

[0078] The spacing distance between two dummy isolation structures DSB3 arranged between two adjacent capacitors 158 in the first horizontal direction (X direction) among the plurality of dummy isolation structures DSB3 may be smaller than the spacing distance between two dummy isolation structures DSB3 spaced apart from each other in the first horizontal direction (X direction) using one capacitor 158 located between the two dummy isolation structures DSB3. The spacing distance between two dummy isolation structures DSB3 arranged between two adjacent capacitors 158 in the second horizontal direction (Y direction) among the plurality of dummy isolation structures DSB3 may be smaller than the spacing distance between two dummy isolation structures DSB3 spaced apart from each other in the second horizontal direction (Y direction) using one capacitor 158 located between the two dummy isolation structures DSB3.

[0079] Some of the dummy isolation structures DSB3 among the plurality of dummy isolation structures DSB3 may each include a portion extending longitudinally in the second horizontal direction (Y direction) in a local region of the substrate 122, the local region of the substrate 122 facing the separation space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row in the first horizontal direction (X direction). Some other of the plurality of dummy isolation structures DSB3 may each include a portion extending longitudinally in the first horizontal direction (X direction) in a local region of the substrate 122, the local region of the substrate 122 facing the separation space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row in the second horizontal direction (Y direction).

[0080] Figure 7 is a plan view illustrating an image sensor 400 according to one or more embodiments. Figure 7 FIG. 4 shows a planar structure of a portion of the capacitor region CA of the image sensor 400. Figure 7 In, with Figures 1 to 5BThe same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0081] Reference Figure 7 , the image sensor 400 has a reference Figure 5A and Figure 5B The image sensor 400 has a substantially same configuration as the image sensor 200 described above. However, the image sensor 400 includes a plurality of dummy isolation structures DSB4, each of which is arranged adjacent to the capacitor 158 in the capacitor area CA. The plurality of dummy isolation structures DSB4 may be spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0082] Each of the plurality of dummy isolation structures DSB4 may have a Figure 3 and Figure 4 The dummy isolation structure DSB4 described above has substantially the same configuration. However, in the image sensor 400 , one dummy isolation structure DSB4 may be disposed between adjacent two capacitors 158 among the plurality of capacitors 158 .

[0083] Some of the plurality of dummy isolation structures DSB4 may be arranged in a row in the first horizontal direction (X direction) to be spaced apart from each other in the first horizontal direction (X direction). Here, the plurality of dummy isolation structures DSB4 arranged in a row in the first horizontal direction (X direction) to be spaced apart from each other in the first horizontal direction (X direction) among the plurality of dummy isolation structures DSB4 may each be referred to as a first dummy isolation structure. Some other dummy isolation structures DSB4 may be arranged in a row in the second horizontal direction (Y direction) to be spaced apart from each other in the second horizontal direction (Y direction). Here, the plurality of dummy isolation structures DSB4 arranged in a row in the second horizontal direction (Y direction) to be spaced apart from each other in the second horizontal direction (Y direction) among the plurality of dummy isolation structures DSB4 may each be referred to as a second dummy isolation structure.

[0084] The first dummy isolation structures among the plurality of dummy isolation structures DSB4 may each be arranged one by one between two capacitors 158 selected from the plurality of capacitors 158 and adjacent to each other in the second horizontal direction (Y direction), and may each have the shape of a first row extending linearly longitudinally in the first horizontal direction (X direction).

[0085] The second dummy isolation structures among the plurality of dummy isolation structures DSB4 may each be arranged one by one between two capacitors 158 selected from the plurality of capacitors 158 and adjacent to each other in the first horizontal direction (X direction), and may each have the shape of a second row extending linearly longitudinally in the second horizontal direction (Y direction). The first row may be orthogonal to the second row.

[0086] In one or more embodiments, the spacing distance between the plurality of dummy isolation structures DSB4 arranged in a row in the first horizontal direction (X direction) may be constant. In one or more embodiments, the spacing distance between the plurality of dummy isolation structures DSB4 arranged in a row in the second horizontal direction (Y direction) may be constant.

[0087] Reference Figure 5A , Figure 5B , Figure 6 and Figure 7 Each of the described image sensors 200, 300, and 400 includes a capacitor region CA adjacent to the sensor array region SA to surround at least a portion of the sensor array region SA, and a plurality of dummy isolation structures DSB2, DSB3, and DSB4 are each arranged in the capacitor region CA such that each dummy isolation structure DSB2, DSB3, or DSB4 is adjacent to the capacitor 158 to pass through the substrate 122 in the vertical direction (Z direction). An end surface of each of the plurality of dummy isolation structures DSB2, DSB3, and DSB4 and an end surface D1 of each of the plurality of isolation structures DSA in the sensor array region SA (see Figure 3 ) extends in the same plane as the backside surface 122B of the substrate 122, and each of the plurality of dummy isolation structures DSB2, DSB3, and DSB4 and the isolation structure DSA in the sensor array area SA includes the same material. Therefore, when the substrate 122 is planarized until the backside surface 122B of the substrate 122 during the manufacturing process of each of the image sensors 200, 300, and 400, by minimizing the difference in polishing rate between the sensor array area SA and the surrounding capacitor area CA, process defects (e.g., defects such as a recess phenomenon generated in the capacitor area CA) due to a step difference between the sensor array area SA and the capacitor area CA can be suppressed. In addition, during the manufacturing process of each of the image sensors 200, 300 and 400, after the process of flattening the substrate 122 until the backside surface 122B of the substrate 122, and when the photolithography process is performed, degradation of process efficiency due to degradation of DOF can be prevented, productivity in the manufacturing process of each of the image sensors 200, 300 and 400 can be improved, and product integrity can be improved by improving the sensitivity and resolution of each of the image sensors 200, 300 and 400.

[0088] FIG. 8A to FIG. 8C are cross-sectional views respectively illustrating a series of processes of a method of manufacturing an image sensor according to one or more embodiments. FIG. 8A to FIG. 8C Description Manufacturing Figure 3 and Figure 4 An example of a method for an image sensor 100 is shown in FIG. FIG. 8A to FIG. 8C In, with Figures 1 to 4 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0089] Reference Fig. 8A , a substrate 122 is prepared, and then a plurality of shallow trenches T1 are formed by partially etching the substrate 122 from the front side surface 122F of the substrate 122 in the sensor array region SA and the capacitor region CA, and then a plurality of local device isolation films 152A and 152B may be formed to fill the plurality of shallow trenches T1, respectively. Next, a plurality of deep trenches T2 may be formed to each pass through the local device isolation film 152B and a portion of the substrate 122, and a plurality of main device isolation films 154A and 154B may be formed to fill the plurality of deep trenches T2, respectively. As a result, a plurality of isolation structures DSA each including a local device isolation film 152A and a main device isolation film 154A may be formed in the sensor array region SA, and a plurality of dummy isolation structures DSB each including a local device isolation film 152B and a main device isolation film 154B may be formed in the capacitor region CA. In the capacitor region CA, a plurality of active regions AC may be defined by the plurality of dummy isolation structures DSB.

[0090] Next, ions may be implanted into the substrate 122 from the front side surface 122F of the substrate 122 in the sensor array area SA, thereby forming a plurality of photodiodes PD in the sensor array area SA.

[0091] Next, a plurality of gate structures may be formed on the front side surface 122F of the substrate 122 in the sensor array region SA, each of the plurality of gate structures including a transfer transistor TX including a gate dielectric film and a transfer gate, and a floating diffusion region FD may be formed by implanting impurity ions into a portion of the substrate 122 from the front side surface 122F of the substrate 122. The plurality of gate structures may respectively include gate structures constituting transistors required to drive a plurality of unit pixels PX included in the image sensor 100.

[0092] When a plurality of gate structures each including a transfer transistor TX is formed in the sensor array region SA, a plurality of insulating films 156 and a plurality of capacitors 158 may be formed on the front side surface 122F of the substrate 122 in the capacitor region CA.

[0093] Next, in the sensor array region SA and the capacitor region CA, a plurality of interlayer dielectrics 130, 132, 134, 136, and 138 may be formed to cover the plurality of capacitors 158 and the plurality of gate structures each including a transfer transistor TX, and a wiring structure including a plurality of via contacts 141 and 143 and a plurality of wiring layers 142, 144, 145, and 146 may be formed. Next, a bonding layer BL may be formed on the externally exposed interlayer dielectric 138 in the wiring structure.

[0094] Reference Figure 8B , the first semiconductor chip 110 may be bonded to the bonding layer BL, and the obtained resultant product may be rotated so that the substrate 122 faces upward in the vertical direction (Z direction).

[0095] Reference Figure 8C , the exposed portion of the substrate 122 in the sensor array area SA and the capacitor area CA, a portion of each of the plurality of isolation structures DSA, and a portion of each of the plurality of dummy isolation structures DSB may be removed by a mechanical grinding process, a chemical mechanical polishing (CMP) process, a wet etching process, or a combination thereof, so that the backside surface 122B of the substrate 122, the end surface D1 of each of the plurality of isolation structures DSA in the sensor array area SA, and the end surface D2 of each of the plurality of dummy isolation structures DSB in the capacitor area CA may extend in the same plane. Here, because the plurality of isolation structures DSA and the plurality of dummy isolation structures DSB having the same structure are respectively formed in the sensor array area SA and the capacitor area CA, when considering the resulting product obtained by removing a portion of the substrate 122, the backside surface 122B of the substrate 122 may extend flatly in each of the sensor array area SA and the capacitor area CA without generating a process defect (such as an unexpected sinking phenomenon) in the capacitor area CA.

[0096] Next, if Figure 3As shown in , a backside insulating film 162 may be formed on a backside surface 122B of a substrate 122, an end surface D1 of each of a plurality of isolation structures DSA, and an end surface D2 of each of a plurality of dummy isolation structures DSB. Next, a plurality of grid patterns 164, a first protective film 166, and a plurality of color filters 170 may be formed on or over the backside insulating film 162 in the active pixel sensor region APS, and a backside metal layer BML and a color filter 170B may be formed on or over the backside insulating film 162 in the optical black sensor region OBS and the capacitor region CA. Next, a microlens 180 and a second protective film 182 may be formed on or over the plurality of color filters 170 in the active pixel sensor region APS, and a third protective film 180B and a fourth protective film 182B may be formed on or over the color filters 170B in the optical black sensor region OBS and the capacitor region CA, thereby manufacturing a reference. Figures 1 to 4 An image sensor 100 is described.

[0097] So far, although reference has been made to FIG. 8A to FIG. 8C Describes the manufacturing reference Figures 1 to 4 The method of the image sensor 100 described herein is an example, but a person of ordinary skill in the art will understand that without departing from the spirit and scope of the disclosure, other methods may be used by referring to the reference FIG. 8A to FIG. 8C Various modifications and changes are made to the examples described to make reference Figure 5A , Figure 5B , Figure 6 and Figure 7 The described image sensors 200 , 300 , and 400 and image sensors having various structures changed and modified therefrom.

[0098] Fig. 9A is a block diagram of an electronic system according to one or more embodiments, and Fig. 9B yes Fig. 9A Detailed block diagram of the electronic system of the camera module.

[0099] Reference Fig. 9A , an electronic system (or electronic device) 1000 may include a camera module group 1100 , an application processor 1200 , a power management integrated circuit (PMIC) 1300 , and an external memory 1400 .

[0100] The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Fig. 9AAn example in which three camera modules 1100a, 1100b, and 1100c are arranged is shown, but the disclosure is not limited thereto. In one or more embodiments, the camera module group 1100 may be modified to include only two camera modules. In addition, in one or more embodiments, the camera module group 1100 may be modified to include n camera modules (where n is a natural number of 4 or greater).

[0101] Although the following reference Fig. 9B A detailed configuration of the camera module 1100 b is described in more detail, but the following description may also be applied to the other camera modules 1100 a and 1100 c according to an embodiment.

[0102] Reference Fig. 9B , the camera module 1100 b may include a prism 1105 , an optical path folding element (OPFE) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage device 1150 .

[0103] The prism 1105 may include a reflective surface 1107 of a light reflective material and thus change a path of light L incident from outside the camera module 1100 b .

[0104] In one or more embodiments, the prism 1105 may be arranged in a first direction ( Fig. 9B The path of the incident light L in the X direction (in the first direction) is changed to a second direction ( Fig. 9B In addition, the prism 1105 may rotate the reflective surface 1107 of the light reflective material around the central axis 1106 in the A direction, or rotate the central axis 1106 in the B direction, so as to change the path of the light L incident in the first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). Here, the OPFE 1110 may also rotate the reflective surface 1107 of the light reflective material around the central axis 1106 in the A direction, or rotate the central axis 1106 in the B direction, so as to change the path of the light L incident in the first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). Fig. 9B Move in the Z direction).

[0105] In one or more embodiments, Fig. 9B As shown in , the maximum rotation angle of the A direction of the prism 1105 may be about 15 degrees or less in the positive (+) A direction and greater than about 15 degrees in the negative (−) A direction, but the disclosure is not limited thereto.

[0106] In one or more embodiments, the prism 1105 can be moved (e.g., rotated) by an angle of up to about 20 degrees, about 10 degrees to about 20 degrees, or about 15 degrees to about 20 degrees in the positive (+) or negative (-) B direction, where the angle at which the prism 1105 moves in the positive (+) B direction can be the same or similar to the angle at which the prism 1105 moves in the negative (-) B direction within a deviation of about 1 degree.

[0107] In one or more embodiments, the prism 1105 may move the reflective surface 1107 of the light reflective material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106 .

[0108] OPFE 1110 may include, for example, m optical lenses (where m is a positive integer). The m lenses may move in the second direction (Y direction) and change the optical zoom ratio of camera module 1100b. For example, assuming that the default optical zoom ratio of camera module 1100b is Z, when the m optical lenses in OPFE 1110 move, the optical zoom ratio of camera module 1100b may be changed to 3Z or 5Z or more.

[0109] The actuator 1130 may move the OPFE 1110 or the optical lens to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0110] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of an object by using light L provided through an optical lens. The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

[0111] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information required for the camera module 1100b to generate image data by using the light L provided from outside the camera module 1100b. For example, the calibration data 1147 may include information about a rotation angle, information about a focal length, information about an optical axis, and the like. When the camera module 1100b is implemented as a multi-state camera having a focal length that varies with the position of an optical lens, the calibration data 1147 may include a focal length value for each position (or each state) of the optical lens and information about autofocus.

[0112] The storage device 1150 may store image data sensed by the image sensor 1142. The storage device 1150 may be disposed outside the image sensing device 1140, and may be implemented in a stacked manner with a sensor chip constituting the image sensing device 1140. In one or more embodiments, the storage device 1150 may include an electrically erasable programmable read-only memory (EEPROM), but the disclosure is not limited thereto.

[0113] Image sensor 1142 may include a reference Figures 1 to 7The described image sensor 100, 200, 300, or 400, or an image sensor in which various modifications and changes are made without departing from the scope of the disclosure.

[0114] Reference Fig. 9A and Fig. 9B In one or more embodiments, each of the camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, the camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 depending on the operation of the actuator 1130 in each of the camera modules 1100a, 1100b, and 1100c.

[0115] In one or more embodiments, one camera module (e.g., 1100b) among the multiple camera modules 1100a, 1100b, and 1100c may be a folded lens type camera module including the prism 1105 and the OPFE 1110 as described above, and the other camera modules (e.g., 1100a and 1100c) may be vertical type camera modules not including the prism 1105 and the OPFE 1110, but the disclosure is not limited thereto.

[0116] In one or more embodiments, one camera module (e.g., 1100c) among the plurality of camera modules 1100a, 1100b, and 1100c may include, for example, a vertical type depth camera that extracts depth information by using infrared rays (IR). In this case, the application processor 1200 may generate a three-dimensional (3D) depth image by merging image data provided from the depth camera with image data provided from another camera module (e.g., 1100a or 1100b).

[0117] In one or more embodiments, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view. In this case, for example, two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different optical lenses, respectively, but the disclosure is not limited thereto.

[0118] In addition, in one or more embodiments, the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view, respectively. In this case, the plurality of camera modules 1100a, 1100b, and 1100c may include different optical lenses, respectively, but the disclosure is not limited thereto.

[0119] In one or more embodiments, the plurality of camera modules 1100a, 1100b, and 1100c may be physically separated from each other. That is, instead of the sensing area of ​​one image sensor 1142 being divided and used by the plurality of camera modules 1100a, 1100b, and 1100c, the image sensor 1142 may be independently included in each of the plurality of camera modules 1100a, 1100b, and 1100c.

[0120] Refer again Fig. 9A , the application processor 1200 may include an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented by semiconductor chips separated from each other.

[0121] The image processing unit 1210 may include a plurality of sub-processors 1212a, 1212b, and 1212c, an image generator 1214, and a camera module controller 1216. The image processing unit 1210 may include as many sub-processors 1212a, 1212b, and 1212c as the camera modules 1100a, 1100b, and 1100c.

[0122] The image data generated by the camera modules 1100a, 1100b, and 1100c, respectively, may be provided to the sub-processors 1212a, 1212b, and 1212c corresponding thereto, respectively, through image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated by the camera module 1100a may be provided to the sub-processor 1212a through the image signal line ISLa, the image data generated by the camera module 1100b may be provided to the sub-processor 1212b through the image signal line ISLb, and the image data generated by the camera module 1100c may be provided to the sub-processor 1212c through the image signal line ISLc. Such image data transmission may be performed by using, for example, a camera serial interface (CSI) based on a mobile industrial processor interface (MIPI), but the disclosure is not limited thereto.

[0123] In one or more embodiments, a single sub-processor may be provided to correspond to multiple camera modules. For example, sub-processors 1212a and 1212c may be different from each other. Fig. 9A Instead of being separated as shown in FIG. 1 , the camera modules 1100a and 1100c may be integrated into a single sub-processor, and image data provided from the camera module 1100a or the camera module 1100c may be selected by a selection element (eg, a multiplexer) and then provided to the integrated sub-processor.

[0124] The image data provided to each of the sub-processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image by using the image data provided from each of the sub-processors 1212a, 1212b, and 1212c according to the image generation information or the mode signal.

[0125] Specifically, the image generator 1214 may generate an output image by merging at least a portion of the image data generated by the camera modules 1100a, 1100b, and 1100c, respectively, having different fields of view, according to the image generation information or the mode signal. In addition, the image generator 1214 may generate an output image by selecting one of the image data generated by the camera modules 1100a, 1100b, and 1100c, respectively, having different fields of view, according to the image generation information or the mode signal.

[0126] In one or more embodiments, the image generation information may include a zoom signal or a zoom factor. Additionally, in one or more embodiments, the mode signal may be based on a mode selected by a user.

[0127] When the image generation information includes a zoom signal or a zoom factor and the camera modules 1100a, 1100b, and 1100c have different fields of view, respectively, the image generator 1214 may perform different operations according to the type of the zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 may merge the image data output from the camera module 1100a and the image data output from the camera module 1100c, and then generate an output image by using the merged image signal and the image data output from the camera module 1100b and not used for merging. When the zoom signal is a second signal different from the first signal, the image generator 1214 may generate an output image by selecting one of the image data output from the camera modules 1100a, 1100b, and 1100c, respectively, instead of performing such merging of the image data. However, the disclosure is not limited thereto, and the method of processing the image data may be changed without limitation as needed.

[0128] In one or more embodiments, the image generator 1214 may receive a plurality of image data having different exposure times from at least one of the plurality of sub-processors 1212a, 1212b, and 1212c, and perform high dynamic range (HDR) processing on the plurality of image data to generate merged image data having an increased dynamic range.

[0129] The camera module controller 1216 may provide a control signal to each of the camera modules 1100a, 1100b, and 1100c. The control signal generated by the camera module controller 1216 may be provided to a corresponding one of the camera modules 1100a, 1100b, and 1100c through a corresponding one of the control signal lines CSLa, CSLb, and CSLc separated from each other.

[0130] According to a mode signal or an image generation signal including a zoom signal, one camera module (e.g., camera module 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be designated as a master camera, and the other camera modules (e.g., camera modules 1100a and 1100c) may be designated as slave cameras. Such designation information may be included in a control signal and provided to each of the camera modules 1100a, 1100b, and 1100c through a corresponding one of control signal lines CSLa, CSLb, and CSLc separated from each other.

[0131] The camera module operating as a master device or a slave device may be changed according to the zoom factor or the operation mode signal. For example, when the field of view of the camera module 1100a is greater than the field of view of the camera module 1100b and the zoom factor indicates a low zoom ratio, the camera module 1100b may operate as a master device and the camera module 1100a may operate as a slave device. On the contrary, when the zoom factor indicates a high zoom ratio, the camera module 1100a may operate as a master device and the camera module 1100b may operate as a slave device.

[0132] In one or more embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may send the synchronization enable signal to the camera module 1100b. The camera module 1100b receiving the synchronization enable signal may generate a synchronization signal based on the received synchronization enable signal, and may provide the generated synchronization signal to the camera modules 1100a and 1100c through the synchronization signal line SSL. The camera modules 1100a, 1100b, and 1100c may be synchronized with the synchronization signal and may send image data to the application processor 1200.

[0133] In one or more embodiments, the control signal provided from the camera module controller 1216 to each of the plurality of camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Each of the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operating mode or a second operating mode related to the sensing speed based on the mode information.

[0134] In the first operation mode, each of the plurality of camera modules 1100a, 1100b, and 1100c may generate an image signal at a first speed (e.g., at a first frame rate), encode the image signal at a second speed higher than the first speed (e.g., at a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor 1200. Here, the second speed may be 30 times or less than the first speed.

[0135] The application processor 1200 may store the received image signal (e.g., the encoded image signal) in the internal memory 1230 in the application processor 1200 or in the external memory 1400 outside the application processor 1200. Next, the application processor 1200 may read the encoded image signal from the internal memory 1230 or the external memory 1400, decode the encoded image signal, and display image data generated based on the decoded image signal. For example, a corresponding sub-processor among the plurality of sub-processors 1212a, 1212b, and 1212c of the image processing unit 1210 may perform decoding, and may also perform image processing on the decoded image signal.

[0136] In the second operation mode, each of the plurality of camera modules 1100a, 1100b, and 1100c may generate an image signal at a third speed lower than the first speed (e.g., at a third frame rate lower than the first frame rate), and transmit the image signal to the application processor 1200. The image signal provided to the application processor 1200 may not have been encoded. The application processor 1200 may perform image processing on the received image signal, or may store the image signal in the internal memory 1230 or the external memory 1400.

[0137] The PMIC 1300 may provide power (e.g., power supply voltage) to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 may provide a first power to the camera module 1100a through a power signal line PSLa, provide a second power to the camera module 1100b through a power signal line PSLb, and provide a third power to the camera module 1100c through a power signal line PSLc.

[0138] The PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and adjust the level of the power. The power control signal PCON may include a power adjustment signal for each operating mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode, and in this case, the power control signal PCON may include information about the camera module to be operated in the low power mode and about the power level to be set. The power levels provided to the plurality of camera modules 1100a, 1100b, and 1100c, respectively, may be the same or different. In addition, the power level may be changed dynamically.

[0139] While the disclosure has been particularly shown and described with reference to disclosed embodiments, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: A sensor array region, comprising: a plurality of unit pixels, each unit pixel comprising a photodiode located in a substrate, wherein the substrate comprises a front side surface and a back side surface; and at least one isolation structure passing through the substrate in a vertical direction from the front side surface to the back side surface, wherein the at least one isolation structure isolates the plurality of unit pixels from each other; and a capacitor region adjacent to the sensor array region, wherein the capacitor region includes: at least one capacitor on the front surface; and at least one dummy isolation structure adjacent to the at least one capacitor, wherein the at least one dummy isolation structure passes through the substrate in a vertical direction, wherein one end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends in the same plane as the backside surface, and The at least one isolation structure and the at least one dummy isolation structure include the same material.

2. The image sensor according to claim 1, wherein: Each of the at least one isolation structure and the at least one dummy isolation structure further includes: a main device isolation film passing through the substrate in a vertical direction from the front side surface to the back side surface; and The local device isolation film passes through a portion of the substrate from the front side surface in a vertical direction and covers a portion of the side wall of the main device isolation film adjacent to the front side surface.

3. The image sensor according to claim 1, wherein: The sensor array area is within the area defined by the capacitor area.

4. The image sensor according to claim 1, in, The at least one capacitor includes a plurality of first capacitors arranged in a row in a first horizontal direction parallel to the rear side surface, and Wherein, the at least one dummy isolation structure includes a portion extending longitudinally in a second horizontal direction in a local area of ​​the substrate, the local area faces the separation space between two adjacent first capacitors among the multiple first capacitors, and the second horizontal direction is parallel to the rear side surface and orthogonal to the first horizontal direction.

5. The image sensor according to claim 1, in, The at least one capacitor includes a plurality of capacitors arranged in a matrix, the matrix including rows in a first horizontal direction and rows in a second horizontal direction, the first horizontal direction and the second horizontal direction are parallel to the rear side surface and orthogonal to each other, and Wherein, the at least one dummy isolation structure includes a plurality of dummy isolation structures, each dummy isolation structure passes through a portion of the separation space between two adjacent capacitors among the plurality of capacitors facing the substrate in the vertical direction, so that the plurality of dummy isolation structures do not overlap with the plurality of capacitors in the vertical direction.

6. The image sensor according to claim 1, in, The at least one capacitor includes a plurality of capacitors spaced apart from each other in a horizontal direction, The at least one dummy isolation structure comprises a plurality of dummy isolation structures respectively arranged around the plurality of capacitors, wherein the plurality of dummy isolation structures are separated from each other, and Wherein, a shape of each of the plurality of dummy isolation structures comprises a rectangular ring, wherein each of the plurality of dummy isolation structures surrounds a capacitor from the plurality of capacitors.

7. The image sensor according to claim 1, in, The at least one capacitor includes a plurality of capacitors spaced apart from each other in a horizontal direction, The at least one dummy isolation structure comprises a plurality of dummy isolation structures respectively arranged around the plurality of capacitors, wherein the plurality of dummy isolation structures are separated from each other, and The dummy isolation structure among the plurality of dummy isolation structures is between two adjacent capacitors among the plurality of capacitors.

8. The image sensor according to claim 1, in, The at least one capacitor includes a plurality of capacitors spaced apart from each other in a horizontal direction, The at least one dummy isolation structure comprises a plurality of dummy isolation structures respectively arranged around the plurality of capacitors, wherein the plurality of dummy isolation structures are separated from each other, and Wherein, two dummy isolation structures among the plurality of dummy isolation structures are between two adjacent capacitors among the plurality of capacitors.

9. An image sensor, comprising: A sensor array region, comprising: a plurality of unit pixels, each unit pixel comprising a photodiode located in a substrate, wherein the substrate comprises a front side surface and a back side surface; and at least one isolation structure passing through the substrate in a vertical direction from the front side surface to the back side surface, wherein the at least one isolation structure isolates the plurality of unit pixels from each other; a pad region surrounding the sensor array region and including a plurality of conductive pads; and a capacitor region between the sensor array region and the pad region, the capacitor region comprising: a plurality of capacitors on the front side surface; and at least one dummy isolation structure passing through the substrate in a vertical direction between two adjacent capacitors among the plurality of capacitors, wherein one end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends in the same plane as the backside surface, and The at least one isolation structure and the at least one dummy isolation structure include the same material.

10. The image sensor according to claim 9, in, In a horizontal direction parallel to the rear surface, the capacitor region is closer to the sensor array region than the pad region, and The capacitor region surrounds at least a portion of the sensor array region.

11. The image sensor according to claim 9, in, The plurality of capacitors include a plurality of first capacitors arranged in a row in a first horizontal direction parallel to the rear side surface, and The at least one dummy isolation structure includes a portion extending longitudinally in a second horizontal direction in a separation space between two adjacent first capacitors among the plurality of first capacitors, and the second horizontal direction is parallel to the rear side surface and orthogonal to the first horizontal direction.

12. The image sensor according to claim 9, in, The plurality of capacitors are arranged in a matrix including rows in a first horizontal direction and rows in a second horizontal direction, the first horizontal direction and the second horizontal direction being parallel to the rear side surface and orthogonal to each other, and Wherein, the at least one dummy isolation structure includes a plurality of dummy isolation structures, each dummy isolation structure passes through a portion of the separation space between two adjacent capacitors among the plurality of capacitors facing the substrate in the vertical direction, so that the plurality of dummy isolation structures do not overlap with the plurality of capacitors in the vertical direction.

13. The image sensor according to claim 9, in, The at least one dummy isolation structure includes a plurality of dummy isolation structures respectively arranged around the plurality of capacitors, and Wherein, a shape of each of the plurality of dummy isolation structures comprises a rectangular ring, and wherein each of the plurality of dummy isolation structures surrounds a capacitor from the plurality of capacitors.

14. The image sensor according to claim 9, in, The at least one dummy isolation structure includes a plurality of dummy isolation structures respectively arranged around the plurality of capacitors, wherein the plurality of capacitors include a plurality of first capacitors arranged in a row in a first horizontal direction parallel to the rear side surface, and The plurality of dummy isolation structures include a plurality of first dummy isolation structures arranged in a row in a first horizontal direction, wherein the plurality of first dummy isolation structures are spaced apart from each other in the first horizontal direction.

15. The image sensor according to claim 9, in, The plurality of capacitors are arranged in a matrix, the matrix comprising rows in a first horizontal direction and rows in a second horizontal direction, the first horizontal direction and the second horizontal direction being parallel to the rear side surface and orthogonal to each other, The at least one dummy isolation structure comprises a plurality of dummy isolation structures respectively arranged around the plurality of capacitors. The plurality of dummy isolation structures include a plurality of first dummy isolation structures arranged in a row in a first horizontal direction and a plurality of second dummy isolation structures arranged in a row in a second horizontal direction, wherein the plurality of first dummy isolation structures are separated from each other in the first horizontal direction, and the plurality of second dummy isolation structures are separated from each other in the second horizontal direction, and Wherein, each of the plurality of first dummy isolation structures and each of the plurality of second dummy isolation structures are arranged between two capacitors among the plurality of capacitors.

16. The image sensor according to claim 15, wherein: A shape of each of the plurality of first dummy isolation structures and each of the plurality of second dummy isolation structures includes a rectangular ring surrounding a capacitor from among the plurality of capacitors.

17. The image sensor according to claim 15, in, Each of the plurality of first dummy isolation structures is arranged between two capacitors of the plurality of capacitors, is adjacent to another first dummy isolation structure of the plurality of first dummy isolation structures in the second horizontal direction, and has a shape of a first row extending linearly longitudinally in the first horizontal direction, and Wherein, each of the plurality of second dummy isolation structures is arranged between two capacitors selected from the plurality of capacitors, is adjacent to another second dummy isolation structure of the plurality of second dummy isolation structures in the first horizontal direction, and has a shape of a second row extending linearly longitudinally in the second horizontal direction.

18. An image sensor, comprising: a first semiconductor chip including a logic region and a peripheral circuit region, wherein the logic region includes logic devices and the peripheral circuit region includes peripheral circuits; and a second semiconductor chip, stacked on the first semiconductor chip, Wherein, the second semiconductor chip comprises: a substrate, comprising a front surface and a rear surface; A sensor array region, comprising: a plurality of unit pixels, each unit pixel comprising a photodiode located in a substrate; and a plurality of isolation structures, penetrating the substrate from a front side surface to a back side surface in a vertical direction and isolating the plurality of unit pixels from each other; and a capacitor region surrounding the sensor array region and comprising: a plurality of capacitors on the front side surface; and a plurality of dummy isolation structures arranged to be adjacent to the plurality of capacitors, respectively, and to pass through the substrate in a vertical direction, wherein one end surface of each of the plurality of isolation structures and the plurality of dummy isolation structures extends in the same plane as the backside surface, and The plurality of isolation structures and the plurality of dummy isolation structures include the same material.

19. The image sensor according to claim 18, in, The sensor array area further includes: an active pixel sensor area including a plurality of active pixels; and an optical black sensor area surrounding the active pixel sensor area and including a plurality of optical black pixels. wherein the optical black sensor region is between the capacitor region and the active pixel sensor region, and wherein the capacitor region surrounds the active pixel sensor region and the optical black sensor region, wherein each of the plurality of capacitors is stacked with at least one wiring layer of the first semiconductor chip, wherein the plurality of capacitors are arranged in a matrix, the matrix comprising rows in a first horizontal direction and rows in a second horizontal direction, the first horizontal direction and the second horizontal direction are parallel to the rear side surface and orthogonal to each other, and The plurality of dummy isolation structures each penetrates a portion of the substrate facing a separation space between two adjacent capacitors among the plurality of capacitors in a vertical direction.

20. An electronic system comprising: at least one camera module comprising the image sensor according to claim 1; at least one processor; as well as at least one memory storing at least one instruction, Wherein, the at least one instruction, when executed by the at least one processor, causes the at least one processor to process image data received from the at least one camera module.

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