A back-contact battery and its manufacturing method

Abstract

The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery and a preparation method thereof, including a post-etching process for opening specific isolation grooves: depositing a stacked conductive film layer on the back surface, the stacked conductive film layer comprising an acid-sensitive transparent conductive thin film and an acid-resistant laser-absorbing metal layer formed in sequence, wherein the thickness ratio of the acid-sensitive transparent conductive thin film to the laser-absorbing metal layer is 1:0.20 - 0.70, and the corrosion time of the laser-absorbing metal layer in a 15 wt% HCl solution at a temperature of 20 °C is 5 - 7 times the corrosion time of the acid-sensitive transparent conductive thin film under the same conditions. The present invention achieves precise laser grooving, forms isolation grooves with good insulation effects, is conducive to reducing battery leakage current, and simultaneously takes into account improving battery reliability and battery conversion efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery and a preparation method thereof. Background Art

[0002] At present, the general process flow of back-contact batteries is as follows: plating a first semiconductor layer on the back of a silicon wafer; removing PSG, rinsing, and then plating a first mask layer; laser or etching openings on the back of the silicon wafer, removing the first mask layer and part of the first semiconductor layer to form a second semiconductor opening area; texturing and cleaning the silicon wafer to form a pyramid-shaped texture on the front of the silicon wafer, and at the same time removing the residual first semiconductor layer in the second semiconductor opening area on the back of the silicon wafer, and then removing the remaining first mask layer; depositing a passivation layer and an antireflection layer on the front of the silicon wafer, and depositing a second semiconductor layer on the back; etching openings on the back of the silicon wafer to form a first semiconductor opening area arranged alternately with the second semiconductor opening area; depositing a transparent conductive thin film on the back of the silicon wafer; forming isolation grooves in the corresponding areas at the junction of the textured surface and the polished surface between the first semiconductor opening area and the second semiconductor opening area by etching; forming silver paste grid line electrodes on the corresponding areas of the first semiconductor opening area and the second semiconductor opening area of the silicon wafer.

[0003] In the post-texturing process of the prior art, when forming isolation grooves in the corresponding areas at the junction of the textured surface and the polished surface after depositing the transparent conductive thin film, in order to ensure the insulation effect, the isolation grooves are set between the first semiconductor opening area and the second semiconductor opening area, that is, between the textured surface and the polished surface. Generally, acid etching is used, which is better than using laser grooving; this is because laser grooving will damage the semiconductor functional layer, especially the second semiconductor opening area (textured surface). Because of the existence of pyramids on the textured surface, when the laser hits it, light scattering in different directions is likely to occur, and this process is uncontrollable. The isolation grooves formed by laser grooving have the defect that the second semiconductor layer is easily damaged, which will directly result in a decrease in Voc in the battery performance and poor battery reliability. Therefore, it is difficult to achieve simple laser grooving on the textured surface. However, the acid etching method has the disadvantage of high requirements for etching alignment accuracy.

[0004] It should be noted that this part of the content of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or well-known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects that in the post-texturing method of back-contact batteries in the prior art, laser grooving of isolation grooves cannot be achieved, and it is impossible to balance battery reliability and battery conversion efficiency. A preparation method of a back-contact battery is provided, which realizes precise laser grooving, forms isolation grooves with good insulation effect, is beneficial to reducing battery leakage current, and at the same time balances the improvement of battery reliability and battery conversion efficiency.

[0006] To achieve the above object, in a first aspect, the present invention provides a method for manufacturing a back-contact battery, including a post-texturing process for opening a specific isolation groove as follows:

[0007] S00. Form a first semiconductor layer on the back surface of the silicon wafer, and then form a second semiconductor opening region; then perform texturing cleaning to form a textured surface on the front surface of the silicon wafer and the second semiconductor opening region, and a part of the silicon wafer corresponding to the position of the first semiconductor layer is a polished surface; then deposit a second semiconductor layer on the back surface, and then form a first semiconductor opening region spaced apart from the second semiconductor opening region on a part of the second semiconductor layer;

[0008] S07. Then deposit a stacked conductive film layer on the back surface. The stacked conductive film layer includes a non-acid-resistant transparent conductive thin film and an acid-resistant laser-absorbing metal layer formed in sequence. Among them, the thickness ratio of the non-acid-resistant transparent conductive thin film to the laser-absorbing metal layer is 1:0.20 - 0.70. The corrosion time of the non-acid-resistant transparent conductive thin film in a 15wt% HCl solution at a temperature of 20°C is 15 - 30s, and the corrosion time of the laser-absorbing metal layer in a 15wt% HCl solution at a temperature of 20°C is 5 - 7 times the corrosion time of the non-acid-resistant transparent conductive thin film under the same conditions. The absorption rate ratio of the non-acid-resistant transparent conductive thin film to the laser-absorbing metal layer at a light wavelength of 320 - 1100nm is 1:250 - 500;

[0009] S08. Perform a third grooving on a part of the stacked conductive film layer in the target area between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove in the corresponding area at the junction of the textured surface and the polished surface. The process of the third grooving includes: first, use laser etching to etch the laser-absorbing metal layer in the target area, and then use hydrochloric acid to corrode away the non-acid-resistant transparent conductive thin film in the target area;

[0010] S10. Form metal fine grid electrodes on the outer surfaces of the corresponding stacked conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0011] In some preferred embodiments of the present invention, the thickness of the non-acid-resistant transparent conductive thin film is 40 - 80nm.

[0012] In some preferred embodiments of the present invention, the corrosion time of the laser-absorbing metal layer in a 15wt% HCl solution at a temperature of 20°C is 100 - 200s.

[0013] In some preferred embodiments of the present invention, the non-acid-resistant transparent conductive thin film is selected from indium tin oxide thin film and / or indium oxide doped with tungsten.

[0014] In some preferred embodiments of the present invention, the laser-absorbing metal layer includes at least one of a nickel metal layer, a nickel-copper alloy layer, a titanium metal layer, and a nickel-titanium alloy layer.

[0015] In some preferred embodiments of the present invention, the thickness of the laser-absorbing metal layer is 10 - 30 nm.

[0016] In some preferred embodiments of the present invention, the mass concentration of hydrochloric acid in S08 is 20% - 30%.

[0017] In some preferred embodiments of the present invention, the conditions for hydrochloric acid corrosion in S08 include: the temperature of hydrochloric acid is 20 - 40 °C, and the corrosion time is 15 - 30 s.

[0018] In some preferred embodiments of the present invention, the laser used for laser etching in S08 is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser.

[0019] In some preferred embodiments of the present invention, the conditions for laser etching include: the power of the laser is 20 - 60 kW, the frequency is 200 - 500 kHz, and the spot size is 30 - 150 μm.

[0020] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

[0021] In some preferred embodiments of the present invention, the width W1 of the second semiconductor opening region is 300 - 700 μm, the width W2 of the first semiconductor opening region is 150 - 350 μm, and the width WgL of the isolation groove is 30 - 150 μm.

[0022] In some preferred embodiments of the present invention, the process of S00 specifically includes:

[0023] S01. Provide a double-sided polished silicon wafer;

[0024] S02. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0025] S03. Perform a first opening on the back surface obtained in S02 to form a second semiconductor opening region;

[0026] S04. Through texturing cleaning, form a textured surface on the front surface of the silicon wafer and in the second semiconductor opening region, and a part of the silicon wafer corresponding to the position of the first semiconductor layer is a polished surface. Then, according to needs, select whether to perform the step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer after cleaning;

[0027] S05. Deposit a second semiconductor layer on the back surface obtained in S04;

[0028] S06. Perform a second opening on a part of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region.

[0029] In some preferred embodiments of the present invention, the method for preparing the back contact battery further includes: before or after depositing the second semiconductor layer, a passivation layer and an antireflection layer are sequentially deposited on the front side of the silicon wafer.

[0030] In some preferred embodiments of the present invention, the method for preparing the back contact battery further includes: S11. Form an insulating ink layer arranged at intervals on the outer surface of the metal fine grid electrode on the back side of the silicon wafer, and then form a metal main grid electrode on the outer surface of the back side.

[0031] In a first aspect, the present invention provides a back contact battery, which is obtained by the method for preparing the back contact battery described in the first aspect.

[0032] Beneficial effects:

[0033] Through the above technical solutions, in the post-texturing method of the present invention, a stacked conductive film layer including a specific acid-intolerant transparent conductive film and an acid-resistant laser-absorbing metal layer is adopted. By utilizing the appropriate different acid resistances and appropriate different laser absorption rates of the acid-intolerant transparent conductive film and the acid-resistant laser-absorbing metal layer, and matching with an appropriate thickness ratio, when forming the isolation groove at the junction of the textured area and the polished area, the laser-absorbing metal layer in the target area can be etched away first by laser grooving, and then the acid-intolerant transparent conductive film in the target area can be corroded away by hydrochloric acid, while the laser-absorbing metal layer in other areas is retained. Thus, the effect of insulating grooving can be achieved without damaging the corresponding passivation layer of the second semiconductor layer during laser grooving, no side etching problem will occur, the insulation effect is good, which is beneficial to reducing the battery leakage current; and in the back contact battery structure obtained by the present invention, the acid-intolerant transparent conductive film is covered with a laser-absorbing metal layer, which can effectively protect the acid-intolerant transparent conductive film, help improve the battery reliability, and thus improve the battery conversion efficiency.

[0034] Among them, an acid-intolerant transparent conductive film and an acid-resistant laser-absorbing metal layer with different corrosion rates in hydrochloric acid are particularly adopted, and combined with subsequent hydrochloric acid corrosion, to achieve the purpose of local precise corrosion grooving, without damaging other film layers, no side etching problem will occur, which is beneficial to improving the insulation effect of the isolation groove and effectively reducing the battery leakage current. Under the same conditions, if hydrochloric acid is replaced by hydrofluoric acid, the acidity of hydrofluoric acid is stronger, and it is easy to corrode both the acid-intolerant transparent conductive film and the laser-absorbing metal layer during the wet etching stage, which is not conducive to the retention of the laser-absorbing metal layer and not conducive to the battery reliability.

[0035] In the preferred scheme of the present invention, a combined passivation structure is adopted, which is more conducive to reducing the battery leakage current in cooperation with a specific isolation groove grooving method. DETAILED DESCRIPTION

[0036] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0037] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0038] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0039] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0040] In a first aspect, the present invention provides a method for preparing a back contact battery, comprising the following specific isolation groove post-texturing process:

[0041] S00, forming a first semiconductor layer on the back side of the silicon wafer, and then forming a second semiconductor opening area; then performing texturing and cleaning, forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening area, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polishing surface; then depositing a second semiconductor layer on the back side, and then forming a first semiconductor opening area on a portion of the second semiconductor layer, which is spaced apart from the second semiconductor opening area;

[0042] S07. Then deposit a laminated conductive film layer on the back. The laminated conductive film layer includes an acid-sensitive transparent conductive thin film and an acid-resistant laser-absorbing metal layer formed in sequence. Among them, the thickness ratio of the acid-sensitive transparent conductive thin film to the laser-absorbing metal layer is 1:0.20 - 0.70, preferably 1:0.30 - 0.70. The corrosion time of the acid-sensitive transparent conductive thin film in a 15wt% HCl solution at a temperature of 20°C is 15 - 30 s. The corrosion time of the laser-absorbing metal layer in a 15wt% HCl solution at a temperature of 20°C is 5 - 7 times, preferably 6 - 7 times, the corrosion time of the acid-sensitive transparent conductive thin film under the same conditions. The absorption rate ratio of the acid-sensitive transparent conductive thin film to the laser-absorbing metal layer at a light wavelength of 320 - 1100 nm is 1:250 - 500, preferably 1:310 - 450;

[0043] S08. Perform a third grooving on a part of the laminated conductive film layer in the target area between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove at the corresponding area at the junction of the texturing surface and the polishing surface. The process of the third grooving includes: first, use laser etching to etch the laser-absorbing metal layer in the target area, and then use hydrochloric acid to corrode away the acid-sensitive transparent conductive thin film in the target area;

[0044] S10. Form metal fine grid electrodes on the outer surfaces of the corresponding laminated conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located, respectively.

[0045] In some preferred embodiments of the present invention, the thickness of the acid-sensitive transparent conductive thin film is 40 - 80 nm.

[0046] In the present invention, the test method for the absorption rate is as follows: Use a spectral analyzer to measure the transmittance curve and reflectance curve of the target film layer in the full wavelength range, and calculate the absorption rate curve according to the principle of transmittance + reflectance + absorption rate = 1. The unit of the absorption rate is %.

[0047] In the present invention, the "corrosion time in a 15wt% HCl solution at a temperature of 20°C" refers to the time when a certain thickness of the film layer in the target area is completely corroded under this specific condition. It can be understood that different thicknesses result in different corrosion times.

[0048] Preferably, the corrosion time of the laser-absorbing metal layer in a 15wt% HCl solution at a temperature of 20°C is 100 - 200 s. With the laser-absorbing metal layer adopting this preferred scheme, it is more conducive to protecting the transparent conductive thin film in the non-grooved area.

[0049] In some preferred embodiments of the present invention, the acid-intolerant transparent conductive film is selected from indium tin oxide film (ITO) and / or indium tungsten oxide (IWO). Conventional IZO / AZO transparent conductive films are extremely vulnerable to corrosion in acid solution and prone to side etching problems in subsequent processing.

[0050] In some preferred embodiments of the present invention, the laser-absorbing metal layer includes at least one of a nickel metal layer, a nickel-copper alloy layer, a titanium metal layer, and a nickel-titanium alloy layer, and more preferably at least one of a nickel metal layer, a nickel-copper alloy layer, and a nickel-titanium alloy layer.

[0051] In some preferred embodiments of the present invention, the thickness of the laser-absorbing metal layer is 10 - 30 nm. Using the laser-absorbing metal layer with this preferred thickness is more conducive to protecting the transparent conductive film in the non-grooved area during the corrosion process.

[0052] In some preferred embodiments of the present invention, the mass concentration of hydrochloric acid in S08 is 20% - 30%. Using hydrochloric acid at this appropriate concentration is more conducive to improving the grooving insulation effect while ensuring that the laser-absorbing metal layer can effectively protect the non-grooved area.

[0053] In some preferred embodiments of the present invention, the conditions for hydrochloric acid corrosion in S08 include: the temperature of hydrochloric acid is 20 - 40 °C, and the corrosion time is 15 - 30 s. Using this preferred scheme is more conducive to completely corroding the transparent conductive film in the grooved area.

[0054] In some preferred embodiments of the present invention, the laser used for laser etching in S08 is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser, and more preferably a flat-top picosecond green laser. Using the preferred laser is more conducive to the absorption of the laser-absorbing metal layer to achieve the purpose of grooving.

[0055] In some preferred embodiments of the present invention, the conditions for laser etching include: the power of the laser is 20 - 60 kW, the frequency is 200 - 500 kHz, and the spot size is 30 - 150 μm. Using the preferred laser etching conditions is more conducive to completely opening the isolation groove.

[0056] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. The first doped silicon layer and the second doped silicon layer are each independently polysilicon, amorphous silicon, or microcrystalline silicon. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer.

[0057] Further preferably, the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer arranged in sequence, and the second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer arranged in sequence. One of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type. The use of a combined passivation structure, combined with a specific isolation groove grooving method, is more conducive to improving the passivation effect, reducing the leakage current, and further improving the battery conversion efficiency.

[0058] The thicknesses and corresponding doping concentrations of the tunneling oxide layer, the intrinsic amorphous silicon layer, the first doped polysilicon layer, and the second doped silicon layer described in the present invention can respectively refer to the ranges of the prior art and can all be used in the present invention. Exemplarily, the thickness of the tunneling oxide layer is 1 - 2 nm, the thickness of the first doped polysilicon layer is 80 - 200 nm, and the effective doping concentration is greater than 5e18 cm -3 , the thickness of the intrinsic amorphous silicon layer is 5 - 15 nm, the thickness of the second doped silicon layer is 10 - 15 nm, and the effective doping concentration is 2e18 cm -3 -3e20 cm -3 .

[0059] In some preferred embodiments of the present invention, the width W1 of the second semiconductor opening region is 300 - 700 μm, the width W2 of the first semiconductor opening region is 150 - 350 μm, and the width WgL of the isolation groove is 30 - 150 μm.

[0060] In some preferred embodiments of the present invention, the process of S00 specifically includes:

[0061] S01. Provide a double-sided polished silicon wafer;

[0062] S02. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0063] S03. Perform a first opening on the back surface obtained in S02 to form a second semiconductor opening region;

[0064] S04. Through texturing and cleaning, form a textured surface on the front surface of the silicon wafer and the second semiconductor opening region, and a part of the silicon wafer at the position corresponding to the first semiconductor layer is a polished surface. Then, according to needs, select whether to perform the step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer after cleaning;

[0065] S05. Deposit a second semiconductor layer on the back surface obtained in S04;

[0066] S06. Perform a second opening on a part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region.

[0067] Other conventional steps may also be included in the present invention. For example, S02 further includes: after forming the first semiconductor layer, removing the PSG on the surface, backwashing, and then depositing a mask layer on the back surface.

[0068] In some preferred embodiments of the present invention, the method for preparing the back contact battery further includes: before or after depositing the second semiconductor layer, sequentially depositing a passivation layer and an antireflection layer on the front surface of the silicon wafer.

[0069] In some preferred embodiments of the present invention, the method for preparing the back contact battery further includes: S11, forming an insulating ink layer arranged at intervals on the outer surface of the metal fine grid electrode on the back surface of the silicon wafer, and then forming a metal main grid electrode on the outer back surface. The connection structure of the metal fine grid electrode, the insulating ink layer, and the metal main grid electrode can refer to the prior art and will not be elaborated herein.

[0070] In a first aspect, the present invention provides a back contact battery, which is prepared by the method for preparing the back contact battery described in the first aspect.

[0071] The embodiments of the present invention will be described in detail below. They are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0072] Example 1

[0073] A back contact battery is prepared by the following method:

[0074] S01, double-sided polishing of the silicon wafer;

[0075] S02, depositing a first semiconductor layer on the back surface of the silicon wafer. The first semiconductor layer is a tunneling oxide layer with a thickness of 1.5 nm and an N-type doped polysilicon layer. The thickness of the N-type doped polysilicon layer is 100 nm and the effective doping concentration is 2e20 cm -3 ; removing PSG, backwashing, and then depositing a mask layer on the back surface. The mask layer is silicon nitride;

[0076] S03, opening an opening on the back surface of the silicon wafer, removing the mask layer and part of the first semiconductor layer to form a second semiconductor opening region. The width W1 of the second semiconductor opening region is 500 μm;

[0077] S04, texturing and cleaning the silicon wafer, forming a pyramid texture on the second semiconductor opening region and the front surface of the silicon wafer. At the same time, removing the first semiconductor layer in the second semiconductor opening region on the back surface of the silicon wafer, and then removing all the mask layers;

[0078] S05, depositing and forming a passivation layer and an antireflection layer on the front surface of the silicon wafer, and depositing and forming a second semiconductor layer on the back surface. The second semiconductor layer is an intrinsic amorphous silicon layer with a thickness of 10 nm and an N-type doped amorphous silicon layer with a thickness of 12.5 nm and an effective doping concentration of 2e19 cm -3The P-type doped amorphous silicon layer is formed by PECVD deposition method;

[0079] S06. Openings are formed on the back side of the silicon wafer by laser to form the first semiconductor opening region arranged alternately with the second semiconductor opening region. The width W2 of the first semiconductor opening region is 250 μm. The silicon wafer is cleaned to remove the oxide layer in the first semiconductor opening region;

[0080] S07. A laminated conductive film layer is deposited on the back side of the silicon wafer;

[0081] The laminated conductive film layer is composed of an acid-intolerant transparent conductive thin film (i.e., ITO) formed in sequence and a laser-absorbing metal layer stacked. Among them, the laser-absorbing metal layer is Ni. The thickness of ITO is 60 nm, and its corrosion time in a 15 wt% HCl solution at a temperature of 20 °C is 24 s. The thickness of the laser-absorbing metal layer is 20 nm, and its corrosion time in a 15 wt% HCl solution at a temperature of 20 °C is 150 s. The absorption ratio of the acid-intolerant transparent conductive thin film to the laser-absorbing metal layer at a light wavelength of 320 - 1100 nm is 1:333.

[0082] S08. An isolation groove is formed in the corresponding area at the junction of the textured surface and the polished surface between the first semiconductor opening region and the second semiconductor opening region. The width WgL of the isolation groove is 100 μm, and the isolation groove is formed at the junction of the textured region and the polished region;

[0083] The isolation groove is formed by the following method: First, by the way of laser using a flat-top picosecond green laser, the power of the laser is 30 kW, the frequency is 400 kHz, and the spot size is 100 μm.

[0084] The laser-absorbing metal layer on the ITO is etched by laser. Since the ITO has poor absorption in the 512 nm band and cannot be etched off, the ITO is etched off by acid (20% HCl by mass concentration) after laser, so as to achieve the effect of slot insulation. The conditions for hydrochloric acid corrosion include: the temperature of hydrochloric acid is 30 °C, and the corrosion time is 20 s.

[0085] S09. Spaced-apart insulating ink layers are formed on the conductive mask layer on the back side of the silicon wafer. The insulating ink is formed by printing or spraying;

[0086] S10. Silver paste fine grid electrodes are formed on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer;

[0087] S11. Spaced-apart insulating ink layers are formed on the outer surface of the metal fine grid electrodes on the back side of the silicon wafer, and then a metal main grid electrode is formed on the outer surface of the back side.

[0088] Example 2

[0089] It was carried out according to the method of Example 1, except that the acid-intolerant transparent conductive film was replaced with indium tin oxide doped with tungsten, and the corrosion time in a 15 wt% HCl solution at a temperature of 20 °C was 30 s. The absorption rate ratio of indium tin oxide doped with tungsten to the laser absorption metal layer at a light wavelength of 320 - 1100 nm was 1:294.

[0090] Example 3

[0091] It was carried out according to the method of Example 1, except that the thickness of the laser absorption metal layer was 15 nm, and its corrosion time in a 15 wt% HCl solution at a temperature of 20 °C was 110 s. The absorption rate ratio of ITO to the laser absorption metal layer at a light wavelength of 320 - 1100 nm was 1:300.

[0092] Example 4

[0093] It was carried out according to the method of Example 1, except that the laser absorption metal layer was replaced with a nickel-copper alloy layer of the same thickness, and its corrosion time in a 15 wt% HCl solution at a temperature of 20 °C was 130 s. The absorption rate ratio of ITO to the laser absorption metal layer at a light wavelength of 320 - 1100 nm was 1:366.

[0094] Example 5

[0095] It was carried out according to the method of Example 1, except that the corrosion time of hydrochloric acid corrosion was 30 s.

[0096] Example 6

[0097] It was carried out according to the method of Example 1, except that the first semiconductor layer structure was different, and the passivation structure was a heterojunction. Specifically, the first semiconductor layer was an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer. The thickness of the intrinsic amorphous silicon layer was 10 nm, and the thickness of the N-type doped amorphous silicon layer was 60 nm with an effective doping concentration of 1e19 cm -3 。

[0098] Comparative Example 1

[0099] It was carried out according to the method of Example 1, except that the laminated conductive film layer was replaced with an ITO single layer (with the same thickness), the laser absorption metal layer was not provided; and in S08, the third grooving was carried out by laser etching the ITO single layer.

[0100] Comparative Example 2

[0101] It was carried out according to the method of Example 1, except that the thickness of the laser absorption metal layer was adjusted so that the thickness ratio of the acid-intolerant transparent conductive film to the laser absorption metal layer was 1:0.16.

[0102] Comparative Example 3

[0103] It was carried out according to the method of Example 1, except that after forming the isolation grooves in the corresponding area at the junction of the textured surface and the polished surface, the remaining all laser absorption metal layers were removed by laser etching, and then metal fine grid electrodes were formed on the outer surface of the acid-resistant transparent conductive thin film; that is, the laser absorption metal layer was not retained in the final structure.

[0104] Comparative Example 4

[0105] It was carried out according to the method of Example 1, except that the ITO layer in the stacked conductive film layer was replaced with indium zinc oxide IZO thin film, its thickness remained unchanged, and its corrosion time in a 15wt% HCl solution at a temperature of 20 °C was 10 s. The absorption rate ratio of the IZO thin film to the laser absorption metal layer at a light wavelength of 320 - 1100 nm was 1:454.

[0106] Comparative Example 5

[0107] It was carried out according to the method of Example 1, except that the hydrochloric acid in S08 was replaced with a hydrofluoric acid solution of the same mass concentration.

[0108] Test Example

[0109] The back-contact batteries obtained from the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. The battery reliability was characterized by the light-induced degradation of the battery, and its test method was: by comparing the maximum output power of the battery before and after light-induced degradation under standard test conditions (1000 W / m 2 , 25 °C, AM1.5), calculating the light-induced degradation rate of the battery, and the light-induced degradation rate = (the maximum output power before light-induced degradation - the maximum output power after light-induced degradation) / the maximum output power before light-induced degradation. The dark current yield refers to the proportion of qualified products that meet IRev2 < 2 A under a reverse voltage of 15 V in the same batch during the batch production of the battery.

[0110] Table 1

[0111]

[0112] From the above results, it can be seen that compared with the comparative examples, by adopting the embodiment scheme of the present invention, precise laser grooving is achieved, an isolation groove with good insulation effect is formed, which is beneficial to reducing the battery leakage current, and at the same time, the battery reliability and the battery conversion efficiency are improved.

[0113] Furthermore, according to Example 1 and Examples 2 - 6, it can be seen that by adopting the preferred scheme of the present invention, it is more beneficial to reduce the battery leakage current, and at the same time, further improve the battery reliability and the battery conversion efficiency.

[0114] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A method for preparing a back contact battery, characterized in that: The post-texturing process of specific isolation groove opening is as follows: S00, forming a first semiconductor layer on the back side of the silicon wafer, and then forming a second semiconductor opening area; then performing texturing and cleaning, forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening area, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polishing surface; then depositing a second semiconductor layer on the back side, and then forming a first semiconductor opening area on a portion of the second semiconductor layer, which is spaced apart from the second semiconductor opening area; S07, then depositing a laminated conductive film layer on the back side, the laminated conductive film layer comprises an acid-resistant transparent conductive film and an acid-resistant laser absorbing metal layer formed in sequence, wherein the thickness ratio of the acid-resistant transparent conductive film to the laser absorbing metal layer is 1:0.20-0.70, the corrosion time of the acid-resistant transparent conductive film in a HCl solution with a temperature of 20°C and a mass concentration of 15wt% is 15-30s, the corrosion time of the laser absorbing metal layer in a HCl solution with a temperature of 20°C and a mass concentration of 15wt% is 5-7 times the corrosion time of the acid-resistant transparent conductive film under the same conditions, the absorptivity ratio of the acid-resistant transparent conductive film to the laser absorbing metal layer at a wavelength of 320-1100nm is 1:250-500, the acid-resistant transparent conductive film is selected from an indium tin oxide film and / or a tungsten-doped indium oxide; the laser absorbing metal layer comprises at least one of a nickel metal layer, a nickel-copper alloy layer, a titanium metal layer, and a nickel-titanium alloy layer; S08, performing a third groove on a portion of the laminated conductive film layer in the target area between the first semiconductor opening area and the second semiconductor opening area, forming an isolation groove in a corresponding area at the junction of the textured surface and the polished surface, the third groove process comprising: firstly etching the laser absorption metal layer in the target area with a laser, and then etching away the acid-resistant transparent conductive film in the target area with hydrochloric acid; S10, forming metal fine gate electrodes on the outer surfaces of the corresponding stacked conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

2. The method for preparing a back contact battery according to claim 1, characterized in that: The thickness of the acid-resistant transparent conductive film is 40-80nm.

3. The method for preparing a back contact battery according to claim 1 or 2, characterized in that The corrosion time of the laser absorbing metal layer in a 15wt% HCl solution at a temperature of 20°C is 100-200s.

4. The method for preparing a back contact battery according to claim 1, characterized in that: The thickness of the laser absorbing metal layer is 10-30 nm.

5. The method for preparing a back contact battery according to claim 1, characterized in that: The mass concentration of hydrochloric acid in S08 is 20%-30%, and / or, The conditions for hydrochloric acid corrosion in S08 include: hydrochloric acid temperature is 20-40°C, and corrosion time is 15-30s.

6. The method for preparing a back contact battery according to claim 1, characterized in that: The laser used for laser etching in S08 is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser; and / or, The conditions for laser etching include: the power of the laser is 20-60 kW, the frequency is 200-500 kHz, and the spot size is 30-150 μm.

7. The method for preparing a back contact battery according to claim 1, characterized in that: The first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer; and / or, The width W1 of the second semiconductor opening region is 300-700 μm, the width W2 of the first semiconductor opening region is 150-350 μm, and the width WgL of the isolation groove is 30-150 μm.

8. The method for preparing a back contact battery according to claim 1, characterized in that: The S00 process specifically includes: S01. Provide double-sided polished silicon wafers; S02, sequentially forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S03, performing a first opening on the back surface obtained in S02 to form a second semiconductor opening region; S04, forming a textured surface on the front side of the silicon wafer and the second semiconductor opening area through texturing and cleaning, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S05, depositing a second semiconductor layer on the back surface obtained in S04; S06. Perform a second opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

9. The method for preparing a back contact battery according to claim 1 or 8, characterized in that: The method for preparing the back contact battery also includes: Before or after depositing the second semiconductor layer, a passivation layer and an anti-reflection layer are sequentially deposited on the front side of the silicon wafer; S11. An insulating ink layer arranged in intervals is formed on the outer surface of the metal fine gate electrode on the back side of the silicon wafer, and then a metal main gate electrode is formed on the outer surface of the back side.

10. A back contact battery, characterized in that: The back contact battery is prepared by the method for preparing a back contact battery as claimed in any one of claims 1 to 9.

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