Display device and wearable electronic device

Abstract

The invention discloses a display device and a wearable electronic device. A light emitting element layer of the display device is disposed on a base layer. A first light emitting portion of the light emitting element layer includes a first organic pattern emitting light, the charge generating layer is disposed on the first light emitting portion, and the second light emitting portion is disposed on the charge generating layer. In plan view, the second light emitting portion covers the charge generation layer. The second light emitting portion includes a second organic pattern disposed in the display area and emitting light and a dummy pattern disposed in the non-display area.

Description

Technical Field

[0001] Embodiments relate to display devices and wearable electronic devices. Background Art

[0002] An organic light emitting diode (OLED) device is an active light emitting display device having the advantages of not only having a wide viewing angle and excellent contrast but also being able to be driven at a low voltage, being lightweight and thin, and having a fast response speed.

[0003] It will be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts or perceptions that were not known or understood by those skilled in the art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0004] The present disclosure provides a display device and a wearable electronic device with improved reliability.

[0005] The objects of the present disclosure are not limited to the above objects, and other objects will be clearly understood from the following description by those skilled in the art.

[0006] According to an embodiment, a display device may include: a display area and a non-display area; a substrate layer; and a light-emitting element layer disposed on the substrate layer. The light-emitting element layer may include: a first light-emitting portion including a first organic pattern that emits light; a charge generation layer disposed on the first light-emitting portion; and a second light-emitting portion disposed on the charge generation layer. In a plan view, the second light-emitting portion covers the charge generation layer. The second light-emitting portion may include a second organic pattern disposed in the display area and a dummy pattern disposed in the non-display area, and the second organic pattern emits light.

[0007] In the shortest path from the display area to the edge of the substrate layer, the charge generation layer may extend from the edge of the display area to the non-display area by about 50 μm or more in a plan view.

[0008] In the shortest path from the display area to the edge of the base layer, the second light emitting portion may extend less than about 200 μm toward the edge of the base layer in a plan view than the charge generation layer.

[0009] An average size of the dummy patterns may be greater than or equal to an average size of the second organic patterns.

[0010] In a plan view, the dummy patterns may partially overlap each other and may completely cover the charge generation layer in the non-display region.

[0011] The second organic pattern and the dummy pattern may have the same stack structure.

[0012] The dummy pattern and the second organic pattern may have different stack structures.

[0013] The second organic pattern may include a hole transport layer and a light emitting layer disposed on the hole transport layer, and the dummy pattern may include the hole transport layer or the light emitting layer.

[0014] The display device may further include: a cathode electrode disposed on the light emitting element layer, the cathode electrode may cover the second light emitting portion, and the charge generating layer and the cathode electrode may be separated by the second light emitting portion.

[0015] The light-emitting element layer may further include: an anode electrode, arranged on the substrate layer; and a pixel defining layer, covering the substrate layer and the anode electrode, the pixel defining layer may include an opening exposing the anode electrode in the display area, the opening may not be arranged in the non-display area, and the first light-emitting portion may be arranged on the pixel defining layer and may be electrically connected to the anode electrode through the opening.

[0016] Organic patterns that overlap each other in a plan view among the first organic pattern and the second organic pattern may emit light of the same color.

[0017] According to an embodiment, a display device may include: a display area and a non-display area; a substrate layer; and a light-emitting element layer disposed on the substrate layer. The light-emitting element layer may include: a first light-emitting portion that emits light; a charge generation layer disposed on the first light-emitting portion; and a second light-emitting portion disposed on the charge generation layer and emitting light. In the non-display area, as the distance from the display area increases, the thickness of each of the first light-emitting portion, the charge generation layer, and the second light-emitting portion becomes thinner. In a plan view, the second light-emitting portion covers the charge generation layer.

[0018] In the shortest path from the display area to the edge of the base layer, the charge generation layer extends from the edge of the display area by about 50% or less than the first light emitting portion or the second light emitting portion in a plan view.

[0019] In the shortest path from the display area to the edge of the base layer, each of the first and second light emitting portions may further expand within a range of about 100 μm to about 500 μm from the edge of the display area in a plan view.

[0020] A reduction rate of a thickness of the charge generation layer according to a distance from an edge of the display region may be greater than a reduction rate of a thickness of the first light emitting portion.

[0021] Each of the first and second light emitting portions may include an organic pattern emitting light, and the organic pattern may be disposed in the display area and may not be disposed in the non-display area.

[0022] The charge generation layer may include a first charge generation layer and a second charge generation layer sequentially stacked between the first light emitting portion and the second light emitting portion, and the second charge generation layer may be disposed at an inner side of the first charge generation layer.

[0023] A reduction rate of the thickness of the second charge generation layer according to a distance from an edge of the display region may be greater than a reduction rate of the thickness of the first charge generation layer.

[0024] The display device may further include: a cathode electrode disposed on the light emitting element layer, the cathode electrode may cover the second light emitting portion, and the charge generating layer and the cathode electrode may be separated by the second light emitting portion.

[0025] According to an embodiment, a wearable electronic device may include: a display panel emitting light; and at least one lens disposed on the display panel. The display panel may include: a display area and a non-display area; a substrate layer; and a light-emitting element layer disposed on the substrate layer. The light-emitting element layer may include: a first light-emitting portion including a first organic pattern emitting light; a charge generation layer disposed on the first light-emitting portion; and a second light-emitting portion disposed on the charge generation layer. In a plan view, the second light-emitting portion covers the charge generation layer. The second light-emitting portion may include a second organic pattern disposed in the display area and a dummy pattern disposed in the non-display area, and the second organic pattern emits light.

[0026] Details of other embodiments are included in the detailed description and accompanying drawings.

[0027] In the display device and the wearable electronic device according to the embodiment, in addition to the organic pattern of the display area, the second light-emitting portion may also include a dummy pattern in the non-display area, and the dummy pattern may completely cover the charge generation layer in the non-display area. Therefore, in the non-display area, the cathode electrode and the charge generation layer may be separated (or physically separated) by the dummy pattern, a short circuit between the cathode electrode and the charge generation layer may be prevented, and the reliability of the display device may be improved.

[0028] In the display device and the wearable electronic device according to the embodiment, as the distance from the display area increases, the thickness of each of the first light-emitting portion, the charge generation layer, and the second light-emitting portion can be reduced or thinned, and the thickness of the charge generation layer can be reduced at a rate greater than the thickness of the second light-emitting portion according to the distance from the edge of the display area. The second light-emitting portion can completely cover the charge generation layer in the non-display area. Therefore, in the non-display area, the cathode electrode and the charge generation layer can be separated by the second light-emitting portion.

[0029] The effects according to the embodiment are not limited to the above-described effects, and further various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram illustrating an embodiment of a display device;

[0032] Figure 2 It is a graphic Figure 1 A block diagram of an embodiment of any one of the sub-pixels;

[0033] Figure 3 yes Figure 2 A schematic diagram of an equivalent circuit of a sub-pixel;

[0034] Figure 4 It is a graphic Figure 1 A schematic plan view of an embodiment of a display panel;

[0035] Figure 5 It is a graphic Figure 4 an exploded perspective view of a portion of a display panel;

[0036] Figure 6 It is a graphic Figure 5 A schematic plan view of an embodiment of any one of the pixels;

[0037] Figure 7 The diagram is along Figure 6 A schematic cross-sectional view of an embodiment of a pixel taken along line II';

[0038] Figure 8 The diagram is along Figure 6 A schematic cross-sectional view of an embodiment of a pixel taken along line II';

[0039] Fig. 9 The diagram is included in Figure 7 A schematic cross-sectional view of an embodiment of a light emitting structure in a pixel of;

[0040] Fig.10 The diagram is along Figure 4 A schematic cross-sectional view of an embodiment of a display panel taken along line II-II';

[0041] Fig.11 It is a graphic Figure 4 A schematic plan view of an embodiment of the first zone of FIG.

[0042] Fig. 12A and Fig. 12B The diagram is along Figure 4 A schematic cross-sectional view of an embodiment of a display panel taken along line II-II';

[0043] Fig.13 The diagram is along Figure 4 A schematic cross-sectional view of an embodiment of a display panel taken along line II-II';

[0044] Fig.14 It is a graphic Figure 4 A schematic plan view of an embodiment of the first zone of FIG.

[0045] Fig.15 The diagram is along Figure 4 A schematic cross-sectional view of an embodiment of a display panel taken along line II-II';

[0046] Fig.16 is a diagram illustrating a deposition process;

[0047] Fig.17 is a block diagram illustrating an embodiment of a display system;

[0048] Fig.18 It is a graphic Fig.17 A schematic perspective view of an application example of a display system; and

[0049] Fig.19 It is a graphic Fig.18 Illustration of a head mounted display device worn by a user. DETAILED DESCRIPTION

[0050] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. It should be noted that in the following description, parts for understanding the operation according to the present disclosure are described, and descriptions of other parts may be omitted so as not to obscure the subject matter of the present disclosure. The present disclosure may be embodied in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided to be described in detail so that those skilled in the art to which the present disclosure belongs can realize the technical spirit of the present disclosure.

[0051] In the drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for ease of description and clarity. Like numbers refer to like elements throughout.

[0052] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0053] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purpose of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in either a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or".

[0054] In the specification and claims, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of" for the purpose of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0055] Throughout the specification, when a part is "connected" to another part, the case includes not only the case where the part is "directly connected" but also the case where the part is "indirectly connected" and another element is disposed therebetween. The terms used herein are used to describe the embodiments and are not intended to limit the present disclosure. Throughout the specification, when a part "includes", unless otherwise specified, the part may further include another component without excluding another component.

[0056] Here, terms such as "first" and "second" can be used to describe various components, but the components are not limited to these terms. These terms are used to distinguish one component from another component. Therefore, a first component can refer to a second component within the scope without departing from the scope disclosed herein.

[0057] Spatially relative terms such as "under..." and "on..." can be used for descriptive purposes to describe the relationship between one element or feature and another (some) element or feature as shown in the drawings. In addition to the directions depicted in the drawings, spatially relative terms are intended to also include other directions in use, operation and / or manufacture. For example, when the device shown in the drawings is reversed, the elements depicted as being "under" other elements or features will be located in the direction "on" other elements or features. Therefore, in an embodiment, the term "under..." can include both directions of upper and lower. The device can face other directions (e.g., rotated 90 degrees or other directions), and the spatially relative terms used in this article are therefore interpreted accordingly.

[0058] The term "overlapping" or "overlapping" means that the first object can be above or below or to the side of the second object, and vice versa. In addition, the term "overlapping" can include layering, stacking, facing, extending over, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will recognize and understand.

[0059] The term "facing" means that the first element can be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first element and the second element, although the first element and the second element still face each other, the first element and the second element can be understood as indirectly opposite to each other.

[0060] When an element is described as “non-overlapping” another element, this may include the elements being spaced apart, offset or separated from each other or any other suitable terminology as would be recognized and understood by one of ordinary skill in the art.

[0061] When used in this specification, the terms "includes", "comprising" and "having" and variations thereof indicate the presence of stated features, integers, steps, operations, elements, parts and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0062] Various embodiments are described with reference to the accompanying drawings that schematically illustrate ideal embodiments. Accordingly, it is expected that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be interpreted as limited to the specific shapes shown, but should be interpreted as including changes in shape that occur, for example, as a result of manufacturing. As described above, the shapes shown in the drawings may not show the actual shape of the area of ​​the device, and the embodiments are not limited thereto.

[0063] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0064] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as that commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (e.g., terms defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and, unless so explicitly defined herein, will not be interpreted in an idealized or overly formal sense.

[0065] Figure 1 is a diagram illustrating an embodiment of a display device.

[0066] refer to Figure 1 , the display device 100 may include a display panel 110 (or a display unit), a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0067] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0068] Each of the sub-pixels SP may include at least one light emitting element for generating light. Accordingly, each of the sub-pixels SP may generate light of a given color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the sub-pixels SP may form one pixel PXL. For example, Figure 1 As shown in FIG. 4 , three sub-pixels SP may form one pixel PXL.

[0069] The gate driver 120 is connected to the sub-pixels SP arranged or disposed in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to the gate control signal GCS. In an embodiment, within the spirit and scope of the present disclosure, the gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting a gate signal in synchronization with the timing of applying a data signal, etc.

[0070] In an embodiment, first to mth emission control lines EL1 to ELm connected to the subpixels SP in the row direction may be further provided. The gate driver 120 may include an emission control driver for controlling the first to mth emission control lines EL1 to ELm, and the emission control driver may operate under the control of the controller 150.

[0071] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and such a driver may be disposed on one side of the display panel 110 and on the other side of the display panel 110 opposite to the one side. As described above, according to the embodiment, the gate driver 120 may be disposed around the display panel 110 in various forms.

[0072] The data driver 130 is connected to the sub-pixels SP arranged or disposed in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 receives the image data DATA and the data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, within the spirit and scope of the present disclosure, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0073] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data line DL1 to the nth data line DLn using a voltage from the voltage generator 140. In the case where a gate signal is applied to each of the first gate line GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLm. Accordingly, the corresponding sub-pixel SP may generate light corresponding to the data signal. Accordingly, an image is displayed on the display panel 110.

[0074] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0075] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 generates a plurality of voltages and provides the generated voltages to components of the display device 100. For example, the voltage generator 140 may generate the plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0076] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS may be provided to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than that of the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0077] The voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a selectable reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate such a reference voltage.

[0078] The controller 150 controls the overall operation of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling display of the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0079] The controller 150 may convert the input image data IMG so that the input image data IMG is suitable for the display device 100 or the display panel 110, and output the image data DATA. In an embodiment, the controller 150 may output the image data DATA by aligning the input image data IMG so that the input image data IMG is suitable for the sub-pixels SP of the row unit.

[0080] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be included in the driver integrated circuit DIC. The data driver 130, the voltage generator 140 and the controller 150 may be functionally separate components in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140 and the controller 150 may be provided as a component different from the driver integrated circuit DIC.

[0081] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may sense the temperature around the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0082] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power voltage VDD and the second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0083] Figure 2 It is a graphic Figure 1 A block diagram of an example of any one of the sub-pixels of FIG. Figure 2 in Figure 1 Among the sub-pixels SP, the sub-pixel SPij arranged or set in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0084] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0085] The light emitting element LD is connected between the first power voltage node VDDN and the second power voltage node VSSN. At this time, the first power voltage node VDDN is the transmission node. Figure 1 The first power voltage node VDD is connected to the second power voltage node VSSN. Figure 1 A node of a second power voltage VSS is connected to the node.

[0086] The anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0087] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm, Figure 1 The i-th emission control line ELi among the first emission control lines EL1 to the m-th emission control lines ELm and Figure 1 The sub-pixel circuit SPC may control the light emitting element LD according to a signal received through such a signal line.

[0088] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, in the case where the i-th gate line GLi may include two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0089] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. In the case where the i-th emission control line ELi may include two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0090] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. In response to the emission control signal received through the i-th emission control line ELi, the sub-pixel circuit SPC may adjust the current flowing from the first power voltage node VDDN through the light emitting element LD to the second power voltage node VSSN according to the stored voltage. Accordingly, the light emitting element LD may generate light of a brightness corresponding to the data signal.

[0091] Figure 3 yes Figure 2 Schematic diagram of the equivalent circuit of a sub-pixel.

[0092] refer to Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0093] The sub-pixel circuit SPC may be connected to the i-th gate line GLi', the i-th emission control line ELi', and the j-th data line DLj. Figure 2 Compared with the i-th gate line GLi, the i-th gate line GLi′ may further include a third sub-gate line SGL3. Figure 2 Compared with the i-th emission control line ELi, the i-th emission control line ELi′ may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0094] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0095] The first transistor T1 is connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 may be connected to the second node N2, and thus the first transistor T1 may be turned on according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0096] The second transistor T2 is connected between the jth data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1, and thus the second transistor T2 may be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0097] The third transistor T3 is connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2, and thus the third transistor T3 may be turned on in response to a gate signal of the second sub-gate line SGL2.

[0098] The fourth transistor T4 is connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub emission control line SEL2, and thus the fourth transistor T4 may be turned on in response to an emission control signal of the second sub emission control line SEL2.

[0099] The fifth transistor T5 is connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN can transmit the initialization voltage. In an embodiment, the initialization voltage can be Figure 1 The initialization voltage may be provided by the voltage generator 140. In other embodiments, the initialization voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3, and thus the fifth transistor T5 may be turned on in response to the gate signal of the third sub-gate line SGL3.

[0100] The sixth transistor T6 is connected between the first power voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub emission control line SEL1, and thus the sixth transistor T6 may be turned on in response to the emission control signal of the first sub emission control line SEL1.

[0101] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power voltage node VDDN and the second node N2.

[0102] As described above, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first capacitors C1 and second capacitors C2. However, embodiments are not limited thereto. The sub-pixel circuit SPC may be implemented as any of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. According to an embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may be variable.

[0103] The first transistor T1 to the sixth transistor T6 may be a P-type transistor. Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide silicon field effect transistor (MOSFET). However, the embodiment is not limited thereto. For example, at least one of the first transistor T1 to the sixth transistor T6 may be replaced by an N-type transistor.

[0104] In an embodiment, within the spirit and scope of the present disclosure, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, and the like.

[0105] The light emitting element LD may include an anode electrode AE, a cathode electrode CE and a light emitting layer. The light emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. After reflecting the data signal transmitted through the j-th data line DLj in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 may be turned on when the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to be low levels. The first transistor T1 may be turned on according to the voltage of the second node N2, and thus current may flow from the first power voltage node VDDN to the second power voltage node VSSN. The light emitting element LD may emit light according to the amount of the flowing current.

[0106] Figure 4 It is a graphic Figure 1 Schematic plan view of an embodiment of a display panel.

[0107] refer to Figure 4 The display panel DP may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0108] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0109] In the case where the display panel DP is used as a display screen of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device, the display panel DP may be positioned very close to the user's eyes. A relatively high integration of sub-pixels SP is required. In order to increase the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on a substrate SUB which is a silicon substrate. A display device 100 (refer to FIG. 1 ) including a display panel DP formed on a substrate SUB which is a silicon substrate Figure 1 ) can be called an OLED on silicon (OLEDoS) display device.

[0110] The sub-pixels SP are disposed on the substrate SUB in the display area DA. The sub-pixels SP may be arranged or disposed in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged or disposed in a zigzag form along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged or disposed in a zigzag form along the first direction DR1 and the second direction DR2. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0111] Two or more sub-pixels among the plurality of sub-pixels SP may form one pixel PXL.

[0112] Components for controlling the sub-pixels SP may be disposed on the substrate SUB in the non-display area NDA. Figure 1 Lines of the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn connected to the sub-pixels SP may be disposed in the non-display area NDA.

[0113] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of the display panel DP may be integrated in the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate driver 120 may be mounted on the display panel DP and may be disposed in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 may be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0114] The pad PD is disposed on the substrate SUB in the non-display area NDA. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0115] The pad PD can connect the display panel DP to the display device 100 (see Figure 1 ) is connected to other components. In an embodiment, the pad PD can be used to connect Figure 1 The driver integrated circuit DIC provides voltages and signals required for the operation of components included in the display panel DP. For example, the first data line DL1 to the nth data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power voltage VDD and the second power voltage VSS may be received from the driver integrated circuit DIC through the pad PD. For example, in the case where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0116] In an embodiment, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. At this time, the circuit board may be a flexible circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0117] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight edges and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, and an ellipse.

[0118] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable or rollable. In these cases, the display panel DP and / or the substrate SUB may include a material having flexible properties.

[0119] Figure 5 It is a graphic Figure 4 An exploded perspective view of a portion of a display panel. Figure 5 In the embodiment, for the sake of clarity and simplicity, the display panel DP is schematically shown. Figure 4 Portions corresponding to two pixels PXL1 and PXL2 among the pixels PXL of the display panel DP may be similarly configured. Portions corresponding to the remaining pixels of the display panel DP may be similarly configured.

[0120] refer to Figure 4 and Figure 5 , each of the first pixel PXL1 and the second pixel PXL2 may include first to third sub-pixels SP1, SP2, and SP3. However, the embodiment is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0121] exist Figure 5 In the embodiment, when viewed from a third direction DR3 crossing the first direction DR1 and the second direction DR2, the first to third sub-pixels SP1, SP2, and SP3 have a quadrilateral shape and have sizes equal to each other. However, the embodiment is not limited thereto. The first to third sub-pixels SP1, SP2, and SP3 may be modified to have various shapes.

[0122] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0123] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. Within the spirit and scope of the present disclosure, the substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0124] The pixel circuit layer PCL is disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. Within the spirit and scope of the present disclosure, the conductive pattern of the pixel circuit layer PCL may function as at least a portion of a circuit element and a line, etc. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0125] The circuit element may include a sub-pixel circuit SPC (refer to Figure 2 ). The sub-pixel circuit SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, in the case where the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, in the case where the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, and an insulating layer is provided between the electrodes.

[0126] Within the spirit and scope of the present disclosure, the lines of the pixel circuit layer PCL may include signal lines connected to each of the first to third sub-pixels SP1, SP2, and SP3, such as gate lines, emission control lines, and data lines. The lines may further include lines connected to Figure 2 The line may further include a line connected to the first power voltage node VDDN. Figure 2 A line to the second power voltage node VSSN.

[0127] The light emitting element layer LDL may include an anode electrode AE, a light emitting structure EMS, and a cathode electrode CE. According to an embodiment, the light emitting element layer LDL may further include a pixel defining layer PDL. In other words, the pixel defining layer PDL may be omitted.

[0128] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0129] The pixel defining layer PDL is disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each of the anode electrodes AE. The opening OP of the pixel defining layer PDL may be understood as emission regions corresponding to the first to third sub-pixels SP1 to SP3, respectively.

[0130] In an embodiment, the pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0131] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. Within the spirit and scope of the present disclosure, the light emitting structure EMS may include a light emitting layer for generating light, an electron transport layer for transporting electrons, and a hole transport layer for transporting holes.

[0132] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be completely disposed on the pixel defining layer PDL. In other words, the light emitting structure EMS may extend over the first sub-pixel SP1 to the third sub-pixel SP3. At least a portion of a layer in the light emitting structure EMS may be disconnected or bent at a boundary between the first sub-pixel SP1 to the third sub-pixel SP3. However, embodiments are not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the portions may be disposed in the opening OP of the pixel defining layer PDL.

[0133] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend throughout the first to third subpixels SP1 to SP3. As described above, the cathode electrode CE may be provided as a common electrode of the first to third subpixels SP1 to SP3.

[0134] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0135] It can be understood that any one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping therewith, and the portion of the cathode electrode CE overlapping therewith form a light emitting element LD (refer to Figure 2 ). In other words, each of the light emitting elements of the first to third sub-pixels SP1 to SP3 may have an anode electrode, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE overlapping therewith. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the light emitting layer of the light emitting structure EMS to form excitons, and in the case where the excitons transition from an excited state to a ground state, light may be generated. The brightness of the light may be determined according to the amount of current flowing through the light emitting layer. According to the configuration of the light emitting layer, the wavelength range of the generated light may be determined.

[0136] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may prevent oxygen and / or moisture, etc. from penetrating into the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers may be alternately stacked with each other. For example, within the spirit and scope of the present disclosure, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0137] In order to improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include aluminum oxide (AlO x The thin film including aluminum oxide may be located on an upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or a lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0138] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0139] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0140] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may filter the light emitted from the light emitting structure EMS, and selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and each of the color filters CF may allow light of a wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter corresponding to the third sub-pixel SP3 may allow blue light to pass through. At least a portion of the color filter CF may be omitted depending on the light emitted from the light emitting structure EMS of each sub-pixel.

[0141] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS to a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not limited thereto.

[0142] In an embodiment, at least a portion of the color filter CF of the color filter layer CFL and at least a portion of the lens LS of the lens array LA may be displaced in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In an area adjacent to the non-display area NDA in the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be displaced in a plane direction from the center of the opening OP of the corresponding pixel defining layer PDL. For example, in an area adjacent to the non-display area NDA in the display area DA, the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Accordingly, at the center of the display area DA, the light emitted from the light emitting structure EMS may be effectively output in the normal direction of the display surface. At the periphery of the display area DA, the light emitted from the light emitting structure EMS may be effectively output in a direction inclined at a selectable angle relative to the normal direction of the display surface.

[0143] A protective layer OC may be disposed on the lens array LA. The protective layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS and / or the pixel circuit layer PCL. The protective layer OC may include various materials suitable for protecting the layers thereunder from foreign matter such as dust or moisture. For example, the protective layer OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the protective layer OC may include an epoxy resin, but the embodiment is not limited thereto. The protective layer OC may have a refractive index lower than that of the lens array LA.

[0144] The cover window CW may be disposed on the protective layer OC. The cover window CW may protect the layers thereunder. The cover window CW may have a refractive index higher than that of the protective layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be encapsulation glass for protecting components disposed thereunder. In other embodiments, the cover window CW may be omitted.

[0145] Figure 6 It is a graphic Figure 5 A schematic plan view of an embodiment of any one of the pixels of FIG. Figure 6 In order to make the description clear and concise, the schematic diagram is shown. Figure 5The first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2 may be configured similarly to the first pixel PXL1.

[0146] refer to Figure 5 and Figure 6 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged or disposed in the first direction DR1.

[0147] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0148] The first emission area EMA1 may be formed from the light emitting structure EMS (refer to Figure 5 ) may be a region where light is emitted from a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1. The second emission region EMA2 may be a region where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission region EMA3 may be a region where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 5 As described above, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0149] Figure 7 The diagram is along Figure 6 A schematic cross-sectional view of an embodiment of a pixel taken along line II'.

[0150] refer to Figure 7 , a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided.

[0151] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0152] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (refer to Figure 2), the transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 , for clarity and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0153] The transistor T_SP1 of the first subpixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0154] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed to be spaced apart from each other in the well WL. A region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0155] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0156] The plurality of layers included in the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers, and such a conductive pattern may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC passing through one or more insulating layers.

[0157] Since the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as any one of the transistors of the first subpixel SP1.

[0158] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured similarly to the transistor T_SP1 of the first subpixel SP1.

[0159] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0160] The via layer VIAL (or base layer) is disposed on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and may have a substantially flat surface. The via layer VIAL may flatten the step difference on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon carbonitride (SiC x N y ), but the embodiment is not limited thereto.

[0161] The light emitting element layer LDL is disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0162] On the via layer VIAL, first to third reflective electrodes RE1 to RE3 are respectively disposed in the first to third subpixels SP1 to SP3. Each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a via hole passing through the via layer VIAL.

[0163] The first to third reflective electrodes RE1 to RE3 may function as a total reflector that reflects light emitted from the light emitting structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom, but the embodiment is not limited thereto.

[0164] In an embodiment, the connection electrode may be disposed under or below each of the first to third reflective electrodes RE1 to RE3. The connection electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (Ti x N y ) and tantalum nitride (Ta x N y ), etc., but the embodiment is not limited thereto. In an embodiment, the corresponding reflective electrode may be located between multiple layers of the connection electrode.

[0165] In order to flatten the step difference between the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may generally cover the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and may have a flat surface. In an embodiment, the planarization layer PLNL may be omitted.

[0166] The first to third anode electrodes AE1 to AE3 respectively overlapping the first to third reflective electrodes RE1 to RE3 are disposed on the planarization layer PLNL. When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may have the same Figure 6 The shapes of the first emission areas EMA1 to the third emission areas EMA3 are similar. The first anode electrode AE1 to the third anode electrode AE3 are respectively connected to the first reflective electrode RE1 to the third reflective electrode RE3. The first anode electrode AE1 may be connected to the first reflective electrode RE1 through the first through hole VIA1 passing through the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 through the second through hole VIA2 passing through the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 through the third through hole VIA3 passing through the planarization layer PLNL.

[0167] In an embodiment, the first to third anode electrodes AE1 to AE3 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0168] The pixel defining layer PDL is disposed on a portion of the first to third anode electrodes AE1 to AE3 and a portion of the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a portion of each of the first to third anode electrodes AE1 to AE3. The opening OP of the pixel defining layer PDL may define an emission region of each of the first to third sub-pixels SP1 to SP3. As described above, the pixel defining layer PDL may be disposed on Figure 6 The non-emitting area NEA is defined Figure 6 The first emission area EMA1 to the third emission area EMA3.

[0169] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL, and may be disposed completely throughout the first to third sub-pixels SP1 to SP3. According to an embodiment, the light emitting structure EMS may be at least partially cut off in a boundary region between the first to third sub-pixels SP1 to SP3. In the case of operating the display panel DP, the current flowing out from each of the first to third sub-pixels SP1 to SP3 to the sub-pixels adjacent thereto through the layers included in the light emitting structure EMS may be reduced. Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0170] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be commonly provided to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0171] The first anode electrode AE1, the portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may form a first light emitting element LD1. The second anode electrode AE2, the portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may form a second light emitting element LD2. The third anode electrode AE3, the portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may form a third light emitting element LD3.

[0172] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE can prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL.

[0173] The optical function layer OFL is disposed on the encapsulation layer TFE. In an embodiment, the optical function layer OFL may be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL may be manufactured separately and attached to the encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may further perform the function of protecting the layer including the lower portion of the encapsulation layer TFE.

[0174] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third subpixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may allow light of different wavelength ranges to pass through. For example, the first to third color filters CF1 to CF3 may allow red light, green light, and blue light to pass through, respectively.

[0175] In an embodiment, the first to third color filters CF1 to CF3 may be formed in the boundary area BDA (refer to Figure 8 In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0176] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third lenses LS1 to LS3 may improve light output efficiency by outputting light emitted from the first to third light emitting elements LD1 to LD3 to a desired path.

[0177] Figure 8 The diagram is along Figure 6 A schematic cross-sectional view of an embodiment of a pixel taken along line II'.

[0178] refer to Figure 7 and Figure 8 , in addition to the buffer pattern BFP and separator SPR, Figure 8 Examples and Figure 7 The embodiments of the present invention are substantially the same or similar. Therefore, repeated descriptions may not be repeated.

[0179] The buffer pattern BFP may be disposed under or below at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may be disposed under or below at least one of the first to third reflective electrodes RE1 to RE3 and may be on the through-hole layer VIAL. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but the embodiment is not limited thereto. The height of the corresponding reflective electrode in the third direction DR3 may be adjusted by disposing the buffer pattern BFP. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the through-hole layer VIAL to adjust the height of the first reflective electrode RE1.

[0180] The first to third reflective electrodes RE1 to RE3 may function as full reflectors, and the cathode electrode CE may function as a half reflector. Light emitted from the light emitting layer of the light emitting structure EMS may be amplified by at least partially reciprocating between the corresponding reflective electrode and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. As described above, the distance between each reflective electrode and the cathode electrode CE may be understood as the resonance distance of light emitted from the light emitting layer of the corresponding light emitting structure EMS.

[0181] Due to the buffer pattern BFP, the first subpixel SP1 can have a resonance distance shorter than the resonance distance of another subpixel. The resonance distance adjusted as described above can allow light of a given wavelength range (e.g., red) to be effectively and efficiently amplified. Accordingly, the first subpixel SP1 can effectively and efficiently output light of the corresponding wavelength range.

[0182] exist Figure 8 In the embodiment, the buffer pattern BFP is provided to the first sub-pixel SP1 and is not provided to the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited thereto. The buffer pattern BFP may also be provided to at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0183] In an embodiment, an insulating layer for adjusting the height of one or more of the first anode electrode AE1 to the third anode electrode AE3 may be further provided. The insulating layer may be disposed between one or more of the first anode electrode AE1 to the third anode electrode AE3 and the corresponding reflective electrode. The planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE.

[0184] The pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x). For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked sequentially, and the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the embodiment is not limited thereto. The first to third inorganic insulating layers may have a step-shaped cross-section in a region adjacent to the opening OP.

[0185] The separator SPR may be provided in the boundary area BDA between adjacent sub-pixels. In other words, the separator SPR may be provided in Figure 4 In each of the boundary regions between the sub-pixels SP.

[0186] The separator SPR may cause discontinuity in forming the light emitting structure EMS at the boundary area BDA. For example, the light emitting structure EMS may be disconnected or bent at the boundary area BDA due to the separator SPR.

[0187] The separator SPR may be provided in or on the pixel defining layer PDL. The pixel defining layer PDL may include one or more trenches TRCH1 and TRCH2 as the separator SPR in the boundary area BDA. Figure 8 As shown in , one or more grooves TRCH1 and TRCH2 may pass through the pixel defining layer PDL and may partially pass through the planarization layer PLNL. In other embodiments, one or more grooves TRCH1 and TRCH2 may pass through the pixel defining layer PDL and the planarization layer PLNL and may partially pass through the via layer VIAL. In other embodiments, one or more grooves TRCH1 and TRCH2 may at least partially pass through the planarization layer PLNL and the via layer VIAL, and a portion of the pixel defining layer PDL may be disposed in one or more grooves TRCH1 and TRCH2.

[0188] For example, two grooves TRCH1 and TRCH2 separated from each other may be provided in the boundary area BDA. For example, the first groove TRCH1 and the second groove TRCH2 may be provided in the boundary area BDA between the second sub-pixel SP2 and the third sub-pixel SP3, the first groove TRCH1 may be provided along the edge of the second sub-pixel SP2, and the second groove TRCH2 may be provided along the edge of the third sub-pixel SP3. In the case where the grooves TRCH1 and TRCH2 are separated from each other, the width of each of the grooves TRCH1 and TRCH2 may remain constant, and the discontinuous portion of the light emitting structure EMS may exist uniformly in the boundary area BDA. In the case where the grooves TRCH1 and TRCH2 are connected, the width of the connected portion of the grooves TRCH1 and TRCH2 may become greater than the width of the other portion, the discontinuous portion of the light emitting structure EMS may become uneven, and the characteristics of the light emitting structure EMS may become uneven.

[0189] exist Figure 8 In the embodiment, two trenches TRCH1 and TRCH2 are provided in the boundary area BDA. However, the embodiment is not limited thereto. For example, the pixel defining layer PDL may include one trench in the boundary area BDA. For example, the pixel defining layer PDL may include three or more trenches in the boundary area BDA.

[0190] Due to the first trench TRCH1 and the second trench TRCH2, in the boundary area BDA, discontinuous portions such as the first void VD1 and the second void VD2 may be formed in the light emitting structure EMS. A portion of a plurality of layers stacked in the light emitting structure EMS may be disconnected or bent by the first void VD1 and the second void VD2. For example, at least one charge generating layer included in the light emitting structure EMS may be disconnected in the first void VD1 and the second void VD2. As described above, a plurality of portions of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3 may be at least partially separated due to the first trench TRCH1 and the second trench TRCH2.

[0191] exist Figure 8 In the boundary area BDA, the first void VD1 and the second void VD2 are formed in the light emitting structure EMS, but this is an example and the embodiment is not limited thereto. For example, in the boundary area BDA, a concave valley may be formed in the light emitting structure EMS. According to the shapes of the first trench TRCH1 and the second trench TRCH2, the discontinuous portion formed in the light emitting structure EMS may be variously changed.

[0192] In an embodiment, within the spirit and scope of the present disclosure, the light emitting structure EMS may be formed by vacuum deposition and inkjet printing, etc. The same material as that of the light emitting structure EMS may be located on the bottom surfaces of the first and second trenches TRCH1 and TRCH2 adjacent to the via layer VIAL.

[0193] The separator SPR may be variously modified and provided so that the light emitting structure EMS may have a discontinuous portion in the boundary area BDA. In an embodiment, in the absence of the first trench TRCH1 and the second trench TRCH2, inorganic insulating patterns stacked one on top of the pixel defining layer PDL may be provided in the boundary area BDA. The width of the topmost inorganic insulating pattern among the additionally stacked inorganic insulating patterns may be greater than the width of the inorganic insulating pattern directly disposed thereunder. For example, in the boundary area BDA, the first to third inorganic insulating patterns may be sequentially stacked from the pixel defining layer PDL, and the topmost third inorganic insulating pattern may have a width greater than the width of the second inorganic insulating pattern. For example, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross-section in the boundary area BDA. Depending on the shape of the pixel defining layer PDL, the plurality of layers included in the light emitting structure EMS may be at least partially disconnected or bent in the boundary area BDA.

[0194] Fig. 9 The diagram is included in Figure 7 A schematic cross-sectional view of an embodiment of a light emitting structure in a pixel of FIG. Fig. 9 Further shown are first to third anode electrodes AE1 to AE3 and a cathode electrode CE.

[0195] refer to Fig. 9 , the light emitting structure EMS may have a series structure in which the first light emitting unit (or portion) EU1 and the second light emitting unit (or portion) EU2 are stacked. In each of the first to third sub-pixels SP1 to SP3, the light emitting structure EMS may be substantially identically or similarly configured.

[0196] Each of the first light emitting unit EU1 and the second light emitting unit EU2 may include at least one light emitting layer that generates light according to an applied current. The first light emitting unit EU1 may include a first light emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light emitting unit EU2 may include a second light emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0197] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and an electron blocking layer, etc., if necessary. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration as or different configurations from each other. The first hole transport unit HTU1 and the second hole transport unit HTU2 may be formed by a deposition process, but are not limited thereto.

[0198] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer, etc., if necessary. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration as or different configurations from each other. The first electron transport unit ETU1 and the second electron transport unit ETU2 may be formed by a deposition process, but are not limited thereto.

[0199] A connection layer, which may be provided in the form of a charge generation layer CGL, may be provided between the first light emitting unit EU1 and the second light emitting unit EU2 to connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other. The charge generation layer CGL may be formed by a deposition process, but is not limited thereto. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, and NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiment is not limited thereto.

[0200] In an embodiment, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color. For example, in the first sub-pixel SP1, each of the first light emitting layer EML1 and the second light emitting layer EML2 may generate red light. In the second sub-pixel SP2, each of the first light emitting layer EML1 and the second light emitting layer EML2 may generate green light. In the third sub-pixel SP3, each of the first light emitting layer EML1 and the second light emitting layer EML2 may generate blue light.

[0201] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors. Light emitted from each of the first light-emitting layer EML1 and the second light-emitting layer EML2 may be mixed and viewed as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. In an embodiment, the second light-emitting layer EML2 may include a structure in which a first sub-light-emitting layer for generating red light and a second sub-light-emitting layer for generating green light may be stacked on each other. Red light and green light may be mixed, and thus yellow light may be provided. The intermediate layer may perform the function of transporting holes and / or blocking the transport of electrons, and may be further disposed between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0202] The first and second light emitting layers EML1 and EML2 may be formed by an inkjet printing method, but the embodiment is not limited thereto.

[0203] Fig.10 The diagram is along Figure 4 Schematic cross-sectional view of an embodiment of a display panel taken along line II-II'. Fig.10 Only part of the structure of the display panel is shown in FIG. Figure 7 and Figure 8 The configuration of the embodiment can be applied to Fig.10 . Fig.11 It is a graphic Figure 4 Schematic plan view of an embodiment of the first zone. Fig.11 The embodiments may be applied not only to the first area A1 located on the right side of the display panel DP but also to other sides (eg, areas on the upper and left sides). Fig. 12A and Fig. 12B The diagram is along Figure 4 Schematic cross-sectional view of an embodiment of a display panel taken along line II-II'.

[0204] refer to Fig.10 and Fig.11 The base layer BS may include a display area DA and a non-display area NDA. The base layer BS may be Figure 7 The through hole layer VIAL is not limited thereto. For example, the base layer BS may be Figure 7 Substrate SUB.

[0205] The light emitting element layer (or light emitting structure) is disposed on the base layer BS. The light emitting element layer may include a first light emitting unit EU1, a charge generation layer CGL, and a second light emitting unit EU2.

[0206] The first light emitting unit EU1 is disposed on the base layer BS. The first light emitting unit EU1 may include an organic pattern OLP (or a patterned organic layer) that emits light. Each of the organic patterns OLP of the first light emitting unit EU1 may include Fig. 9 The first light emitting layer EML1, the first electron transport unit ETU1 and the first hole transport unit HTU1 are formed.

[0207] The organic pattern OLP of the first light emitting unit EU1 may generate light of different colors. For example, the first organic pattern OLP1 may generate red light, the second organic pattern OLP2 may generate green light, and the third organic pattern OLP3 may generate blue light. However, the embodiment is not limited thereto. The organic pattern OLP of the first light emitting unit EU1 may be formed by an inkjet printing method using a fine metal mask, but is not limited thereto.

[0208] The first light emitting unit EU1 may be disposed in the display area DA (refer to Fig.14 According to an embodiment, the first light emitting unit EU1 may be further disposed in a portion of the non-display area NDA adjacent to an edge of the display area DA.

[0209] As reference Figure 7 As described above, the first to third anode electrodes AE1 to AE3 may be disposed on the base layer BS (or the through hole layer VIAL), and the pixel defining layer PDL may cover the base layer BS and the first to third anode electrodes AE1 to AE3. Fig.11 As shown in , in the display area DA, an opening OP exposing the first to third anode electrodes AE1 to AE3 may be formed in the pixel defining layer PDL. The first light emitting unit EU1 may be disposed on the pixel defining layer PDL, and may contact or be connected to the first to third anode electrodes AE1 to AE3 through the opening OP. Therefore, in the display area DA, the first light emitting unit EU1 may normally emit light. The opening OP of the pixel defining layer PDL is not formed in the non-display area NDA, and therefore, even if the first light emitting unit EU1 is disposed in the non-display area NDA, the first light emitting unit EU1 in the non-display area NDA does not emit light.

[0210] The charge generation layer CGL is disposed on the first light emitting unit EU1.

[0211] In an embodiment, the charge generation layer CGL may also be disposed in the non-display area NDA. Fig.10, the charge generation layer CGL may be formed up to a first point X1 located outside the reference point X0 (which is the edge of the display area DA). For example, a distance D1 between the reference point X0 and the first point X1 may be about 50 μm or more. In other words, based on the shortest path from the display area DA to the edge of the base layer BS in a plan view, the charge generation layer CGL may extend from the edge of the display area DA to the non-display area NDA by about 50 μm or more (e.g., X1>X0+50 μm).

[0212] exist Fig.10 In the embodiment, the end of the charge generation layer CGL is aligned with the end of the first light emitting unit EU1, but the present disclosure is not limited thereto. For example, the end of the charge generation layer CGL and the end of the first light emitting unit EU1 may not be aligned, and the end of the charge generation layer CGL may be located outside or inside compared to the end of the first light emitting unit EU1.

[0213] The second light emitting unit EU2 is disposed on the charge generation layer CGL.

[0214] In an embodiment, the second light emitting unit EU2 may cover the charge generation layer CGL. Fig.10 , the second light emitting unit EU2 may be formed up to a second point X2 located outside the first point X1. For example, a distance D2 between the first point X1 and the second point X2 may be about 200 μm or less. In other words, based on the shortest path from the display area DA to the edge of the base layer BS in a plan view, the second light emitting unit EU2 may extend beyond the charge generation layer CGL and may extend toward the edge of the base layer BS by less than about 200 μm (X1 <X2<X1+200μm)。

[0215] In an embodiment, the second light emitting unit EU2 may include an organic pattern OLP (or a patterned organic layer) and a dummy pattern DOLP (or a dummy organic pattern).

[0216] The organic patterns OLP of the second light emitting unit EU2 may be located in the display area DA and may emit light. Each of the organic patterns OLP of the second light emitting unit EU2 may include Fig. 9 The second light emitting layer EML2, the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0217] The organic pattern OLP of the second light emitting unit EU2 may generate light of different colors.

[0218] According to an embodiment, the organic pattern OLP of the second light emitting unit EU2 and the organic pattern OLP of the first light emitting unit EU1 that overlap each other may emit light of the same color. For example, the first organic pattern OLP1 of the second light emitting unit EU2 may generate red light, the second organic pattern OLP2 of the second light emitting unit EU2 may generate green light, and the third organic pattern OLP3 of the second light emitting unit EU2 may generate blue light. However, the embodiment is not limited thereto. The organic pattern OLP of the second light emitting unit EU2 may be formed by an inkjet printing method using a fine metal mask (FMM), but is not limited thereto.

[0219] The dummy pattern DOLP may be located in the non-display area NDA. The dummy pattern DOLP may have a structure and a size corresponding to the organic pattern OLP of the second light emitting unit EU2.

[0220] In an embodiment, at least a portion of the dummy pattern DOLP may have the same stacking structure as the stacking structure of the organic pattern OLP of the second light emitting unit EU2. For example, the dummy pattern DOLP may include Fig. 9 The second light emitting layer EML2, the second electron transport unit ETU2 and the second hole transport unit HTU2 may be provided. For example, the first dummy pattern DOLP1 may have the same stacking structure as the first organic pattern OLP1, the second dummy pattern DOLP2 may have the same stacking structure as the second organic pattern OLP2, and the third dummy pattern DOLP3 may have the same stacking structure as the third organic pattern OLP3. However, the present disclosure is not limited thereto.

[0221] In an embodiment, at least a portion of the dummy pattern DOLP may have a stacking structure different from the stacking structure of the organic pattern OLP of the second light emitting unit EU2. For example, the organic pattern OLP of the second light emitting unit EU2 may include Fig. 9 The second light emitting layer EML2, the second electron transport unit ETU2, and the second hole transport unit HTU2 may be formed in the dummy pattern DOLP, and at least a portion of the dummy pattern DOLP may include only a portion of the second light emitting layer EML2, the second electron transport unit ETU2, and the second hole transport unit HTU2.

[0222] For example, Fig. 12A As shown in , at least a portion of the dummy pattern DOLP may include only the second light emitting layer EML2. Fig. 12B As shown in , at least a portion of the dummy pattern DOLP may include only the second hole transport unit HTU2 (or hole transport layer). Fig. 12A and Fig. 12BIn the embodiment, between the reference point X0 and the first point X1, the dummy pattern DOLP has the same stacking structure as the stacking structure of the organic pattern OLP of the second light emitting unit EU2, but is not limited thereto. Fig. 12A and Fig. 12B In the embodiment, between the reference point X0 and the first point X1, the dummy pattern DOLP may include only the second light emitting layer EML2 or the second hole transport unit HTU2.

[0223] The dummy pattern DOLP may be formed by the same process as that of the organic pattern OLP of the second light emitting unit EU2. For example, the dummy pattern DOLP may be formed by an inkjet printing method using FMM, but is not limited thereto.

[0224] In an embodiment, the average size of the dummy pattern DOLP may be greater than or equal to the average size of the organic pattern OLP of the second light emitting unit EU2. In a plan view, adjacent dummy patterns DOLP may partially overlap each other and may completely cover the charge generation layer CGL in the non-display area NDA.

[0225] For example, the width S2 of the first dummy pattern DOLP1 may be equal to the width S1 of the first organic pattern OLP1. As an embodiment, the width S2 of the first dummy pattern DOLP1 may be greater than the width S1 of the first organic pattern OLP1. Similarly, the width of the second dummy pattern DOLP2 may be greater than or equal to the width of the second organic pattern OLP2, and the width of the third dummy pattern DOLP3 may be greater than or equal to the width of the third organic pattern OLP3.

[0226] For reference, adjacent organic patterns OLP among the first organic pattern OLP1, the second organic pattern OLP2, and the third organic pattern OLP3 may partially overlap each other, or may not partially overlap each other. Due to process errors, adjacent organic patterns OLP among the first organic pattern OLP1, the second organic pattern OLP2, and the third organic pattern OLP3 may not overlap and may be spaced apart from each other. The dummy patterns DOLP may need to overlap each other so as to completely cover the charge generation layer CGL. To this end, the average size of the dummy pattern DOLP may be greater than the average size of the organic pattern OLP.

[0227] The cathode electrode CE is disposed on the second light emitting unit EU2. The cathode electrode CE may cover the second light emitting unit EU2. Fig.10 , the cathode electrode CE may be formed up to a third point X3 located outside the second point X2.

[0228] In the non-display area NDA, the cathode electrode CE and the charge generation layer CGL may be separated (or physically separated) by the second light emitting unit EU2 (or the dummy pattern DOLP). Since the charge generation layer CGL is completely covered by the second light emitting unit EU2, the cathode electrode CE and the charge generation layer CGL may be spaced apart from each other. Therefore, a short circuit between the cathode electrode CE and the charge generation layer CGL may be prevented.

[0229] For reference, in the case where the second light-emitting unit EU2 does not cover the charge generation layer CGL, the end of the charge generation layer CGL may be exposed in the non-display area NDA, and the end of the charge generation layer CGL may contact the cathode electrode CE. A drop (e.g., a voltage drop) may occur in the power voltage applied to the cathode electrode CE, and the reliability of the display device may be reduced. In order to prevent this, the charge generation layer CGL may be located on the inner side compared to the first light-emitting unit EU1 and the second light-emitting unit EU2, but due to product specifications (e.g., distance D1), the display area DA may be reduced and the non-display area NDA (or dead zone) may be increased. In view of this, only the second light-emitting unit EU2 according to the embodiment may be extended to cover the charge generation layer CGL, and the second light-emitting unit EU2 may prevent a short circuit between the charge generation layer CGL and the cathode electrode CE and may minimize the increase of the non-display area NDA.

[0230] The encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE may cover the cathode electrode CE.

[0231] As described above, in addition to the organic pattern OLP of the display area DA, the second light emitting unit EU2 may further include a dummy pattern DOLP in the non-display area NDA, and the dummy pattern DOLP may completely cover the charge generation layer CGL in the non-display area NDA. Therefore, in the non-display area NDA, the cathode electrode CE and the charge generation layer CGL may be separated (or physically separated) by the dummy pattern DOLP, a short circuit between the cathode electrode CE and the charge generation layer CGL may be prevented, and the reliability of the display device may be improved.

[0232] Fig.13 The diagram is along Figure 4 Schematic cross-sectional view of an embodiment of a display panel taken along line II-II'. Fig.13 Only part of the structure of the display panel is shown in FIG. Figure 7 and Figure 8 The configuration of the embodiment can be applied to Fig.13 . Fig.14 It is a graphic Figure 4 Schematic plan view of an embodiment of the first zone. Fig.14The embodiments may be applied not only to the first area A1 located on the right side of the display panel DP but also to other sides (eg, areas on the upper and left sides). Fig.15 The diagram is along Figure 4 Schematic cross-sectional view of an embodiment of a display panel taken along line II-II'. Fig.16 is a diagram illustrating a deposition process.

[0233] refer to Fig.13 and Fig.14 The light emitting element layer (or light emitting structure) is disposed on the base layer BS. The light emitting element layer may include a first light emitting unit EU1, a charge generating layer CGL and a second light emitting unit EU2.

[0234] The first light emitting unit EU1 is disposed on the base layer BS. The first light emitting unit EU1 may also be disposed in the non-display area NDA. Fig.13 , the first light emitting unit EU1 may be formed up to a first point X1 located outside the reference point X0 (which is the edge of the display area DA).

[0235] The first light emitting unit EU1 may include Fig. 9 The first light emitting layer EML1, the first electron transport unit ETU1 (or electron transport unit ETU) and the first hole transport unit HTU1 (or hole transport unit HTU) are provided, and the first light emitting layer EML1 may be provided only in the display area DA. Fig.11 As described above, in the display area DA, an opening OP may be formed in the pixel defining layer PDL, and the organic pattern OLP of the first light emitting layer EML1 (or the first to third organic patterns OLP1 to OLP3) may contact or be connected to a lower structure (e.g., an anode electrode) through the opening OP. The first light emitting layer EML1 (or the organic pattern OLP) is not disposed in the non-display area NDA. However, the present disclosure is not limited thereto.

[0236] In the non-display area NDA, as the distance from the display area DA increases, the thickness of the first light emitting unit EU1 may decrease or become thinner.

[0237] For example, the first hole transport unit HTU1 (and the first electron transport unit ETU1) of the first light emitting unit EU1 may be formed by using Fig.16 A mask MASK (or opening mask) is formed by a deposition process.

[0238] The mask MASK may include an opening corresponding to the display area DA, and a material supplied from a deposition source SOURCE may be deposited in the display area DA to form a corresponding layer (e.g., a first hole transport unit HTU1). The mask MASK may include a half-etched area in the non-display area NDA, and in the half-etched area, the mask MASK may be spaced apart from the base layer BS by a given gap G1. For example, the mask MASK may have a reference thickness T0, and may have a thickness reduced by a given gap G1 in the half-etched area.

[0239] The deposition shadow is generated by the half-etched area of ​​the mask MASK, and the corresponding layer (e.g., the first hole transport unit HTU1) may also be deposited in the non-display area NDA, and the thickness of the corresponding layer (e.g., the first hole transport unit HTU1) may become thinner as the distance from the opening (or display area DA) increases. The width W_S (or amplitude) of the deposition shadow may be determined by the reference thickness T0 of the mask MASK and the gap G1 in the half-etched area.

[0240] The charge generation layer CGL is disposed on the first light emitting unit EU1. The charge generation layer CGL may also be disposed in the non-display area NDA. In the non-display area NDA, as the distance from the display area DA increases, the thickness of the charge generation layer CGL may decrease or become thinner. The charge generation layer CGL may be formed by Fig.16 formed by a deposition process.

[0241] In an embodiment, Fig.13 As shown in FIG. 1 , the charge generation layer CGL may be formed only up to the fourth point X4 located inside the first point X1. For example, by reducing the charge generation layer CGL as compared to the case of forming the first light emitting unit EU1. Fig.16 The charge generation layer CGL may be formed only up to the fourth point X4. For example, the distance D4 between the fourth point X4 and the reference point X0 which is the edge of the display area DA may be about 50% or less of the distance D1 between the reference point X0 and the first point X1. Fig.13 In the embodiment of FIG. 1 , the distance D1 to the first point X1 may be about 100 μm to about 500 μm.

[0242] In other words, based on the shortest path from the display area DA to the edge of the base layer BS in a plan view, the charge generation layer CGL may extend from the edge of the display area DA by approximately 50% or less than the first light emitting unit EU1, and the first light emitting unit EU1 may further extend from the edge of the display area DA by approximately 100 μm to approximately 500 μm.

[0243] In an embodiment, the reduction rate of the thickness of the charge generation layer CGL according to the distance from the edge of the display area DA may be greater than the reduction rate of the thickness of the first light emitting unit EU1. Here, the reduction rate may mean a ratio (e.g., reduction rate) of the thickness at a given position based on the thickness of the reference point X0. For example, in the case where the distance D4 between the reference point X0 and the fourth point X4 is about half of the distance D1 between the reference point X0 and the first point X1, the reduction rate of the thickness of the charge generation layer CGL may be about twice the reduction rate of the thickness of the first light emitting unit EU1.

[0244] The second light emitting unit EU2 is disposed on the charge generating layer CGL. The second light emitting unit EU2 may cover the charge generating layer CGL. The second light emitting unit EU2 may completely cover the charge generating layer CGL. Fig.14 As shown in , in a plan view, each of the second light emitting unit EU2 and the first light emitting unit EU1 may cover the charge generation layer CGL. The second light emitting unit EU2 may be formed up to the first point X1. In the case where each of the second light emitting unit EU2 and the first light emitting unit EU1 is formed using the same mask MASK, an end of the second light emitting unit EU2 may coincide with or be aligned with an end of the first light emitting unit EU1.

[0245] The second light emitting unit EU2 may include Fig. 9 The second light-emitting layer EML2, the second electron transport unit ETU2 (or the electron transport unit ETU), and the second hole transport unit HTU2 (or the hole transport unit HTU), and the second light-emitting layer EML2 (or the organic pattern OLP of the second light-emitting layer EML2) may be disposed only in the display area DA. The second light-emitting layer EML2 (or the organic pattern OLP) is not disposed in the non-display area NDA. However, the present disclosure is not limited thereto.

[0246] In the non-display area NDA, as the distance from the display area DA increases, the thickness of the second light emitting unit EU2 may decrease or become thinner. In the case where each of the second light emitting unit EU2 and the first light emitting unit EU1 is formed using the same mask MASK, the end of the second light emitting unit EU2 may coincide with or align with the end of the first light emitting unit EU1. The reduction rate of the thickness of the second light emitting unit EU2 according to the distance from the edge of the display area DA may be less than the reduction rate of the thickness of the charge generation layer CGL. For example, the reduction rate of the thickness of the second light emitting unit EU2 may be substantially the same as the reduction rate of the thickness of the first light emitting unit EU1.

[0247] The cathode electrode CE is disposed on the second light emitting unit EU2. The cathode electrode CE may cover the second light emitting unit EU2. For example, the cathode electrode CE may be formed up to a third point X3 located outside the second point X2.

[0248] In the non-display area NDA, the cathode electrode CE and the charge generation layer CGL may be separated (or physically separated) by the second light emitting unit EU2. Since the charge generation layer CGL is completely covered by the second light emitting unit EU2, the cathode electrode CE and the charge generation layer CGL may be spaced apart from each other. Therefore, a short circuit between the cathode electrode CE and the charge generation layer CGL may be prevented.

[0249] In an embodiment, the charge generation layer CGL may include a first charge generation layer CGL1 and a second charge generation layer CGL2 sequentially stacked between the first light emitting unit EU1 and the second light emitting unit EU2, and one of the first charge generation layer CGL1 and the second charge generation layer CGL2 may be located inside relative to the other. For example, the first charge generation layer CGL1 may be an n-dopant layer including an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof, and the second charge generation layer CGL2 may be a p-dopant layer including a p-type dopant such as HAT-CN, TCNQ, and NDP-9. For example, referring to Fig.15 , the second charge generation layer CGL2 may be located at the inner side compared to the first charge generation layer CGL1. For example, a reduction rate of the thickness of the second charge generation layer CGL2 according to the distance from the edge of the display area DA may be greater than a reduction rate of the thickness of the first charge generation layer CGL1. In the non-display area NDA, the cathode electrode CE and the second charge generation layer CGL2 may be separated (or physically separated) by the second light emitting unit EU2, and a short circuit between the cathode electrode CE and the second charge generation layer CGL2 may be prevented.

[0250] As described above, the thickness of each of the first light emitting unit EU1, the charge generation layer CGL, and the second light emitting unit EU2 may decrease or become thinner as the distance from the display area DA increases, and the reduction rate of the thickness of the charge generation layer CGL according to the distance from the edge of the display area DA may be greater than the reduction rate of the thickness of the second light emitting unit EU2. The second light emitting unit EU2 may completely cover the charge generation layer CGL in the non-display area NDA. Therefore, in the non-display area NDA, the cathode electrode CE and the charge generation layer CGL may be separated (or physically separated) by the second light emitting unit EU2, a short circuit between the cathode electrode CE and the charge generation layer CGL may be prevented, and the reliability of the display device may be improved.

[0251] Fig.10 The embodiments can be applied to Figures 13 to 15 For example, in Figures 13 to 15 In the embodiment of the present invention, the second light emitting unit EU2 may include a dummy pattern DOLP (refer to Fig.10 ).

[0252] Fig.17is a block diagram illustrating an embodiment of a display system.

[0253] refer to Fig.17 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0254] The processor 1100 may perform various tasks and calculations. In an embodiment, within the spirit and scope of the present disclosure, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system and may control the other components.

[0255] exist Fig.17 In the embodiment, the display system 1000 may include a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0256] Through the first channel CH1, the processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The display device 100 described above is similarly constructed. The first image data IMG1 and the first control signal CTRL1 may be respectively used as Figure 1 Input image data IMG and a control signal CTRL are provided.

[0257] Through the second channel CH2, the processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display device 100 described above is similarly constructed. The second image data IMG2 and the second control signal CTRL2 may be respectively used as Figure 1 Input image data IMG and a control signal CTRL are provided.

[0258] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, and an ultra mobile personal computer (UMPC). The display system 1000 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0259] Fig.18 It is a graphic Fig.17 A perspective view of an example application of the display system.

[0260] refer to Fig.18 , Fig.17 The display system 1000 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that may be worn on a user's head.

[0261] The head-mounted display device 2000 may include a head-mounted strap 2100 and a display device housing 2200. The head-mounted strap 2100 may be connected to the display device housing 2200. The head-mounted strap 2100 may include a horizontal strap and / or a vertical strap for fixing the head-mounted display device 2000 to the user's head. The horizontal strap may surround the side of the user's head, and the vertical strap may surround the upper part of the user's head. However, the embodiment is not limited thereto. For example, within the spirit and scope of the present disclosure, the head-mounted strap 2100 may be implemented in the form of a glasses frame or a helmet, etc.

[0262] The display device receiving housing 2200 can receive Fig.17 The first display device 1210 and the second display device 1220. The display device receiving housing 2200 may further receive Fig.17 Processor 1100.

[0263] Fig.19 It is a graphic Fig.18 Illustration of a head mounted display device worn by a user.

[0264] refer to Fig.19 The head mounted display device 2000 (or wearable electronic device) may include a display panel emitting light and a lens unit disposed on the display panel (or on the emission path of light). The display panel may include a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220. The lens unit may include one or more lenses LLNS and RLNS.

[0265] The right-eye lens RLNS may be disposed between the first display panel DP1 and the right eye of the user in the display device accommodating housing 2200. The left-eye lens LLNS may be disposed between the second display panel DP2 and the left eye of the user in the display device accommodating housing 2200.

[0266] The image output from the first display panel DP1 may be displayed to the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract the light from the first display panel DP1 to direct it to the right eye of the user. The right eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the right eye of the user.

[0267] The image output from the second display panel DP2 may be displayed to the left eye of the user through the left eye lens LLNS. The left eye lens LLNS may refract the light from the second display panel DP2 to direct it to the left eye of the user. The left eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the left eye of the user.

[0268] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a flat cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. Each display panel may output images corresponding to the sub-regions of the multi-channel lens, respectively, and the output images may pass through the respective corresponding sub-regions and may be viewed by a user.

[0269] Although embodiments and examples are described herein, other embodiments and modifications may be derived from the above description. Therefore, the spirit of the present disclosure is not limited to such embodiments, but extends to the scope of the claims, various obvious modifications and equivalents.

Claims

1. A display device, comprising: Display area and non-display area; basal layer; as well as The light emitting element layer is disposed on the base layer, wherein: The light emitting element layer comprises: a first light emitting portion including a first organic pattern that emits light; a charge generation layer disposed on the first light emitting portion; and a second light emitting portion disposed on the charge generating layer, In a plan view, the second light emitting portion covers the charge generating layer, and The second light emitting portion includes a second organic pattern disposed in the display area and a dummy pattern disposed in the non-display area, the second organic pattern emitting light.

2. The display device according to claim 1, wherein: In the shortest path from the display area to the edge of the base layer, the charge generation layer extends from the edge of the display area toward the non-display area by 50 μm or more in the plan view.

3. The display device according to claim 2, wherein: In the shortest path from the display area to the edge of the base layer, the second light emitting portion extends less than 200 μm toward the edge of the base layer than the charge generating layer in the plan view.

4. The display device according to claim 1, wherein: An average size of the dummy patterns is greater than or equal to an average size of the second organic patterns.

5. The display device according to claim 4, wherein: In the plan view, the dummy patterns partially overlap each other and completely cover the charge generation layer in the non-display area.

6. The display device according to claim 1, wherein: The second organic pattern and the dummy pattern have the same stacking structure.

7. The display device according to claim 1, wherein: The dummy pattern and the second organic pattern have different stack structures.

8. The display device according to claim 7, wherein: The second organic pattern includes a hole transport layer and a light emitting layer disposed on the hole transport layer, and The dummy pattern includes the hole transport layer or the light emitting layer.

9. The display device according to claim 1, further comprising: A cathode electrode is disposed on the light emitting element layer, wherein: The cathode electrode covers the second light emitting portion, and The charge generation layer and the cathode electrode are separated by the second light emitting portion.

10. The display device according to claim 1, wherein: The light emitting element layer further comprises: an anode electrode, disposed on the substrate layer; and a pixel defining layer, covering the base layer and the anode electrode, The pixel defining layer includes an opening in the display area exposing the anode electrode, The opening is not disposed in the non-display area, and The first light emitting portion is disposed on the pixel defining layer and is electrically connected to the anode electrode through the opening.

11. The display device according to any one of claims 1 to 10, wherein: Organic patterns overlapping each other among the first organic patterns and the second organic patterns in the plan view emit light of the same color.

12. A display device, comprising: Display area and non-display area; basal layer; as well as The light emitting element layer is disposed on the base layer, wherein: The light emitting element layer comprises: A first light emitting portion that emits light; a charge generation layer disposed on the first light emitting portion; and a second light emitting portion disposed on the charge generating layer and emitting light, In the non-display area, the thickness of each of the first light emitting portion, the charge generation layer, and the second light emitting portion becomes thinner as the distance from the display area increases, and The second light emitting portion covers the charge generating layer in a plan view.

13. The display device according to claim 12, wherein: In the shortest path from the display area to the edge of the base layer, the charge generation layer extends from the edge of the display area by 50% or less than the first light emitting portion or the second light emitting portion in the plan view.

14. The display device according to claim 13, wherein: In the shortest path from the display area to the edge of the base layer, each of the first light emitting portion and the second light emitting portion further expands within a range of 100 μm to 500 μm from the edge of the display area in the plan view.

15. The display device according to claim 12, wherein: A reduction rate of the thickness of the charge generation layer according to a distance from an edge of the display area is greater than a reduction rate of the thickness of the first light emitting portion.

16. The display device according to any one of claims 12 to 15, wherein: Each of the first light emitting portion and the second light emitting portion includes an organic pattern that emits light, and The organic pattern is disposed in the display area and is not disposed in the non-display area.

17. The display device according to claim 12, wherein: The charge generation layer includes a first charge generation layer and a second charge generation layer sequentially stacked between the first light emitting portion and the second light emitting portion, and The second charge generation layer is disposed on the inner side of the first charge generation layer.

18. The display device according to claim 17, wherein: A reduction rate of a thickness of the second charge generation layer according to a distance from an edge of the display region is greater than a reduction rate of a thickness of the first charge generation layer.

19. The display device according to claim 12, further comprising: A cathode electrode is disposed on the light emitting element layer, wherein: The cathode electrode covers the second light emitting portion, and The charge generation layer and the cathode electrode are separated by the second light emitting portion.

20. A wearable electronic device comprising: A display panel, emitting light; as well as At least one lens is disposed on the display panel, wherein: The display panel comprises: Display area and non-display area; basal layer; and A light emitting element layer is disposed on the base layer. The light emitting element layer comprises: a first light emitting portion including a first organic pattern that emits light; a charge generation layer disposed on the first light emitting portion; and a second light emitting portion disposed on the charge generating layer, In a plan view, the second light emitting portion covers the charge generating layer, and The second light emitting portion includes a second organic pattern disposed in the display area and emitting light, and a dummy pattern disposed in the non-display area.

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