Display device

Abstract

The invention provides a display device. A display device according to an embodiment includes: a substrate; a plurality of pixels disposed in the display area on the substrate; and a data signal line supplying a data signal to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit composed of a plurality of transistors, and a light emitting element driven by the pixel circuit. The pixel circuit drives the light-emitting element such that the light-emitting element emits light in a time-sharing manner. A first transistor connected to a data signal line among a plurality of transistors constituting a pixel circuit is an oxide transistor.

Description

[0001] This application is based on Japanese Patent Application No. 2023-185593 (filing date: October 30, 2023) and claims priority from the present application, and the present application incorporates all the contents of the application by reference. Technical Field

[0002] Embodiments of the present invention relate to a display device. Background Art

[0003] In recent years, display devices using organic light emitting diodes (OLEDs), which are light emitting elements that function as display elements, have been put into practical use.

[0004] In such a display device, a light emitting element is driven by a pixel circuit. However, the display quality of the display device may be degraded due to differences in the circuit configuration of the pixel circuit. Summary of the invention

[0005] An object of the present invention is to provide a display device capable of suppressing a decrease in display quality.

[0006] A display device of an embodiment includes: a substrate; a plurality of pixels arranged in a display area on the substrate; and a data signal line for supplying a data signal to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit composed of a plurality of transistors and a light-emitting element driven by the pixel circuit. The pixel circuit drives the light-emitting element so that the light-emitting element emits light in a time-sharing manner. The first transistor connected to the data signal line among the plurality of transistors constituting the pixel circuit is an oxide transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a diagram showing a configuration example of a display device according to an embodiment.

[0008] Figure 2 A diagram showing an example of a layout of a plurality of sub-pixels included in a pixel.

[0009] Figure 3 FIG. 2 is a diagram showing another example of the layout of a plurality of sub-pixels included in a pixel.

[0010] Figure 4 It is along Figure 2 A schematic cross-sectional view of the display device taken along line AA in FIG.

[0011] Figure 5 It is a schematic enlarged cross-sectional view of the partition wall.

[0012] Figure 6 This is a schematic cross-sectional view for explaining a light-emitting element formed using partition walls.

[0013] Figure 7 This is a schematic cross-sectional view for explaining a light-emitting element formed using partition walls.

[0014] Figure 8 This is a schematic cross-sectional view for explaining a light-emitting element formed using partition walls.

[0015] Fig. 9 This is a diagram for explaining an example of a circuit configuration of a pixel circuit.

[0016] Fig.10 This is a diagram showing an overview of PWM driving.

[0017] Fig.11 This is a diagram for explaining the operation of the pixel circuit during PWM driving.

[0018] Fig.12 This is a diagram for explaining the display quality of a display device to which PWM driving is applied.

[0019] Fig.13 It is a diagram for explaining a region where ghosting occurs.

[0020] Fig.14 A diagram showing an example of a layout of a pixel circuit.

[0021] The reference numerals are described as follows:

[0022] DSP display device, DA display area, NDA non-display area, PX pixel,

[0023] SP, SP1, SP2, SP3 sub-pixel, AP, AP1, AP2, AP3 opening, LE, LE1,

[0024] LE2, LE3 lower electrode, UE, UE1, UE2, UE3 upper electrode, OR, OR1, OR2,

[0025] OR3 organic layer, SE, SE1, SE2, SE3 sealing layer, Tr1 to Tr7 transistors, Cst holding capacitor, 5 rib, 6 partition wall, 10 substrate, 11 insulating layer, 12 circuit layer, 13 insulating layer, 14 resin layer, 15 sealing layer, 16 resin layer, 20 light emitting element, 61 lower part, 62 upper part, 100 pixel circuit DETAILED DESCRIPTION

[0026] An embodiment will be described with reference to the drawings.

[0027] The present disclosure is only an example, and appropriate changes that maintain the main purpose of the invention and that are easily conceivable by those skilled in the art are of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part of the drawings are sometimes schematically shown compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same figure mark is sometimes used to mark the constituent elements that perform the same or similar functions as the constituent elements described in the drawings that appeared in the previous text, and repeated detailed descriptions are appropriately omitted.

[0028] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are described as needed for ease of understanding. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. In addition, observing various elements parallel to the third direction Z is referred to as a top view.

[0029] The display device of this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element (light emitting element), and is mounted on a television, a notebook computer, a portable terminal, a mobile phone, and the like.

[0030] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the present embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0031] In the present embodiment, the shape of the substrate 10 in plan view is a rectangle, but the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0032] The display area DA includes a plurality of pixels PX arranged (configured) in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the plurality of sub-pixels SP include a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. It should be noted that the plurality of sub-pixels SP may include sub-pixels of other colors such as white together with the sub-pixels SP1, SP2, and SP3. In addition, the plurality of sub-pixels SP may also include sub-pixels of other colors instead of any one of the sub-pixels SP1, SP2, and SP3.

[0033] It should be noted that, as will be described in detail later, each of the plurality of sub-pixels SP includes a pixel circuit and a light-emitting element driven by the pixel circuit. The pixel circuit is composed of, for example, a plurality of transistors (switching elements composed of thin film transistors). The light-emitting element is the above-mentioned organic light-emitting diode. For example, the sub-pixel SP1 has a light-emitting element that emits light in a red wavelength range, the sub-pixel SP2 has a light-emitting element that emits light in a green wavelength range, and the sub-pixel SP3 has a light-emitting element that emits light in a blue wavelength range.

[0034] Figure 2 An example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in a pixel PX is shown. Here, four pixels PX will be described.

[0035] The sub-pixels SP1, SP2, and SP3 constituting one pixel PX are respectively formed in a substantially rectangular shape extending in the second direction Y, and are arranged in the first direction X. If the two pixels PX arranged in the first direction X are focused on, the colors displayed in the sub-pixels SP adjacent to each other in the first direction X are different from each other. In addition, if the two pixels PX arranged in the second direction Y are focused on, the colors displayed in the sub-pixels SP adjacent to each other in the second direction Y are the same. It should be noted that the area of ​​each of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0036] Figure 3 Another example of the layout of the plurality of sub-pixels SP ( SP1 , SP2 , and SP3 ) included in the pixel PX is shown.

[0037] Sub-pixels SP1 and SP2 constituting one pixel PX are arranged in the second direction Y, sub-pixels SP1 and SP3 are arranged in the first direction X, and sub-pixels SP2 and SP3 are arranged in the first direction X. Sub-pixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and sub-pixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of ​​sub-pixel SP2 is larger than that of sub-pixel SP1, and the area of ​​sub-pixel SP3 is larger than that of sub-pixel SP2. It should be noted that the shape and area of ​​sub-pixel SP1 may be the same as those of sub-pixel SP2.

[0038] If the focus is on two pixels PX arranged in the first direction X, in the region where sub-pixels SP1 and SP3 are alternately arranged, and in the region where sub-pixels SP2 and SP3 are alternately arranged, the colors displayed in the sub-pixels SP adjacent to each other in the first direction X are different from each other. On the other hand, if the focus is on two pixels PX arranged in the second direction Y, in the region where sub-pixels SP1 and SP2 are alternately arranged, the colors displayed in the sub-pixels SP adjacent to each other in the second direction Y are different from each other. In addition, in the region where a plurality of sub-pixels SP3 are arranged, the colors displayed in the sub-pixels SP adjacent to each other in the second direction are the same.

[0039] It should be noted that Figure 2 as well as Figure 3 The outer shapes of the sub-pixels SP1, SP2, and SP3 shown correspond to the outer shapes of the regions displaying colors (that is, light-emitting regions) in the sub-pixels SP, but the outer shapes are shown in a simplified manner and do not necessarily reflect the actual shapes.

[0040] Here, the display area DA in the present embodiment is provided with ribs and partitions, the details of which will be described later. The ribs have openings in the sub-pixels SP1, SP2, and SP3, respectively. The partitions are provided at the boundaries of adjacent sub-pixels SP, and overlap with the ribs when viewed from above. Specifically, the partitions are provided between the adjacent openings (sub-pixels SP) in the first direction X, and between the adjacent openings (sub-pixels SP) in the second direction Y. Thus, the partitions as a whole have a lattice shape formed in a manner of dividing the sub-pixels SP1, SP2, and SP3. In other words, the partitions, like the ribs, can also be said to have openings in the sub-pixels SP1, SP2, and SP3.

[0041] Figure 4 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AA in FIG. In the display device DSP, an insulating layer 11 called a primer layer is disposed on a light-transmitting substrate 10 such as glass (on the side where the light-emitting element is disposed).

[0042] The insulating layer 11 has a three-layer stacked structure including, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). It should be noted that the insulating layer 11 is not limited to a three-layer stacked structure. The insulating layer 11 may have a stacked structure having more than three layers, or may have a single-layer structure or a two-layer stacked structure.

[0043] The circuit layer 12 is disposed on the insulating layer 11 . The circuit layer 12 has a pixel circuit (various circuits and wirings) for driving the light-emitting element included in each of the sub-pixels SP1 , SP2 , and SP3 as described above. The circuit layer 12 is covered with the insulating layer 13 .

[0044] The insulating layer 13 functions as a planarizing film that planarizes the unevenness generated by the circuit layer 12. Figure 4 Although not shown in the figure, a contact hole for connecting the lower electrode LE to the pixel circuit is provided in the insulating layer 13 .

[0045] The lower electrodes LE (LE1, LE2, and LE3) are arranged on the insulating layer 13. The ribs 5 are arranged on the insulating layer 13 and the lower electrodes LE. The end portions (parts) of the lower electrodes LE are covered by the ribs 5.

[0046] The partition wall 6 has a lower portion 61 disposed on the rib 5, and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a greater width than the lower portion 61 in the first direction X and the second direction Y. Thus, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. This shape of the partition wall 6 can be called an overhanging shape.

[0047] The organic layer OR (OR1, OR2, and OR3) and the upper electrodes UE (UE1, UE2, and UE3) together with the lower electrodes LE (LE1, LE2, and LE3) constitute a light emitting element included in the sub-pixel SP.

[0048] like Figure 4 As shown, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b separated from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b separated from each other. The first organic layer OR1a passes through the opening AP1 (the opening of the rib 5 in the sub-pixel SP1) and contacts the lower electrode LE1, and covers a part of the rib 5. The second organic layer OR1b is located above the upper portion 62. The first upper electrode UE1a is opposite to the lower electrode LE1 and covers the first organic layer OR1a. Moreover, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0049] In addition, if Figure 4 As shown, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b separated from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b separated from each other. The first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 (the opening of the rib 5 in the sub-pixel SP2) and covers a portion of the rib 5. The second organic layer OR2b is located above the upper portion 62. The first upper electrode UE2a is opposite to the lower electrode LE2 and covers the first organic layer OR2a. Moreover, the first upper electrode UE2a contacts the side of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0050] In addition, if Figure 4 As shown, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b separated from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b separated from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 (the opening of the rib 5 in the sub-pixel SP3) and covers a portion of the rib 5. The second organic layer OR3b is located above the upper portion 62. The first upper electrode UE3a is opposite to the lower electrode LE3 and covers the first organic layer OR3a. Moreover, the first upper electrode UE3a contacts the side of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0051] exist Figure 4 In the illustrated example, the sub-pixels SP1 , SP2 , and SP3 include cover layers CP1 , CP2 , and CP3 (optical path adjustment layers) for adjusting optical characteristics of light emitted from the light emitting layers of the organic layers OR1 , OR2 , and OR3 .

[0052] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b which are separated from each other. The first cap layer CP1a is located at the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0053] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b which are separated from each other. The first cap layer CP2a is located at the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0054] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b which are separated from each other. The first cap layer CP3a is located at the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0055] Sealing layers SE1, SE2 and SE3 are respectively arranged in sub-pixels SP1, SP2 and SP3. Sealing layer SE1 continuously covers the components of sub-pixel SP1 including the first cap layer CP1a, the partition wall 6 and the second cap layer CP1b. Sealing layer SE2 continuously covers the components of sub-pixel SP2 including the first cap layer CP2a, the partition wall 6 and the second cap layer CP2b. Sealing layer SE3 continuously covers the components of sub-pixel SP3 including the first cap layer CP3a, the partition wall 6 and the second cap layer CP3b.

[0056] exist Figure 4In the example shown, the second organic layer OR1b, the second upper electrode UE1b, the second cover layer CP1b, and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the partition wall 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the partition wall 6 between the sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, the second cover layer CP3b, and the sealing layer SE3 on the partition wall 6.

[0057] The sealing layers SE1 , SE2 , and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15 . Furthermore, the sealing layer 15 is covered with a resin layer 16 .

[0058] The insulating layer 13 and the resin layers 14 and 16 are formed of an organic material. The ribs 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are formed of an inorganic material such as silicon nitride (SiNx).

[0059] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may also be formed of a conductive oxide such as ITO.

[0060] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE is equivalent to an anode and the upper electrode UE is equivalent to a cathode. In addition, when the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE is equivalent to an anode and the lower electrode LE is equivalent to a cathode.

[0061] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. For example, the organic layer OR has a structure in which a hole injection layer, a hole input layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order.

[0062] The cap layer CP (CP1, CP2 and CP3) is formed, for example, by a multilayer body of multiple transparent thin films. The multilayer body may also include a thin film formed of an inorganic material and a thin film formed of an organic material as multiple thin films. In addition, these multiple thin films have different refractive indices from each other. The material of the thin film constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. It should be noted that the cap layer CP may also be omitted.

[0063] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surface of the lower portion 61. The pixel voltage is supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 included in each of the sub-pixels SP (SP1, SP2, and SP3).

[0064] If a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in a red wavelength range. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in a green wavelength range. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in a blue wavelength range.

[0065] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may also emit light of the same color (for example, white). In this case, the display device DSP may also include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0066] Figure 5 6 is a schematic enlarged cross-sectional view of the partition wall 6. Figure 5 In FIG. 1 , elements other than the ribs 5 , the partition walls 6 , the insulating layer 13 , and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE corresponds to any one of the lower electrodes LE1 , LE2 , and LE3 described above.

[0067] exist Figure 5 In the example shown, the lower portion 61 of the partition wall 6 includes a blocking layer (bottom portion) 611 disposed on the rib portion 5, and a metal layer (shaft portion) 612 disposed on the blocking layer 611. The blocking layer 611 is formed of a material different from that of the metal layer 612, for example, a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN). The metal layer 612 is formed thicker than the blocking layer 611. The metal layer 612 may be a single-layer structure or a stacked structure of different metal materials. As an example, the metal layer 612 is formed of, for example, aluminum (Al) or an aluminum alloy.

[0068] The upper portion (top portion) 62 is thinner than the lower portion 61. Figure 5In the example shown, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is formed of titanium (Ti), and the second layer 622 is formed of ITO.

[0069] exist Figure 5 In the example shown, the width of the lower portion 61 decreases as it approaches the upper portion 62. That is, the side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the direction Z. The upper portion 62 includes an end 62a protruding from the side surface 61a and an end 62b protruding from the side surface 61b.

[0070] The protrusion amount D of the end portions 62a and 62b from the side surfaces 61a and 61b (hereinafter, referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. The protrusion amount D of the partition wall 6 in the present embodiment corresponds to the distance between the lower end (blocking layer 611) of the side surfaces 61a and 61b and the end portions 62a and 62b in the width direction (first direction X or second direction Y) orthogonal to the third direction Z of the partition wall 6.

[0071] It should be noted that in Figure 5 In the example shown, the side surface of the blocking layer 611 is aligned with the side surface of the metal layer 612 to form a plane without steps, but for example, the side surface of the blocking layer 611 may be slightly retreated relative to the side surface of the metal layer 612, or may protrude relative to the side surface of the metal layer 612. Figure 5 In the embodiment, the side surfaces of the blocking layer 611 and the metal layer 612 (that is, the side surfaces 61a and 61b of the lower portion 61) are inclined relative to the third direction Z, but the side surfaces may also be parallel to the third direction Z.

[0072] The structure of the partition wall 6 and the material of each part of the partition wall 6 can be appropriately selected in consideration of, for example, the method of forming the partition wall 6 .

[0073] Here, in this embodiment, the partition wall 6 is formed to divide the sub-pixel SP in a plan view. The organic layer OR is formed by, for example, an anisotropic or directional vacuum deposition method. However, when an organic material for forming the organic layer OR is deposited on the entire substrate 10 with the partition wall 6 disposed, the partition wall 6 has Figure 4 as well as Figure 5 Since the shape shown is shown, the organic layer OR is hardly formed on the side surface of the partition wall 6. Thus, the organic layer OR (light-emitting element) partitioned for each sub-pixel SP can be formed by the partition wall 6.

[0074] Figure 6 to Figure 8 FIG. 6 is a schematic cross-sectional view for explaining a light emitting element formed by using the partition wall 6. Figure 6 to Figure 8In the figure, the substrate 10, the insulating layer 11 and the circuit layer 12 are omitted. Figure 6 to Figure 8 The sub-pixels SPα, SPβ, and SPγ shown correspond to any of the sub-pixels SP1, SP2, and SP3.

[0075] First, as described above, in the state where the partition wall 6 is arranged, Figure 6 As shown, an organic layer OR, an upper electrode UE, a cap layer CP, and a sealing layer SE are sequentially formed by evaporation relative to the entire substrate 10. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. The organic layer OR is separated into a first organic layer ORa that passes through the opening AP and contacts the lower electrode LE and a second organic layer Orb on the partition wall 6 by a suspended partition wall 6, the upper electrode UE is separated into a first upper electrode UEa that covers the first organic layer Ora and a second upper electrode UEb that covers the second organic layer Orb, and the cap layer CP is separated into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa contacts the lower portion 61 of the partition wall 6. The sealing layer SE continuously covers the first cap layer CPa, the partition wall 6, and the second cap layer CPb.

[0076] Next, if Figure 7 As shown in FIG. 1 , a resist R is formed on the sealing layer SE. The resist R covers the sub-pixel SPα. That is, the resist R is arranged directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located in the sub-pixel SPα. The resist R is also located directly above the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the sub-pixel SPα and the sub-pixel SPβ, which are close to the sub-pixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0077] Furthermore, by etching with the resist R as a mask, as Figure 8 As shown, the exposed portions of the organic layer OR, the upper electrode UE, the cover layer CP, and the sealing layer SE from the resist R are removed. As a result, a light-emitting element including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cover layer CPa is formed in the sub-pixel SPα. On the other hand, in the sub-pixels SPβ and SPγ, the lower electrode LE is exposed. It should be noted that the above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cover layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0078] As described above, when the light-emitting element of the sub-pixel SPα is formed, the resist R is removed, and the light-emitting elements of the sub-pixels SPβ and SPγ are sequentially formed in the same manner as the sub-pixel SPα.

[0079] As exemplified for the above sub-pixels SPα, SPβ, and SPγ, the light-emitting elements of the sub-pixels SP1, SP2, and SP3 are formed, and the resin layer 14, the sealing layer 15, and the resin layer 16 are further formed, thereby achieving Figure 4 The structure of the display device DSP is shown.

[0080] Here, as described above, each of the plurality of sub-pixels SP includes a pixel circuit for driving a light-emitting element. Fig. 9 An example of the circuit configuration of a pixel circuit is described below. Fig. 9 The pixel circuit 100 shown is a 7Tr1C pixel circuit including seven transistors (hereinafter, referred to as first to seventh transistors) Tr1 to Tr7 and one storage capacitor Cst.

[0081] In the following description, Fig. 9 One of the source / drain terminals of each of the first to seventh transistors Tr1 to Tr7 shown is set as the first terminal, and the other is set as the second terminal. Fig. 9 One terminal of the storage capacitor Cst (capacitance element realizing the storage capacitor Cst) shown is set as a first terminal, and the other terminal is set as a second terminal.

[0082] The first terminal of the first transistor Tr1 is connected to the first terminal of the second transistor Tr2 and the second terminal of the fifth transistor Tr5 via the node n3. The second terminal of the first transistor Tr1 is connected to the data signal line that supplies the data signal Data. The data signal Data is equivalent to a signal (pixel signal) written to the pixel. In addition, the first transistor Tr1 is, for example, an n-channel transistor.

[0083] The second transistor Tr2 is equivalent to a driving transistor (DRT) that supplies current to the light emitting element 20 included in the sub-pixel SP (that is, the light emitting element 20 driven by the pixel circuit 100). The first terminal of the second transistor Tr2 is connected to the first terminal of the first transistor Tr1 and the second terminal of the fifth transistor Tr5 via the node n3. The second terminal of the second transistor Tr2 is connected to the second terminal of the third transistor Tr3, the first terminal of the fourth transistor Tr4, and the first terminal of the seventh transistor Tr7 via the node n1. In addition, the second transistor Tr2 is, for example, an n-channel transistor.

[0084] The first terminal of the third transistor Tr3 is connected to the gate terminal of the second transistor Tr2 and the second terminal of the holding capacitor Cst via the node n2. The second terminal of the third transistor Tr3 is connected to the second terminal of the second transistor Tr2, the first terminal of the fourth transistor Tr4, and the first terminal of the seventh transistor Tr7 via the node n1. In addition, the third transistor Tr3 is, for example, an n-channel transistor.

[0085] The first terminal of the fourth transistor Tr4 is connected to the second terminal of the second transistor Tr2, the second terminal of the third transistor Tr3, and the first terminal of the seventh transistor Tr7 via the node n1. The second terminal of the fourth transistor Tr4 is connected to a power line that supplies a power supply voltage VDDEL. In addition, the fourth transistor Tr4 is, for example, a p-channel transistor.

[0086] The first terminal of the fifth transistor Tr5 is connected to the first terminal of the sixth transistor Tr6, the first terminal of the holding capacitor Cst, and the anode terminal of the light emitting element 20 via the node n4. The second terminal of the fifth transistor Tr5 is connected to the first terminal of the first transistor Tr1 and the first terminal of the second transistor Tr2 via the node n3. It should be noted that the fifth transistor Tr5 is, for example, a p-channel transistor.

[0087] The first terminal of the sixth transistor Tr6 is connected to the first terminal of the fifth transistor Tr5, the first terminal of the storage capacitor Cst, and the anode terminal of the light emitting element 20 via the node n4. The second terminal of the sixth transistor Tr6 is connected to a power supply line for supplying the initialization voltage Vini. In addition, the sixth transistor Tr6 is, for example, an n-channel transistor.

[0088] The first terminal of the seventh transistor Tr7 is connected to the second terminal of the second transistor Tr2, the second terminal of the third transistor Tr3, and the first terminal of the fourth transistor Tr4 via the node n1. The second terminal of the seventh transistor Tr7 is connected to a power line that supplies a power supply voltage VSH. In addition, the seventh transistor Tr7 is, for example, an n-channel transistor.

[0089] In addition, if Fig. 9 As shown, the gate terminal of the first transistor Tr1 is connected to the gate signal line supplied with the gate signal Scan2. The gate terminal of the third transistor Tr3 is connected to the gate signal line supplied with the gate signal Scan1. The gate terminals of the fourth to sixth transistors Tr4 to Tr6 are connected to the control signal line supplied with the control signal EM. The gate terminal of the seventh transistor Tr7 is connected to the gate signal line supplied with the gate signal Scan3.

[0090] The first terminal of the storage capacitor Cst is connected to the first terminal of the fifth transistor Tr5, the first terminal of the sixth transistor Tr6, and the anode terminal of the light emitting element 20 via the node n4. The second terminal of the storage capacitor Cst is connected to the gate terminal of the second transistor Tr2 and the first terminal of the third transistor Tr3 via the node n2.

[0091] The anode terminal of the light emitting element 20 is connected to the first terminal of the fifth transistor Tr5, the first terminal of the sixth transistor Tr6, and the first terminal of the holding capacitor Cst via the node n4. The cathode terminal of the light emitting element 20 is connected to a power line that supplies the power supply voltage VSSEL. The power supply voltage VDDEL is equivalent to the anode voltage supplied to the light emitting element 20, and the power supply voltage VSSEL is equivalent to the cathode voltage supplied to the light emitting element 20.

[0092] It should be noted that although Fig. 9 Although not shown in the figure, for example, a data signal line for supplying a data signal Data, a power line for supplying a power voltage VDDEL, and a power line for supplying a power voltage VSH are arranged in the first direction X in such a manner as to extend in the second direction Y. In other words, the data signal line, the power line for supplying a power voltage VDDEL, and the power line for supplying a power voltage VSH are connected to each of the plurality of sub-pixels SP (pixel circuit 100) arranged in the second direction Y. In addition, for example, a gate signal line for supplying gate signals Scan1 to Scan3, a control signal line for supplying a control signal EM, and a power line for supplying an initialization voltage Vini are arranged in the second direction Y in such a manner as to extend in the first direction X. In other words, the gate signal line, the control signal line, and the power line for supplying an initialization voltage Vini are connected to each of the plurality of sub-pixels SP (pixel circuit 100) arranged in the first direction X.

[0093] In addition, in the display device DSP, various screens (images) can be displayed in the display area DA by driving the light emitting element 20 by the pixel circuit 100 included in each of the plurality of sub-pixels SP. However, in the case where, for example, the entire screen displayed in the display area DA is to be darkened, it is considered that the light emitting element 20 included in each of the plurality of sub-pixels SP is to be made to emit light at a low brightness. However, when the light emitting element 20 included in each of the plurality of sub-pixels SP is made to emit light at a low brightness, unevenness is likely to occur on the screen.

[0094] Therefore, in the display device DSP, in order to avoid unevenness on the screen, PWM (Pulse Width Modulation) driving can be applied, which does not make the light emitting element 20 emit light (light up) at low brightness throughout the entire period, but makes the light emitting element 20 emit light (light up) at high brightness and in a time-sharing manner.

[0095] Fig.10 shows an overview of PWM drive. Fig.10 In the graph, the vertical axis represents 1 to N rows (hereinafter referred to as 1 to N rows of the display area DA) composed of a plurality of pixels PX (sub-pixels SP) arranged in the display area DA, and the horizontal axis represents time. It should be noted that N is an integer greater than or equal to 2.

[0096] In PWM driving, a data signal Data is written to each row of the display area DA during each frame period in which one frame (image) is displayed. It should be noted that the data signal Data is written sequentially to rows 1 to N of the display area DA.

[0097] In addition, in PWM driving, after the data signal Data is written to each row of the display area DA, the light-emitting element 20 included in the pixel PX (sub-pixel SP) constituting each row emits light (lights up) and turns off repeatedly (that is, the light-emitting element 20 is illuminated and turned off in a time-sharing manner).

[0098] exist Fig.10 In the example shown, a write scan period P1 for writing a data signal Data to each of the 1 to N rows of the display area DA, a 1st to 4th light-emitting periods P11 to 14 for making the light-emitting element 20 emit light, and a 1st to 4th extinguishing periods P21 to P24 for extinguishing the light-emitting element 20 are configured within 1 frame period. In the PWM drive, the light-emitting element 20 repeatedly emits light and extinguishes four times.

[0099] It should be noted that in Fig.10 , an example is shown in which the light emitting element 20 is repeatedly lit and turned off four times, but the number of times of light emission and turning off repetition may be other than four times.

[0100] According to this PWM driving, compared with a driving method (normal driving) in which the light emitting element 20 emits light at a low brightness throughout the entire period of one frame (a period other than the writing scanning period P1), it is easy to drive the light emitting element 20 via, for example, the driving transistor DRT ( Fig. 9 By controlling the current supplied to the light emitting element 20 by the second transistor Tr2 shown, it becomes less likely that unevenness will occur on the screen displayed in the display area DA.

[0101] In addition, PWM driving can adjust the brightness of the screen by changing, for example, the proportion of the first to fourth light-emitting periods P11 to P14 in one frame period, so that, for example, the data signal (image data) will not be changed, and brightness adjustment can be easily performed. In addition, PWM driving can also be used to correct unevenness (uneven image quality) generated in low-grayscale screens (images).

[0102] Here, refer to Fig.11 ,illustrate Fig. 9 The operation of the pixel circuit 100 during PWM driving is shown. Fig.11 The timing chart shows an output example of gate signals Scan1 to Scan3 and control signal EM for sub-pixels SP (pixel circuit 100) arranged in rows n-1 and n among rows 1 to N in the display area DA. It should be noted that n is an integer greater than 2 and less than N.

[0103] Here, we mainly explain the above Fig.10 The operations of the pixel circuit 100 in the fourth light emission period P14, the fourth light-off period P24, and the write scanning period P1 arranged in one frame period and the first light emission period P11 arranged in the next frame period are shown.

[0104] It should be noted that the plurality of transistors constituting the pixel circuit 100 include n-channel transistors and p-channel transistors, but the n-channel transistor is a switch element that becomes an off state (non-conducting state) when a low (level) signal is supplied to the gate terminal, and becomes a conducting state (conducting state) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switch element that becomes an off state (non-conducting state) when a high (level) signal is supplied to the gate terminal, and becomes a conducting state (conducting state) when a low (level) signal is supplied to the gate terminal.

[0105] First, in Fig.11 In the fourth light emission period P14 shown, the control signal EM is at a low level. Therefore, among the seven transistors included in the pixel circuit 100, the fourth transistor Tr4 and the fifth transistor Tr5 are in an on state, and the sixth transistor Tr6 is in an off state.

[0106] Furthermore, in the fourth light emitting period P14 , the gate signals Scan1 to Scan3 are at a low level, and therefore the first transistor Tr1 , the third transistor Tr3 , and the seventh transistor Tr7 are in an off state.

[0107] Thus, a current controlled by the gate voltage of the second transistor Tr2 (voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the light emitting element 20 (OLED), causing the light emitting element 20 to emit light.

[0108] Next, in Fig.11 At the timing when the fourth light-off period P24 shown starts, the control signal EM is switched from the low level to the high level.

[0109] As a result, the fourth transistor Tr4 and the fifth transistor Tr5 are turned off, so that no current is supplied to the light emitting element 20 , and the light emitting element 20 is turned off.

[0110] Next, in Fig.11 In the period P1a of the writing scanning period P1 shown, the control signal EM is at a high level, so the sixth transistor Tr6 is in an on state. In this case, the initialization voltage Vini is supplied to the node n4 via the sixth transistor Tr6, but the initialization voltage Vini is set to a value that does not flow current to the light emitting element 20, so that in the period P1a, no current flows to the light emitting element 20 (that is, the light emitting element 20 does not emit light).

[0111] In addition, at the timing of the start of period P1a, the gate signal Scan1 is switched from a low level to a high level. Therefore, during period P1a, the third transistor Tr3 is turned on. Moreover, at the timing of the start of write scan period P1, the gate signal Scan3 is switched from a low level to a high level. Therefore, during period P1a, the seventh transistor Tr7 is turned on. Thus, the power supply voltage VSH is supplied to the gate terminal of the second transistor Tr2 via the seventh transistor Tr7 and the third transistor Tr3. In this case, a voltage of VSH-Vini is applied to the holding capacitor Cst (between the first and second terminals), and the information of the previous frame is reset.

[0112] It should be noted that, at the timing when the period P1a ends, the gate signal Scan3 is switched from the high level to the low level.

[0113] In addition, at the start timing of period P1b in the write scanning period P1, the gate signal Scan2 is switched from low level to high level. Therefore, in period P1b, the first transistor Tr1 is turned on. In addition, the gate signal Scan3 is low level, so the seventh transistor Tr7 is turned off.

[0114] In this case, the data signal Data (voltage Vdata corresponding to the signal) and the threshold voltage Vth of the second transistor Tr2 (that is, a voltage equivalent to Vdata+Vth) are supplied to the gate terminal of the second transistor Tr2 via the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3. Thus, a voltage of Vdata+Vth-Vini is applied to the holding capacitor Cst, and information related to Vdata and Vth is written into the holding capacitor Cst (that is, the voltage of the current supplied by the second control transistor Tr2 to the light emitting element 20 is held by the holding capacitor Cst).

[0115] It should be noted that, at the timing when the period P1b ends, the gate signal Scan1 is switched from the high level to the low level.

[0116] Next, in Fig.11 In the first light-emitting period P11 shown, the gate signal Scan1 is at a low level, so the third transistor Tr3 is in an off state. In addition, before the first light-emitting period P11 starts, the gate signal Scan2 is switched from a high level to a low level, so the first transistor Tr1 is in an off state. Moreover, at the timing when the first light-emitting period P11 starts, the control signal EM is switched from a high level to a low level. Therefore, the fourth transistor Tr4 and the fifth transistor Tr5 are in an on state, and the sixth transistor Tr6 is in an off state.

[0117] Here, if the first terminal of the second transistor Tr2 is set as the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n2 to node n3) of the second transistor Tr2 becomes the voltage (Vdata+Vth-Vini) of the holding capacitor Cst. In this case, the second transistor Tr2 becomes conductive, and the current flows from the power line (the power line supplying the power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n4. Along with this, the potential of the node n4 begins to rise, and when the potential exceeds the threshold of the light-emitting element 20 (OLED), the circuit begins to flow to the light-emitting element 20, and the light-emitting element 20 begins to emit light. Finally, when the current Ioled flowing to the light-emitting element 20 reaches the output current (the output current in the saturation region of the second transistor Tr2) Idrt given by the second transistor Tr2, the potential of the node n4 stops rising, and the light-emitting element 20 becomes a stable light-emitting state.

[0118] It should be noted that when the voltage Vgs=Vdata+Vth-Vini between the gate terminal and the source terminal of the second transistor Tr2 is substituted into the TFT saturation formula, Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2When Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini) 2 In addition, Cox is the gate electrostatic capacitance per unit area, μ is the carrier mobility, W is the channel width of the second transistor Tr2, and L is the channel length of the second transistor Tr2.

[0119] It can be seen from this that Idrt is a value that does not depend on the threshold voltage Vth of the second transistor Tr2 (that is, a current that does not depend on the threshold voltage Vth of the second transistor Tr2 flows through the light emitting element 20), and the influence of the variation in the threshold voltage Vth on Idrt can be eliminated.

[0120] That is, we can say Fig. 9 The pixel circuit 100 (7Tr1C pixel circuit) shown has a function of correcting the variation of the threshold voltage Vth of the second transistor Tr2 (Vth correction function).

[0121] It should be noted that, here, Fig.11 The operation of the pixel circuits 100 arranged in the n-1 row is shown, but the pixel circuits 100 arranged in the n row perform the same operation in such a manner that the data signal Data is written to the n-1 row and then the data signal Data is written to the n row.

[0122] Next, consider the display area DA of the display device DSP to which the above PWM drive is applied. Fig.12 The left side of the screen (Window) is shown. It should be noted that Fig.12 A black belt portion 101 (a black belt-shaped image) is arranged near the center of the screen shown on the left side of . In this case, the n-1 row of the display area DA corresponds to the row displaying the black belt portion 101, and the n row corresponds to the row displayed in a portion (non-black belt portion) different from the black belt portion 101 and located in the second direction Y relative to the black belt portion 101.

[0123] It should be noted that in the following description, for the sake of convenience, the action of the pixel circuit 100 in the above-mentioned 4th light-emitting period P14 is called a light-emitting action, the action of the pixel circuit 100 in the 4th extinction period P24 is called an extinction action, and the action of the pixel circuit 100 in the write scan period P1 is called a write action.

[0124] Here, when the pixel circuit 100 arranged in the n-1 row performs a write operation, the data signal Data (black voltage corresponding to the data signal Data) for displaying the black band portion 101 is supplied to the data signal line connected to the first transistor Tr1 constituting the pixel circuit 100 arranged in the n-1 row. In the present embodiment, the black voltage refers to a voltage that does not cause the light emitting element 20 to emit light (does not flow a current to the light emitting element 20).

[0125] On the other hand, as described above, the data signal line to which the data signal Data for displaying the black band portion 101 is supplied is also connected to the first transistor Tr1 constituting the pixel circuit 100 arranged in the n-1 row. However, when the pixel circuit 100 arranged in the n-1 row is in a writing operation, the pixel circuit 100 arranged in the n row is in a extinguishing operation, and the node n1 and the node n3 of the pixel circuit 100 arranged in the n row are in a floating state.

[0126] In the case where the node n1 and the node n3 of the pixel circuit 100 arranged in n rows are in a floating state, if the data signal Data (that is, the black voltage) for displaying the black band portion 101 is supplied to the data signal line connected to the first transistor Tr1 constituting the pixel circuit 100 as described above, a leakage current (OFF leakage) from the node n3 side toward the data signal line side flows to the first transistor Tr1, causing a potential change at the node n1 and the node n3 in the floating state.

[0127] The pixel circuits 100 arranged in the nth row perform a write operation after the extinguishing operation. However, in the extinguishing operation, the potential variation generated at the nodes n1 and n3 also affects the gate voltage of the second transistor Tr2 after the write operation (remains as a potential difference of the gate voltage). Therefore, in the display device DSP using PWM drive, when it is desired to display a pixel in the display area DA, Fig.12 When the screen shown on the left side is Fig.12 As shown on the right side of , for example, in the area 102 after the nth row where the writing operation is performed after the n-1th row of the display area DA, a ghost image is visually confirmed (occurred).

[0128] It should be noted that the ghosting occurs during the blackout action (that is, during the period when the nodes n1 and n3 are in a floating state). Since the data signal Data (black voltage) for displaying the black band portion 101 is supplied to the data signal line, the ghosting does not occur in the display device DSP that applies the above-mentioned normal drive (that is, no blackout period is configured within 1 frame period).

[0129] The area 102 where the ghosting occurs is as follows. Fig.13As shown in FIG. 1 , in the fourth extinguishing period P24 configured before the writing scanning period P1, it is an area composed of pixels PX (sub-pixels SP) to which the data signal Data for displaying the black belt portion 101 is supplied to the data signal line. In other words, the area 102 where the ghost image is generated can be said to be an area where at least a part of the fourth extinguishing period P24 overlaps with the period in which the writing of the black belt portion 101 is not performed.

[0130] In the display device DSP to which PWM driving is applied as described above, when a screen with the black belt portion 101 is displayed in the display area DA, ghosting may occur, which may reduce the display quality in the display device DSP. It should be noted that, for the sake of convenience, the black belt portion 101 (black belt-shaped image) is displayed in a part of the display area DA, but ghosting may also occur when displaying a belt-shaped image of another color, which may reduce the display quality in the display device DSP.

[0131] Here, the first transistor Tr1 constituting the pixel circuit 100 is usually a polysilicon transistor using low temperature polysilicon (LTPS: Low Temperature Ply Silicon), but in this embodiment, in view of the fact that the above-mentioned ghosting is caused by the leakage current generated in the first transistor Tr1, an oxide transistor (Oxide TFT) using an oxide semiconductor is used as the first transistor Tr1. Compared with the polysilicon transistor, the leakage current of the oxide transistor is extremely small, so even if the data signal Data (black voltage) for displaying the black band portion 101 is supplied to the data signal line during the above-mentioned extinguishing operation, the potential change of the node n1 and the node n3 in the pixel circuit 100 arranged in the above-mentioned area 102 will not occur, and the generation of ghosting can be suppressed.

[0132] Here, Fig.14 An example of the layout of the pixel circuit 100 is shown. Fig.14 , for example, various elements of the pixel circuit 100 (first to seventh transistors Tr1 to Tr7, holding capacitor Cst, gate signal lines, control signal lines, data signal lines, and various power supply lines) formed in the circuit layer 12 composed of the first to fifth layers are shown.

[0133] It should be noted that the first layer is a layer formed under the second layer, the second layer is a layer formed under the third layer, the third layer is a layer formed under the fourth layer, and the fourth layer is a layer formed under the fifth layer. In other words, the first to fifth layers are stacked in order, with the first layer being the lowermost layer and the fifth layer being the uppermost layer.

[0134] In addition, the first layer is a layer for forming a polycrystalline silicon semiconductor layer (p-Si layer), the second, fourth and fifth layers are layers for forming electrodes constituting a transistor and wiring connected to the transistor (Metal layer), and the third layer is a layer for forming an oxide semiconductor layer (Oxide layer).

[0135] Specifically, if Fig.14 As shown, the first transistor Tr1 as an oxide transistor is formed across the second to fourth layers. Here, it is assumed that the first transistor Tr1 includes a double gate structure in which an oxide semiconductor is sandwiched between a first gate electrode formed in the fourth layer (upper layer) and a second gate electrode formed in the second layer (lower layer) (that is, the third layer).

[0136] Note that, in order to appropriately hold the voltage supplied to the gate terminal of the second transistor Tr2 in the holding capacitor Cst during one frame period, an oxide transistor is often used as the third transistor Tr3 connected to the node n2.

[0137] On the other hand, the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 are polysilicon transistors, and are formed across the first and second layers. That is, the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 are formed in a lower layer than the first transistor Tr1 and the third transistor Tr3 (oxide transistors). It should be noted that, similarly to the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7, the holding capacitor Cst is formed across the first and second layers.

[0138] In addition, gate signal lines, control signal lines, and power supply lines for supplying initialization voltage Vini are formed in the second layer. Furthermore, data signal lines and other power supply lines are formed in the fifth layer.

[0139] It should be noted that the connections between the various elements of the pixel circuit 100 are as shown in Fig. 9 Therefore, a detailed description thereof will be omitted here, but Fig.14 As shown, elements formed in different layers are connected together via contact holes CH.

[0140] In addition, Fig.14In the figure, it is described that the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 are all polysilicon transistors, but some of the second transistor Tr2 and the fourth to seventh transistors Tr4 to Tr7 may be oxide transistors. Specifically, for example, the second transistor Tr2, the fourth transistor Tr4, and the fifth transistor Tr5 that supply current to the light emitting element 20 may be polysilicon transistors with relatively high stability, and the sixth transistor Tr6 and the seventh transistor Tr7 may be oxide transistors.

[0141] It should be noted that Fig.14 The layout of the pixel circuit 100 shown in the figure is an example. The positions or directions of the configuration of each element of the pixel circuit 100 may be different from those of the pixel circuit 100. Fig.14 The examples shown are different.

[0142] As described above, the display device DSP of the present embodiment includes: a substrate 10; a plurality of sub-pixels SP arranged in a display area DA on the substrate 10; and a data signal line for supplying a data signal Data to each of the plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a pixel circuit 100 composed of a plurality of transistors, and a light-emitting element 20 driven by the pixel circuit 100. In addition, the pixel circuit 100 drives the light-emitting element 20 in a time-division manner to emit light. Moreover, the first transistor Tr1 connected to the data signal line among the plurality of transistors constituting the pixel circuit 100 is an oxide transistor.

[0143] In this embodiment, according to the above-mentioned configuration, even when the display area DA of the display device DSP using PWM drive displays a screen configured with a black belt portion 101, etc., it is possible to suppress the reduction in display quality of the display device DSP (that is, to achieve good display quality without ghosting).

[0144] In addition, in the present embodiment, the second transistor Tr2 that supplies current to the light emitting element 20 among the plurality of transistors constituting the pixel circuit 100 is a polysilicon transistor, so that a stable current can be supplied to the light emitting element 20. It should be noted that in the present embodiment, the fourth transistor Tr4 disposed between the power supply line that supplies the power supply voltage VDDEL and the second transistor Tr2 and the fifth transistor Tr5 disposed between the light emitting element 20 and the second transistor Tr2 are also preferably polysilicon transistors.

[0145] Moreover, in the present embodiment, the first terminal (one side of the source terminal and the drain terminal) of the second transistor Tr2 is connected to the first terminal of the first transistor Tr1, the first terminal (one side of the source terminal and the drain terminal) is connected to the gate terminal of the second transistor Tr2 and the second terminal (one side of the terminal) of the holding capacitor Cst, and the third transistor Tr3 connected to the second terminal (the other side of the source terminal and the drain terminal) of the second transistor Tr2 via the second terminal (the other side of the source terminal and the drain terminal) is an oxide transistor, which is not affected by the leakage current and can enable the holding capacitor Cst to properly maintain the voltage supplied to the gate terminal of the second transistor Tr2.

[0146] It should be noted that in this embodiment, the first transistor Tr1 connected to the data signal line is described as an oxide transistor, but the first transistor Tr1 only needs to be a transistor with less leakage current than the second transistor that supplies current to, for example, the light-emitting element 20 among the multiple transistors constituting the pixel circuit 100.

[0147] Any display device implemented by a person skilled in the art after appropriately changing the design based on the display device described above as the embodiment of the present invention belongs to the scope of the present invention as long as it includes the gist of the present invention.

[0148] In the scope of the concept of the present invention, those skilled in the art can think of various variations, and it should be understood that these variations also belong to the scope of the present invention. For example, variations obtained by those skilled in the art appropriately adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes relative to the above-mentioned embodiments are also included in the scope of the present invention as long as they have the gist of the present invention.

[0149] In addition, other effects brought about by the forms described in the above embodiments that are clearly derived from the description of this specification or that can be appropriately thought of by a person skilled in the art should of course be understood to be brought about by the present invention.

Claims

1. A display device, characterized in that: have: Base material; A plurality of pixels arranged in a display area on the substrate; and a data signal line for supplying a data signal to each of the plurality of pixels, Each of the plurality of pixels includes a pixel circuit composed of a plurality of transistors and a light emitting element driven by the pixel circuit. The pixel circuit drives the light emitting element so that the light emitting element emits light in a time-sharing manner. A first transistor connected to the data signal line among a plurality of transistors constituting the pixel circuit is an oxide transistor.

2. The display device according to claim 1, characterized in that A second transistor among the plurality of transistors constituting the pixel circuit, which supplies current to the light emitting element, is a polysilicon transistor.

3. The display device according to claim 2, characterized in that The pixel circuit further includes a holding capacitor in addition to the plurality of transistors, the holding capacitor holding a voltage for controlling a current supplied from the second transistor to the light emitting element. A third transistor among the plurality of transistors constituting the pixel circuit is an oxide transistor, One of a source terminal and a drain terminal of the second transistor is connected to one of a source terminal and a drain terminal of the first transistor, One of the source terminal and the drain terminal of the third transistor is connected to the gate terminal of the second transistor and one terminal of the holding capacitor, and the other of the source terminal and the drain terminal is connected to the other of the source terminal and the drain terminal of the second transistor.

4. The display device according to claim 3, characterized in that The fourth transistor and the fifth transistor of the plurality of transistors constituting the pixel circuit are polysilicon transistors. The fourth transistor is arranged between a power line for supplying a power supply voltage and the second transistor. The fifth transistor is arranged between the light emitting element and the second transistor.

5. A display device, characterized in that: have: Base material; A plurality of pixels arranged in a display area on the substrate; and a data signal line for supplying a data signal to each of the plurality of pixels, Each of the plurality of pixels includes a pixel circuit composed of a plurality of transistors and a light emitting element driven by the pixel circuit. The pixel circuit drives the light emitting element so that the light emitting element emits light in a time-sharing manner. A first transistor connected to the data signal line among the plurality of transistors constituting the pixel circuit is configured to have a smaller leakage current than a second transistor among the plurality of transistors that supplies current to the light emitting element.

Images