Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of groups of data signal lines, each group of data signal lines comprising a first data signal line and a second data signal line; a plurality of sub-pixels arranged in a plurality of sub-pixel columns along a second direction; the first data signal line and the second data signal line of the same group are electrically connected to different sub-pixels in the same sub-pixel column; a plurality of first power lines are located in a display area and are configured to transmit a low-voltage signal; the display substrate comprises a first connection line and a multiplexing circuit, the first connection line comprises a plurality of traces located in different conductive layers, the multiplexing circuit is located in a first frame area, part of the first connection line is located between the multiplexing circuit and the display area, part of the first connection line is located on one side of the multiplexing circuit along a first direction, and the first connection line and the multiplexing circuit do not overlap in the orthographic projection of the substrate, which can improve the display quality.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, a display device using an OLED as a light emitting element and controlled by a thin film transistor (TFT) has become a mainstream product in the current display field.

[0003] At present, the electric signal in the display substrate has the problems of high current density and high attenuation. SUMMARY

[0004] The display substrate and the display device provided by the embodiments of the present disclosure can improve the uniformity of voltage distribution and improve the display quality of the display device.

[0005] In one aspect, the present disclosure provides a display substrate, comprising:

[0006] A substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a plurality of frame areas;

[0007] A plurality of groups of data signal lines located in the display area, and the plurality of groups of data signal lines are arranged at intervals along a first direction and extend along a second direction, each group of data signal lines comprising a first data signal line and a second data signal line; the first direction intersects the second direction and the plane formed thereby is parallel to the plane in which the substrate lies;

[0008] A plurality of sub-pixels located in the display area, and the plurality of sub-pixels are arranged along the second direction to form a plurality of sub-pixel columns; the first data signal line and the second data signal line of the same group are respectively electrically connected to different sub-pixels in the same sub-pixel column;

[0009] A plurality of first power lines located in the display area and configured to transmit a low-voltage signal;

[0010] The plurality of frame regions comprises a first frame region and a second frame region arranged opposite along the second direction, and a third frame region and a fourth frame region arranged opposite along the first direction; the display substrate further comprises at least one first connecting line, the first connecting line comprises a first end and a second end arranged opposite, the first end is connected with the first power line, and the second end is located in the first frame region, and the first connecting line comprises a plurality of tracks located in different conductive layers;

[0011] The display substrate further comprises a multiplexing circuit located in the first frame region, part of the first connecting line is located between the multiplexing circuit and the display region, part of the first connecting line is located on one side of the multiplexing circuit along the first direction, and the first connecting line and the multiplexing circuit do not overlap in the orthogonal projection of the substrate plane.

[0012] In some example embodiments, at least part of the plurality of first power lines is arranged in pairs with at least part of the plurality of groups of data signal lines, and the first power line is located between the first data signal line and the second data signal line arranged in pairs, and the first power line and the data signal lines arranged in pairs are located in different conductive layers.

[0013] In some example embodiments, the plurality of tracks comprises a first track, a second track and a third track connected in sequence, and the third track is farther away from the display region than the first track, and the first track and the third track both extend along the second direction, and the second track extends along the first direction; the first end of the first connecting line is located in the first track, and the second end of the first connecting line is located in the third track; at least part of the second track is located between the multiplexing circuit and the display region, and at least part of the third track is located on one side of the multiplexing circuit along the first direction;

[0014] The display substrate further comprises a second power bus located in the first frame region, the second power bus extends along the first direction, and the second power bus is configured to transmit a high-voltage signal to a plurality of sub-pixels;

[0015] The orthogonal projection of the first track and the second power bus on the substrate plane at least partially overlaps, and the first track and the second power bus are located in different conductive layers; the orthogonal projection of the second track and at least one data signal line on the substrate plane at least partially overlaps, and the second track and the data signal line are located in different conductive layers.

[0016] In some example embodiments, the peripheral region further comprises at least one transition region, at least one set of two adjacent bezel regions are connected via the transition region; at least a portion of the boundary of the transition region close to the side of the display region is an arc-shaped boundary.

[0017] The display substrate further comprises at least one connection line, at least a portion of the connection line is located in the transition region, the connection line comprises oppositely arranged first and second ends, the first end is connected with the first power supply line, and the second end is located in the transition region.

[0018] In some example embodiments, the at least one transition region comprises a first transition region, and the first transition region is located between the first bezel region and the third bezel region.

[0019] The connection line comprises a second connection line, and at least a portion of the second connection line is located in the first transition region; the second connection line comprises a fourth trace, a fifth trace and a sixth trace connected in sequence, and the fourth trace is closer to the display region than the sixth trace; a first end of the second connection line is located at the fourth trace, and a second end of the second connection line is located at the sixth trace.

[0020] The display substrate further comprises a second power supply transmission line extending along the first direction, at least a portion of the second power supply transmission line is located in the transition region, and the second power supply transmission line is configured to be connected with a second power supply bus and transmit a high-voltage signal to a plurality of sub-pixels.

[0021] The fourth trace and the second power supply transmission line at least partially overlap in the orthographic projection of the plane on which the substrate is located, and the fourth trace and the second power supply transmission line are located in different conductive layers; the fifth trace and at least one data signal line at least partially overlap in the orthographic projection of the plane on which the substrate is located, and the fifth trace and the data signal line are located in different conductive layers.

[0022] In some example embodiments, the fifth traces of a plurality of the second connection lines are an integral structure connected with each other, and / or the sixth traces of a plurality of the second connection lines are shared.

[0023] In some example embodiments, the at least one transition region comprises a first transition region, and the first transition region is located between the first bezel region and the third bezel region.

[0024] The at least one connection line includes a second connection line, and at least part of the second connection line is located in the first transition area; the display substrate further includes at least one auxiliary power supply line, at least part of the auxiliary power supply line is located in the first transition area, the auxiliary power supply line includes oppositely arranged first and second ends, the first end is connected with the second connection line, and the second end is located in the third frame area.

[0025] In some example embodiments, the display substrate further includes a plurality of horizontal wires, a plurality of vertical wires and a first power supply bus located in the second frame area, the horizontal wires extend along the first direction, and the vertical wires extend along the second direction, the vertical wires are connected with the first power supply bus, and the horizontal wires and the vertical wires are connected with each other to form a mesh; the horizontal wires and the vertical wires are located in the same conductive layer, the first power supply bus is located in another conductive layer, and the first power supply bus is configured to transmit a low-voltage signal.

[0026] In some example embodiments, the display area includes a first area and a second area which do not overlap with each other, the first area surrounds at least one side of the second area, and the plurality of first power supply lines are located in the first area.

[0027] The display substrate further includes a first power supply transmission line located in the first area, at least part of the first power supply transmission line is in a stepped shape in the plane of the substrate, and the first power supply transmission line surrounds at least part of the second area and is connected with the plurality of first power supply lines.

[0028] In another aspect, the embodiments of the present disclosure provide a display device including the display substrate according to any one of the preceding embodiments.

[0029] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. Other advantages of the present application will be realized and attained by the methods and solutions particularly pointed out in the written description and claims hereof. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate the embodiments of the present application, and are used to explain the technical solutions of the present application, but do not constitute limitations on the technical solutions of the present application.

[0031] Figure 1 FIG. 1 is a structural schematic diagram of a display device;

[0032] Figure 2 FIG. 2 is a plan structural schematic diagram of a display area in a display substrate;

[0033] Figure 3A A plan view of a display substrate according to an embodiment of the present disclosure;

[0034] Figure 3B A partial cross-sectional view of a display region of a display substrate according to an embodiment of the present disclosure;

[0035] Figure 4 A partial structure view of a first bezel region of a display substrate according to an embodiment of the present disclosure;

[0036] Figure 5A A partial structure view of a first transition region of a display substrate according to an embodiment of the present disclosure;

[0037] Figure 5B A partial structure view of a first transition region of a display substrate according to another embodiment of the present disclosure;

[0038] Figure 6 A partial structure view of a first transition region of a display substrate according to another embodiment of the present disclosure;

[0039] Figure 7 A partial structure view of a second bezel region of a display substrate according to an embodiment of the present disclosure;

[0040] Figure 8 A plan view of a display substrate according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] For the purpose of making the objects, technical solutions, and advantages of the present disclosure clearer, below will be a detailed description of the embodiments of the present disclosure with reference to the drawings. The embodiments can be implemented in multiple different forms. One of ordinary skill in the art can easily understand that the manners and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict.

[0042] In the drawings, the size, the thickness, or the region of one or more constituent elements can be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to such a scale. The shapes and the sizes of the components shown in the drawings can not reflect the actual ones. In addition, the drawings are schematically shown ideal examples, and one embodiment of the present disclosure is not limited to the shapes or the numerical values shown in the drawings.

[0043] The ordinal numbers "first", "second", "third", and the like in the present disclosure are used to avoid confusion between constituent elements and are not intended to limit the numbers thereof. The "plurality" in the present disclosure includes two or more.

[0044] In the present disclosure, the words of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicating the positional or directional relationship are used to refer to the positional relationship of the components with reference to the drawings for the purpose of facilitating the description of the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which the components are described. Therefore, it is not limited to the words described in the specification, and can be appropriately replaced according to the situation.

[0045] In the present disclosure, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be broadly understood. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the situation.

[0046] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0047] In the present disclosure, "electrically connected" includes the case where the components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit an electrical signal between the connected components. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.

[0048] In the present disclosure, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus can include a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus can include a state in which the angle is 85° or more and 95° or less.

[0049] In the present disclosure, "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced by "conductive film". Similarly, "insulating film" can be replaced by "insulating layer".

[0050] "About" in the present disclosure means not strictly limited to the boundary, allowing the range of process and measurement error values.

[0051] Figure 1 It is a structural schematic diagram of a display device. As Figure 1As shown, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller being connected to the data driver, the scan driver, and the light emitting driver respectively, the data driver being connected to a plurality of data signal lines (D1 to Dn) respectively, the scan driver being connected to a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver being connected to a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit being connected to the scan signal line, the light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device, the light emitting device being connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0052] Figure 2 FIG. 1 is a schematic view of a planar structure of a display area in a display substrate. Figure 2As shown, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one pixel unit P can include a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light. Each sub-pixel can include a circuit unit and a light emitting unit, the light emitting unit can include a light emitting device, and the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with a scan signal line, a data signal line and a light emitting signal line respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting device in each sub-pixel is connected with the pixel driving circuit of the sub-pixel respectively, and is configured to emit light with a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0053] In some example embodiments, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In example embodiments, the shape of the sub-pixel can be rectangular, diamond, pentagonal or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0054] In some example embodiments, the pixel unit can include four sub-pixels. For example, the four sub-pixels can include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel emitting white (W) light. For another example, the four sub-pixels can include a red sub-pixel, a blue sub-pixel and two green sub-pixels. In example embodiments, the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, square or diamond shape, which is not limited in the present disclosure.

[0055] In some example embodiments, the light emitting device can be any one of a light emitting diode, an organic light emitting diode, a quantum dot light emitting diode, a micro LED (including: mini-LED or micro-LED), etc. For example, the light emitting device can be an OLED, and the light emitting device can emit red light, green light, blue light or white light, etc. under the driving of the corresponding pixel driving circuit. In some examples, the light emitting device can include an anode, a cathode and an organic light emitting layer between the anode and the cathode. The anode of the light emitting device can be electrically connected with the corresponding pixel driving circuit.

[0056] Embodiments of the present disclosure provide a display substrate, which includes:

[0057] A substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a plurality of frame areas;

[0058] a plurality of groups of data signal lines located in the display region and spaced apart along a first direction and extending along a second direction, each group of the data signal lines comprising a first data signal line and a second data signal line, the first direction intersecting the second direction and the plane formed thereby being parallel to the plane in which the substrate lies;

[0059] a plurality of sub-pixels located in the display region and arranged along the second direction to form a plurality of sub-pixel columns, the first data signal line and the second data signal line of the same group being electrically connected to different sub-pixels in the same sub-pixel column, respectively;

[0060] a plurality of first power supply lines located in the display region and configured to transmit a low-voltage signal;

[0061] The plurality of frame regions comprises a first frame region and a second frame region arranged opposite to each other along the second direction, and a third frame region and a fourth frame region arranged opposite to each other along the first direction. The display substrate further comprises at least one first connection line comprising a first end and a second end arranged opposite to each other, the first end being connected to the first power supply line, and the second end being located in the first frame region, and the first connection line comprising a plurality of traces located in different conductive layers.

[0062] The display substrate further comprises a multiplexing circuit located in the first frame region, part of the first connection line being located between the multiplexing circuit and the display region, part of the first connection line being located on one side of the multiplexing circuit along the first direction, and the first connection line and the multiplexing circuit not overlapping in the orthogonal projection of the plane in which the substrate lies.

[0063] In the embodiments of the present disclosure, by designing the display substrate with double data signal lines, high-frequency driving can be achieved, threshold voltage compensation capability can be improved, threshold voltage compensation time can be shortened, the SIP (VSS In Panel) design of the display substrate can reduce the overall voltage drop of the low-voltage signal, can improve the uniformity of voltage distribution, and the orthogonal projection of the first connection line and the multiplexing circuit in the plane in which the substrate lies not overlapping can avoid mutual interference between different signals, can improve the display quality of the display device, and can reduce display power consumption.

[0064] Figure 3A A schematic diagram of the planar structure of the display substrate of an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the display substrate comprises a substrate 1, a plurality of frame regions 2, a display region 3, a plurality of first power supply lines 4, a plurality of groups of data signal lines 5, and a plurality of sub-pixels 6. Figure 3AAs shown, the display substrate can include a substrate, a display area AA located on the substrate, and a peripheral area BB located on the substrate and surrounding the display area AA. The display area AA can include a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display dynamic pictures or still images. In some examples, the display substrate can be a flexible substrate, and thus the display substrate can be deformable, for example, rolled, bent, or folded. The shape of the display area AA can be a quadrilateral, a circle, an ellipse, or a polygon with rounded corners, and the present disclosure does not limit the shape of the display area AA.

[0065] The peripheral area BB can include a plurality of bezel areas, the plurality of bezel areas can include a first bezel area B1 located on one side of the display area AA, and a second bezel area B2 located opposite the first bezel area B1, the first bezel area B1 and the second bezel area B2 being located on two sides of the display area AA along the second direction Y, respectively. The plurality of bezel areas can further include a third bezel area B3 located on one side of the display area AA, and a fourth bezel area B4 located opposite the third bezel area B3, the third bezel area B3 and the fourth bezel area B4 being located on two sides of the display area AA along the first direction X, respectively. In the embodiments of the present disclosure, the first bezel area B1 can also be referred to as a lower bezel of the display substrate, the second bezel area B2 can also be referred to as an upper bezel of the display substrate, the third bezel area B3 can also be referred to as a left bezel of the display substrate, and the fourth bezel area B4 can also be referred to as a right bezel of the display substrate. In the embodiments of the present disclosure, the first direction X and the second direction Y intersect and form a plane parallel to the plane on which the substrate is located. For example, the first direction X and the second direction Y can be perpendicular to each other.

[0066] The peripheral area BB can further include at least one transition area, at least one group of two adjacent bezel areas being connected via a transition area, at least a part of the at least one transition area near the boundary of the display area AA can be an arc-shaped boundary. Figure 3AIn the figure, the peripheral area BB includes four transition areas, which are respectively the first transition area G1, the second transition area G2, the third transition area G3 and the fourth transition area G4. The first transition area G1 is located between the first frame area B1 and the third frame area B3, and the first frame area B1 and the third frame area B3 are connected via the first transition area G1. The second transition area G2 is located between the first frame area B1 and the fourth frame area B4, and the first frame area B1 and the fourth frame area B4 are connected via the second transition area G2. The third transition area G3 is located between the second frame area B2 and the fourth frame area B4, and the second frame area B2 and the fourth frame area B4 are connected via the third transition area G3. The fourth transition area G4 is located between the second frame area B2 and the third frame area B3, and the second frame area B2 and the third frame area B3 are connected via the fourth transition area G4.

[0067] In some exemplary embodiments, Figure 3A As shown, the display area AA may include at least a plurality of scan signal lines (e.g., S1, S2) and a plurality of groups of data signal lines. The plurality of scan signal lines may extend along a first direction X and be arranged at intervals along a second direction Y, and the plurality of groups of data signal lines may extend along the second direction Y and be arranged at intervals along the first direction X. The orthographic projections of the plurality of scan signal lines and the plurality of groups of data signal lines on the plane where the substrate is located intersect to form a plurality of sub-pixel areas, and a sub-pixel is provided in each sub-pixel area. The plurality of groups of data signal lines are electrically connected to the plurality of sub-pixels, and the plurality of groups of data signal lines may be configured to provide data signals to the plurality of sub-pixels. The plurality of scan signal lines are electrically connected to the plurality of sub-pixels, and the plurality of scan signal lines may be configured to provide gate control signals to the plurality of sub-pixels. In some examples, the gate control signal may include a scan signal and a light emitting control signal.

[0068] In some exemplary embodiments, Figure 3AAs shown, each group of data signal lines includes a first data signal line DL-1 and a second data signal line DL-2, and the first data signal line DL-1 and the second data signal line DL-2 are electrically connected to different sub-pixels in a same sub-pixel column (along the second direction Y) respectively. For example, the first group of data signal lines DL1 includes the first data signal line DL-1 and the second data signal line DL-2. For example, the first data signal line DL-1 is electrically connected to sub-pixels in odd rows (along the first direction X) in the same sub-pixel column, and the second data signal line DL-2 is electrically connected to sub-pixels in even rows in the same sub-pixel column. In the embodiment of the present disclosure, by designing the display substrate with double data signal lines, high-frequency driving can be achieved, threshold voltage (Vth) compensation capability can be improved, threshold voltage compensation time can be shortened, and in addition, the display substrate can be integrated with a driving integrated circuit without data storage function, so that the cost of the display device can be reduced.

[0069] In some example embodiments, as shown in Figure 3A As shown, the display substrate can further include a plurality of first power lines 10, the plurality of first power lines 10 extend along the second direction Y and are arranged at intervals along the first direction X, and the plurality of first power lines 10 are located in the display area AA. The first power line 10 is also a low-level power line or a negative voltage power line. In the embodiment of the present disclosure, the display substrate adopts the SIP (VSS In Panel) design, which can reduce the overall voltage drop of the low-voltage signal, improve the uniformity of voltage distribution, improve the display effect of the display device, and reduce the display power consumption.

[0070] In some example embodiments, as shown in Figure 3A As shown, at least part of the plurality of first power lines 10 is arranged in pairs with at least part of the plurality of groups of data signal lines, and the first power line 10 is located between the first data signal line DL-1 and the second data signal line DL-2 arranged in pairs, and the first power line 10 and the data signal lines arranged in pairs are located in different conductive layers. In the embodiment of the present disclosure, the first power line and the data signal lines arranged in pairs are arranged in different conductive layers, which can avoid electrical interference between the first power line and the data signal lines.

[0071] In some example embodiments, as shown in Figure 3A As shown, the display substrate can further include a first power supply line 11, and the first power supply line 11 can be located in the peripheral area BB. For example, part of the first power supply line 11 can surround the display area AA, and the first power supply line 11 is connected with the first power line 10.

[0072] In some example embodiments, as shown in Figure 3AAs shown, the display substrate can further include a plurality of second power lines 20 extending along the second direction Y and arranged at intervals along the first direction X. Part of the plurality of second power lines 20 is located in the display area AA, and the plurality of second power lines 20 can extend to the first frame area B1. The second power line 20 is a high-level power line. The second power line 20 can be electrically connected to the pixel driving circuit of the plurality of sub-pixels, and is configured to transmit a high-voltage signal to the plurality of sub-pixels.

[0073] In some example embodiments, as shown in Figure 3A As shown, the display substrate can further include a second power bus 21 located in the first frame area B1 and extending along the first direction X, and the second power bus 21 can be connected to the plurality of second power lines 20.

[0074] In some example embodiments, as shown in Figure 3A As shown, along a direction away from the display area AA, the first frame area B1 can include at least a first sub-frame area B11 and a second sub-frame area B12. The first sub-frame area B11 can be connected to the display area AA, and the second sub-frame area B12 is located on a side of the first sub-frame area B11 away from the display area AA. The first sub-frame area B11 can include at least the second power bus 21 and a multiplexing circuit 22, and the multiplexing circuit 22 can be configured to enable one signal source to provide data signals to the plurality of data signal lines. Towards a direction away from the first sub-frame area B11, the second sub-frame area B12 can include a bending area, a driving chip area and a binding pin area arranged in sequence. The bending area can include a composite insulating layer provided with a groove, and the groove can be configured to enable part of the first frame area B1 to bend to the back of the display area AA. The driving chip area can include at least a driving integrated circuit 23 (IC), and the driving integrated circuit 23 can be connected to the multiplexing circuit 22 through a data transmission line. The driving integrated circuit 23 can send data signals to the sub-pixels of the display area AA through the multiplexing circuit 22. For example, the multiplexing circuit 22 can adopt a MUX1:4 scheme. By designing the multiplexing circuit, the number of data transmission lines (connecting the driving integrated circuit and the data signal line) can be reduced, the size of the driving integrated circuit can be reduced, and the narrow frame design of the display device is facilitated. The binding pin area can include at least a plurality of binding pins configured to be bound to a flexible printed circuit (FPC).

[0075] In some exemplary embodiments, the display substrate may further include a gate drive circuit and a plurality of gate drive signal lines. The gate drive circuit may be located in the third frame area B3 and the fourth frame area B4. The gate drive circuit may include a plurality of cascaded shift registers GOA1, GOA2, ..., GOAn, which may be electrically connected to a plurality of scan signal lines in the display area AA. A plurality of gate drive signal lines GSTV, GCK, and GCB are electrically connected to the gate drive circuit, and each shift register is electrically connected to a scan signal line.

[0076] Figure 3B FIG1 is a schematic partial cross-sectional view of a display area of ​​a display substrate according to an embodiment of the present disclosure. Figure 3B Only a partial connection structure of the connection area between the pixel driving circuit and the light emitting device is shown. Figure 3B As shown, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include at least a circuit structure layer 200, a light-emitting structure layer 300, and an encapsulation structure layer 400 sequentially arranged on the substrate 100. The circuit structure layer 200 may include at least a pixel driving circuit for a plurality of sub-pixels, and the pixel driving circuit for each sub-pixel may include a plurality of transistors and at least one capacitor. For example, the transistor may be a thin film transistor. The light-emitting structure layer 300 may include at least a light-emitting device for a plurality of sub-pixels. In other examples, a touch structure layer 500 may be provided on the side of the encapsulation structure layer 400 away from the substrate 100 to integrate the touch function.

[0077] In some example embodiments, the circuit structure layer 200 can include a semiconductor layer, a first insulating layer 101, a first gate metal layer, a second insulating layer 102, a second gate metal layer, a third insulating layer 103 (interlayer insulating layer), a first source-drain metal layer, a first planar layer 104, a second source-drain metal layer, and a second planar layer 105, which are sequentially stacked. The semiconductor layer of the display area can include an active layer T10 of a transistor T of a pixel driving circuit. The active layer T10 of the transistor T can include a first region, a second region, and a channel region between the first region and the second region. The first gate metal layer of the display area can include a gate T11 of the transistor T and a first plate C11 of a capacitor C. The second gate metal layer can include a second plate C22 of the capacitor C. The second plate C22 and the first plate C11 can at least partially overlap in the orthographic projection of the plane on which the substrate 100 is located, for example, the two can coincide. The first source-drain metal layer of the display area can include a source T12 and a drain T13 of the transistor T. The source T12 of the transistor T can be electrically connected to the first region of the active layer T10, and the drain T13 can be electrically connected to the second region of the active layer T10. The second source-drain metal layer of the display area can include a transfer electrode T14, and one of the source T12 and the drain T13 is electrically connected to the transfer electrode T14 through a via provided in the first planar layer 104, for example, the drain T13 is electrically connected to the transfer electrode T14 through a via provided in the first planar layer 104. The transfer electrode T14 is configured to be electrically connected to a light emitting device to achieve electrical connection between the light emitting device and the pixel driving circuit.

[0078] The light emitting structure layer 300 can include a pixel definition layer 304 and a plurality of light emitting devices. Each light emitting device can include a first electrode 301, an organic light emitting layer 302, and a second electrode 303, which are stacked. The first electrode 301 of the light emitting device can be electrically connected to the transfer electrode T14 through a via provided in the second planar layer 105. The pixel definition layer 304 is provided on the side of the first electrode 301 away from the substrate 100, and the pixel definition layer 304 can be provided with a plurality of pixel openings, and one pixel opening can expose at least part of the surface of the corresponding first electrode 301. At least part of the organic light emitting layer 302 can be provided in one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be provided on the side of the organic light emitting layer 302 away from the substrate 100 and connected to the organic light emitting layer 302. The organic light emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303.

[0079] In some exemplary embodiments, the organic light-emitting layer 302 of the light-emitting device may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 301 and the second electrode 303, the organic light-emitting layer 302 may emit light of a corresponding color.

[0080] Figure 4 FIG. 1 is a schematic diagram of a partial structure of the first frame region of a display substrate according to an embodiment of the present disclosure. Figure 4 As shown, the display substrate may further include at least one first connection line 12, at least a portion of which is located in the first border area B1. The first connection line 12 may include a first end and a second end that are oppositely disposed. The first end may be connected to a first power line 10, and the second end may be located on a side of the first end opposite to the second direction Y. For example, the display substrate may include multiple first connection lines 12, and the multiple first connection lines 12 may be arranged in pairs with the multiple first power lines 10.

[0081] like Figure 4 As shown, the first connecting line 12 may include a plurality of lines connected in sequence, and the plurality of lines may include a first line 12-1, a second line 12-2, and a third line 12-3. The first line 12-1 and the third line 12-3 may extend along the second direction Y, and the second line 12-2 may extend along the first direction X. The second line 12-2 and the third line 12-3 may both be located in the first frame area B1, a portion of the first line 12-1 is located in the first frame area B1, and the remaining portion of the first line 12-1 is located in the display area AA. Each line has a first end and a second end that are arranged opposite to each other. The first end of the first line 12-1 is connected to the first power line 10, and the second end of the first line 12-1 is located on a side opposite to the first end of the first line 12-1 along the second direction Y. The second end of the first line 12-1 is connected to the first end of the second line 12-2, and the second end of the second line 12-2 is located on a side opposite to the first end of the second line 12-2 along the first direction X. The first end of the third trace 12 - 3 is connected to the second end of the second trace 12 - 2 , and the second end of the third trace 12 - 3 is located on a side opposite to the first end of the third trace 12 - 3 along the second direction Y.

[0082] like Figure 4 As shown, along a direction perpendicular to the plane of the substrate, the first border area B1 of the display substrate may include a first conductive layer and a second conductive layer stacked together, and the first conductive layer is closer to the substrate than the second conductive layer. For example, the first conductive layer may be arranged in the same layer as the first source and drain metal layer, and the second conductive layer may be arranged in the same layer as the second source and drain metal layer. The first power line 10 may be located in the first conductive layer, and the first data signal line DL-1 and the second data signal line DL-2 may be located in the second conductive layer. The first power line 10 and the first data signal line DL-1 and the second data signal line DL-2 are arranged in layers to avoid problems such as short circuits between signals caused by overly dense signal line layout. The first trace 12-1 extends along the second direction Y and is located between adjacent first data signal lines DL-1 and second data signal lines DL-2. The orthographic projections of the first trace 12-1 and the second power bus 21 on the substrate plane at least partially overlap. The second power bus 21 is located in the first conductive layer, while the first trace 12-1 is located in the second conductive layer. By arranging the second power bus 21 and the first trace 12-1 on different conductive layers, a short circuit between the second power bus 21 and the first trace 12-1 can be avoided. The second trace 12-2 extends along the first direction X, and the orthographic projections of the second trace 12-2 on the substrate plane partially overlap with at least one data signal line. The second trace 12-2 is located in the first conductive layer, while the data signal line is located in the second conductive layer. This prevents a short circuit between the second trace 12-2 and the data signal line.

[0083] The display substrate may further include a plurality of multiplexing control lines, which may include at least a first multiplexing control line MUX1, a second multiplexing control line MUX2, a third multiplexing control line MUX3, and a fourth multiplexing control line MUX4. The third routing line 12-3 overlaps with the orthographic projection of at least one of the multiplexing control lines on the plane where the substrate is located. The third routing line 12-3 is located in the second conductive layer, and the multiplexing control lines are located in the first conductive layer. This arrangement can avoid signal coupling between the third routing line 12-3 and the multiplexing control lines, thereby improving the display quality of the display device. For example, the third routing line 12-3 overlaps with the orthographic projections of the first multiplexing control line MUX1, the second multiplexing control line MUX2, the third multiplexing control line MUX3, and the fourth multiplexing control line MUX4 on the plane where the substrate is located.

[0084] like Figure 4As shown, the display substrate may further include at least one second power bus branch line 21-1. The second power bus branch line 21-1 may be located in the first border region B1 and located in the first conductive layer. The second power bus branch line 21-1 may extend along a second direction Y. The second power bus branch line 21-1 may include a first end and a second end disposed opposite each other. The first end may be connected to the second power bus 21, and the second end may be located on a side opposite to the second direction Y of the first end.

[0085] like Figure 4 As shown, at least a portion of the second trace 12-2 is located between the multiplexing circuit 22 and the display area AA. For example, the entire second trace 12-2 is located between the multiplexing circuit 22 and the display area AA. At least a portion of the third trace 12-3 is located on one side of the multiplexing circuit 22 along the first direction X. For example, at least a portion of the third trace 12-3 is located on a side of the multiplexing circuit 22 opposite to the first direction X.

[0086] The multiplexing circuit 22 may include at least a plurality of multiplexing control transistors 22-1. For example, the multiplexing circuit 22 may include four multiplexing control transistors 22-1, and the four multiplexing control transistors 22-1 may be arranged sequentially along the first direction X. The multiplexing control transistor 22-1 may include at least a gate, a source, and a drain. The gate (not shown) of the multiplexing control transistor 22-1 may be connected to the multiplexing control line, one of the source and the drain of the multiplexing control transistor 22-1 may be connected to the data signal line, and the other of the source and the drain of the multiplexing control transistor 22-1 may be connected to the data transmission line 30. For example, the four multiplexing control transistors 22-1 may be connected to the same data transmission line 30.

[0087] The orthographic projection of the third trace 12 - 3 on the plane where the substrate is located can be located between the orthographic projection of the second power bus branch line 21 - 1 and the multiplexing circuit 22 on the plane where the substrate is located, thereby avoiding crosstalk between different signals.

[0088] Figure 5A FIG. 1 is a schematic diagram of a partial structure of the first transition region of a display substrate according to an embodiment of the present disclosure. Figure 5AAs shown, the display substrate can further include at least one second connection line 13, at least part of the second connection line 13 can be located in the first transition area G1, the second connection line 13 can include oppositely arranged first and second ends, the first end can be connected with one first power line 10, and the second end is located on the side of the first end in the reverse direction of the second direction Y. In an example, the display substrate can include a plurality of second connection lines 13, and the number of the second connection lines 13 is less than the number of the first power lines 10. In an example, the display substrate includes a plurality of first power lines 10, part of the plurality of first power lines 10 is connected with the second connection line 13, and the remaining part of the plurality of first power lines 10 is connected with the first connection line 12. As shown, Figure 5A As shown, the second connection line 13 can include a plurality of wires connected in sequence, the plurality of wires can include a fourth wire 13-4, a fifth wire 13-5 and a sixth wire 13-6, the fourth wire 13-4 and the sixth wire 13-6 can extend along the second direction Y, the fifth wire 13-5 and the sixth wire 13-6 can be located in the first transition area G1, part of the fourth wire 13-4 can be located in the first transition area G1, and the remaining part of the fourth wire 13-4 can be located in the display area AA. Each wire has oppositely arranged first and second ends, the first end of the fourth wire 13-4 is connected with the first power line 10, and the second end of the fourth wire 13-4 is located on the side of the first end of the fourth wire 13-4 in the reverse direction of the second direction Y. The second end of the fourth wire 13-4 is connected with the first end of the fifth wire 13-5, and the second end of the fifth wire 13-5 is located on the side of the first end of the fifth wire 13-5 in the reverse direction of the second direction Y. The first end of the sixth wire 13-6 is connected with the second end of the fifth wire 13-5, and the second end of the sixth wire 13-6 is located on the side of the first end of the sixth wire 13-6 in the reverse direction of the second direction Y. As shown, Figure 5A As shown, the fourth wire 13-4 and the sixth wire 13-6 can be located in the second conductive layer, and the fifth wire 13-5 can be located in the first conductive layer. In the embodiments of the present disclosure, by arranging the second connection line, the low-voltage signals of the sub-pixels close to the first transition area and the sub-pixels close to the first frame area can be kept substantially consistent, which is beneficial to ensuring the uniformity of display.

[0089] In some example embodiments, as Figure 5AAs shown, the display substrate can further include at least one second power transmission line 21-2, at least part of the second power transmission line 21-2 can be located in the first transition area G1, one end of the second power transmission line 21-2 close to the first border area B1 can be connected with the second power bus 21, and the second power transmission line 21-2 can be connected with a plurality of second power lines 20 located in the display area AA. The second power transmission line 21-2 is used to transmit a high-voltage signal to the pixel driving circuit of the plurality of sub-pixels. The fourth trace 13-4 can at least partially overlap with the second power transmission line 21-2 in the orthographic projection of the substrate. The fourth trace 13-4 can be located in the second conductive layer, and the second power transmission line 21-2 can be located in the first conductive layer. By arranging the fourth trace 13-4 and the second power transmission line 21-2 in different conductive layers, signal crosstalk between the fourth trace 13-4 and the second power transmission line 21-2 can be avoided.

[0090] In some example embodiments, as shown in Figure 5A As shown, the fifth trace 13-5 at least partially overlaps with at least one data signal line in the orthographic projection of the substrate. The fifth trace 13-5 can be arranged in the first conductive layer, and the data signal line can be arranged in the second conductive layer. By arranging the fifth trace 13-5 and the data signal line in different conductive layers, signal crosstalk between the fifth trace 13-5 and the data signal line can be avoided.

[0091] In some example embodiments, as shown in Figure 5A As shown, the sixth trace 13-6 partially overlaps with at least one multiplexing control line in the orthographic projection of the substrate. The sixth trace 13-6 can be arranged in the second conductive layer, and the multiplexing control line can be arranged in the first conductive layer. By arranging the sixth trace 13-6 and the multiplexing control line in different conductive layers, signal crosstalk between the sixth trace 13-6 and the multiplexing control line can be avoided. For example, the sixth trace 13-6 overlaps with the first multiplexing control line MUX1, the second multiplexing control line MUX2, the third multiplexing control line MUX3, and the fourth multiplexing control line MUX4 in the orthographic projection of the substrate.

[0092] In some example embodiments, the fifth trace 13-5 of the plurality of second connection lines 13 can be an integral structure connected with each other, which can reduce the number of traces and facilitate the realization of a narrow-frame design of the display substrate.

[0093] In some example embodiments, the sixth trace 13-6 of the plurality of second connection lines 13 can be shared, which can reduce the number of traces and facilitate the realization of a narrow-frame design of the display substrate.

[0094] In some example embodiments, the line width of the fifth trace 13-5 can be about 10 microns.

[0095] In some example embodiments, the display region AA can have a first center line, which can be a straight line that bisects the display region in the first direction X and extends along the second direction Y. The first transition region G1 and the second transition region G2 can be symmetrical about the first center line.

[0096] In some example embodiments, the display substrate can further include at least one third connection line, at least a portion of the third connection line being located in the second transition region G2, and at least a portion of the third connection line can be symmetrical to at least a portion of the second connection line 13 about the first center line.

[0097] In some example embodiments, the display region AA can have a second center line, which can be a straight line that bisects the display region in the second direction Y and extends along the first direction X. The first transition region G1 and the fourth transition region G4 can be symmetrical about the second center line. The second transition region G2 and the third transition region G3 can be symmetrical about the second center line.

[0098] In some example embodiments, the display substrate can further include at least one fourth connection line, at least a portion of the fourth connection line being located in the third transition region G3, and at least a portion of the fourth connection line can be symmetrical to at least a portion of the third connection line about the second center line.

[0099] In some example embodiments, the display substrate can further include at least one fifth connection line, at least a portion of the fifth connection line being located in the fourth transition region G4, and at least a portion of the fifth connection line can be symmetrical to at least a portion of the second connection line 13 about the second center line.

[0100] Figure 5B A partial structure schematic view of a first transition region of a display substrate of another embodiment of the present disclosure is shown in FIG. 6. As shown in FIG. 6, because the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 in the display region AA are not all the same, for example, the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 are all different, as shown in FIG. 6, the second connection line 13 can be bent at a position close to each sub-pixel column, that is, at least a portion of the second connection line 13 close to the side of the display region AA can be a step shape in the orthographic projection of the plane where the substrate is located, which can reduce the space occupied by the display substrate and achieve a narrow frame of the display device. Figure 5B Figure 5B As shown in FIG. 6, because the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 in the display region AA are not all the same, for example, the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 are all different, as shown in FIG. 6, the second connection line 13 can be bent at a position close to each sub-pixel column, that is, at least a portion of the second connection line 13 close to the side of the display region AA can be a step shape in the orthographic projection of the plane where the substrate is located, which can reduce the space occupied by the display substrate and achieve a narrow frame of the display device.

[0101] In some example embodiments, the step shape can be a 90-degree step, or can be a step of other angles, and the present disclosure does not limit the angle of the step shape.

[0102] Figure 6 A partial structure schematic view of a first transition region of a display substrate of another embodiment of the present disclosure is shown in FIG. 6. As shown in FIG. 6, because the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 in the display region AA are not all the same, for example, the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 are all different, as shown in FIG. 6, the second connection line 13 can be bent at a position close to each sub-pixel column, that is, at least a portion of the second connection line 13 close to the side of the display region AA can be a step shape in the orthographic projection of the plane where the substrate is located, which can reduce the space occupied by the display substrate and achieve a narrow frame of the display device.​Figure 6 As shown, the display substrate can further include at least one auxiliary power supply line 14 and at least one reset signal line FW configured to provide a reset signal to the gate driving circuit. At least part of the auxiliary power supply line 14 and at least part of the reset signal line FW can be located in the first transition region G1. The auxiliary power supply line 14 can include oppositely arranged first and second ends. The first end of the auxiliary power supply line 14 can be connected to the second connection line 13, and the second end of the auxiliary power supply line 14 can be located on the side opposite to the first end along the first direction X. In an example, the second end of the auxiliary power supply line 14 can be located in the third bezel region B3. In an embodiment of the present disclosure, by providing the auxiliary power supply line 14, the resistance can be reduced, and the effect of current density reduction by shunting can be achieved, which can prevent the first transition region from being burned due to a large current density.

[0103] In some example embodiments, the auxiliary power supply line 14 can include a plurality of sub-line segments connected together. At least two sub-line segments of the plurality of sub-line segments can be located in different conductive layers. The plurality of sub-line segments can include a first sub-line segment 14-1, a second sub-line segment 14-2, and a third sub-line segment 14-3. The first sub-line segment 14-1, the second sub-line segment 14-2, and the third sub-line segment 14-3 can be connected in sequence. The first sub-line segment 14-1 and the third sub-line segment 14-3 can be located in the second conductive layer, and the second sub-line segment 14-2 can be located in the first conductive layer.

[0104] In some example embodiments, as shown, Figure 6 The second sub-line segment 14-2 and the reset signal line FW at least partially overlap in the orthogonal projection on the plane where the substrate is located. The second sub-line segment 14-2 can be provided on the first conductive layer, and the reset signal line FW can be provided on the second conductive layer, which can avoid signal crosstalk between the second sub-line segment 14-2 and the reset signal line FW.

[0105] Figure 7 A partial structure schematic view of the second bezel region of the display substrate of an embodiment of the present disclosure is shown. As shown, Figure 7 The display substrate can further include at least one horizontal wire 15 and at least one vertical wire 16. The horizontal wire 15 extends along the first direction X, the vertical wire 16 extends along the second direction Y, and the horizontal wire 15 and the vertical wire 16 cross and connect with each other. In an example, a plurality of horizontal wires 15 and a plurality of vertical wires 16 cross and connect with each other to form a mesh. In an example, the horizontal wire 15 and the vertical wire 16 can be located in the second bezel region B2. In an example, the horizontal wire 15 and the vertical wire 16 can be located in the second conductive layer.

[0106] The display substrate can further include a first power bus 17 located in the second frame region B2 and extending along the first direction X. The horizontal wire 15 is located on one side of the first power bus 17 along the second direction Y, and the vertical wire 16 can include oppositely arranged first and second ends, the first end being connected to the first power bus 17, and the second end being located on one side of the first end along the second direction Y. The first power bus 17 can be configured to transmit a low-voltage signal. In the embodiments of the present disclosure, by arranging the horizontal wire, the vertical wire and the first power bus, the low-voltage resistance can be reduced.

[0107] Figure 8 A schematic diagram of a planar structure of a display substrate according to another embodiment of the present disclosure is shown. The display device can have a display side and a non-display side. The display side can be a side on which the display device can display an image. When the human eye is on the display side, the image displayed by the display device can be viewed. The non-display side is opposite the display side. The sensor can be disposed on the non-display side of the display device, and thus the sensor can be referred to as an under-screen sensor. Since the sensor needs to receive light signals transmitted through the display device from the outside, the display device needs to have a higher light transmittance in the area corresponding to the sensor.

[0108] As shown in Figure 8 The display substrate can include a substrate, a display region AA on the substrate, and a peripheral region BB on the substrate and surrounding the display region AA. The display region AA can include a first region AA1 and a second region AA2 that do not overlap each other. The first region AA1 can be referred to as a sensor non-corresponding area, and the second region AA2 can be referred to as a sensor corresponding area. The light transmittance of the second region AA2 is higher than that of the first region AA1. The orthographic projection of the sensor on the display substrate can at least partially overlap the second region AA2, so that more light can pass through the display substrate and be received by the sensor. For example, a part of the orthographic projection of the sensor on the display substrate is located within the second region AA2. Alternatively, the entire orthographic projection of the sensor on the display substrate is located within the second region AA2. The first region AA1 can be a region of the display region AA other than the second region AA2.

[0109] In some example embodiments, the first region AA1 can surround at least one side of the second region AA2. For example, the second region AA2 can be located at the top center of the display region AA, and the first region AA1 can surround the second region AA2. For example, the second region AA2 can be located at the upper left corner or the upper right corner of the display region AA, and the present disclosure does not limit the location.

[0110] In some example embodiments, the display area AA can be a rectangle, for example, a round-cornered rectangle. The second area AA2 can be a circle or an ellipse or a rectangle or a pentagon or a hexagon, etc., which are not limited in the present disclosure.

[0111] In some example embodiments, as shown in FIG. 1, the display substrate can further include a first power transmission line 18 configured to transmit a low-voltage signal. The first power transmission line 18 is located in the first area AA1 and surrounds at least part of the second area AA2. For example, the first power transmission line 18 can surround the entire second area AA2. The first power transmission line 18 can be connected with the plurality of first power lines 10, which can improve the uniformity of the display area as a whole and avoid display dark areas. Figure 8 In some example embodiments, as shown in FIG. 1, the display substrate can further include a first power transmission line 18 configured to transmit a low-voltage signal. The first power transmission line 18 is located in the first area AA1 and surrounds at least part of the second area AA2. For example, the first power transmission line 18 can surround the entire second area AA2. The first power transmission line 18 can be connected with the plurality of first power lines 10, which can improve the uniformity of the display area as a whole and avoid display dark areas.

[0112] Figure 8 In some example embodiments, as shown in FIG. 1, the display substrate can further include a first power transmission line 18 configured to transmit a low-voltage signal. The first power transmission line 18 is located in the first area AA1 and surrounds at least part of the second area AA2. For example, the first power transmission line 18 can surround the entire second area AA2. The first power transmission line 18 can be connected with the plurality of first power lines 10, which can improve the uniformity of the display area as a whole and avoid display dark areas.

[0113] In some example embodiments, the sub-pixels located in the second area AA2 and at least part of the sub-pixels close to the boundary of the second area AA2 are arranged in a stepped manner.

[0114] The embodiments of the present disclosure also provide a display device including the display substrate of any of the foregoing embodiments. In some examples, the display substrate can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. However, the present disclosure is not limited thereto.

[0115] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. It should be noted that the above examples or embodiments are only exemplary and not restrictive. Therefore, the present disclosure is not limited to the content specifically shown and described herein. Various modifications, replacements, or omissions can be made to the forms and details without departing from the scope of the present disclosure.​

Claims

1. A display substrate, characterized in that: include: A substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a plurality of frame areas; a plurality of groups of data signal lines located in the display area, the plurality of groups of data signal lines being arranged at intervals along a first direction and extending along a second direction, each group of data signal lines including a first data signal line and a second data signal line; the first direction intersecting the second direction and the plane formed by the intersecting direction being parallel to the plane of the substrate; a plurality of sub-pixels located in the display area, and arranged along the second direction to form a plurality of sub-pixel columns; the first data signal line and the second data signal line located in the same group are electrically connected to different sub-pixels in the same sub-pixel column; a plurality of first power lines, located in the display area and configured to transmit low-voltage signals; The multiple frame areas include a first frame area and a second frame area arranged opposite to each other along the second direction, and a third frame area and a fourth frame area arranged opposite to each other along the first direction; the display substrate further includes at least one first connecting line, the first connecting line including a first end and a second end arranged opposite to each other, the first end being connected to the first power line, and the second end being located in the first frame area, and the first connecting line including a plurality of traces located in different conductive layers; The display substrate also includes a multiplexing circuit, which is located in the first frame area. Part of the first connecting line is located between the multiplexing circuit and the display area. Part of the first connecting line is located on one side of the multiplexing circuit along the first direction, and the first connecting line and the multiplexing circuit do not overlap in their orthographic projection on the plane of the substrate.

2. The display substrate according to claim 1, wherein At least part of the multiple first power lines are arranged in pairs with at least part of the multiple groups of data signal lines, and the first power line is located between the first data signal line and the second data signal line arranged in pairs, and the first power line and the paired data signal lines are located in different conductive layers.

3. The display substrate according to claim 1 or 2, wherein: The plurality of routing lines include a first routing line, a second routing line, and a third routing line connected in sequence, the third routing line being farther away from the display area than the first routing line, the first routing line and the third routing line both extending along the second direction, and the second routing line extending along the first direction; a first end of the first connecting line is located on the first routing line, and a second end of the first connecting line is located on the third routing line; at least a portion of the second routing line is located between the multiplexing circuit and the display area, and at least a portion of the third routing line is located on one side of the multiplexing circuit along the first direction; The display substrate further includes a second power bus located in the first frame area, the second power bus extending along the first direction, and the second power bus configured to transmit a high-voltage signal to the plurality of sub-pixels; The orthographic projections of the first routing line and the second power bus on the plane where the substrate is located at least partially overlap, and the first routing line and the second power bus are located on different conductive layers; the orthographic projections of the second routing line and at least one data signal line on the plane where the substrate is located at least partially overlap, and the second routing line and the data signal line are located on different conductive layers.

4. The display substrate according to claim 1 or 2, wherein: The peripheral area further includes at least one transition area, and at least one group of two adjacent frame areas are connected via the transition area; at least a portion of the boundary of the transition area close to the display area is an arc-shaped boundary; The display substrate further includes at least one connecting line, at least a portion of which is located in the transition region. The connecting line includes a first end and a second end oppositely disposed, the first end being connected to the first power line, and the second end being located in the transition region.

5. The display substrate according to claim 4, wherein: The at least one transition region includes a first transition region, and the first transition region is located between the first frame region and the third frame region; The connecting wires include a second connecting wire, and at least a portion of the second connecting wire is located in the first transition area; the second connecting wires include a fourth routing wire, a fifth routing wire, and a sixth routing wire connected in sequence, and the fourth routing wire is closer to the display area than the sixth routing wire; a first end of the second connecting wire is located on the fourth routing wire, and a second end of the second connecting wire is located on the sixth routing wire; The display substrate further includes a second power transmission line extending along the first direction, at least a portion of the second power transmission line is located in the transition region, and the second power transmission line is configured to be connected to a second power bus and transmit a high-voltage signal to a plurality of sub-pixels; The fourth routing line at least partially overlaps with the orthographic projection of the second power transmission line on the plane where the substrate is located, and the fourth routing line and the second power transmission line are located in different conductive layers; the fifth routing line at least partially overlaps with the orthographic projection of at least one data signal line on the plane where the substrate is located, and the fifth routing line and the data signal line are located in different conductive layers.

6. The display substrate according to claim 5, wherein: The fifth routing lines of the plurality of second connecting lines are an integrated structure connected to each other, and / or the sixth routing lines of the plurality of second connecting lines are shared.

7. The display substrate according to claim 4, wherein: The at least one transition region includes a first transition region, and the first transition region is located between the first frame region and the third frame region; The at least one connecting line includes a second connecting line, and at least a portion of the second connecting line is located in the first transition area; the display substrate also includes at least one auxiliary power line, at least a portion of the auxiliary power line is located in the first transition area, and the auxiliary power line includes a first end and a second end arranged opposite to each other, the first end is connected to the second connecting line, and the second end is located in the third frame area.

8. The display substrate according to claim 1 or 2, wherein: The display substrate also includes a plurality of horizontal lines, a plurality of vertical lines and a first power bus located in the second frame area, and the horizontal lines extend along the first direction, and the vertical lines extend along the second direction, the vertical lines are connected to the first power bus, and the horizontal lines and the vertical lines are interconnected to form a mesh; the horizontal lines and the vertical lines are located on the same conductive layer, the first power bus is located on another conductive layer, and the first power bus is configured to transmit low-voltage signals.

9. The display substrate according to claim 1 or 2, wherein: The display area includes a first area and a second area that do not overlap each other, the first area surrounds at least one side of the second area, and the plurality of first power lines are located in the first area; The display substrate also includes a first power transmission line located in the first area, and the first power transmission line surrounds at least a portion of the second area, and the first power transmission line is connected to the multiple first power lines; in the plane where the substrate is located, at least a portion of the first power transmission line is stepped.

10. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 9.

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