GTX Quad resource reuse method and system based on Xilinx FPGA

Abstract

The invention relates to a GTX Quad resource multiplexing method and system based on a Xilinx FPGA. The method comprises the steps that a public configuration module of a GTX transceiver in a protocol IP core is stripped into an independent shared resource module; constructing a standardized interface bus for connecting each protocol IP core with the independent shared resource module; dynamically allocating resource information of the quaternary phase locked loop and the channel phase locked loop according to a protocol rate demand; and deploying a priority arbitration state machine in each channel in the Quad, monitoring protocol bandwidth requirements of each channel, and performing configuration snapshot switching based on the protocol bandwidth requirements so as to realize time division multiplexing of GTX Quad resources. According to the method and the device, the common configuration module is decoupled into the independent shared resources, the standardized interface bus is constructed, the clock resources are dynamically allocated, and the snapshot is configured in a time division multiplexing manner, so that the problems of resource monopolization limitation and insufficient protocol compatibility in the prior art are solved, the GTX Quad resource multiplexing rate is improved, and multi-protocol dynamic switching can be supported.

Description

Technical Field

[0001] The present application relates to the field of FPGA high-speed serial communication technology, and in particular to a GTXQuad resource reuse method and system based on Xilinx FPGA. Background Art

[0002] In Xilinx FPGAs, the GTX Quad is the core unit for high-speed serial communication. Each Quad contains four GTX channels and shared GTX Common resources (such as PLL clock management and reset circuits). Existing Xilinx-provided protocol IP cores (such as PCIe, Aurora, and SRIO) typically bundle the GTX transceiver's physical layer configuration (including the GTX Common module) with the protocol logic, leading to the following issues:

[0003] First, there are significant resource exclusivity limitations. Different protocol IP cores within the same GTX Quad must independently access GTXCOMMON resources. However, Xilinx's default IP core hardware description layer (HDL) does not expose interface reuse for the GTXCOMMON module, preventing multiple protocol IP cores from sharing common resources within the same Quad. Second, there is insufficient protocol compatibility. In traditional solutions, the GTX transceiver's clock domain and equalizer parameters are statically configured by the protocol IP core, making them unable to adapt to the dynamic rate requirements of different protocols. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to propose a GTX Quad resource reuse method and system based on Xilinx FPGA to achieve dynamic adaptation of multiple protocols and improve resource utilization.

[0005] To solve the above technical problems, the present invention provides a Xilinx FPGA-based GTX Quad resource reuse method, including:

[0006] Separate the common configuration module of the GTX transceiver in the protocol IP core into an independent shared resource module;

[0007] Constructing a standardized interface bus connecting each of the protocol IP cores and the independent shared resource modules;

[0008] Dynamically allocate resource information of quaternary phase-locked loop and channel phase-locked loop according to protocol rate requirements;

[0009] A priority arbitration state machine is deployed in each channel within the Quad, and the protocol bandwidth requirements of each channel are monitored. Configuration snapshot switching is performed based on the protocol bandwidth requirements to enable time-sharing multiplexing of GTX Quad resources.

[0010] To solve the above technical problems, the embodiment of the present application provides a GTX Quad resource multiplexing system based on Xilinx FPGA, comprising:

[0011] A resource decoupling module is configured to strip the common configuration module of the GTX transceiver in the protocol IP core into an independent shared resource module.

[0012] An interface bus standardization module is configured to construct a standardized interface bus connecting each protocol IP core and the independent shared resource module.

[0013] A resource information allocation module is configured to dynamically allocate resource information of the quad-phase-locked loop and the channel phase-locked loop according to the protocol rate requirement.

[0014] A snapshot switching module is configured to deploy a priority arbitration state machine in each channel in the Quad, monitor the protocol bandwidth requirement of each channel, and perform configuration snapshot switching based on the protocol bandwidth requirement, so as to realize time-sharing multiplexing of the GTX Quad resource.

[0015] The embodiment of the present application provides a GTX Quad resource multiplexing method and system based on Xilinx FPGA. The method comprises the following steps: stripping the common configuration module of the GTX transceiver in the protocol IP core into an independent shared resource module; constructing a standardized interface bus connecting each protocol IP core and the independent shared resource module; dynamically allocating resource information of the quad-phase-locked loop and the channel phase-locked loop according to the protocol rate requirement; deploying a priority arbitration state machine in each channel in the Quad, monitoring the protocol bandwidth requirement of each channel, and performing configuration snapshot switching based on the protocol bandwidth requirement, so as to realize time-sharing multiplexing of the GTX Quad resource. The embodiment of the present application solves the problems of resource exclusivity limitation and insufficient protocol compatibility in the prior art by decoupling the common configuration module into an independent shared resource, constructing a standardized interface bus, dynamically allocating clock resources, and performing configuration snapshot switching for time-sharing multiplexing, and has the advantages of improving the GTX Quad resource multiplexing rate and supporting dynamic switching of multiple protocols. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the scheme in the present application, the drawings needed in the description of the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is the implementation flowchart of the GTX Quad resource multiplexing method flow provided by the embodiment of the present application based on Xilinx FPGA;

[0018] Figure 2 is a GTX Quad resource multiplexing block diagram based on Xilinx FPGA provided by another embodiment of the application;

[0019] Figure 3 is a method for implementing the process of the GTX Quad resource multiplexing based on Xilinx FPGA provided by the embodiment of the application;

[0020] Figure 4 is a first sub-process implementation flowchart of the GTX Quad resource multiplexing method based on Xilinx FPGA provided by the embodiment of the application;

[0021] Figure 5 is a second sub-process implementation flowchart of the GTX Quad resource multiplexing method based on Xilinx FPGA provided by the embodiment of the application;

[0022] Figure 6 is a third sub-process implementation flowchart of the GTX Quad resource multiplexing method based on Xilinx FPGA provided by the embodiment of the application;

[0023] Figure 7 is a fourth sub-process implementation flowchart of the GTX Quad resource multiplexing method based on Xilinx FPGA provided by the embodiment of the application;

[0024] Figure 8 is a fifth sub-process implementation flowchart of the GTX Quad resource multiplexing method based on Xilinx FPGA provided by the embodiment of the application;

[0025] Figure 9 is a GTX Quad resource multiplexing system diagram based on Xilinx FPGA provided by the embodiment of the application. DETAILED DESCRIPTION

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the specification herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the description and claims of this application as well as the above abstract are intended to cover all alternatives, modifications, and equivalents thereof. The terms "comprising", "having", "including", and "containing" used herein are meant to be open-ended terms that specifically allow for the inclusion of unspecified items, and are not meant to be limiting. The terms "first", "second", and the like used herein do not necessarily denote any ordinal, chronological or spatial relationship.

[0027] Reference to“an embodiment” herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase“in one embodiment” in various places in the specification are not necessarily referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0028] For those skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings.

[0029] The application will be described in detail below in conjunction with the drawings and embodiments.

[0030] Please refer to Figures 1 to 3 , Figure 1 An embodiment of the GTX Quad resource multiplexing method based on Xilinx FPGA is shown, Figure 2 is a GTX Quad resource multiplexing block diagram based on Xilinx FPGA provided by another embodiment of the present application, Figure 3 is an embodiment of the GTX Quad resource multiplexing method based on Xilinx FPGA.

[0031] The GTX Quad resource multiplexing method based on Xilinx FPGA provided by the present application is applicable to Xilinx 7 series to UltraScale+ architecture FPGA chips, and aims to improve the resource utilization rate of high-speed serial channels and the design flexibility of multi-service integration scenarios.

[0032] It should be noted that the method of the present application is not limited to the order of the flowchart shown Figure 1 The method includes the following steps:

[0033] S1: The common configuration module of the GTX transceiver in the protocol IP core is stripped off as an independent shared resource module.

[0034] Based on the open non-core IP hardware description layer (HDL) modification permission of Xilinx, the common configuration module (clock management, reset control) of the GTX transceiver is restructured at the physical layer. Specifically, the common configuration module (such as PLL configuration, reset synchronization) of the GTX transceiver originally integrated in each protocol IP core is independently formed as a shared resource module, and the protocol logic layer of the original IP core is retained.

[0035] Please refer to Figure 4 , Figure 4 An embodiment of step S1 is shown, described as follows:

[0036] S11: stripping the common configuration module of the GTX transceiver in the protocol IP core to generate the independent shared resource module, wherein the independent shared resource module comprises a clock management PLL unit and a reset control unit.

[0037] S12: retaining the protocol logic layer in the protocol IP core, wherein the protocol logic layer comprises a PCIe link training state machine and an Aurora frame parsing state machine.

[0038] The independent shared resource module (GTX COMMON module) refers to an independent functional entity formed by decoupling and reconstructing the physical layer common functional module originally embedded in the protocol IP core. Specifically, the clock management PLL unit and the reset control unit of the GTX transceiver can be modularly packaged by using a hardware description language to achieve this. The module provides clock distribution and reset control services to the outside through a standardized interface. The clock management PLL unit refers to a phase-locked loop circuit that generates multiple clock signals and synchronizes the phases. Specifically, the QPLL resource in the Xilinx GTXE2_COMMON primitive can be configured to generate reference clocks of different frequencies by dynamically adjusting the frequency division coefficient. The reset control unit refers to a timing control module that coordinates the global reset and local reset of the transceiver. Specifically, a multi-level reset synchronization circuit driven by a state machine can be used to achieve this, ensuring the synchronized release of cross-clock-domain reset signals. The protocol logic layer refers to a functional module that implements protocol standard specification processing, such as the link training state machine in the PCIe protocol and the frame parsing state machine in the Aurora protocol. Specifically, the logic circuit responsible for protocol negotiation and data encapsulation in the IP core can be retained to achieve this. The IP core (Intellectual Property Core) is a pre-designed reusable functional module (such as the PCIe and Ethernet protocol stack) that is directly integrated into the FPGA design.

[0039] Specifically, the physical layer and the protocol layer of the protocol IP core are decoupled through hardware description layer reconstruction, and the GTX common resource configuration module originally integrated in the IP core is independently packaged as a shareable functional module. In specific implementation, the clock generation unit and the reset control unit of the GTX transceiver are separated from the IP core to form an independent hardware module using modular design methods. The module is connected to multiple protocol IP cores through a standardized interface bus, providing unified clock distribution and reset control services for different protocols. At the same time, the link training state machine and the data frame parsing logic specific to each protocol IP core are retained to maintain the complete functionality of the protocol layer. For example, in the PCIe protocol implementation, the link training state machine is retained for negotiating link rate and width, and in the Aurora protocol, the frame parsing state machine is retained for extracting payload data.

[0040] The traditional scheme hard-binds the physical layer configuration module with the protocol logic layer, resulting in that different protocol IP cores in the same Quad cannot share common resources. The embodiment of the present application breaks through the architecture limitation of the default IP core of Xilinx by decoupling the physical layer from the protocol layer, so that multiple protocol IP cores can share the same set of clock management and reset control resources. For example, the existing technology requires independent QPLL resources for running PCIe and Aurora protocols, while the embodiment of the present application allows the two protocols to share the QPLL module in the same Quad. Therefore, the embodiment of the present application effectively eliminates the exclusive limitation of the protocol IP core on the common resources of the GTX, and realizes the sharing and multiplexing of the clock management and reset control resources of multiple protocol IP cores in the same Quad. Specifically, under the premise of maintaining the integrity of the protocol logic function, the embodiment of the present application reduces the repeated configuration of the physical layer resources, improves the multiplexing efficiency of the Quad resources, and thus reduces the hard requirement of the FPGA chip size for a multi-protocol system. For example, in the heterogeneous protocol mixed running scene, the hardware waste caused by separately allocating Quad resources for each protocol can be avoided.

[0041] S2: Construct a standardized interface bus connecting each protocol IP core and the independent shared resource module.

[0042] Specifically, a uniform interface bus (such as a clock output interface and a dynamic reset request signal) is defined for the independent shared resource module, so that each protocol IP core is connected with the independent shared resource module. The standardized interface bus refers to a hardware connection system with a uniform timing specification, which can be implemented by using a self-defined parallel bus structure and includes clock distribution, reset synchronization and configuration writing function modules, and is used to establish a physical layer interaction channel between the multi-protocol IP core and the shared resource.

[0043] Please refer to Figure 5 , Figure 5 A specific implementation of step S2 is shown as follows:

[0044] S21: Divide the reference clock output by the quad phase-locked loop into multiple phase-synchronized clock signals, and connect each clock signal to the target protocol IP core through an independent buffer;

[0045] S22: Adopt an asynchronous reset synchronization release mechanism to distribute the global reset signal generated by the independent shared resource module to each protocol IP core after synchronization processing;

[0046] S23: Write the PLL frequency division coefficient, equalizer parameter and channel binding configuration into each protocol IP core through a programmable interface.

[0047] Specifically, after the reference clock is output by the quaternary phase-locked loop, a plurality of phase-synchronized signals are generated by a clock distribution network, each signal is driven by an independent buffer and then transmitted to a corresponding protocol IP core, which not only maintains strict synchronization of the clock phase, but also isolates signal crosstalk between different protocols through the buffer. After the global reset signal is generated in the independent shared resource module, it first triggers the asynchronous reset circuit, and then synchronously releases in the local clock domain of the target protocol IP core through two-stage synchronous registers, which ensures the reliable transmission of the reset state across the clock domain. Each protocol IP core accesses the configuration register of the shared resource module through the bus interface, dynamically writes the PLL division coefficient, equalizer parameter and channel binding configuration, which enables different protocols to adjust the physical layer parameters according to real-time needs, breaking the limitations of the traditional fixed configuration mode.

[0048] The plurality of phase-synchronized clock signals refer to splitting the same reference clock source into a plurality of copies with strictly aligned phases, which can be implemented by using a digital delay-locked loop in combination with a clock tree balancing technique to ensure that the clock signals received by each protocol IP core have a determined phase relationship. The independent buffer refers to a signal isolation unit arranged on the clock transmission path, which can be implemented by using the BUFGCTRL primitive to eliminate the mutual interference of the clock networks between different protocol IP cores. The asynchronous reset synchronous release mechanism refers to synchronously processing the global reset signal in the target clock domain through two or more registers, which can be implemented by using a cross-clock-domain synchronization circuit to eliminate the metastability risk in the transmission process of the reset signal. The programmable interface refers to a register access channel that supports dynamic parameter configuration, which can be implemented by using the APB bus protocol to allow different protocol IP cores to adjust the transmitter operating parameters as needed.

[0049] In the traditional scheme, the protocol IP core directly calls the GTX transceiver hard core, resulting in non-uniform interface specifications, phase deviation of clock signals of different protocols, asynchronous operation of reset signals easily causing logic conflicts, and lack of dynamic adjustment capability of parameter configuration. The embodiments of the present application establish a unified resource access specification through a standardized interface bus, eliminate clock deviation between multiple protocols by using phase-synchronized clock distribution, ensure the reliability of the system reset state by using an asynchronous reset synchronous release mechanism, and implement runtime reconstruction of the transceiver parameters by using a programmable interface. The embodiments of the present application effectively eliminate the clock phase mismatch problem when multiple protocol IP cores share resources, avoid logic conflicts caused by asynchronous reset signals, and meet the dynamic configuration needs of different protocols for transceiver parameters. The design enables multiple protocol IP cores in the same GTX Quad to work stably and cooperatively, supports online update of hardware parameters while maintaining the synchronization accuracy of the clock, and provides infrastructure protection for multi-protocol time-sharing multiplexing.

[0050] S3: Dynamically allocate resource information of the quaternary phase-locked loop and the channel phase-locked loop according to the protocol rate requirement.

[0051] Specifically, based on the limited quad phase-locked loop (1) and channel phase-locked loop (1 per channel) resources in the GTX Quad, a dynamic configuration strategy is designed to adjust the PLL division ratio, equalizer parameters and transceiver operating mode in real time according to the protocol rate requirement (such as 5Gbps of PCIe 2.0 and 10Gbps of Aurora), so as to realize time-sharing multiplexing of heterogeneous protocols. That is, in the embodiments of the present application, the resource information of the quad phase-locked loop and the channel phase-locked loop is dynamically allocated according to the protocol rate requirement.

[0052] Among them, the quad phase-locked loop (QPLL, Quad PLL) is a high-frequency phase-locked loop integrated in the GTX Quad, which provides a reference clock for the entire Quad and supports high-speed protocols (such as above 10Gbps). The channel phase-locked loop (CPLL, Channel PLL) is a phase-locked loop independently configured for each GTX channel, which supports dynamic division ratio adjustment and adapts to medium and low-speed protocols (such as 3-6Gbps).

[0053] Please refer to Figure 6 , Figure 6 An embodiment of step S3 is shown as follows:

[0054] S31: If the protocol rate requirement is a first protocol rate, allocate the resource information of the quad phase-locked loop.

[0055] S32: If the protocol rate requirement is a second protocol rate, dynamically adjust the division ratio of the quad phase-locked loop and the channel phase-locked loop, so that a single channel phase-locked loop meets the second protocol rate.

[0056] Specifically, the PLL operating mode is divided according to the protocol rate requirement. When the protocol rate requirement is a first protocol rate (≥10Gbps, such as Aurora 10G), which is a QPLL dedicated mode, QPLL resources are allocated, and a high-precision clock is fixedly output. When the protocol rate requirement is a second protocol rate, which is a low-speed protocol (such as PCIe 2.0 5Gbps or SRIO 3.125Gbps), the frequency division ratio of the four-phase phase-locked loop and the channel phase-locked loop is dynamically adjusted (such as 1:2 to 1:8), so that a single channel phase-locked loop meets the second protocol rate. The frequency division ratio refers to the ratio of the output clock frequency of the phase-locked loop to the input reference clock frequency, and can be specifically realized by modifying the frequency division coefficient parameter in the phase-locked loop register, which determines the frequency accuracy and jitter characteristics of the output clock. The embodiment of the application solves the protocol rate compatibility problem caused by the fixed frequency division ratio of the phase-locked loop, and realizes time division multiplexing of different rate protocols in the same GTX Quad. For example, when the system needs to switch from a 10Gbps Aurora protocol to a 2.5Gbps SATA protocol, no additional quad phase-locked loop resources are required, and rate adaptation can be completed by only adjusting the channel phase-locked loop frequency division ratio, thereby reducing the dependence on Quad resources and improving hardware utilization in a multi-protocol scenario.

[0057] S4: A priority arbitration state machine is deployed in each channel in the Quad, and the protocol bandwidth requirements of each channel are monitored, and configuration snapshot switching is performed based on the protocol bandwidth requirements, so that time division multiplexing of GTX Quad resources is realized.

[0058] Specifically, priority arbitration logic is deployed among the four channels in the Quad, and protocol bandwidth requirements are monitored in real time, and time division multiplexing is realized through configuration snapshot switching. For example, when channel 1 runs a PCIe protocol, the QPLL occupation of channel 2 is dynamically closed, and the CPLL frequency division ratio is switched to match the rate, to ensure clock domain isolation and timing convergence when multiple protocols are run in parallel. The configuration snapshot switching is a key technology for dynamically adjusting hardware parameters to support multi-protocol time division multiplexing. The core is to pre-store the hardware configuration states (i.e., “snapshots”) required by different protocols, and quickly switch these states according to the protocol requirements at runtime, thereby efficiently multiplexing limited physical resources (such as PLLs, clock domains, etc.).

[0059] In one specific embodiment, high-speed protocols (10Gbps+) are supported by QPLL, medium and low-speed protocols (3-6Gbps) are adapted by CPLL, and dynamic switching configuration is realized by using a channel state machine, so that a single Quad can stably run up to four protocols (such as PCIe+Aurora+SRIO) at the same time in actual measurement, and the resource multiplexing rate is improved by 300%.

[0060] Please refer toFigure 7 , Figure 7 One embodiment of step S4 is shown as follows:

[0061] S41: deploying the priority arbitration state machine in each lane of the Quad.

[0062] S42: monitoring the change of bandwidth requirement of each lane protocol, and suspending the current low-priority lane by the priority arbitration state machine when a new protocol access request is detected.

[0063] S43: pre-storing multiple sets of hardware configuration snapshots in the non-volatile memory, and switching the hardware configuration snapshot based on the new protocol to realize time-sharing multiplexing of GTX Quad resources.

[0064] Specifically, when the lane bandwidth monitoring module detects a new protocol access request, the arbitration state machine suspends the data transmission of the current low-priority lane according to the preset priority rule, and freezes the physical layer configuration state at the same time. At this time, the system loads the hardware configuration snapshot corresponding to the target protocol from the non-volatile memory, writes the pre-stored transceiver parameters into the control register in batches through the bus interface, and then starts the clock link relocking and signal integrity verification process. After the eye diagram monitoring module at the receiving end confirms that the signal quality meets the standard, the arbitration state machine resumes the data transmission of the target protocol lane and updates the priority mapping table, thereby realizing multi-protocol dynamic switching without increasing physical resources. The priority arbitration state machine refers to a lane priority dynamic management system established by a finite state machine model, which can be specifically implemented by using state transition logic based on a weighted round-robin algorithm, and is used for real-time evaluation of the priority of each lane protocol and execution of resource allocation decisions. The protocol bandwidth requirement monitoring refers to a technical means for counting the lane data throughput by using a hardware counter, which can be specifically implemented by using a FIFO depth monitoring module built-in the transceiver, and is used for triggering configuration switching events. The hardware configuration snapshot refers to a set of physical layer parameters pre-stored in a storage medium, which can be specifically stored in the form of FPGA configuration register image file, and contains key configuration parameters such as transceiver equalizer parameters and clock division ratio.

[0065] In the conventional scheme, different protocols need to exclusively use the GTX Quad resource and cannot dynamically adjust the configuration parameters, resulting in low utilization of physical layer resources. Embodiments of the present application eliminate the parameter reconfiguration delay during protocol switching through the hardware configuration snapshot prestorage and dynamic loading mechanism, while the priority arbitration state machine guarantees the quality of service of high-priority protocols, solving the resource competition problem in the multi-protocol concurrent scenario. Embodiments of the present application effectively solve the resource conflict problem during dynamic switching of multiple protocols in the same GTX Quad, implement on-demand allocation of physical resources through the hardware-level configuration parameter fast switching mechanism, significantly improve the multiplexing efficiency of high-speed serial interface resources, and avoid the problem of increased hardware cost caused by resource monopoly in the conventional scheme.

[0066] Please refer to Figure 8 , Figure 8 An embodiment of step S43 is shown as follows:

[0067] S431: Prestore the plurality of groups of hardware configuration snapshots in the non-volatile memory, wherein each group of hardware configuration snapshots includes the QPLL / CPLL frequency division ratio required by the target protocol, the transceiver equalizer parameters, and the lock threshold of the clock data recovery CDR module.

[0068] S432: When the request of the new protocol is received, suspend the data transmission of the current channel, and save the current configuration state to a temporary buffer area.

[0069] S433: Load the target protocol configuration parameters from the hardware configuration snapshot to the channel control register, and start the clock relocking and link training process.

[0070] S434: When the receiver signal eye diagram quality monitor returns a lock success signal, resume the channel data transmission and update the protocol priority table.

[0071] Specifically, by pre-storing configuration snapshots containing QPLL / CPLL frequency division ratio, equalizer parameters and CDR lock threshold, a dynamically loadable physical layer parameter system is constructed. When a new protocol access request is detected, the data transmission of the current low-priority channel is first suspended, and the running transceiver parameters are saved to a temporary buffer area to ensure that the original configuration information is not lost during the protocol switching process. Then the target protocol configuration parameters are extracted from the non-volatile memory, and the physical layer parameters are quickly switched by directly writing into the channel control register. After the parameter loading is completed, the lock process of the clock data recovery module is started, and the establishment of the new protocol clock domain is completed through the built-in clock calibration circuit of the GTX. At the same time, the link training state machine is triggered, and the negotiation handshake process is performed according to the target protocol specification. In this process, the signal quality monitoring unit of the receiving end continuously detects the eye diagram opening, and feeds back a lock success signal when the bit error rate is lower than the preset threshold, triggering the channel data transmission recovery and updating the protocol priority table, completing the complete dynamic switching process.

[0072] Among them, the hardware configuration snapshot refers to the complete configuration set containing the physical layer parameters required for protocol running, which can be implemented by using Flash or EEPROM memory, and is used to save the key parameters such as QPLL / CPLL frequency division ratio, equalizer parameters and CDR lock threshold corresponding to different protocols, so as to realize the quick calling of protocol parameters. The temporary buffer area refers to a storage area for temporarily storing the running state of the current protocol, which can be implemented by using the internal Block RAM of the FPGA, and is used to maintain the integrity of the original configuration during the protocol switching process. The signal eye diagram quality monitor refers to a hardware module for evaluating the integrity of the received signal, which can be implemented by using the bit error rate test unit integrated in the GTX receiver, and the link lock state is judged by monitoring the eye diagram opening, jitter margin and other indicators. The embodiments of the application solve the protocol switching obstacles caused by static solidification of physical layer parameters, and realize the dynamic multiplexing of GTX Quad resources in a multi-protocol scenario. Through the pre-storage and calling mechanism of the hardware configuration snapshot, a single GTX channel can adapt to the physical layer parameter requirements of different protocols, avoiding the hardware resource conflicts caused by protocol switching in the traditional scheme. By using the switching mode combining configuration state caching and register direct writing, the business interruption time during protocol switching is significantly shortened while ensuring the integrity of protocol data. Combined with the closed-loop feedback mechanism of signal quality monitoring, the stability and reliability of the link after dynamic switching are ensured, and the system resource utilization in the multi-protocol integration scenario is effectively improved.

[0073] In the embodiment of the application, the common configuration module of the GTX transceiver in the protocol IP core is stripped off as an independent shared resource module; a standardized interface bus connecting each protocol IP core and the independent shared resource module is constructed; resource information of a quadrature phase locked loop and a channel phase locked loop is dynamically allocated according to protocol rate requirements; a priority arbitration state machine is deployed in each channel in the Quad, and the protocol bandwidth requirements of each channel are monitored, and configuration snapshot switching is performed based on the protocol bandwidth requirements, so that the time multiplexing of the GTX Quad resource is realized. Through decoupling the common configuration module into an independent shared resource, constructing a standardized interface bus, dynamically allocating clock resources and time multiplexing configuration snapshots, the embodiment of the application solves the problems of resource exclusivity limitation and insufficient protocol compatibility in the prior art, and has the advantages of improving the GTX Quad resource multiplexing rate and supporting multi-protocol dynamic switching.

[0074] Through the resource decoupling and dynamic allocation mechanism, the embodiment of the application enables different protocols to share the common resources in the same Quad, while supporting dynamic adjustment of protocol rates. The prior art cannot adapt to a multi-protocol mixed scene due to the dependence on statically configured PLL parameters, while the application achieves flexible adaptation of protocol rates through dynamic adjustment of frequency division ratios and configuration snapshot switching. In addition, the traditional scheme needs to allocate an independent Quad unit for each protocol, and the embodiment of the application significantly reduces the hardware resource occupation through time multiplexing. In addition, the embodiment of the application enables the same GTX Quad to carry multiple heterogeneous protocols, improves the hardware resource utilization rate, realizes multi-protocol rate compatible operation through a dynamic clock allocation mechanism, expands the application scene adaptability, reduces the link reconstruction time during protocol switching through configuration snapshot fast switching, and improves the system response efficiency.

[0075] For a better understanding of the present application, reference will be made to the following Figure 9 , as an implementation of the method shown in Figure 1 , the application provides an embodiment of a GTX Quad resource multiplexing system based on Xilinx FPGA, which corresponds to the method embodiment shown in Figure 1 . The system can be applied to various electronic devices.

[0076] As shown in Figure 9 , the GTX Quad resource multiplexing system based on Xilinx FPGA of the embodiment includes a resource decoupling module 51, an interface bus standardization module 52, a resource information allocation module 53 and a snapshot switching module 54, wherein:

[0077] The resource decoupling module 51 is used to strip off the common configuration module of the GTX transceiver in the protocol IP core as an independent shared resource module;

[0078] An interface bus standardization module 52 is configured to construct a standardized interface bus connecting each protocol IP core and the independent shared resource module;

[0079] A resource information allocation module 53 is configured to dynamically allocate resource information of the quad phase-locked loop and the channel phase-locked loop according to protocol rate requirements;

[0080] A snapshot switching module 54 is configured to deploy a priority arbitration state machine in each channel in the Quad, monitor protocol bandwidth requirements of each channel, and configure snapshot switching based on the protocol bandwidth requirements, so as to time-multiplex the GTX Quad resources.

[0081] Further, the resource decoupling module 51 comprises:

[0082] A stripping unit is configured to strip a common configuration module of a GTX transceiver in the protocol IP core to generate the independent shared resource module, wherein the independent shared resource module comprises a clock management PLL unit and a reset control unit.

[0083] A protocol logic layer reservation unit is configured to reserve a protocol logic layer in the protocol IP core, wherein the protocol logic layer comprises a PCIe link training state machine and an Aurora frame parsing state machine.

[0084] Further, the interface bus standardization module 52 comprises:

[0085] A clock signal division unit is configured to divide a reference clock output by the quad phase-locked loop into multiple phase-synchronous clock signals, and connect each clock signal to a target protocol IP core through an independent buffer.

[0086] A global reset signal generation unit is configured to adopt an asynchronous reset synchronous release mechanism, and distribute a global reset signal generated by the independent shared resource module to each protocol IP core after synchronization processing.

[0087] A parameter writing unit is configured to write a PLL frequency division coefficient, an equalizer parameter, and a channel binding configuration into each protocol IP core through a programmable interface.

[0088] Further, the snapshot switching module 54 comprises:

[0089] A state machine deployment unit is configured to deploy the priority arbitration state machine in each channel in the Quad.

[0090] A state machine suspension unit is configured to monitor changes in protocol bandwidth requirements of each channel, and suspend the priority arbitration state machine for a current low-priority channel when a new protocol access request is detected.

[0091] The snapshot switching implementation unit is configured to pre-store multiple groups of hardware configuration snapshots in the non-volatile memory and perform the hardware configuration snapshot switching based on the new protocol, so as to realize time-sharing multiplexing of the GTX Quad resources.

[0092] Further, the snapshot switching implementation unit comprises:

[0093] The snapshot pre-storing sub-unit is configured to pre-store the multiple groups of hardware configuration snapshots in the non-volatile memory, wherein each group of the hardware configuration snapshots comprises a QPLL / CPLL frequency division ratio required by a target protocol, a transceiver equalizer parameter and a lock threshold of a clock data recovery (CDR) module.

[0094] The state saving sub-unit is configured to pause data transmission of a current channel and save a current configuration state to a temporary buffer area when a request of the new protocol is received.

[0095] The parameter loading sub-unit is configured to load the target protocol configuration parameters from the hardware configuration snapshots to channel control registers and start a clock re-locking and link training process.

[0096] The priority table updating sub-unit is configured to resume channel data transmission and update a protocol priority table when a lock success signal is returned by an end signal eye diagram quality monitor.

[0097] Further, the resource information allocation module 53 comprises:

[0098] The first allocation unit is configured to allocate resource information of the quad phase-locked loop if the protocol rate requirement is a first protocol rate.

[0099] The second allocation unit is configured to dynamically adjust a frequency division ratio of the quad phase-locked loop and the channel phase-locked loop if the protocol rate requirement is a second protocol rate, so that a single channel phase-locked loop satisfies the second protocol rate.

[0100] In the embodiment of the present application, the resource decoupling module is used to strip the common configuration module of the GTX transceiver in the protocol IP core into an independent shared resource module; the interface bus standardization module is used to construct a standardized interface bus connecting each protocol IP core and the independent shared resource module; the resource information distribution module is used to dynamically distribute resource information of the four-phase phase-locked loop and the channel phase-locked loop according to the protocol rate requirement; the snapshot switching module is used to deploy a priority arbitration state machine in each channel in the Quad and monitor the protocol bandwidth requirement of each channel, and configure snapshot switching based on the protocol bandwidth requirement to realize time division multiplexing of the GTX Quad resource. The embodiment of the present application solves the problems of resource exclusivity limitation and insufficient protocol compatibility in the prior art by decoupling the common configuration module into an independent shared resource, constructing a standardized interface bus, dynamically distributing clock resources, and time division multiplexing configuration snapshots, and has the advantages of improving the GTX Quad resource multiplexing rate and supporting multi-protocol dynamic switching.

[0101] Obviously, the above-described embodiments are only some of the embodiments of the present application, not all the embodiments, and the preferred embodiments of the present application are given in the drawings, but do not limit the scope of the present application. The present application can be implemented in many different forms, and conversely, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing specific embodiments or equivalently replace some of the technical features. Any equivalent structure made by using the content of the specification and drawings, directly or indirectly applied to other related technical fields, is also within the protection scope of the present application.

Claims

1. A GTX Quad resource reuse method based on Xilinx FPGA, characterized in that: include: Separate the common configuration module of the GTX transceiver in the protocol IP core into an independent shared resource module; Constructing a standardized interface bus connecting each of the protocol IP cores and the independent shared resource modules; Dynamically allocate resource information of quaternary phase-locked loop and channel phase-locked loop according to protocol rate requirements; A priority arbitration state machine is deployed in each channel within the Quad, and the protocol bandwidth requirements of each channel are monitored. Configuration snapshot switching is performed based on the protocol bandwidth requirements to enable time-sharing multiplexing of GTX Quad resources.

2. The GTX Quad resource reuse method based on Xilinx FPGA according to claim 1, characterized in that: The method of separating the common configuration module of the GTX transceiver in the protocol IP core into an independent shared resource module includes: Stripping the common configuration module of the GTX transceiver in the protocol IP core to generate the independent shared resource module, wherein the independent shared resource module includes a clock management PLL unit and a reset control unit; The protocol logic layer in the protocol IP core is retained, wherein the protocol logic layer includes a PCIe link training state machine and an Aurora frame parsing state machine.

3. The GTX Quad resource reuse method based on Xilinx FPGA according to claim 1, characterized in that: The step of constructing a standardized interface bus connecting each of the protocol IP cores and the independent shared resource modules includes: Divide the reference clock output by the quaternary phase-locked loop into multiple phase-synchronized clock signals, and connect each clock signal to the target protocol IP core through an independent buffer; Adopting an asynchronous reset synchronous release mechanism, the global reset signal generated by the independent shared resource module is distributed to each of the protocol IP cores after synchronization processing; The PLL frequency division coefficient, equalizer parameters and channel bonding configuration are written into each of the protocol IP cores through a programmable interface.

4. The GTX Quad resource reuse method based on Xilinx FPGA according to claim 1, characterized in that: The method includes deploying a priority arbitration state machine in each channel of the Quad, monitoring the protocol bandwidth requirements, and performing configuration snapshot switching based on the protocol bandwidth requirements to enable time-sharing multiplexing of GTX Quad resources, including: Deploy the priority arbitration state machine in each channel of the Quad; monitoring changes in bandwidth requirements of each of the channel protocols, and suspending the priority arbitration state machine on a current low-priority channel when a new protocol access request is detected; Multiple sets of hardware configuration snapshots are pre-stored in a non-volatile memory, and the hardware configuration snapshots are switched based on the new protocol to enable time-sharing multiplexing of GTX Quad resources.

5. The GTX Quad resource reuse method based on Xilinx FPGA according to claim 4, characterized in that: Pre-storing multiple sets of hardware configuration snapshots in a non-volatile memory and switching the hardware configuration snapshots based on the new protocol to enable time-sharing multiplexing of GTX Quad resources includes: Pre-storing the multiple groups of hardware configuration snapshots in the non-volatile memory, wherein each group of the hardware configuration snapshots includes the QPLL / CPLL frequency division ratio, transceiver equalizer parameters, and the lock threshold of the clock data recovery (CDR) module required by the target protocol; When receiving a request for the new protocol, suspending data transmission on the current channel and saving the current configuration state to a temporary buffer; Loading the target protocol configuration parameters from the hardware configuration snapshot into the channel control register and initiating clock relocking and link training processes; When the signal eye diagram quality monitor at the receiving end returns a lock success signal, channel data transmission is resumed and the protocol priority table is updated.

6. The GTX Quad resource reuse method based on Xilinx FPGA according to any one of claims 1 to 5, characterized in that: The resource information of the quaternary phase-locked loop and the channel phase-locked loop is dynamically allocated according to the protocol rate requirement, including: If the protocol rate requirement is the first protocol rate, allocating resource information of the quaternary phase-locked loop; If the protocol rate requirement is a second protocol rate, the frequency division ratio of the quaternary phase-locked loop and the channel phase-locked loop is dynamically adjusted so that a single channel phase-locked loop meets the second protocol rate.

7. A GTX Quad resource reuse system based on Xilinx FPGA, characterized in that: include: Resource decoupling module, used to separate the common configuration module of the GTX transceiver in the protocol IP core into independent shared resource modules; An interface bus standardization module, used to construct a standardized interface bus connecting each of the protocol IP cores and the independent shared resource modules; Resource information allocation module, used to dynamically allocate resource information of quaternary phase-locked loop and channel phase-locked loop according to protocol rate requirements; The snapshot switching module is used to deploy a priority arbitration state machine in each channel within the Quad, monitor the protocol bandwidth requirements of each channel, and configure snapshot switching based on the protocol bandwidth requirements to enable time-sharing multiplexing of GTX Quad resources.

8. The Xilinx FPGA-based GTX Quad resource reuse system according to claim 7, characterized in that: The resource decoupling module includes: a stripping unit, configured to strip the common configuration module of the GTX transceiver in the protocol IP core to generate the independent shared resource module, wherein the independent shared resource module includes a clock management PLL unit and a reset control unit; The protocol logic layer retaining unit is used to retain the protocol logic layer in the protocol IP core, wherein the protocol logic layer includes a PCIe link training state machine and an Aurora frame parsing state machine.

9. The Xilinx FPGA-based GTX Quad resource reuse system according to claim 7, characterized in that: The interface bus standardization module includes: A clock signal division unit, configured to divide the reference clock output by the quaternary phase-locked loop into multiple phase-synchronized clock signals, and connect each clock signal to the target protocol IP core through an independent buffer; A global reset signal generating unit, configured to adopt an asynchronous reset synchronous release mechanism to distribute the global reset signal generated by the independent shared resource module to each of the protocol IP cores after synchronization processing; The parameter writing unit is used to write the PLL frequency division coefficient, equalizer parameters and channel binding configuration of each protocol IP core through a programmable interface.

10. The Xilinx FPGA-based GTX Quad resource reuse system according to claim 7, characterized in that: The snapshot switching module includes: A state machine deployment unit, configured to deploy the priority arbitration state machine in each channel within the Quad; a state machine suspension unit, configured to monitor changes in bandwidth requirements of each of the channel protocols, and suspend the priority arbitration state machine on the current low-priority channel when a new protocol access request is detected; The snapshot switching implementation unit is used to pre-store multiple sets of hardware configuration snapshots in a non-volatile memory and perform the hardware configuration snapshot switching based on the new protocol to achieve time-sharing multiplexing of GTX Quad resources.

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