Semiconductor package

Abstract

The invention relates to a semiconductor package. The semiconductor package includes: a first semiconductor chip; at least one second semiconductor chip; the first end of the switch protection circuit is connected with the first semiconductor chip, the second end of the switch protection circuit is connected with each second semiconductor chip, and the switch protection circuit is in a turn-off state when the semiconductor package is used for charging device model (CDM) discharging. The first semiconductor chip and the second semiconductor chip are connected to each other to disconnect the connection between the first semiconductor chip and the second semiconductor chip. Therefore, when CDM discharge is carried out on the semiconductor package, the probability that the semiconductor package is burnt out due to electrostatic discharge is reduced.

Description

A semiconductor package

[0001] The present disclosure relates to the field of storage technology, and in particular to a semiconductor package.

[0002] Integrated Circuit (IC) chips are easily subjected to destructive electrostatic discharge (ESD) during manufacturing, assembly and testing or in final applications, which can damage IC chips. Currently, ESD protection for IC chips still needs to be further optimized to meet demand.

[0003] Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor chip and a semiconductor package.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor package, including:

[0006] a first semiconductor chip;

[0007] at least one second semiconductor chip; and

[0008] A switch protection circuit, wherein a first end of the switch protection circuit is connected to the first semiconductor chip, a second end of the switch protection circuit is connected to each of the second semiconductor chips, and when the semiconductor package performs a charged device model (CDM) discharge, the switch protection circuit is in an off state to disconnect the connection between the first semiconductor chip and the second semiconductor chip.

[0009] In the above solution, when the semiconductor package works normally, the switch protection circuit is in a conducting state to connect the first semiconductor chip and the second semiconductor chip.

[0010] In the above solution, the switch protection circuit is arranged in the first semiconductor chip and comprises: a first sub-circuit; wherein,

[0011] A first end of the first subcircuit is connected to a first node in the first semiconductor chip, a second end of the first subcircuit is connected to a second node in the first semiconductor chip, a control end of the first subcircuit is connected to a first control signal, and when the first control signal is connected to a first state, the first subcircuit is in a disconnected state, or when the first control signal is connected to a second state, the first subcircuit is in a conducting state;

[0012] When the first sub-circuit is in a disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in a connected state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0013] In the above scheme, the switch protection circuit further includes: a second sub-circuit; wherein the second sub-circuit includes a first capacitive element, a first end of the first capacitive element is connected between the second end of the first sub-circuit and a second node in the first semiconductor chip, and a second end of the first capacitive element is connected to a third node in the first semiconductor chip;

[0014] The control terminal of the first sub-circuit is connected between the second terminal of the first capacitive element and the third node.

[0015] In the above scheme, the switch protection circuit further includes: a second sub-circuit; wherein the second sub-circuit includes a second capacitive element, a first end of the second capacitive element is connected between the second end of the first sub-circuit and the second node of the first semiconductor chip; a second end of the second capacitive element is connected to a first node in a second semiconductor chip;

[0016] The control terminal of the first sub-circuit is connected between the second terminal of the second capacitive element and a first node in the second semiconductor chip.

[0017] In the above solution, the second sub-circuit further includes: a first resistive element, a first end of the first resistive element is connected to the third node in the first semiconductor chip; a second end of the first resistive element is connected to a second end of the first capacitive element;

[0018] The control terminal of the first sub-circuit is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0019] In the above solution, the second sub-circuit further includes: a second resistive element, a first end of the second resistive element is connected to a first node in the second semiconductor chip; a second end of the second resistive element is connected to a second end of the second capacitive element;

[0020] The control terminal of the first sub-circuit is connected between the second terminal of the second capacitive element and the second terminal of the second resistor.

[0021] In the above solution, the first sub-circuit includes: a first N-type metal oxide semiconductor (NMOS) transistor.

[0022] In the above scheme, wherein the first resistive element comprises at least one resistor connected in series; the first capacitive element comprises at least one capacitor connected in series;

[0023] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0024] In the above solution, wherein the second resistive element comprises at least one resistor connected in series; the second capacitive element comprises at least one capacitor connected in series;

[0025] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0026] In the above scheme, the first node in the first semiconductor chip is connected to the ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to the ground pin of the first semiconductor chip; and the third node in the first semiconductor chip is connected to the power PAD in the first semiconductor chip.

[0027] In the above scheme, the first node in the first semiconductor chip is connected to the ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to the ground pin of the first semiconductor chip; the first node in a certain second semiconductor chip is connected to the power PAD in a certain second semiconductor chip.

[0028] In the above solution, the switch protection circuit is arranged in each second semiconductor chip and comprises: a third sub-circuit; wherein,

[0029] A first end of the third subcircuit is connected to a second node in the second semiconductor chip, a second end of the third subcircuit is connected to a third node in the second semiconductor chip, a control end of the third subcircuit is connected to a second control signal, and when the second control signal in the first state is connected, the third subcircuit is in a disconnected state, or, when the second control signal in the second state is connected, the third subcircuit is in a conducting state;

[0030] When the third sub-circuit is in a disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the third sub-circuit is in a conductive state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0031] In the above scheme, wherein the switch protection circuit further includes: a fourth subcircuit; wherein the fourth subcircuit includes a third capacitive element, a first end of the third capacitive element is connected between the second end of the third subcircuit and a third node in the second semiconductor chip, and a second end of the third capacitive element is connected to a first node in the second semiconductor chip;

[0032] The control terminal of the third sub-circuit is connected between the second terminal of the third capacitive element and a first node in the second semiconductor chip.

[0033] In the above scheme, the switch protection circuit further includes: a fourth sub-circuit; wherein the fourth sub-circuit includes a fourth capacitive element, a first end of the fourth capacitive element is connected between the second end of the third sub-circuit and a third node in the second semiconductor chip; a second end of the fourth capacitive element is connected to the third node in the first semiconductor chip;

[0034] The control terminal of the third sub-circuit is connected between the second terminal of the fourth capacitive element and a third node in the first semiconductor chip.

[0035] In the above scheme, wherein the fourth sub-circuit further comprises a third resistive element; wherein a first end of the third resistive element is connected to a first node in the second semiconductor chip; and a second end of the third resistive element is connected to a second end of the third capacitive element;

[0036] The control terminal of the third sub-circuit is connected between the second terminal of the third capacitive element and the second terminal of the third resistive element.

[0037] In the above scheme, the fourth sub-circuit further includes a fourth resistive element; wherein a first end of the fourth resistive element is connected to a third node in the first semiconductor chip; and a second end of the fourth resistive element is connected to a second end of the fourth capacitive element;

[0038] The control terminal of the third sub-circuit is connected between the second terminal of the fourth capacitive element and the second terminal of the fourth resistive element.

[0039] In the above solution, the third sub-circuit includes a second N-type metal oxide semiconductor (NMOS) transistor.

[0040] In the above solution, wherein the third resistive element comprises at least one resistor connected in series; the third capacitive element comprises at least one capacitor connected in series;

[0041] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0042] In the above solution, wherein the fourth resistive element comprises at least one resistor connected in series; the fourth capacitive element comprises at least one capacitor connected in series;

[0043] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0044] In the above solution, the substrate of the first NMOS transistor and the substrate of the first semiconductor chip are isolated by a deep N well (DNW).

[0045] In the above solution, the substrate of the second NMOS transistor and the substrate of the second semiconductor chip are isolated by a deep N well (DNW).

[0046] In the above solution, the first semiconductor chip includes an interface chip; the second semiconductor chip includes a NAND flash memory chip.

[0047] In a second aspect, the present disclosure also provides another semiconductor package, including:

[0048] A packaging shell; the packaging shell is provided with a first pin capable of performing a charge device model (CDM) discharge;

[0049] A first semiconductor chip is located in the packaging shell; and

[0050] at least one second semiconductor chip, located in the package shell and each second semiconductor chip is connected to the first semiconductor chip via an N-type metal oxide semiconductor (NMOS) transistor;

[0051] The NMOS transistor is arranged in the first semiconductor chip or each of the second semiconductor chips; and the control end of the NMOS transistor is connected to a control signal; and the state of the control signal is controlled by whether the first pin performs charge device model (CDM) discharge control.

[0052] In the above solution, wherein the NMOS transistor is arranged in the first semiconductor chip;

[0053] The first end of the NMOS transistor is connected to the first node in the first semiconductor chip, the second end of the NMOS transistor is connected to the second node in the first semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein, the second node in the first semiconductor chip is connected to the first pin of the first semiconductor chip; the first semiconductor chip is also connected to each of the second semiconductor chips through the first pin of the first semiconductor chip.

[0054] In the above scheme, a first capacitive element is further provided in the first semiconductor chip, a first end of the first capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; a second end of the first capacitive element is connected to a third node in the first semiconductor chip;

[0055] The control terminal of the NMOS transistor is connected between the second terminal of the first capacitive element and a third node in the first semiconductor chip;

[0056] When the first pin of the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the first capacitive element; when the first pin of the semiconductor package performs normal operation, the third node in the first semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the first capacitive element.

[0057] In the above scheme, a second capacitive element is further provided in the first semiconductor chip, and a first end of the second capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; a second end of the second capacitive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip;

[0058] The control end of the NMOS transistor is connected between the second end of the second capacitive element and the first pin of the second semiconductor chip;

[0059] When the first pin of the semiconductor package performs CDM discharge, the first pin of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the second capacitive element; when the first pin of the semiconductor package performs normal operation, the first pin of the second semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the second capacitive element.

[0060] In the above solution, a first resistive element is further provided in the first semiconductor chip;

[0061] The first end of the first resistive element is connected to a third node in the first semiconductor chip; the second end of the first resistive element is connected to the second end of the first capacitive element;

[0062] The control terminal of the NMOS transistor is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0063] In the above solution, a second resistive element is also provided in the first semiconductor chip; wherein,

[0064] The first end of the second resistive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip; the second end of the second resistive element is connected to the second end of the second capacitive element;

[0065] The control terminal of the NMOS transistor is connected between the second terminal of the second capacitive element and the second terminal of the second resistive element.

[0066] In the above scheme, the NMOS transistor is arranged in each second semiconductor chip; in a second semiconductor chip, the first end of the NMOS transistor is connected to the second node in the second semiconductor chip, the second end of the NMOS transistor is connected to the third node in the second semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein the third node in the second semiconductor chip is connected to the second pin of the second semiconductor chip, and the second semiconductor chip is also connected to the first semiconductor chip through the second pin in the second semiconductor chip.

[0067] In the above solution, a third capacitive element is provided in the second semiconductor chip, a first end of the third capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and a second end of the third capacitive element is connected to a first node in the second semiconductor chip;

[0068] The control of the NMOS transistor is connected between the second end of the third capacitive element and the first node in the second semiconductor chip;

[0069] When the first pin of the semiconductor package performs CDM discharge, the first node of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the first node of the second semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0070] In the above solution, the first semiconductor chip is further provided with a fourth capacitive element, a first end of the fourth capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and a second end of the fourth capacitive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip;

[0071] When the first pin of the semiconductor package performs CDM discharge, the third pin of the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the third pin of the first semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0072] In the above solution, wherein the second semiconductor chip is further provided with a third resistive element, wherein;

[0073] A first end of the third resistive element is connected to a first node in the second semiconductor chip, and a second end of the third resistive element is connected to a second end of the third capacitive element;

[0074] The control terminal of the NMOS transistor is connected between the second terminal of the third resistive element and the second terminal of the third capacitive element.

[0075] In the above solution, a fourth resistive element is further provided in the second semiconductor chip, wherein;

[0076] The first end of the fourth resistive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip, and the second end of the fourth resistive element is connected to the second end of the fourth capacitive element;

[0077] The control terminal of the NMOS transistor is connected between the second terminal of the fourth resistive element and the second terminal of the fourth capacitive element.

[0078] In the above solution, the first pin of the semiconductor package includes an input pin or an output pin.

[0079] In the above solution, the first pin of the first semiconductor chip includes a ground pin; the second pin of the first semiconductor chip and the first pin of the second semiconductor chip include power pins.

[0080] In the above solution, the second pin of the second semiconductor chip includes a ground pin; the third pin of the first semiconductor chip and the third pin of the first semiconductor chip include a power pin.

[0081] In the above solution, the first semiconductor chip is an interface chip; the second semiconductor chip is a NAND flash memory chip.

[0082] The present disclosure provides a semiconductor package, wherein the semiconductor package includes: a first semiconductor chip; at least one second semiconductor chip; and a switch protection circuit, wherein the first end of the switch protection circuit is connected to the first semiconductor chip, the second end of the switch protection circuit is connected to each of the second semiconductor chips, and when the semiconductor package performs a charge device model (CDM) discharge, the switch protection circuit is in an off state to disconnect the connection between the first semiconductor chip and the second semiconductor chip. The semiconductor package provided by the present disclosure can disconnect the switch protection circuit during CDM discharge, thereby disconnecting the connection between the first semiconductor chip and the second semiconductor chip, thereby preventing the first semiconductor chip or the second semiconductor chip from being connected to the ground through a pin in large quantities, causing the semiconductor chip to fail through breakdown.

[0083] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0084] FIG. 1 is an exemplary system block diagram of an electronic device having a memory system according to some aspects of the present disclosure;

[0085] FIG. 2 is a schematic diagram of an exemplary memory card having a memory provided according to some aspects of the present disclosure;

[0086] FIG. 3 is a schematic diagram of an exemplary SSD having a memory provided according to some aspects of the present disclosure;

[0087] FIG4 is a first structural diagram of a semiconductor package provided according to some aspects of the present disclosure;

[0088] FIG5 is a first structural diagram of a NAND package provided according to some aspects of the present disclosure;

[0089] FIG6 is a second structural diagram of a NAND package provided according to some aspects of the present disclosure;

[0090] FIG. 7 is a schematic diagram of CMD discharge of a NAND package provided according to some aspects of the present disclosure;

[0091] FIG8 is a schematic diagram of a path of CMD discharge of a NAND package according to some aspects of the present disclosure;

[0092] FIG9 is a second structural schematic diagram of a semiconductor package provided according to some aspects of the present disclosure;

[0093] FIG10 is a schematic diagram of the position structure of a first NMOS transistor provided according to some aspects of the present disclosure;

[0094] 11 to 22 are some exemplary structural diagrams of structures of semiconductor packages provided according to some aspects of the present disclosure;

[0095] FIG23 is a schematic diagram of an exemplary structure of the semiconductor package shown in FIG12 according to some aspects of the present disclosure;

[0096] FIG. 24 is another exemplary structural schematic diagram of the semiconductor package shown in FIG. 13 provided according to some aspects of the present disclosure.

[0097] The following is a more detailed description of various embodiments of the present disclosure with reference to the accompanying drawings. Other embodiments that can be used as a variation of any disclosed embodiment can be formed by configuring or arranging the elements and features in the disclosed embodiments in different ways. Therefore, the disclosed embodiments are not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the disclosed embodiments are thorough and complete, and the scope of the disclosed embodiments is fully conveyed to the technicians in the technical field to which the disclosed embodiments belong. It should be noted that references to "embodiment", "another embodiment", etc. do not necessarily represent only one embodiment, and different references to any such phrases are not necessarily for the same embodiment. It should be understood that, although the terms "first", "second", "third", etc. can be used in this article to identify various elements, these elements are not limited by these terms. These terms are used to distinguish an element from another element with the same or similar name. Therefore, without departing from the spirit and scope of the disclosed embodiments, the first element in one embodiment may also be referred to as the second or third element in another embodiment.

[0098] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it should also be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present.

[0099] The terms used in this article are only for the purpose of describing a specific embodiment, and are not intended to limit the present disclosure. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified or can be clearly understood from the context as a singular form, otherwise the articles "one" and / or "one" used in the embodiments of the present disclosure and the appended claims should be collectively interpreted as indicating "one or more". It should be further understood that the terms "including", "including", "including" and "including" used in the embodiments of the present disclosure specify the presence of the elements and do not exclude the presence or addition of one or more other elements. The term "and / or" used in the embodiments of the present disclosure includes any and all combinations of one or more associated listed items. Unless otherwise defined, all terms including technology and scientific technology used in the embodiments of the present disclosure have the same meanings as those of ordinary skill in the art to which the present disclosure belongs in view of the embodiments of the present disclosure. It should be further understood that unless the embodiments of the present disclosure are clearly defined, such as those defined in common dictionaries, belonging to should be interpreted as having a meaning consistent with its meaning in the environment of the embodiments of the present disclosure and the related technology, and should not be interpreted in an idealized or overly formalized manner.

[0100] In the following description, many specific details are set forth to provide a thorough understanding of the present disclosure, and the present disclosure can be practiced without some or all of these specific details. In other cases, well-known processing structures and / or processing are not described in detail to avoid unnecessarily obscuring the present disclosure. It should also be understood that in some cases, unless otherwise special, it is obvious to those skilled in the relevant art that the features or elements described with respect to one embodiment can be used alone or in combination with other features or elements of another embodiment. Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of the embodiments of the present disclosure. Well-known technical details may be omitted to avoid obscuring the features and aspects of the embodiments of the present disclosure.

[0101] The disclosed embodiment provides a semiconductor package (including an IC chip), including a protection switch circuit, which can prevent a large amount of static charge carried by the semiconductor chip in the package from flowing into a certain semiconductor chip during CDM discharge, thereby causing the semiconductor chip and the semiconductor package to fail due to breakdown.

[0102] FIG. 1 shows a block diagram of an exemplary system with a memory device provided by an embodiment of the present disclosure. In FIG. 1 , the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in FIG. 1 , the system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104. Specifically, the memory device 104 may be any memory disclosed in the present application. For example, Phase Change Random Access Memory (PCRAM), three-dimensional NAND flash memory, etc.

[0103] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108. And is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), wherein the SSD or eMMC is used as a data storage for mobile devices with high duty cycle environments such as smart phones, tablet computers, laptop computers, and enterprise storage arrays. The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0104] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example as shown in FIG. 2, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector 204 that couples the memory card to a host (e.g., the host 108 in FIG. 1). In another example as shown in FIG. 3, the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 302. The SSD may also include an SSD connector 304 that couples the SSD to a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card. In addition, the memory controller 106 may also be configured to control the erase, read, and write operations of the memory device 104 .

[0105] The memory device and memory system provided above include a large number of IC chips (such as the interface chip or NAND flash memory chip described later). These large number of IC chips are more likely to be subjected to destructive ESD during manufacture, assembly, testing and final use. Among them, ESD is generated due to the static electricity of the IC chip itself. This type of ESD can be generated by a single pin of the IC chip, and this type of ESD can be made into a charged device model (CDM) protection circuit for ESD protection. When the IC chip is discharged by CDM, the external circuit connected to the IC chip will also carry static charge. Then, the static charge carried by the external circuit will also flow to the IC chip and discharge through the pins of the IC chip. At this time, the static charge through the pins of the IC is bound to increase, so it is very easy to cause the IC chip pins to break down and fail. That is to say: at present, the protection ability of the CDM protection circuit of the semiconductor chip (or package) containing the IC chip is affected by other semiconductor chips (or circuits) connected to it that carry static charge, and the effect is not good, which is very easy to cause the IC chip pins to break down and fail.

[0106] To solve one or more of the above problems, as shown in FIG. 4 , an embodiment of the present disclosure provides a semiconductor package 400, including:

[0107] A first semiconductor chip 401;

[0108] at least one second semiconductor chip 402 ; and

[0109] A switch protection circuit 403; a first end 4031 of the switch protection circuit 403 is connected to the first semiconductor chip 401, a second end 4032 of the switch protection circuit 403 is connected to each of the second semiconductor chips 402, and when the semiconductor package 400 performs a charged device model (CDM) discharge, the switch protection circuit 403 is in an off state to disconnect the connection between the first semiconductor chip 401 and the second semiconductor chip 402.

[0110] It should be noted that the switch protection circuit 403 also includes a third terminal 4033, which can be connected to a control signal to control the on or off state of the switch protection circuit 403. This will be described in detail later and will not be repeated here.

[0111] Here, the first semiconductor chip 401 may include an interface chip; the second semiconductor chip 402 includes a memory chip. The interface chip may refer to a chip with an internal interface circuit. Specifically, the internal interface circuit may have at least one of the following functions: a) setting data storage and buffering logic to adapt to the speed difference between the memory controller and the memory device; b) information format conversion, such as serial and parallel conversion; c) coordinating the type and level differences between the memory controller and the memory device in the information, such as level conversion drive, digital-to-analog or analog-to-digital conversion, etc. The memory chip may refer to the specific application of the concept of embedded system chip in the storage industry. For example, the aforementioned NAND flash memory chip with NAND storage array may be one of the memory chips.

[0112] Here, the semiconductor package 400 may refer to a structure formed by packaging multiple semiconductor chips in a package board (package board, or package structure). For example, in the present disclosure, a semiconductor package is formed by packaging a first semiconductor chip and at least one second semiconductor chip in a package board. In actual use, with the development of integrated circuits, package packaging modes are also constantly developing, and the number of chips packaged in a package is increasing. Among them, the packaging modes may include: DDP (two-chip package), QDP (four-chip package), ODP (eight-chip package) and HDP (16-chip package) and the like. As more and more memory chips are integrated in a package, the load of the external signal (DQ) pin (pin) of the package structure is getting larger and larger, which limits the working speed of the DQ. For example, as more and more NAND chips are integrated in a package, the load of the external signal (DQ) pin (pin) of the package structure is getting larger and larger, which limits the working speed of the DQ. In some embodiments, multiple NAND chips are packaged in a Combo-NAND packaging method. The Combo-NAND packaging method may mean that in addition to the conventional NAND chip, one or more interface (or buffer) chips are integrated in the package to process and transmit signals inside and outside the NAND package, optimize the timing of each NAND chip, and thus achieve high-speed operation of the signal pins of the package, which has become a development trend of large-capacity and high-speed NAND products. Specifically, as shown in Figures 5 and 6.

[0113] FIG5 is a schematic diagram of a structure of a NAND package according to some aspects of the present disclosure. FIG5 shows a global low voltage (global VSS) solution after Combo-NAND packaging. Specifically, the global VSS solution, on the one hand, connects the VSS of each NAND chip together through a bonding wire, and then connects it to the VSS pin of the package; on the other hand, the VSS of the interface chip is also connected to the VSS pin of the package through a bonding wire, so the VSS of all NAND chips and interface chips are connected together, so the substrates of all these chips are also connected together.

[0114] Among them, Figure 6 is a second structural schematic diagram of a NAND package provided according to some aspects of the present disclosure. Figure 6 shows the signal scheme of Combo-NAND. Inside the package, the signal pins (i.e., signal pins) of each NAND chip are first connected to the interface chip, and after the interface processing and timing optimization, they are then connected to the signal pins of the package through the signal pins of the interface chip, that is, the NAND chip is not directly connected to the signal pins of the package, and only the signal pins of the interface chip are connected to the signal pins of the package.

[0115] For the semiconductor package using the Combo-NAND packaging method described in Figures 5 and 6, the technical problem proposed by the above disclosure (IC chip undergoes CDM discharge, causing IC chip pin breakdown failure) also exists and is more serious. Specifically, as shown in Figures 7 and 8, they are schematic diagrams of CMD discharge of NAND packages provided according to some aspects of the present disclosure. Based on Figures 7 and 8. Before a certain signal pin of the package undergoes CDM ESD discharge, all chips (NAND chip and interface chip) in the package will be filled with static charge. When the package pin undergoes CDM discharge, the static charge accumulated on the substrate of each chip will be quickly discharged to the outside of the chip through the package pin. Since the CDM current is very large (several amperes to tens of amperes), a high voltage difference will be generated across the input gate, causing the input gate to breakdown and fail. The CDM of the external pin of the combo-NAND package is protected by the pin ESD of the interface chip. Since the NAND chip and the interface chip substrate are connected together, the static charge of all NAND chip substrates will also be discharged through the interface chip pin ESD. In the package, the static charge of a total of 17 chips is discharged through an interface chip pin ESD, which far exceeds the protection capability of the interface chip pin ESD and will cause the package pin ESD breakdown failure. One way to solve the above problem is to increase the ESD size of the interface chip to 17 times, which may not be effective. Even if it is effective, it will cause the pin parasitic capacitance to be too large, which seriously affects the signal transmission speed, which leads to the loss of the timing optimization advantage of the combo-NAND, which is unacceptable. In addition, the CDM fail caused by the combo-NAND may also occur inside the NAND or at the interface between the NAND and the buffer chip. The conventional IV test of the package pin after ESD cannot detect this failure, which is easily overlooked and becomes an invisible bomb in the use of the product. It should be noted that Figure 8 shows the principle structure of the CDM discharge in the package structure shown in Figures 5 to 7. For a specific understanding, please refer to the relevant technology, which will not be elaborated here.

[0116] Based on this, the present disclosure adds a switch protection circuit 403 in the semiconductor package, which is in the off state when the semiconductor package 400 performs a charge device model (CDM) discharge to disconnect the connection between the first semiconductor chip 401 and the second semiconductor chip 402, thereby blocking the static charge carried by the second semiconductor chip from flowing to the first semiconductor chip, and then blocking the static charge from flowing to the pins of the semiconductor package through the pins of the first semiconductor chip, thereby avoiding the breakdown failure of the pins of the first semiconductor chip and the semiconductor package. It should be noted that the static charge carried by the second semiconductor chip (such as a NAND chip) and the first semiconductor chip (such as an interface chip) can be accumulated during the normal operation of the semiconductor package, or can be charged when the semiconductor package is subjected to a CDM test before leaving the factory to test the ability of the pins to withstand ESD.

[0117] In some embodiments, when the semiconductor package operates normally, the switch protection circuit is in an on state to enable connection between the first semiconductor chip and the second semiconductor chip.

[0118] It should be noted that the semiconductor package performs CDM discharge only in one working state of ESD protection. The semiconductor package is still working normally most of the time, such as reading operation, writing operation, erasing operation, etc. When it is working normally, the switch protection circuit cannot affect the normal operation, that is, the switch protection circuit is in the on state when the semiconductor package is working normally, so as to connect the first semiconductor chip and the second semiconductor chip to ensure the normal operation of the semiconductor package.

[0119] That is to say, the semiconductor package performs CDM discharge or performs normal operation, wherein CDM discharge and normal operation are two independent operation modes of the semiconductor package, and only one of the modes can be operated at the same time, that is: when the semiconductor package performs CDM discharge, the semiconductor package will not be in the normal operation mode at this time; furthermore, when the semiconductor package is in normal operation, the semiconductor package will not perform CDM discharge.

[0120] There are several options for the setting and structure of the switch protection circuit:

[0121] Specifically, in some embodiments, as shown in FIG. 9 , the switch protection circuit 403 is disposed in the first semiconductor chip 401 and includes: a first sub-circuit 900; wherein,

[0122] The first end 900-1 of the first sub-circuit is connected to the first node 901 in the first semiconductor chip, the second end 900-2 of the first sub-circuit is connected to the second node 902 in the first semiconductor chip, and the control end 900-3 of the first sub-circuit is connected to the first control signal, and when the first control signal in the first state is connected, the first sub-circuit is in the disconnected state, or, when the first control signal in the second state is connected, the first sub-circuit is in the on state;

[0123] When the first sub-circuit is in a disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in a connected state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0124] Here, the first node 901 of the first semiconductor chip can be connected to the ground pad (PAD) within the first semiconductor chip; the second node 902 within the first semiconductor chip can be connected to the ground pin of the first semiconductor chip; and the third node within the first semiconductor chip can be connected to the power PAD within the first semiconductor chip.

[0125] The ground pad (PAD) described may specifically refer to a pad for grounding (GND). The ground pin of the first semiconductor chip may refer to a pin (or pin) for connecting to GND that is exposed to the outside of the first semiconductor chip after packaging. The power pad (PAD) may specifically refer to a pad for connecting a power signal (such as a voltage signal).

[0126] Here, the first sub-circuit may include: a first N-type Metal Oxide Semiconductor (NMOS) transistor. The substrate of the first NMOS transistor and the substrate of the first semiconductor chip are isolated by a deep N well (DNW).

[0127] Specifically, as shown in Figure 10, it shows a schematic diagram of an NMOS transistor provided in a DNW according to some aspects of the present disclosure. In Figure 10, there is a DNW on the substrate of the first semiconductor chip, and the first NMOS transistor is arranged between adjacent DNWs, so that the substrate of the first NMOS transistor and the substrate of the first semiconductor chip are isolated by the DNW, avoiding the parasitic P / N junction from being turned on.

[0128] Here, the first subcircuit has two states: an off state and an on state. Therefore, to realize the switching between these two states, two control signals of different states are required for control, namely, a control signal of the first state and a control signal of the second state. That is: under the control of the control signal of the first state, the first subcircuit is in an off state; under the control of the control signal of the second state, the first subcircuit is in an on state. Among them, for example, the first control signal of the first state may refer to a control signal at a low level (such as 0 volts (V)); correspondingly, the first control signal of the second state may refer to a control signal at a high level (such as VDD, such as 3.3V). Or, for example, the diyi control signal of the first state may refer to a control signal at a high level; correspondingly, the first control signal of the second state may refer to a control signal at a low level.

[0129] Furthermore, in the present disclosure, when the first sub-circuit is in an off state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in an on state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0130] In some embodiments, as shown in FIG. 11 , the switch protection circuit 403 includes: a second sub-circuit 1100; wherein the second sub-circuit 1100 includes a first capacitive element 1101, a first end 1101-1 of the first capacitive element is connected between the second end 900-2 of the first sub-circuit and the second node 902 in the first semiconductor chip, and a second end 1101-2 of the first capacitive element is connected to a third node 903 in the first semiconductor chip;

[0131] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal 1101 - 2 of the first capacitive element and a third node 903 in the first semiconductor chip.

[0132] It should be noted that the control end of the first subcircuit described above needs to be connected to the first control signal. In fact, the generation of the first control signal can also be generated by a related circuit. For example, the first capacitive element and its connection are used to form the related circuit to generate the first control signal. Specifically, the first end of the first capacitive element is connected between the second end of the first subcircuit and the second node in the first semiconductor chip, and the second end is connected to the third node in the first semiconductor chip. At this time, the control end of the first subcircuit is connected between the second end of the first capacitive element and the third node in the first semiconductor chip, and when the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the first subcircuit is connected to the first control signal in the first state through the first capacitive element; when the semiconductor package is working normally, the third node in the first semiconductor chip is connected to the power supply signal, and the control end of the first subcircuit is connected to the first control signal in the second state through the first capacitive element. Here, the power supply signal can refer to a voltage signal, that is, the third node in the first semiconductor chip is connected to the voltage signal so that the semiconductor package can work normally.

[0133] In some other embodiments, in order to protect the safety of the first capacitive element, as shown in FIG12 , the second sub-circuit further includes: a first resistive element 1102, wherein a first end 1102-1 of the first resistive element is connected to the third node 903 in the first semiconductor chip; a second end 1102-2 of the first resistive element is connected to a second end 1101-2 of the first capacitive element;

[0134] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0135] It should be noted that if the two ends of the first capacitive element are directly connected to the power signal, when the voltage of the power signal is relatively large, the first capacitive element will be broken down, so that the first capacitive element fails and the control signal cannot be connected to the first sub-circuit. Therefore, in order to ensure the safety of the first capacitive element, the second sub-circuit may also include a first resistive element, and the voltage at both ends of the first capacitive element is reduced to a range that it can withstand in a voltage-dividing manner or a current-limiting manner. When the second sub-circuit also includes a first resistive element, the control end of the first sub-circuit is connected between the second end of the first capacitive element and the second end of the first resistive element, and when the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the first sub-circuit is connected to the first control signal in the first state through the first capacitive element and the first resistive element; when the semiconductor package is working normally, the third node in the first semiconductor chip is connected to the power signal, and the control end of the first sub-circuit is connected to the first control signal in the second state through the first capacitive element and the first resistive element.

[0136] In some embodiments, the first resistive element may include at least one resistor connected in series; the first capacitive element may include at least one capacitor connected in series;

[0137] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0138] Here, the relationship between the first capacitive element and the first resistive element is described, that is, the value range of the product of the capacitance value of at least one capacitor included in the first capacitive element and the resistance value of at least one resistor included in the first resistive element is 1 nanosecond to 1 microsecond. After the above conditions are met, the second subcircuit can enable the first subcircuit to timely access the control signal of the first state when the semiconductor package is performing CDM discharge, so as to disconnect the connection between the first semiconductor chip and each second semiconductor chip, so as to block the static charge carried by the second semiconductor chip from flowing into the first semiconductor chip, and then connect to the ground through the semiconductor package to cause the breakdown failure of the semiconductor package pins and the pins of the first semiconductor chip. In addition, the second subcircuit can also enable the first subcircuit to timely access the control signal of the second state when the semiconductor package is performing normal operation, so as to connect the connection between the first semiconductor chip and the second semiconductor chip to ensure normal operation.

[0139] In some other embodiments, as shown in FIG. 13 , the switch protection circuit 403 may further include: a second sub-circuit 1300; wherein the second sub-circuit includes a second capacitive element 1301, a first end 1301-1 of the second capacitive element is connected between the second end 900-2 of the first sub-circuit and the second node 902 of the first semiconductor chip; a second end 1301-2 of the second capacitive element is connected to a first node 1302 in a second semiconductor chip;

[0140] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal 1301 - 2 of the second capacitive element and the first node 1302 in the second semiconductor chip.

[0141] It should be noted that the structure and connection relationship of a second sub-circuit are described above. The second sub-circuit shown in Figure 13 is another structure and connection relationship of the second sub-circuit that can be realized. Here, the second sub-circuit includes a second capacitive element 1301, and the first end 1301-1 of the second capacitive element is connected in the same way as the first end of the first capacitive element, that is, connected between the second end of the first sub-circuit and the second node of the first semiconductor chip. The second end 1301-2 of the second capacitive element is different from the connection of the second end of the first capacitive element, that is: the second end 1301-2 of the second point capacitive element is connected to the first node 1302 of a second semiconductor chip; and the second end of the first capacitive element is connected to the third node 903 of the first semiconductor chip. In this connection relationship, the control end of the first sub-circuit can be connected between the second end of the second capacitive element and the first node in a second semiconductor chip, and when the semiconductor package performs CDM discharge, the first node in a second semiconductor chip is in a floating state, and the first sub-circuit is connected to the first control signal of the first state through the second capacitive element; when the semiconductor package performs normal operation, the first node in a second semiconductor chip is connected to the power signal, and the first sub-circuit is connected to the first control signal of the second state through the second capacitive element. It should be noted that the second end 1301-2 of the second capacitive element is connected to its first node 1302 through the pin 1304 on the second semiconductor chip 402.

[0142] Here, the first node in the first semiconductor chip can be connected to the ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to the ground pin of the first semiconductor chip; and the first node in a second semiconductor chip is connected to the power PAD in a second semiconductor chip.

[0143] It should be noted that the first node and the second node in the first semiconductor chip are the same as those described above and will not be described in detail here. The first node in a second semiconductor chip is now connected to the power PAD in the second semiconductor chip. The advantage of this arrangement is that it can avoid the power PAD connected to the third node in the first semiconductor chip from interfering with the switch protection circuit and reduce the power consumption of the power PAD.

[0144] In some embodiments, as shown in FIG. 13 , the second sub-circuit further includes: a second resistive element 1303, wherein a first end 1303-1 of the second resistive element is connected to a first node 1302 in the second semiconductor chip; a second end 1303-2 of the second resistive element is connected to a second end 1301-2 of the second capacitive element;

[0145] The control terminal 900 - 3 of the first sub-circuit is connected between the second terminal of the second capacitive element and the second terminal of the second resistor.

[0146] In some embodiments, the second resistive element comprises at least one resistor connected in series; the second capacitive element comprises at least one capacitor connected in series;

[0147] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0148] It should be noted that the second resistive element here has the same function as the aforementioned first resistive element, which can be understood by referring to the previous description and will not be repeated here.

[0149] The first subcircuit and the second subcircuit included in the switch protection circuit described above are both arranged in the first semiconductor chip. In other embodiments, the switch protection circuit can also be arranged in each second semiconductor chip, and the above functions can also be realized.

[0150] Specifically, as shown in FIG. 14 , the switch protection circuit 403 is disposed in each second semiconductor chip 402 and includes: a third sub-circuit 1400; wherein,

[0151] The first terminal 1400-1 of the third sub-circuit is connected to the second node 1401 in the second semiconductor chip, the second terminal 1400-2 of the third sub-circuit is connected to the third node 1402 in the second semiconductor chip, and the control terminal 1400-3 of the third sub-circuit is connected to the second control signal, and when the second control signal in the first state is connected, the third sub-circuit is in the disconnected state, or, when the second control signal in the second state is connected, the third sub-circuit is in the on state;

[0152] When the third sub-circuit is in a disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the third sub-circuit is in a conductive state, the connection between the first semiconductor chip and the second semiconductor chip is connected.

[0153] In some embodiments, as shown in FIG. 15 , the switch protection circuit 403 may further include: a fourth sub-circuit 1500; wherein the fourth sub-circuit includes a third capacitive element 1501, a first end 1501-1 of the third capacitive element is connected between the second end 1400-2 of the third sub-circuit and a third node 1402 in the second semiconductor chip, and a second end 1501-2 of the third capacitive element is connected to the first node 1302 in the second semiconductor chip;

[0154] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the third capacitive element and the first node in the second semiconductor chip.

[0155] In some embodiments, as shown in FIG. 15 , the fourth sub-circuit further includes a third resistive element 1502; wherein a first end 1502-1 of the third resistive element is connected to a first node in the second semiconductor chip; and a second end 1502-2 of the third resistive element is connected to a second end of the third capacitive element;

[0156] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the third capacitive element and the second terminal of the third resistive element.

[0157] In some embodiments, the third resistive element comprises at least one resistor connected in series; the third capacitive element comprises at least one capacitor connected in series;

[0158] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0159] In some other embodiments, as shown in FIG. 16 , the switch protection circuit 403 further includes: a fourth sub-circuit 1600; wherein the fourth sub-circuit includes a fourth capacitive element 1601, a first end 1601-1 of the fourth capacitive element is connected between the second end 1400-2 of the third sub-circuit and the third node 1402 in the second semiconductor chip; a second end 1601-2 of the fourth capacitive element is connected to the third node 903 in the first semiconductor chip;

[0160] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the fourth capacitive element and the third node 903 in the first semiconductor chip.

[0161] Here, the second end 1601-2 of the fourth capacitive element is connected to the third node 903 of the first semiconductor chip via the pin 1602. This situation is not shown in Fig. 16. Fig. 16 shows an example diagram including a fourth resistive element.

[0162] In some embodiments, as shown in FIG. 16 , the fourth sub-circuit further includes a fourth resistive element 1603; wherein a first end 1603-1 of the fourth resistive element is connected to a third node 903 in the first semiconductor chip; and a second end 1603-2 of the fourth resistive element is connected to a second end of the fourth capacitive element;

[0163] The control terminal 1400 - 3 of the third sub-circuit is connected between the second terminal of the fourth capacitive element and the second terminal of the fourth resistive element.

[0164] Here, the first end 1603 - 1 of the fourth resistive element is connected to the third node 903 of the first semiconductor chip via the pin 1602 .

[0165] In some embodiments, the fourth resistive element comprises at least one resistor connected in series; the fourth capacitive element comprises at least one capacitor connected in series;

[0166] The product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor has a value in the range of 1 nanosecond to 1 microsecond.

[0167] In some embodiments, the third sub-circuit includes a second N-type metal oxide semiconductor (NMOS) transistor. Here, the substrate of the second NMOS transistor and the substrate of the second semiconductor chip are isolated by a deep N well (DNW). It should be noted that the principle of DNW isolation here has been described above and will not be repeated here.

[0168] It should be noted that the structure and connection method of the switch protection circuit described in Figures 14 to 16 are different from the structure and connection method of the switch protection circuit described in Figures 4 to 13 above. This is because they are arranged in different semiconductor chips, but their working principles and the functions of each component are similar. The functions of each component in the switch protection circuit in Figures 4 and 13 have been described in detail above. The functions of each component in the switch protection circuit in Figures 14 to 16 are similar to those described above, which can be referred to for understanding and will not be described in detail here.

[0169] Based on the same inventive concept, the present disclosure also provides another embodiment. As shown in FIG. 17 , the present disclosure also provides another semiconductor package 1700, including:

[0170] The packaging shell 1701 is provided with a first pin 1701-1 capable of performing charge device model (CDM) discharge;

[0171] A first semiconductor chip 1702 is located in the packaging shell; and

[0172] At least one second semiconductor chip 1703, located in the package shell and each second semiconductor chip is connected to the first semiconductor chip via an N-type metal oxide semiconductor (NMOS) transistor 1704;

[0173] The NMOS transistor is arranged in the first semiconductor chip or each of the second semiconductor chips; and the control end of the NMOS transistor is connected to a control signal; and the state of the control signal is controlled by whether the first pin performs charge device model (CDM) discharge control.

[0174] Here, the first pin of the semiconductor package may include an input pin or an output pin, that is, the signal pin of the semiconductor package shown in FIGS. 7 to 9 above.

[0175] In some embodiments, as shown in FIG18 , the NMOS transistor is disposed in the first semiconductor chip;

[0176] The first end 1704-1 of the NMOS transistor is connected to the first node 1801 in the first semiconductor chip, the second end 1704-2 of the NMOS transistor is connected to the second node 1802 in the first semiconductor chip, and the control end 1704-3 of the NMOS transistor is connected to the control signal; wherein, the second node 1802 in the first semiconductor chip is connected to the first pin 1803 of the first semiconductor chip; the first semiconductor chip is also connected to each of the second semiconductor chips through the first pin of the first semiconductor chip.

[0177] In some embodiments, as shown in FIG. 18 , a first capacitive element 1804 is further provided in the first semiconductor chip, and a first end 1804-1 of the first capacitive element 1804 is connected between the second end of the NMOS transistor and the first pin 1803 of the first semiconductor chip; a second end 2403-2 of the first capacitive element is connected to a third node 1805 in the first semiconductor chip;

[0178] The control terminal 1704-3 of the NMOS transistor is connected between the second terminal of the first capacitive element and a third node in the first semiconductor chip;

[0179] When the first pin of the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the first capacitive element; when the first pin of the semiconductor package performs normal operation, the third node in the first semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the first capacitive element.

[0180] Here, the first pin 1803 is connected to the second node 1802 in the first semiconductor chip. The first end of the first capacitive element 1804 is connected between the second end 1704-2 of the NMOS transistor and the first pin 1803 of the first semiconductor chip, which can refer to any accessible place connected between the second end 1704-2 and the first pin 1803, or the second node 1802. The connection between the external pin and the internal node in the remaining figures is understood in this way and is not specifically explained.

[0181] In some embodiments, as shown in FIG. 19 , a first resistive element 1806 is further disposed in the first semiconductor chip;

[0182] The first end 1806-1 of the first resistive element is connected to the third node 1805 in the first semiconductor chip; the second end 1806-2 of the first resistive element is connected to the second end of the first capacitive element;

[0183] The control terminal 1704 - 3 of the NMOS transistor is connected between the second terminal of the first capacitive element and the second terminal of the first resistive element.

[0184] In some embodiments, as shown in FIG. 20 , a second capacitive element 2001 is further disposed in the first semiconductor chip, and a first end 2001-1 of the second capacitive element 2001 is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; a second end 2001-2 of the second capacitive element is connected to a first pin 2003 of the second semiconductor chip via a second pin 2002 of the first semiconductor chip;

[0185] The control terminal 1704 of the NMOS transistor is connected between the second end of the second capacitive element and the first pin 2003 of the second semiconductor chip;

[0186] When the first pin of the semiconductor package performs CDM discharge, the first pin of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the second capacitive element; when the first pin of the semiconductor package performs normal operation, the first pin of the second semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the second capacitive element.

[0187] In some embodiments, as shown in FIG. 20 , a second resistive element 2004 is also provided in the first semiconductor chip; wherein,

[0188] The first end 2004-1 of the second resistive element is connected to the first pin 2003 of the second semiconductor chip via the second pin 2002 of the first semiconductor chip; the second end 2004-2 of the second resistive element is connected to the second end 2001-2 of the second capacitive element;

[0189] The control terminal 1704 - 3 of the NMOS transistor is connected between the second terminal of the second capacitive element and the second terminal of the second resistive element.

[0190] In some embodiments, the first pin 1803 of the first semiconductor chip comprises a ground pin; the second pin 2002 of the first semiconductor chip and the first pin 2003 of the second semiconductor chip comprise power pins.

[0191] In some embodiments, as shown in Figure 21, the NMOS transistor is arranged in each second semiconductor chip; in a certain second semiconductor chip, the first end 1704-1 of the NMOS transistor is connected to the second node 2101 in the second semiconductor chip, the second end 1704-2 of the NMOS transistor is connected to the third node 2102 in the second semiconductor chip, and the control end 1704-3 of the NMOS transistor is connected to the control signal; wherein the third node 2102 in the second semiconductor chip is connected to the second pin 2103 of the second semiconductor chip, and the second semiconductor chip is also connected to the first semiconductor chip through the second pin 2103 in the second semiconductor chip.

[0192] In some embodiments, as shown in FIG. 21 , a third capacitive element 2104 is disposed in the second semiconductor chip, a first end 2104-1 of the third capacitive element is connected between the second end of the NMOS transistor and the second pin 2103 of the second semiconductor chip, and a second end 2104-2 of the third capacitive element is connected to a first node 2105 in the second semiconductor chip;

[0193] The control 1704-3 of the NMOS transistor is connected between the second end of the third capacitive element and the first node 2105 in the second semiconductor chip;

[0194] When the first pin of the semiconductor package performs CDM discharge, the first node of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the first node of the second semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0195] In some embodiments, as shown in FIG. 21 , the second semiconductor chip is further provided with a third resistive element 2106 , wherein;

[0196] The first end 2106-1 of the third resistive element is connected to the first node 2105 in the second semiconductor chip, and the second end 2106-2 of the third resistive element is connected to the second end 2104-1 of the third capacitive element;

[0197] The control terminal 1704 - 3 of the NMOS transistor is connected between the second terminal of the third resistive element and the second terminal of the third capacitive element.

[0198] In some embodiments, as shown in FIG. 22 , the second semiconductor chip is further provided with a fourth capacitive element 2201, a first end 2201-1 of the fourth capacitive element is connected between the second end 1704-2 of the NMOS transistor and the second pin 2103 of the second semiconductor chip, and a second end 2202-2 of the fourth capacitive element is connected to the third pin 2203 of the first semiconductor chip via the third pin 2202 of the second semiconductor chip;

[0199] When the first pin of the semiconductor package performs CDM discharge, the third pin of the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the third pin of the first semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element.

[0200] In some embodiments, a fourth resistive element 2204 is further disposed in the second semiconductor chip, wherein;

[0201] The first end 2204-1 of the fourth resistive element is connected to the third pin 2203 of the first semiconductor chip via the third pin 2202 of the second semiconductor chip, and the second end 2204-2 of the fourth resistive element is connected to the second end 2201-2 of the fourth capacitive element;

[0202] The control terminal of the NMOS transistor is connected between the second terminal of the fourth resistive element and the second terminal of the fourth capacitive element.

[0203] In some embodiments, the second pin 2103 of the second semiconductor chip comprises a ground pin; and the third pin 2202 of the first half-cell chip and the third pin 2203 of the first semiconductor chip comprise power pins.

[0204] In some embodiments, the first semiconductor chip may be an interface chip; and the second semiconductor chip may be a NAND flash memory chip.

[0205] To facilitate understanding of the semiconductor package described above, as shown in FIG23 , an exemplary structural schematic diagram of the semiconductor package shown in FIG12 provided according to some aspects of the present disclosure is shown.

[0206] In FIG23 , the structure of the semiconductor package is simplified, and the present disclosure is illustrated only by taking the semiconductor package including a NAND chip and an interface chip as an example. Here, the switch protection circuit is arranged in the interface chip, and the first end of the NMOS transistor contained therein is connected to the ground pad VSS2 inside the interface chip, and the second end is connected to the ground pin of the interface chip, and its control end is connected between the series-connected resistor R1 and capacitor C1. In addition, the ground pin of the NAND chip is connected to the ground pin of the interface chip through a bonging wire. VCC1 in FIG23 is a sub-power pin or sub-power pad of the NAND chip; VCC2 is a power pin or power pad of the interface chip, which can be connected to the third node in the aforementioned first semiconductor chip. In this structure, if the signal pin of the semiconductor package is discharged by CDM, VCC1 and VCC2 are in floating state, and the control terminal of the NMOS transistor is pulled to the low potential of VSS1 by C1. Therefore, the NMOS transistor is in the off state, and VSS1 and VSS2 are electrically disconnected. Therefore, the static charge in the NAND chip will not be transmitted to the interface chip. Therefore, the interface chip only needs to complete the discharge of its own CDM charge, and does not need to bear the large amount of CDM charge from the NAND chip, so as to avoid the interface chip pin being broken down by CDM and failing. When the semiconductor package is working normally, VCC2 is at a high potential, and the control terminal (gate) of the NMOS transistor is pulled to the high potential of VCC2 by R1. Therefore, the second NMOS transistor remains in the on state, and VSS1 and VSS2 are electrically connected, which does not affect the normal operation of the overall Combo-NAND.

[0207] In some other embodiments, as shown in FIG24, it is a schematic diagram showing another exemplary structure of the semiconductor package shown in FIG13 provided according to some aspects of the present disclosure. The difference between FIG23 and FIG24 is that the resistor R1 is connected to VCC1, that is, when the semiconductor package works normally, the control terminal (gate) of the NMOS transistor is pulled to the high potential of VCC1 by R1, so the NMOS transistor remains in the on state, and VSS1 and VSS2 are in an electrically connected state, which does not affect the normal operation of the overall Combo-NAND.

[0208] A semiconductor package provided by an embodiment of the present disclosure adds a CDM discharge switch protection circuit (such as an NMOS circuit) to the vss2 bus of the interface chip to control the connection and disconnection of the VSS1 of the NAND chip and the VSS2 of the interface chip. During CDM discharge, under transient conditions, the gate of the switch NMOS is pulled to the VSS1 potential by C1, and the switch NMOS is turned off, so that VSS1 and VSS2 are disconnected, cutting off the path for the CDM charge of the NAND chip to flow to the interface chip, thereby preventing the large amount of static charge of the NAND chip from causing electrostatic failure to the signal pin of the interface chip; when the chip is working normally, the gate of the switch NMOS is pulled up to VCC2 by R1, fully turned on, and VSS1 and VSS2 are connected. In addition, the NMOS can be set in the DNW in the substrate of the interface chip, so that the substrate of the NMOS and the substrate of the interface chip are isolated by the DNW, thereby preventing VSS1 and VSS2 from being turned on through the parasitic P / N junction. Furthermore, the resistor R1 of the switch circuit may also be connected to VCC1 through a bonding wire to avoid interference of VCC2 on the switch circuit and reduce power consumption of VCC2, thereby achieving the same effect.

[0209] It should be noted that the semiconductor package provided in the embodiment of the present disclosure can also set the switch protection circuit in the memory chip (such as a NAND flash memory chip). Based on this, the connection method of the switch protection circuit in the memory chip is also slightly different. Its function and structure are the same as the aforementioned switch protection circuit. For specific understanding, please refer to the aforementioned description, which will not be repeated here. Among them, setting the switch protection circuit in the memory chip can avoid the interference of the interface chip on the switch circuit, reduce the power consumption of the interface chip, and reduce the area of ​​the interface chip, which can achieve the same effect. However, it is necessary to integrate the switch circuit in each NAND chip to cut off the CDM current of all NAND chips.

[0210] It should be noted that in the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0211] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0212] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0213] A person skilled in the art can understand that: all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, etc. Various media that can store program codes.

[0214] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure can essentially or in other words, the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0215] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A semiconductor package, comprising: a first semiconductor chip; at least one second semiconductor chip; and a switch protection circuit, wherein a first end of the switch protection circuit is connected to the first semiconductor chip, a second end of the switch protection circuit is connected to each of the second semiconductor chips, and when the semiconductor package performs a charged device model (CDM) discharge, the switch protection circuit is in an off state to disconnect the connection between the first semiconductor chip and the second semiconductor chip. The semiconductor package according to claim 1, wherein When the semiconductor package operates normally, the switch protection circuit is in a conducting state to connect the first semiconductor chip and the second semiconductor chip. The semiconductor package according to claim 1 or 2, wherein: The switch protection circuit is arranged in the first semiconductor chip, and includes: a first sub-circuit; wherein, the first end of the first sub-circuit is connected to the first node in the first semiconductor chip, the second end of the first sub-circuit is connected to the second node in the first semiconductor chip, the control end of the first sub-circuit is connected to the first control signal, and when the first control signal is connected to the first state, the first sub-circuit is in a disconnected state, or, when the first control signal is connected to the second state, the first sub-circuit is in a conductive state; wherein, when the first sub-circuit is in the disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the first sub-circuit is in the conductive state, the connection between the first semiconductor chip and the second semiconductor chip is connected. The semiconductor package according to claim 3, wherein The switch protection circuit also includes: a second sub-circuit; wherein the second sub-circuit includes a first capacitive element, a first end of the first capacitive element is connected between the second end of the first sub-circuit and a second node in the first semiconductor chip, and a second end of the first capacitive element is connected to a third node in the first semiconductor chip; and a control end of the first sub-circuit is connected between the second end of the first capacitive element and the third node. The semiconductor package according to claim 3, wherein The switch protection circuit also includes: a second sub-circuit; wherein the second sub-circuit includes a second capacitive element, a first end of the second capacitive element is connected between the second end of the first sub-circuit and the second node of the first semiconductor chip; a second end of the second capacitive element is connected to a first node in a second semiconductor chip; and a control end of the first sub-circuit is connected between the second end of the second capacitive element and the first node in the second semiconductor chip. The semiconductor package according to claim 4, wherein The second sub-circuit also includes: a first resistive element, a first end of the first resistive element is connected to the third node in the first semiconductor chip; a second end of the first resistive element is connected to the second end of the first capacitive element; and a control end of the first sub-circuit is connected between the second end of the first capacitive element and the second end of the first resistive element. The semiconductor package according to claim 5, wherein The second sub-circuit also includes: a second resistive element, a first end of the second resistive element is connected to a first node in the second semiconductor chip; a second end of the second resistive element is connected to a second end of the second capacitive element; and a control end of the first sub-circuit is connected between the second end of the second capacitive element and the second end of the second resistive element. The semiconductor package according to claim 3, wherein The first sub-circuit includes: a first N-type metal oxide semiconductor (NMOS) transistor. The semiconductor package according to claim 6, wherein The first resistive element includes at least one resistor connected in series; the first capacitive element includes at least one capacitor connected in series; wherein the product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor ranges from 1 nanosecond to 1 microsecond. The semiconductor package according to claim 7, wherein The second resistive element includes at least one resistor connected in series; the second capacitive element includes at least one capacitor connected in series; wherein the product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor ranges from 1 nanosecond to 1 microsecond. The semiconductor package according to claim 6, wherein The first node in the first semiconductor chip is connected to a ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to a ground pin of the first semiconductor chip; and the third node in the first semiconductor chip is connected to a power supply PAD in the first semiconductor chip. The semiconductor package according to claim 7, wherein The first node in the first semiconductor chip is connected to a ground pad (PAD) in the first semiconductor chip; the second node in the first semiconductor chip is connected to a ground pin of the first semiconductor chip; and the first node in a second semiconductor chip is connected to a power supply PAD in a second semiconductor chip. The semiconductor package according to claim 1 or 2, wherein: The switch protection circuit is arranged in each second semiconductor chip, and includes: a third sub-circuit; wherein, the first end of the third sub-circuit is connected to the second node in the second semiconductor chip, the second end of the third sub-circuit is connected to the third node in the second semiconductor chip, the control end of the third sub-circuit is connected to the second control signal, and when the second control signal in the first state is connected, the third sub-circuit is in a disconnected state, or, when the second control signal in the second state is connected, the third sub-circuit is in a conductive state; wherein, when the third sub-circuit is in a disconnected state, the connection between the first semiconductor chip and the second semiconductor chip is disconnected; when the third sub-circuit is in a conductive state, the connection between the first semiconductor chip and the second semiconductor chip is connected. The semiconductor package according to claim 13, wherein The switch protection circuit also includes: a fourth sub-circuit; wherein the fourth sub-circuit includes a third capacitive element, a first end of the third capacitive element is connected between the second end of the third sub-circuit and a third node in the second semiconductor chip, and a second end of the third capacitive element is connected to a first node in the second semiconductor chip; and a control end of the third sub-circuit is connected between the second end of the third capacitive element and the first node in the second semiconductor chip. The semiconductor package according to claim 13, wherein The switch protection circuit also includes: a fourth sub-circuit; wherein the fourth sub-circuit includes a fourth capacitive element, a first end of the fourth capacitive element is connected between the second end of the third sub-circuit and a third node in the second semiconductor chip; a second end of the fourth capacitive element is connected to the third node in the first semiconductor chip; and a control end of the third sub-circuit is connected between the second end of the fourth capacitive element and the third node in the first semiconductor chip. The semiconductor package according to claim 14, wherein The fourth sub-circuit also includes a third resistive element; wherein the first end of the third resistive element is connected to the first node in the second semiconductor chip; the second end of the third resistive element is connected to the second end of the third capacitive element; and the control end of the third sub-circuit is connected between the second end of the third capacitive element and the second end of the third resistive element. The semiconductor package according to claim 15, wherein The fourth sub-circuit also includes a fourth resistive element; wherein the first end of the fourth resistive element is connected to the third node in the first semiconductor chip; the second end of the fourth resistive element is connected to the second end of the fourth capacitive element; and the control end of the third sub-circuit is connected between the second end of the fourth capacitive element and the second end of the fourth resistive element. The semiconductor package according to claim 13, wherein The third sub-circuit includes a second N-type metal oxide semiconductor (NMOS) transistor. The semiconductor package according to claim 16, wherein The third resistive element includes at least one resistor connected in series; the third capacitive element includes at least one capacitor connected in series; wherein the product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor ranges from 1 nanosecond to 1 microsecond. The semiconductor package according to claim 17, wherein The fourth resistive element includes at least one resistor connected in series; the fourth capacitive element includes at least one capacitor connected in series; wherein the product of the resistance value of the at least one resistor and the capacitance value of the at least one capacitor ranges from 1 nanosecond to 1 microsecond. The semiconductor package according to claim 8, wherein The substrate of the first NMOS transistor and the substrate of the first semiconductor chip are isolated by a deep N well (DNW). The semiconductor package according to claim 18, wherein A substrate of the second NMOS transistor and a substrate of the second semiconductor chip are isolated by a deep N well (DNW). The semiconductor package according to claim 1, wherein The first semiconductor chip includes an interface chip; the second semiconductor chip includes a NAND flash memory chip. A semiconductor package, comprising: Encapsulation shell; The packaging shell is provided with a first pin capable of performing charge device model (CDM) discharge; A first semiconductor chip is located in the packaging shell; And at least one second semiconductor chip is located in the packaging shell and each second semiconductor chip is connected to the first semiconductor chip via an N-type metal oxide semiconductor (NMOS) transistor; wherein the NMOS transistor is set in the first semiconductor chip or each second semiconductor chip; and the control end of the NMOS transistor is connected to a control signal; the state of the control signal is controlled by whether the first pin performs charge device model (CDM) discharge control. The semiconductor package according to claim 24, wherein The NMOS transistor is arranged in the first semiconductor chip; the first end of the NMOS transistor is connected to the first node in the first semiconductor chip, the second end of the NMOS transistor is connected to the second node in the first semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein, the second node in the first semiconductor chip is connected to the first pin of the first semiconductor chip; the first semiconductor chip is also connected to each of the second semiconductor chips through the first pin of the first semiconductor chip. The semiconductor package according to claim 25, wherein A first capacitive element is also provided in the first semiconductor chip, and the first end of the first capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; the second end of the first capacitive element is connected to the third node in the first semiconductor chip; the control end of the NMOS transistor is connected between the second end of the first capacitive element and the third node in the first semiconductor chip; wherein, when the first pin of the semiconductor package performs CDM discharge, the third node in the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the first capacitive element; when the first pin of the semiconductor package performs normal operation, the third node in the first semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the first capacitive element. The semiconductor package according to claim 25, wherein A second capacitive element is also arranged in the first semiconductor chip, and the first end of the second capacitive element is connected between the second end of the NMOS transistor and the first pin of the first semiconductor chip; the second end of the second capacitive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip; the control end of the NMOS transistor is connected between the second end of the second capacitive element and the first pin of the second semiconductor chip; wherein, when the first pin of the semiconductor package performs CDM discharge, the first pin of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state via the second capacitive element; when the first pin of the semiconductor package performs normal operation, the first pin of the second semiconductor chip is connected to a power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state via the second capacitive element. The semiconductor package according to claim 26, wherein A first resistive element is also provided in the first semiconductor chip; wherein the first end of the first resistive element is connected to the third node in the first semiconductor chip; the second end of the first resistive element is connected to the second end of the first capacitive element; and the control end of the NMOS transistor is connected between the second end of the first capacitive element and the second end of the first resistive element. The semiconductor package according to claim 27, wherein A second resistive element is also provided in the first semiconductor chip; wherein the first end of the second resistive element is connected to the first pin of the second semiconductor chip via the second pin of the first semiconductor chip; the second end of the second resistive element is connected to the second end of the second capacitive element; and the control end of the NMOS transistor is connected between the second end of the second capacitive element and the second end of the second resistive element. The semiconductor package according to claim 24, wherein The NMOS transistor is arranged in each second semiconductor chip; in a second semiconductor chip, the first end of the NMOS transistor is connected to the second node in the second semiconductor chip, the second end of the NMOS transistor is connected to the third node in the second semiconductor chip, and the control end of the NMOS transistor is connected to the control signal; wherein the third node in the second semiconductor chip is connected to the second pin of the second semiconductor chip, and the second semiconductor chip is also connected to the first semiconductor chip through the second pin in the second semiconductor chip. The semiconductor package according to claim 30, wherein A third capacitive element is arranged in the second semiconductor chip, and the first end of the third capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and the second end of the third capacitive element is connected to the first node in the second semiconductor chip; the control of the NMOS transistor is connected between the second end of the third capacitive element and the first node in the second semiconductor chip; wherein, when the first pin of the semiconductor package performs CDM discharge, the first node of the second semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state through the third capacitive element; when the first pin of the semiconductor package performs normal operation, the first node of the second semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state through the third capacitive element. The semiconductor package according to claim 30, wherein The first semiconductor chip is also provided with a fourth capacitive element, the first end of the fourth capacitive element is connected between the second end of the NMOS transistor and the second pin of the second semiconductor chip, and the second end of the fourth capacitive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip; wherein, when the first pin of the semiconductor package performs CDM discharge, the third pin of the first semiconductor chip is in a floating state, and the control end of the NMOS transistor is connected to the control signal in the first state via the third capacitive element; when the first pin of the semiconductor package performs normal operation, the third pin of the first semiconductor chip is connected to the power supply signal, and the control end of the NMOS transistor is connected to the control signal in the second state via the third capacitive element. The semiconductor package according to claim 31, wherein The second semiconductor chip is further provided with a third resistive element, wherein; The first end of the third resistive element is connected to the first node in the second semiconductor chip, and the second end of the third resistive element is connected to the second end of the third capacitive element; the control end of the NMOS transistor is connected between the second end of the third resistive element and the second end of the third capacitive element. The semiconductor package according to claim 32, wherein A fourth resistive element is also provided in the second semiconductor chip, wherein; The first end of the fourth resistive element is connected to the third pin of the first semiconductor chip via the third pin of the second semiconductor chip, and the second end of the fourth resistive element is connected to the second end of the fourth capacitive element; the control end of the NMOS transistor is connected between the second end of the fourth resistive element and the second end of the fourth capacitive element. The semiconductor package according to claim 25 or 30, wherein: The first pin of the semiconductor package includes an input pin or an output pin. The semiconductor package according to claim 27, wherein The first pin of the first semiconductor chip includes a ground pin; the second pin of the first semiconductor chip and the first pin of the second semiconductor chip include power pins. The semiconductor package according to claim 32, wherein The second pin of the second semiconductor chip comprises a ground pin; the third pin of the first semiconductor chip and the third pin of the first semiconductor chip comprise a power pin. The semiconductor package according to claim 24, wherein The first semiconductor chip is an interface chip; the second semiconductor chip is a NAND flash memory chip.

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