Spread spectrum video transmission with orthogonal frequency division multiplexing and OFDM video transmission

Abstract

An Orthogonal Frequency Division Multiplexing (OFDM) transmitter maps digital levels to I and Q components. The transmitter uses each other digital level as an I or Q component, or divides the MSB and LSB of the digital level into the I and Q components. An analog OFDM transmitter uses a pair of input analog levels as I and Q components. The inverse FFT outputs a complex value and transmits an OFDM symbol. The inverse FFT may also use complex conjugate output real values. Prior to input to the OFDM transmitter, an optional encoder encodes digital or analog samples into L levels using N orthogonal codes. An OFDM receiver receives an OFDM signal and outputs digital or analog samples. A video signal is input into a distributor, the distributor distributes analog or digital samples to vectors, and each vector is input into an OFDM transmitter and transmitted to a corresponding receiver.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 398,460, filed on August 16, 2022, entitled “SPREAD-SPECTRUM VIDEO TRANSPORTWITH ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING,” [P008P], U.S. Provisional Patent Application No. 63 / 421,062, filed on October 31, 2022, entitled “SPREAD-SPECTRUM VIDEO TRANSPORT WITH ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING AND OFDM VIDEO TRANSPORT,” [P008P2], and U.S. Provisional Patent Application No. 63 / 421,062, filed on October 31, 2022, entitled “ANALOG VIDEOTRANSPORT TO ADISPLAY PANEL AND SOURCE DRIVER INTEGRATION WITH ADISPLAYPANEL," priority to U.S. Provisional Patent Application No. 63 / 500,341, [P0015P2], all of which are incorporated herein by reference.

[0003] This application incorporates by reference U.S. Application No. 15 / 925,123, filed on March 19, 2018, (Docket No. HYFYP001, now U.S. Patent No. 10,158,396, issued on December 18, 2018), U.S. Application No. 16 / 494,901, filed on September 17, 2019 (Docket No. HYFYP002), U.S. Application No. 17 / 879,499, filed on August 2, 2022 (Docket No. HYFYP003), U.S. Application No. 17 / 686,790, filed on March 4, 2022 (Docket No. HYFYP004AX1), U.S. Application No. 17 / 887,849, filed on August 15, 2022 (Docket No. HYFYP006), and U.S. Application No. 17 / 879,499, filed on August 2, 2022 (Docket No. HYFYP007). U.S. application No. 17 / 851,821 filed on June 28, 2022 (docket number: HYFYP007), U.S. patent application No. 17 / 900,570 filed on August 31, 2022 (docket number: HYFYP009), U.S. patent application No. 17 / 946,479 filed on August 16, 2022 (docket number: HYFYP010), U.S. application No. 18 / 095,801 filed on January 11, 2023 (docket number: HYFYP011), U.S. patent application No. 18 / 098,612 filed on January 18, 2022 (docket number: HYFYP013), and U.S. patent application No. 18 / 117,288 filed on March 3, 2023 (docket number: HYFYP014). Technical Field

[0004] The present invention generally relates to the transmission of sampled signals over electromagnetic channels. More particularly, the present invention relates to the transmission of video signals using coding and Orthogonal Frequency Division Multiplexing (OFDM) or OFDM itself. Background Art

[0005] Image sensors, display panels, and video processors are in a constant race to achieve larger formats, greater color depth, higher frame rates, and higher resolutions. Video transmission (whether within a sensor, device, or display, in the built environment around a person, within a vehicle, or over greater distances) necessarily involves the transmission of a media signal (such as a video signal) through one or more electromagnetic (EM) pathways.

[0006] Each EM path degrades the EM signal propagating through it due to phenomena such as attenuation, reflections caused by impedance mismatches, and impinging attack signals, that is, the measurement of the EM signal at the receiving end must differ from the corresponding level, characteristics, parameters, etc. available at the transmitting end. Therefore, each EM path can be considered as an imperfect electromagnetic propagation path. The quality of any given EM path is characterized by the comparison of the level measured at the receiving end after transmission through the EM path with the level available at the transmitter.

[0007] U.S. Patent No. 10,158,396 discloses systems and techniques for encoding analog or digital samples and transmitting those encoded samples over electromagnetic paths for corresponding decoding and use of those samples. U.S. Application No. 16 / 494,901 discloses systems and techniques for distributing and transmitting encoded samples over multiple electromagnetic paths for ultimate decoding and use, while U.S. Application No. 63 / 232,486 discloses systems and techniques for distributing, grading, and arranging samples prior to encoding and transmitting them over one or more electromagnetic paths (and then correspondingly decoding, grading, arranging, and collecting those samples). U.S. Application No. 17 / 686,790 discloses specific embodiments for constructing a transmitter with an encoder (and a receiver with a decoder) for implementing transmission of encoded analog or digital samples over electromagnetic paths. U.S. Application Nos. 63 / 317,746 and 63 / 280,017 disclose transmitters and receivers for transmitting video within a display unit using SSVT technology.

[0008] Considering that electromagnetic pathways are inherently imperfect, and recognizing that the above disclosures use specific techniques for transmitting samples through electromagnetic pathways, additional techniques are needed to improve the quality of the electromagnetic signal transmitted from a transmitting end to a receiving end. Summary of the invention

[0009] To achieve the above, and in accordance with the purpose of the present invention, a technique is disclosed for modulating optionally coded analog or digital samples for transmission from a transmitting end to a receiving end using an improvement in orthogonal frequency division multiplexing (OFDM), and demodulating the received OFDM signal into analog or digital samples. The input samples of an OFDM transmitter can be analog or digital, and can be coded or non-coded.

[0010] In one embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting digital levels separates the input digital levels into I and Q components. An encoder successively encodes a vector of N samples using N codes of length L to generate digital levels.

[0011] In a second embodiment, an Orthogonal Frequency Division Multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs digital levels. A decoder successively decodes the L levels using N codes of length L to produce a vector of N samples.

[0012] In a third embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting analog levels uses a pair of input analog levels as components I and Q. An encoder successively encodes a vector of N samples using N codes of length L to generate analog levels.

[0013] In a fourth embodiment, an Orthogonal Frequency Division Multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs analog levels. A decoder successively decodes L levels using N codes of length L to produce a vector of N samples.

[0014] In a fifth embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting digital video samples maps input digital samples into I and Q components and outputs a signal representing the video samples using OFDM.

[0015] In a sixth embodiment, an Orthogonal Frequency Division Multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs digital samples. An inverse mapping maps the I and Q components to an output digital sample stream.

[0016] In a seventh embodiment, an orthogonal frequency division multiplexing (OFDM) transmitter for transmitting analog video samples maps input analog samples into I and Q components and outputs a signal representing the video samples using OFDM.

[0017] In an eighth embodiment, an Orthogonal Frequency Division Multiplexing (OFDM) receiver receives an OFDM modulated signal and outputs analog samples. A circuit combines the I and Q components to produce an output analog sample stream.

[0018] In a ninth embodiment, a source driver of a display unit includes a receiver that receives analog video samples, a register, and an amplifier that transmits the samples to a column of a display panel. The source driver does not include a DAC.

[0019] In a tenth embodiment, an apparatus includes a distributor that distributes digital video samples to OFDM transmitters, each transmitter mapping the digital samples to a constellation and generating an OFDM signal.

[0020] In an eleventh embodiment, a video transmitter includes a distributor that distributes digital video samples to a plurality of paths, each path including a digital-to-analog converter followed by an OFDM transmitter.

[0021] In a twelfth embodiment, a video receiver includes an OFDM receiver that outputs analog video samples, followed by a collector that outputs the samples to a plurality of column drivers.

[0022] In a thirteenth embodiment, a video transmitter includes a distributor that distributes digital video samples into input vectors and outputs samples of each input vector to an OFDM transmitter.

[0023] In a fourteenth embodiment, a video receiver includes an OFDM receiver that outputs digital video samples, followed by a digital-to-analog converter, and then a collector that outputs analog video samples to a plurality of column drivers.

[0024] In a fifteenth embodiment, a video transmitter includes a distributor that distributes analog video samples to input vectors and outputs samples of each input vector to an OFDM transmitter.

[0025] The present invention is particularly applicable to displays used in computer systems, televisions, monitors, gaming displays, home theater displays, retail signs, outdoor signs, and the like. Embodiments of the present invention are also applicable to video transmission within vehicles such as automobiles, trains, airplanes, ships, and the like, not only for video transmission from a transmitter to a display or monitor of the vehicle, but also for video transmission within such a display or monitor. In a particular embodiment, the present invention is useful within a display unit for transmitting and receiving video signals. For example, a transmitter of the present invention may be used to implement a transmitter described in U.S. Application No. 63 / 317,746, and a receiver of the present invention may be used to implement a receiver described in U.S. Application No. 63 / 280,017. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention and further advantages thereof may be better understood by reference to the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 An OFDM scheme for transmitting data using complex input is shown.

[0028] Figure 2 An example OFDM transmitter is shown.

[0029] Figure 3A An embodiment is shown of how the partitioning of MSBs and LSBs occurs within the mapping circuit.

[0030] Figure 3B A diagram showing how the values ​​represent points on the complex QAM plane is shown.

[0031] Figure 3C An example QAM constellation is shown.

[0032] Figure 4AAnother embodiment of how digital samples may be mapped within a mapping circuit is shown.

[0033] Figure 4B A diagram showing how the values ​​represent points on the complex QAM plane is shown.

[0034] Figure 5 A constellation mapping is shown, which helps describe how OFDM can use analog input levels.

[0035] Figure 6 An improved OFDM transmitter using simulated input values ​​is shown.

[0036] Fig. 7A An OFDM transmitter with a digital input is shown.

[0037] Figure 7B An OFDM transmitter with analog input is shown.

[0038] Figure 7C The IFFT bins used to produce the actual output are shown.

[0039] Figure 8 The digital encoding of the sampled signal before input to the OFDM transmitter is shown.

[0040] Fig. 9 A logical block diagram showing a specific implementation of the SSVT transmitter.

[0041] Fig.10 A simple example is shown, showing how a signal sample (in this case an analog value) is encoded within an encoder and then sent over an electromagnetic path.

[0042] Fig.11 It is shown that this novel encoding technique is applicable to signal samples that are digital values.

[0043] Fig.12 Shows the use of Fig.10 The encoder encodes the decoding of the analog input levels.

[0044] Fig.13A The use of an analog encoder and a corresponding analog decoder is shown.

[0045] Fig. 13B The use of a digital encoder and a corresponding analog decoder is shown.

[0046] Fig. 13C The use of a digital decoder to decode an encoded analog signal that has arrived via an electromagnetic path over a transmission medium is shown.

[0047] Fig.14 A simulation of a SSVT waveform sent via an electromagnetic pathway is shown.

[0048] Fig.15 The transmission of digital video samples from a video source to a video receiver using an OFDM transmitter and an OFDM receiver is shown.

[0049] Fig.16 The transmission of analog video samples from a video source to a video receiver using an OFDM transmitter and an OFDM receiver is shown.

[0050] Fig.17 An embodiment is shown in which both the OFDM transmitter and the OFDM receiver are located within a display unit 840, such as a large size television or screen.

[0051] Fig.18 A digital OFDM receiver with analog outputs at the source drivers is shown.

[0052] Fig.19 An analog OFDM receiver with analog outputs at the source drivers is shown.

[0053] Fig. 20 A source driver architecture of a display panel 850 that receives analog video samples output from an OFDM receiver is shown.

[0054] Fig.21 The structure of the transmitter is shown, which can be external or internal to the display unit.

[0055] Fig. 22 A preferred structure for the source drivers is shown, where each divider amplifier drives adjacent columns and all control signals are processed by a single amplifier.

[0056] Fig.23 The source drive inputs of a source driver for interleaving multiple input amplifiers are shown.

[0057] Fig.24 is a summary of the pixel transfer sequence, showing how pixels and control signals are transferred from the transmitter input vector to Fig. 22 source driver.

[0058] Fig.25 is a block diagram of an input vector to a transmitter having a predetermined arrangement that provides Fig.24 The required sequence of sub-pixel transfers.

[0059] Fig.26 The video transmission system within the display unit is shown. DETAILED DESCRIPTION

[0060] As previously mentioned, various embodiments of the present invention disclose analog signals for transmitting video information locally (e.g., within a display unit) or over long distances. For the purposes of this disclosure, an electromagnetic signal (EM signal) is a variable of electromagnetic energy represented by its amplitude varying over time. EM signals propagate from a transmitting end to a receiving end via EM paths, such as wire pairs (or cables), free space (or wireless), and light or waveguides (optical fibers). EM signals can be characterized as continuous or discrete in two dimensions, time and amplitude, respectively. A "pure analog" signal is an EM signal of continuous time and continuous amplitude, and a "digital" signal is an EM signal of discrete time and discrete amplitude. Discrete-time continuous amplitude EM signals may be referred to as "sampled analog" signals (although the signal is not necessarily sampled, discrete time values ​​may be inherent at its source), "discrete-time analog" signals, "clocked analog", or even "pulsating" signals. Continuous-time, discrete amplitude EM signals may be referred to as "discrete amplitude analog" signals, or even "neuron" signals. The analog levels, analog samples, and analog video samples mentioned herein are preferably discrete-time analog signals.

[0061] As mentioned above, electromagnetic pathways are inherently imperfect. In order to identify how the quality of an electromagnetic signal degrades when transmitting from a transmitter to a receiver in the case of transmitting encoded analog or digital samples, and to improve that transmission, the inventors of the present disclosure made the following realizations.

[0062] Important in the transmission of encoded analog or digital samples is the signal-to-noise ratio (SNR) of the electromagnetic signal, especially on electromagnetic paths such as cables. Moreover, various degradation mechanisms have been identified that lead to degradation of the signal-to-noise ratio - crosstalk, attenuation, thermal noise and nonlinear distortion. With respect to crosstalk, especially on shielded cables, it is recognized that far-side crosstalk (FEXT) is particularly problematic and is seen as noise in the receiver. In addition, again with respect to cables such as Cat-5, Cat-6 or Cat-7, it is recognized that the SNR is frequency-dependent and becomes significantly lower at higher frequencies and greater cable lengths. At these higher frequencies and longer cable lengths, the signal becomes attenuated, while crosstalk increases, both of which reduce the SNR. The second mechanism that reduces the SNR of electromagnetic signals is thermal noise. Due to these effects, the attenuation of the signal in the cable brings the signal closer to the constant background noise, again causing SNR degradation. The third mechanism that causes SNR degradation is nonlinear distortion. It is further recognized that SNR degradation also exists in other channels, such as wireless (wireless point links, such as point-to-point backhaul, LTE, Wi-Fi, etc.), optical channels, etc.

[0063] Therefore, knowing the importance of SNR in transmitting samples, the inventors have analyzed possible modulation techniques for transmitting these samples that would exploit the flexibility provided by SSVT to effect greater information density. One such modulation technique is Orthogonal Frequency Division Modulation (OFDM). Considering the encoding and transmission of digital or analog samples, it is recognized that OFDM combined with SSVT would provide increased information density while using increased electrical flexibility. Therefore, the inventors have concluded that combining OFDM with the encoding and transmission of analog and digital samples and improving OFDM would provide important advantages.

[0064] In particular, OFDM combined with SSVT output will have advantages when using electromagnetic paths with strong path length dependence and nonlinearity in optical fiber and in noisy environments and systems that require greater use of available bandwidth (such as cables and other media). In addition, in the absence of noisy or adverse environments, the improved performance due to the OFDM / SSVT combination directly translates to longer range in any such more ideal environments.

[0065] Furthermore, it is recognized that OFDM has been used in many high data rate wireless systems (as well as other EM pathways) because it provides many advantages that the OFDM / SSVT combination will also provide, including the following:

[0066] Resistant to Selective Fading: OFDM is more resistant to frequency selective fading than single carrier systems because it divides the overall channel into multiple narrowband signals which are individually affected as flat fading sub-channels.

[0067] Interference immunity: Interference that appears on a channel may be bandwidth limited so that it does not affect all sub-channels. This means that not all data is lost.

[0068] Spectral efficiency: OFDM makes efficient use of the available spectrum.

[0069] ISI immunity: OFDM is very resistant to inter-symbol and inter-frame interference. This is because of the low data rate on each sub-channel.

[0070] Resistant to narrowband effects: Using appropriate channel coding and interleaving, symbols lost due to frequency selectivity of the channel and narrowband interference can be recovered. Not all data is lost.

[0071] Simpler channel equalization: One of the problems with CDMA systems is the complexity of channel equalization that must be applied across the entire channel. The advantage of OFDM is that using multiple sub-channels, channel equalization becomes much simpler.

[0072] As described in more detail below, it is further recognized that video transmission using modified OFDM techniques (without SSVT input) has advantages in various embodiments.

[0073] OFDM transmitter with complex input

[0074] Figure 1 An OFDM scheme 1 for transmitting data using a complex input is shown. Other schemes for implementing an OFDM transmitter may also be used. As is known in the art, Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier modulation technique that uses multiple subcarriers in a channel. Each subcarrier will be modulated with a specific modulation scheme. OFDM is a traditional frequency division multiplexing (FDM), but it differs in that the multiple subcarriers are orthogonal to each other. Typically, an OFDM transmitter outputs complex numbers from its IFFT, but the present invention also contemplates a specific OFDM scheme with real numbers output from its inverse FFT, which will be described in more detail below.

[0075] exist Figure 1 Not shown is the input to the transmitter, which can be a digital input of a bit stream, or an analog input of analog levels, both of which will be described in detail below. In the case of digital input, the input bit stream can be encoded, interleaved and grouped, and then mapped to a specific constellation to produce a complex stream; digital modulation schemes such as BPSK, QPSK or QAM can be used, although QAM is preferred due to its better performance. As described in more detail below, an embodiment discloses a new technique for mapping the digital output levels or analog output levels of an encoder to a complex stream 7 for use by an OFDM transmitter. The encoder encodes digital or analog samples (e.g., video samples).

[0076] In another embodiment, for fixed channels that do not change over time (or infrequently), a technique called "bin loading" can also be used. For digital modulation, the attenuated bins (due to the channel) are either zeroed or mapped with a lower modulation order (e.g., QPSK instead of 64QAM). Bin loading requires a negotiation period between the receiver and the transmitter; the receiver updates the transmitter with the status of each bin in the channel estimate.

[0077] like Figure 1As shown, the OFDM scheme 1 has a specific channel bandwidth 3 and utilizes an arbitrary number of K orthogonal subcarriers 5, which may overlap. The input to the OFDM transmitter will be a complex stream 7 (the generation of which will be described in more detail below) for loading an arbitrary number of FFT bins 9, i.e., one complex number per bin. Each of these complex numbers (or source symbols) is considered to be in the frequency domain and will be input into an Inverse Fast Fourier Transform (IFFT) block 10 to transform the data into the time domain. Therefore, each complex number will specify the amplitude and phase of the sinusoid of a particular subcarrier. The number of orthogonal subcarriers used, and therefore the number of bins 9, will depend on the specific implementation.

[0078] Typically, not all bins contain input data, as some bins are pilot bins and zero bins do not contain input data. In addition, some bins in the high and low parts of the spectrum are also ordered and are called guard bins. These guard bins are intended to reduce interference to adjacent channels. Using today's technology, especially low phase noise frequency sources, the number of guard bins is about four on each side. Typically, the IFFT size is a power of 2 (e.g., 64, 128, 256, etc.), and to reduce implementation complexity, it will be a power of 4 (64, 256, 1024, etc.). As mentioned earlier, the zero subcarrier (bin) as the center frequency (or DC) is not used and is always zero. Pilot bins can be added for phase tracking or for channel estimation tracking during reception (if the channel is not fixed). In common practice in other standards that adopt low fading channels (pseudo-fixed channels), a pilot bin can be allocated for every 15 data bins. For fixed channels, pilot bins may be redundant and not used at all.

[0079] Once all bins of the IFFT block 10 have been loaded (each bin contains a complex number from the input stream), the inverse FFT takes this frequency domain input data (i.e., complex numbers representing subcarriers) and converts it to time domain output data, i.e., each subcarrier is independently modulated with its corresponding complex data. Each block 11 of K output samples is considered to be a single OFDM symbol. Each OFDM symbol 11 can be clocked in and out at a specific rate, thereby providing an OFDM waveform of a specific duration. Once in the time domain, a guard interval 13 of a specific duration is typically added between each OFDM symbol (usually added at the beginning of each waveform) to prevent interference between symbols at the receiver. Therefore, an OFDM symbol consists of the IFFT OFDM waveform plus the guard interval.

[0080] Each OFDM symbol may be further processed and the above process repeated to continuously generate OFDM symbols 11 from the input data. Prior to transmission, multiple OFDM symbols may be concatenated 15 and a preamble added (to help the receiver synchronize due to imperfections during transmission) to form a single time domain burst signal. This burst signal (or component baseband signals) may then be used to modulate a main RF carrier (for example) for transmission as an OFDM burst to an OFDM receiver, as is known in the art. At the OFDM receiver, an FFT is performed on the received OFDM symbols to bring them back to the frequency domain, as is known in the art.

[0081] To recover the original data input to the OFDM transmitter (the digital or analog output levels from the encoder), the novel mapping technique is reversed, as discussed in detail below. The digital or analog levels are then decoded to recover the original digital or analog samples (e.g., video samples) input to the encoder.

[0082] The number of concatenated OFDM symbols depends on the system requirements, for example, how quickly the system needs to resynchronize to the stream if the connection is lost. If fast lock is required, the preamble may appear more frequently. If the receiver needs to lock on the first preamble it receives, it should choose a preamble with a good autocorrelation peak; otherwise, a shorter and simpler preamble can be used.

[0083] Typically, to compute a single output of an IFFT, all input samples of the IFFT are used. Each output is the sum of all samples at the input, with each sample multiplied by a different factor that depends on the input / output index. Therefore, computing the K output samples uses all K bin components. After filling the K input bins, they are all used to compute the K output samples in the time domain. The K output samples represent the signal waveform of K consecutive samples, and each output is a complex value (in the case of a complex IFFT; real IFFT will be discussed below). These K output samples are collectively called an OFDM symbol.

[0084] Typically, a cyclic prefix (or guard interval) copies M samples from the end of the K IFFT output samples to the beginning of the OFDM symbol to eliminate inter-symbol interference. In most cases, the K IFFT output samples plus the M guard interval samples are called an OFDM symbol, not just the K IFFT output samples.

[0085] OFDM transmitter that maps digital input to complex numbers

[0086] The following embodiments use SSVT followed by OFDM, where digital samples or analog samples are input to an OFDM transmitter (e.g., Figure 2 and 6). This type of video transmission can be used to send video over long distances to a display, TV, or monitor, or it can be used internally in a display to send video from the display's inputs to the source drivers.

[0087] Figure 2 An improved OFDM transmitter 80 with digital input is shown. As shown, the output of the encoder described herein is L digital output levels 21 (e.g. Figure 8 The input digital levels 161) are input to the symbol mapping unit 30. Any of the techniques described herein may be used to map the input digital levels into complex numbers, namely the Q and I components 32 and 36.

[0088] In one example, a mapping technique from quadrature amplitude modulation (QAM) is used to generate complex numbers for modulation. As is known in the art, a sinusoid with angle modulation can be synthesized from two amplitude modulated sinusoids that are phase-shifted by a quarter period (pi / 2 radians); these amplitude modulated sinusoids are referred to as in-phase (I) and quadrature (Q) components. The digital levels 21 are received one at a time as a bit stream and are first input to a serial-to-parallel converter (not shown), which converts the bit stream into groups of parallel bits representing digital values, for example, if the digital value to be modulated is 4 bits long, the converter converts the bit stream into groups of 4 bits each. Each group is then input to a mapping unit 30 in a specific manner, depending on the mapping technique used. In this example, there is a single mapping unit that inputs the digital value and outputs I and Q values ​​to an inverse FFT circuit 39.

[0089] The symbol mapping unit 30 generates a Q component 32 and an I component 36; these two components, representing complex numbers, are then input to an inverse FFT circuit block 39 for processing by an IFFT as described above. Not shown is a guard interval (or cyclic prefix) insertion block, which may be located within or immediately following block 39. Thus, the IFFT circuit 39 generates output samples, each of which is a complex number having Q and I components 32a and 36a, which are input to low pass filters 40 and 42.

[0090] The Q and I components (I and Q are real signals, and the pair {I, Q} is a complex signal) are passed through low pass filters 40, 42, respectively, to limit the signal bandwidth. Next, the IF source 44 (essentially a numerically controlled oscillator) takes the in-phase component and the quadrature component and multiplies each signal by its amplitude, making the quadrature component 90° out of phase, and then adds the two in the summer 50. The output of the summer 50 will be a real signal representing the original digital value input to the transmitter; the DAC 51 converts the digital value to an analog value. A bandpass filter 60 can be used to filter out unwanted hotspurs and harmonics, and the resulting signal 70 can be fed into a variable gain amplifier (VGA) 78 to output an OFDM signal 90 representing a level 21. In another more conventional implementation (not shown), again referring to Figure 2 , there are DACs on both the I and Q paths (immediately before the low pass filters 42 and 40), and the subsequent blocks are implemented in analog fashion and do not require DAC 51. This implementation requires a lower sampling rate and may use cheaper components. Typically, amplifier 78 (and amplifiers 680, 748, 798 below) is used, but it does not have to be a VGA. In addition, although the output is shown as an RF signal 90 (or 690, 749, 799 below), the output signal can be any electromagnetic signal that propagates in wires, cables, optical fibers, etc.

[0091] As discussed above, it is recognized that QAM can be used to modulate subcarriers using various improvements to the mapping of the OFDM transmitter, as described below. Depending on the implementation, QAM constellations of different sizes can be used. In one example, a 16-QAM constellation can be used in conjunction with the transmitter 80 to map digital values ​​to complex numbers. In a 16-QAM constellation, each digital value is 4 bits; using the constellation mapping each digital value results in a vector having an amplitude and a phase. Of course, other smaller or larger constellations can also be used. For example, a 1024-QAM constellation can be used; each digital value in this constellation is 10 bits long. The most common QAM constellation sizes can be 4 n Calculated: 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM. Higher QAM constellation sizes are rarely used. Other 2 n QAM constellations do exist, but the encoding is more complex.

[0092] In other embodiments, the OFDM transmitter may be implemented in different ways. For example, there may be two mapping units 30a and 30b (each an M array PAM) instead of a single mapping unit 30. Each group of bits representing a digital value is split, for example, two bits are routed to unit 30a to produce a Q component, and two bits are routed to unit 30b to produce an I component. The inverse FFT circuit 39 may output the Q and I components 32a and 36a to an interpolation filter for increasing the sampling rate of the input signal. Two frequency conversion components receive the output from each interpolation filter and provide an upconverter of the frequency from the baseband signal. The NCO (numerically controlled oscillator, instead of an IF source) interacts with the conversion component to produce in-phase and quadrature components that are added together by a summer to produce a real output signal, followed by a DAC, filter, and VGA. These components may be embodied in the MAX5857 RF DAC (including a clock multiplication PLL / VCO and a 14-bit RF DAC core). Real samples with amplitude and phase derived from a constellation diagram are input at each clock cycle. This implementation assumes that the DACs are clocked at a high frequency, higher than or close to the RF frequency. In another alternative, there would be two DACs instead of a single DAC, one each on the I and Q paths before the interpolation filters. The implementation described in this paragraph may be superior to Figure 2 in , as it is a cleaner implementation.

[0093] Mapping numeric values ​​to complex numbers

[0094] Figure 2 The mapping in unit 30 implements symbol mapping and can be mapped in any suitable manner using circuit techniques known in the art. The symbol mapping 30 can also include a mapping circuit that maps the incoming digital levels in an improved manner as described below. In one embodiment, for each digital output level from the encoder, the lower half of each output level is sent via the Q path, and the upper half of the bit from each output level is sent via the I path. In another embodiment, each odd output level is sent via the Q path, and each even output level is sent via the I path. In another embodiment, if each digital output level is 12 bits long and 16-QAM is used, the value is divided into three groups of 4 bits each, each group is divided into two bits of I and Q values; other divisions can also be used. In another mapping embodiment, Gray encoding can be used. For digital data, Gray encoding is used to reduce the probability of multi-bit errors. Gray encoding means that the encoding of adjacent constellation points differs by only 1 bit.

[0095] In a preferred embodiment, the most significant bit (MSB) of each digital output level from the encoder is split and becomes the MSB of the I and Q paths, while the least significant bit (LSB) of each digital output level is split and becomes the LSB of the I and Q paths. For example, consider that the digital output level is a four-bit binary string [ABCD], each of the letters A, B, C, D represents a single binary digit (e.g., "1" or "0"), AB represents the most significant bit, and CD represents the least significant bit. These four bits will be distributed between the I and Q paths as follows: I=AC, Q=BD. Therefore, the most significant bit of the digital output level becomes the most significant bit on the I and Q paths, and the least significant bit of the digital output level becomes the least significant bit on the I and Q paths.

[0096] The reason for this allocation is due to the recognition that if there is noise or other interference in the transmission medium, then the received OFDM signal may be slightly distorted and the least significant bit may be lost. However, since the digital output levels of the present invention can represent media signals (e.g., pixel values ​​from a camera source), it is not strictly required from the transmitter to the receiver that every bit is perfectly preserved. In contrast, when transmitting digital data (such as documents) between computers, every bit transmitted must be perfectly preserved and complex error detection is required. In other words, OFDM receivers are less sensitive to errors on the LSB than errors on the MSB. Therefore, this allocation provides better protection for the MSB than the LSB. Unlike digital data transmission where every bit is critical, not all bits in this allocation have the same weight; the closer the position of the bit is to the MSB, the greater its importance. Therefore, by dividing the MSB and LSB of each digital output level between the I and Q paths, if the received OFDM signal is distorted and received errors occur, only the LSB of the original digital output level will be lost. Losing an LSB in the received media signal is not catastrophic.

[0097] Figure 3A An embodiment 500 is shown of how this division of MSBs and LSBs in a mapping circuit can occur. Assuming the digital output level X m 510 is represented by N bits, 510 has any number of MSB bits 512 and any number of LSB bits 514, the MSB bits are half or approximately half of the total number of bits. Then, assuming N is an even number, by selecting even bits and odd bits, the digital output level can be divided into two digital values, namely, XI m 530 and XQ m 520, that is, even bits (including 0) are assigned to the value 530 and odd bits are assigned to the value 520. Each new digital value XI m and XQ mIt can be further converted to a binary representation of signed values, where the MSB of each value becomes the sign of the value and the remaining bits become the magnitude of the value. The resulting values ​​531 and 521 are then used as the values ​​of the I and Q paths on the complex QAM plane, respectively. Of course, even bits can be assigned to the value 520 and odd bits to the value 530.

[0098] Even though in the above scheme, the MSB of each digital value becomes the sign bit, the value represented by the MSB is not lost. The idea is that values ​​that are "closer" to each other, such as the values ​​-1 and 0, map to very close constellation points. Even if the MSBs of two values ​​are not identical, if there is an error between the two values, there will only be an error of "1", which is the minimum possible error for an "analog" sample.

[0099] Other techniques for generating signed values ​​from values ​​520 and 530 are also possible. For example, another way of mapping the values ​​to constellation points rather than mapping the MSB to the sign bit can be performed by taking the unsigned value and subtracting an offset that is midway between the minimum and maximum values.

[0100] Figure 3B A diagram showing how values ​​521 and 531 represent point 542 on the complex QAM plane is shown.

[0101] Figure 3C An example QAM constellation 560 is shown. Note that since the number of bits used to represent XIM and XQM is finite, the number of actual values ​​that Im and QM may have is also finite. In this example, the raw digital output level 510 has 6 bits, so there are 3 bits each representing Im and QM, the first bit being the sign bit, which means that the value of each bit ranges from -3 to 3 as shown in the constellation diagram. Therefore, this constellation can be used to map XIM and XQM to I and Q values ​​for the I and Q paths of an OFDM transmitter.

[0102] Figure 4A Another embodiment of how to map digital output levels in a mapping circuit is shown. Here, the even and odd digital levels X m-1 and X m Each is directly mapped to the I and Q components using the same binary representation to map the digital levels to the QAM plane. Again, the MSB of each is treated as the sign bit. Assuming the input digital level X m 570 and subsequent digital level X m-1 572 are represented by N bits respectively. The obtained values ​​581 and 583 are then used as the values ​​of the I and Q paths in the complex QAM plane respectively.

[0103] Figure 4B A graph 590 showing how values ​​581 and 583 represent a point 592 on the complex QAM plane is shown.

[0104] OFDM transmitter with analog input mapped to complex numbers

[0105] As previously mentioned, and as described herein, one embodiment of the present invention may encode analog samples and generate analog output levels, rather than Figure 8 As shown, digital samples 112 are encoded to produce digital output levels 161. Thus, the L output levels from the encoder will be analog levels and may appear, for example, as Fig.14 This embodiment of the invention is also capable of using an improvement in orthogonal frequency division multiplexing (OFDM) to modulate and transmit these L analog output levels, as will now be described. Fig.14 As shown, analog levels can be positive or negative. These levels do not change how the mapping is performed. In the digital case, the idea behind setting the MSB as the sign bit is exactly to map an "unsigned" value to a value that can be positive or negative.

[0106] Figure 5 A constellation mapping 300 is shown which helps describe how OFDM uses the analog output levels of the encoder as input. Although the constellation still shows 16 digital values ​​304, no mapping to these values ​​is used and these values ​​are only shown to help the reader understand how the analog levels are input. Although a series of L analog output levels from the encoder can be converted to digital output levels and then input into the OFDM transmitter, such as Figure 2 The embodiment described herein uses the analog output levels directly, but in other words, the analog output levels themselves can directly represent the in-phase (I) and out-of-phase (Q) components.

[0107] Figure 6 An improved OFDM transmitter 610 with analog input is shown. L analog output levels 601 from an encoder as described herein are shown, which are input to the transmitter 610.

[0108] The switch device 612 performs a sample and hold function to present alternating samples (odd, even) of the received analog levels as time-aligned pairs that are simultaneously down the Q path 626 and the I path 628. Thus, every two analog levels will produce an {I, Q} pair. This time alignment is necessary to ensure that the serially presented analog levels are modulated simultaneously in the constellation. The switch 612 can be any suitable hardware device for selecting the destination of each level and assigning those levels to either path. In a corresponding OFDM receiver, the switch 612 is replaced by a combining device or synthesis circuit that accepts the {I, Q} pairs of the FFT, combines each pair into a series of two analog levels, and outputs a stream of analog levels corresponding to the analog levels originally received at the OFDM transmitter 610.

[0109] As previously described, switch 612 produces a Q component 626 and an I component 628. These two components represent complex numbers and are then input to an inverse FFT circuit block 639 for processing by the IFFT as described above. Therefore, each input to the IFFT circuit 639 also produces a complex number having Q and I components 626a and 628a, which are input to low pass filters 640 and 642. The Q and I components (I and Q are real signals and the pair {I, Q} is a complex signal) are passed through low pass filters 640 and 642, respectively, to limit the signal bandwidth. Next, IF source 644 (essentially a numerically controlled oscillator) takes the in-phase component and the quadrature component and multiplies each signal by its amplitude (which is the amplitude of the NCO and NCO offset by 90 degrees), makes the quadrature component 90 degrees out of phase, and then adds the two in summer 650. The output of the summer 650 will be a real signal (this real signal is also called a passband signal, which is a baseband signal offset to the frequency of the NCO) representing the original two continuous analog levels input to the transmitter. Unwanted hotspurs and harmonics can be filtered out with a bandpass filter 660, and finally amplified and output by a variable gain amplifier 680 OFDM signal 690, representing the original continuous input of the analog output level 601 from the encoder.

[0110] Before the inverse FFT block 639, a serial-to-parallel converter can be added to align the L samples in parallel (i.e., generate I, Q inputs in parallel) and then perform an IFFT. After the IFFT, a parallel-to-serial combiner is then used.

[0111] As an example, consider that given a series of L analog output levels 601, odd values ​​will be placed on the I path 628 and even values ​​will be placed on the Q path 626. Of course, odd values ​​can be placed on the Q path and even values ​​can be placed on the I path. Therefore, the I and Q components can each have different analog output levels. Taking output level 601 as an example, the first analog output level 602 will be placed on the I path, the second level will be placed on the Q path, the third level will be placed on the I path, and so on. To illustrate the example, return to Figure 5 , consider the first analog level is "2" and the second analog level is "3". Conceptually, these two values ​​(I, Q) can be mapped to point 310, resulting in a vector 312 with a specific amplitude and phase as shown. Next, consider the third analog level is "-2" and the fourth analog level is "-.5". Similarly, these two levels can be mapped to point 320, resulting in a vector 322 with a specific amplitude and phase as shown. In this manner, a series of L analog output levels 601 can be input into an OFDM transmitter 610 to produce an RF signal 690. Although the output 690 is shown as an RF output, it can also be output through other types of electromagnetic pathways, such as cables and optical fibers.

[0112] In fact, despite Figure 5 The QAM constellation is shown for ease of explanation, but it is not necessary to map each analog level to a specific digital constellation point (e.g., point 304) because each analog level can be used directly to provide I and Q values; the amplitude and phase of the resulting vector are determined using the I and Q values ​​as shown.

[0113] Direct mapping and other techniques using analog output levels are also possible. In the case of analog samples, it is useful to minimize the magnitude of the error. Therefore, it makes sense to map even samples and odd samples to I and Q respectively. Gray coding may not be suitable because for analog samples, the lower bits of each sample have a lower weight and are not as important as the higher bits. Therefore, odd levels can be sent down along the Q path 626 and even levels can be sent down along the I path 628, or vice versa.

[0114] OFDM transmitter with digital or analog input and real output from IFFT

[0115] The following embodiments generate real output values ​​from the inverse FFT. In general, if the inverse FFT of N values ​​is calculated, the output is complex. However, if the input bin is ensured to be conjugate symmetric, the inverse FFT output will be only real numbers, that is, for all N output values, the I component will be 0. Basically, this is achieved by using their conjugate repeating N / 2-1 complex I and Q symbols to generate N real values ​​at the output of the IFFT. This implementation does not require any NCO or frequency conversion because the output is real and it can be transmitted directly from the IFFT output. This is an advantage because there is no need to use an I / Q modulator of a carrier (NCO) to phase shift the I component (90 degrees) before the I component is added to the Q component. This 90-degree offset (for the entire signal spectrum) can only occur through this NCO+IQ mixer mechanism. These embodiments can be used to replace the above-mentioned embodiments in which the inverse FFT outputs complex numbers.

[0116] It is recognized that it is advantageous to generate signals directly into the spectrum of a "baseband" channel (such as an Ethernet cable). An Ethernet cable (or, for example, a telephone line) will pass signals starting at very low frequencies (perhaps a few Hertz) up to some finite frequency. Thus, the zero bin, also known as the DC bin, is the zero frequency (DC) and is not mapped to the center frequency of the available bandwidth. Furthermore, no frequency conversion is required in this embodiment.

[0117] Fig. 7A An improved OFDM transmitter 700a using digital input is shown. As shown, the output from the encoder as described herein is L digital output levels 701 that are input to a symbol mapping unit 730. Any of the techniques described herein (such as QAM modulation) can be used to map the input digital levels to complex numbers, i.e., I and Q components 732 and 734. In block 735, N real frequency FFT bins (corresponding to N subcarrier frequencies) are loaded with N / 2-1 of the I, Q symbol pairs received from unit 730.

[0118] Block 735 may be implemented as follows, assuming that there are N FFT bins corresponding to N subcarrier symbols, numbered from 0 to N-1. First, N / 2-1 symbols are collected from symbol map 730 (in the case of digital input) or switch 780 (in the case of analog input); each symbol x(i) is an I,Q pair representing a complex number from the map or switch, where: x(i), i = [1:N / 2-1]. Next, FFT bin 0 is set to 0 and FFT bin i = [1:N / 2-1] is set to x(i). Next, FFT bin N / 2 is set to 0 and FFT bin i = [N / 2+1:N-1] is set to x*(Ni), where "*" is the complex conjugate operator, i.e., bins immediately on either side of bin N / 2 will store the complex conjugates of each other, e.g., if bin N / 2-1 stores a+bi, then bin N / 2+1 stores a-bi, and bins immediately on either side of these first bins will store the complex conjugates, and so on. Therefore, the inverse FFT of these bins will produce real output, not complex output.

[0119] Furthermore, in many descriptions of the FFT, frequencies are indexed as positive and negative. Therefore, the above description can be changed to conform to the above criteria, and the following may occur: Next, FFT bin 0 is set to 0, and FFT bin i = [1:N / 2-1] is set to x(i). Next, FFT bin i = [-N / 2+1:-1] is set to x*(-i), and bin -N / 2 is set to 0, where "*" is the complex conjugate operator.

[0120] Block 735 generates an FFT bin that holds N-2 of the I, Q pairs 736 and 738 as described above, which are input to an inverse FFT block 739 and processed using an inverse FFT as described above and known in an OFDM transmitter. Due to the replication of N / 2-1 complex numbers in block 735, the inverse operation of FFT 739 will output real numbers instead of complex numbers. A cyclic prefix (or guard interval) is added in block 740, a digital-to-analog conversion is performed in block 742, a low-pass filter is performed in block 746, and finally the signal is amplified in VGA 748 to generate a final OFDM RF signal 749 to be output to an OFDM receiver along an electromagnetic path. Blocks 739-748 can be implemented as known in the art. Although output 749 is shown as an RF output, it can also be output through other types of electromagnetic paths such as cables and optical fibers.

[0121] Figure 7B An improved OFDM transmitter 700b with analog input is shown. As shown, the output from the encoder as described herein is L analog output levels 751 that are input to a switch 780. Any of the techniques described herein (such as Figure 5 and Figure 6784. The analog mapping techniques shown and described above may be used to map the input analog levels to complex numbers, namely, I and Q components 782 and 784. In block 785, the N real frequency FFT bins (corresponding to the N subcarrier frequencies) are loaded with N / 2-1 of the I,Q symbol pairs received from unit 780, as described above. Blocks 789-798 may be implemented as described above, except that DAC 742 is not required in this embodiment. Although output 799 is shown as an RF output, it may also be output via other types of electromagnetic paths such as cables or optical fibers. As described above Figure 6 As shown, the IFFT 789 may be preceded by a serial-to-parallel converter and followed by a parallel-to-serial combiner. Figure 6 As shown, no DAC is required.

[0122] Figure 7C IFFT bins used to generate real output are shown. Shown is an example of bin 710 where N=8; zero bin 722 is set to 0, and intermediate bin 723 is also set to 0. Bins 724 and 726 illustrate the application of complex conjugation for symmetric loading of the bins.

[0123] OFDM Receiver and Demodulator

[0124] Embodiments for an OFDM transmitter and embodiments for inputting and mapping L digital output levels from an encoder and for inputting and distributing L analog output levels from an encoder to transmit an OFDM electromagnetic signal to a receiver are described above. After reading this disclosure, those skilled in the art will find it straightforward to implement a corresponding OFDM demodulator and receiver that accepts an OFDM electromagnetic signal and outputs L digital output levels or L analog output levels as appropriate, using conventions used in the corresponding OFDM transmitter regarding digital mapping techniques or analog distribution techniques for generating complex numbers input to an inverse FFT. Similarly, if the OFDM transmitter inputs real numbers instead of the complex numbers described above, then it will be straightforward for those skilled in the art to implement the corresponding OFDM demodulator and receiver using conventions in the corresponding OFDM transmitter regarding how real numbers are input to an inverse FFT. In addition, similar to Figure 2 The OFDM transmitter in may be implemented with one or two DACs as described above, and the OFDM receiver may be implemented with one or two ADCs, one each in the I and Q paths, as will be appreciated by those skilled in the art.

[0125] Spread Spectrum Video Transmission (SSVT) signal

[0126] The embodiments of the present disclosure described above use a new type of discrete-time continuous-amplitude EM signal called a "Spread Spectrum Video Transmission" (SSVT) signal, which is an improvement over the existing SSDS-CDMA signal. SSVT refers to the transmission of electromagnetic (EM) video signals over an EM path to a video receiver using the new technology disclosed herein.

[0127] Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used in radio communication technologies, including cellular telephones. CDMA is an example of multiple access, in which several transmitters can send information simultaneously on a single communication channel. In telecommunications applications, CDMA allows multiple users to share a given frequency band without interference from other users. CDMA employs spread spectrum direct sequence (SSDS) coding, which relies on a unique code to encode each user's data. By using a unique code, the transmissions of multiple users can be combined and sent without interference between them. At the receiving end, the same unique code is used for each of the multiple users to demodulate the transmission, recovering each user's data separately. SSVT is different from CDMA, as will be explained in more detail below.

[0128] SSVT Transmitter Distributor / Encoder

[0129] Figure 8 1 shows the digital encoding of the sampled signal prior to input to the OFDM transmitter 80. As described herein, in U.S. Patent No. 10,158,396 and U.S. Patent Application Nos. 16 / 494,901 and 17 / 503,984, an input vector 110 comprising an arbitrary number of digital or analog samples is encoded within an encoder using a code from a codebook to produce L output levels 160 for input to the OFDM transmitter 80 and then transmitted over an electromagnetic path. A further description of this encoding technique can be found below. In this example, the samples are digital values, digital encoding is used, and the output levels 160 are digital values. As will be described in more detail below, analog samples, analog encoding, and analog output levels may also be used, Figure 6 and 7B An example of L analog output levels input to an OFDM transmitter is shown.

[0130] The input vector 110 includes N samples 112-118. In this example, each sample is 5 bits long and the value of sample 112 is "01101". There are N codes 122-128, each code corresponding to a sample, each code is L bits long, and are orthogonal to each other. In order to encode, each code chip of the code corresponding to a particular sample modulates 130 that sample, thereby producing L modulation values ​​for each sample. In this simple example, modulation of sample 112 by the first code chip of code 122 results in modulation value 142(1). Modulation of each sample by the first code chip of its corresponding code results in modulation values ​​142(1)-148(1). These modulation values ​​142(1)-148(1) are then summed 150 to produce a first digital output level 161. The other modulation values ​​142(2:L)-148(2:L) are then summed in a similar manner to produce the remaining output levels 160. This stream of digital output levels can then be input to Figure 2 and 7A OFDM transmitter, as described above. Although outputs 90 and 749 are shown as RF outputs, they can also be output via other types of electromagnetic pathways such as cables or optical fibers.

[0131] The output levels 160 may have any suitable bit length; in one embodiment, each output level is 10 bits long. Thus, the mapping of these values ​​may be performed using a 1024-QAM (e.g., for each number of bits n, 2^n QAM would be used) constellation for use with an OFDM transmitter that receives a digital input. And, as described above, if analog values ​​are input to the OFDM transmitter, no mapping to a constellation is required. Additionally, the digital or analog output levels from the encoder may also result in the OFDM transmitter using real numbers (rather than complex numbers). Improvements to the mapping of digital inputs, the mapping of analog inputs, and the use of real numbers are described in detail above.

[0132] Fig. 9A logical block diagram of a specific implementation of the SSVT transmitter 428 is shown. The distributor 440 includes an assembly library 450, a classification library 452, a representation library 454, and a controller 456. The encoder block 460 includes a library of digital-to-analog converters (DACs) 462 and four encoders 442, one for each EM path of the transmission medium. As previously described, a sample stream from a single source (such as a camera, an image sensor, another sensor, etc.) arrives at the transmitter 428 for encoding. Each encoder 442 encodes an input vector, such as input vector 110, and produces a series of output levels, such as output level 160, as an EM signal. Therefore, there can be any number (P) of encoders 102 and corresponding OFDM transmitters, one encoder and OFDM transmitter for each EM path. It is also possible to multiplex multiple encoder outputs to a single OFDM transmitter, in which case there will be fewer transmitters than encoders.

[0133] The distributor 440 is arranged to receive the exposed color information (e.g., RGB) of the sample set stream one by one. In response, the assembly library 450 constructs four vectors V0, V1, V2, and V3 according to the exposed color information (e.g., RGB) of the input stream of the sample set. When the sample sets are received, they are stored in the assembly library 450 according to a predetermined arrangement. The distributor 440 can use any number of different arrangements when constructing each vector containing N samples.

[0134] The staging library 452 facilitates crossing the N samples of each of the four vectors V0, V1, V2, and V3 from a first clock frequency (or first clock domain) used by the retimer to a second clock frequency (or second clock domain) used to encode and transmit the resulting electromagnetic signal over a transmission medium. Using the example of N=60 and S=3, samples representing exactly 80 sets of RGB samples are contained in the four encoder input vectors V0, V1, V2, and V3.

[0135] In various embodiments, the first clock frequency can be faster, slower, or the same as the second clock frequency. The first clock frequency f_pix is ​​determined by the video format selected by the video source. The second clock frequency f_ssvt is a function of f_pix, the number of EM paths P in the transmission medium, the number of samples S in each group of input / output samples, and the SSVT transformation parameters N (the number of input / output vector positions) and L (the length of each SSDS code), f_ssvt = (f_pix**L) / (P*N). With such an arrangement, the input clock (pix_clk) oscillates at one rate and the SSVT clock (ssvt_clk) oscillates at another rate. These rates can be the same or different. In preparation for the next input vector, the encoder performs encoding. The representation library 454 presents N samples of each of the four encoder input vectors V0, V1, V2, and V3 to the encoder block 460 (for example, vector V0 includes Sample 0,0 To Sample 0,N-1 )

[0136] Controller 456 controls the operation and timing of assembly library 450, staging library 452, and representation library 454. In particular, the controller is responsible for defining the number of permutations and samples N used when constructing the four encoder input vectors V0, V1, V2, and V3. Controller 456 is also responsible for coordinating the clock domain crossing from a first clock frequency to a second clock frequency performed by staging library 452. Controller 456 is further responsible for coordinating the timing at which representation library 454 presents N samples of each of encoder input vectors V0, V1, V2, and V3 to encoder block 460.

[0137] In the encoder block 460, a plurality of digital-to-analog converters (DACs) 462 are provided, each of which is arranged to receive P*N samples (Sample) commonly distributed to four encoder input vectors V0, V1, V2 and V3. 0,0 To Sample P-1,N-1 ) in one of the DACs 462. Each DAC 462 converts the samples it receives from the digital domain into a differential pair of voltage signals having amplitudes proportional to its input digital values. The output range of the DAC 462 can be from a maximum voltage to a minimum voltage.

[0138] Four encoders 442 are provided with four encoder input vectors V0, V1, V2 and V3, respectively. Each encoder 442 receives a differential signal pair of N samples of its encoder input vector, modulates each of the differential pairs of N voltage signals using a chip corresponding to the code of each sample, accumulates the modulated values, and then generates a differential EM signal output. Since there are four encoders 442 in this example, there are EM signals (Signal0 to Signal3) that are transmitted simultaneously through the transmission medium.

[0139] The sequencer circuit 465 coordinates the operation timing of the DAC 462 and the encoder 442. The sequencer circuit 465 is responsible for controlling the clocks of the DAC 462 and the encoder 442. The sequencer circuit 465 is also responsible for generating two clock phase signals, “clk1” and “clk2”, which are responsible for controlling the operation of the encoder 442.

[0140] A receiver corresponding to the transmitter 428 may be used to receive the output levels, decode, and collect the samples into an RGB signal, as will be understood by those skilled in the art upon reading this disclosure. This example shows analog encoding, but digital encoding (and decoding) may also be used. The DAC or ADC may precede or follow the encoder (or decoder), depending on the circumstances and the needs of the implementation.

[0141] SSVT signals, encoding and decoding

[0142] As described above, various embodiments of the present invention disclose a coded output level (analog or digital) - SSVT signal - input to an OFDM transmitter, or an OFDM receiver receives an OFDM modulated signal and generates an SSVT signal for decoding. The SSVT signal will be described in more detail below and its advantages will be provided.

[0143] Embodiments of the present invention disclose a new "Spread Spectrum Video Transmission" (SSVT) signal (which is a discrete time, continuous amplitude EM signal) that is an improvement over existing SSDS-CDMA signals. SSVT refers to the transmission of electromagnetic signals over an EM path using an improved Spread Spectrum Direct Sequence (SSDS) based modulation.

[0144] Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used in radio communication technologies, including cellular phones. CDMA is an example of multiple access, where several different transmitters can send information simultaneously on a single communication channel. In telecommunications applications, CDMA allows multiple users to share a given frequency band without interference from other users. CDMA employs spread spectrum direct sequence (SSDS) coding, which relies on a unique code to encode each user's data. By using a unique code, the transmissions of multiple users can be combined and sent without interfering with each other. At the receiving end, the same unique code is used for each user to demodulate the transmission and recover each user's data separately.

[0145] SSVT signals are different from CDMA. When the encoder receives a stream of input video (for example) samples, they are encoded by applying SSDS-based modulation to each of the multiple encoder input vectors to generate an SSVT signal. The SSVT signal is then transmitted over the transmission medium. At the receiving end, the incoming SSVT signal is decoded by applying the corresponding SSDS-based demodulation to reconstruct the encoded samples. As a result, the original time-sequential video sample stream containing color and pixel related information is transmitted from a single video source to a single video receiver, rather than transmitting data from multiple users to multiple receivers as in CDMA.

[0146] Fig.10 A simple example is shown showing how signal samples (in this case analog values) are encoded in an encoder and then sent over an electromagnetic path. Shown is an input vector of N analog values ​​902-908 representing the voltages of individual pixels within a video frame. These voltages can represent the brightness of a black and white image or the brightness of a particular color value in a pixel, such as the R, G, or B color value of a pixel, i.e., each value represents the amount of light perceived or measured in a specified color space. Although pixel voltages are used in this example, this encoding technique can be used with voltages representing any of a variety of signals from sensors, such as LIDAR values, sound values, tactile values, aerosol values, etc., and the analog values ​​can represent other samples, such as currents, etc. Signal samples that are digital values ​​can also be encoded, and such digital encoding will be explained below. In addition, even though one encoder and one EM path are shown, embodiments of the present invention can work well with multiple encoders, each transmitting on an EM path.

[0147] Preferably, for efficiency, these voltages range from 0 to 1V, but different ranges are possible. These voltages are typically taken from the pixels in a row of a frame in a particular order, but another convention may be used to select and order these pixels. Regardless of which convention is used to select these pixels and order them for encoding, the decoder at the receiving end will also use the same convention to decode these voltages in the same order and then place them into the resulting frame to which they belong. Similarly, if the frame is color and uses RGB, the convention in this encoder may be to encode all the R pixel voltages first, then the G and B voltages, or the convention may be that voltages 902-906 are the RGB values ​​of the pixels in the row, and the next three voltages 908-912 represent the RGB values ​​of the next pixel, and so on. Again, the same convention used by this encoder to order and encode the voltages will be used by the decoder at the receiving end. Any particular convention for ordering the analog values ​​902-908 (whether by color value, by row, etc.) may be used as long as the decoder uses the same convention. As shown, any number of N analog values ​​902-908 may be present at one time for encoding using codebook 920, limited only by the number of entries in the codebook.

[0148] As previously described, codebook 920 has an arbitrary number of N codes 932-938; in this simple example, the codebook has 4 codes, which means that 4 analog values ​​902-908 are encoded at a time. A larger number of codes can be used, such as 127 codes, 255 codes, etc., but due to practical considerations such as circuit complexity, it is preferred to use fewer codes. As is known in the art, codebook 920 includes N mutually orthogonal codes of length L; in this example, L=4. Typically, each code is an SSDS code, but not necessarily a spreading code as discussed herein. As shown in the figure, each code is divided into L time intervals (also called "chips"), each time interval including a binary value of the code. As shown in code representation 942, code 934 can be represented in the traditional binary form "1100", although the same code can also be represented as "11-1-1", as shown in code representation 944, for convenient use when modulating values, as will be explained below. Codes 932 and 936-938 can also be represented by 942 or 944. Note that unlike what is done in CDMA, each code of length L is not associated with a different computing device (eg, a phone), a different person, or a different transmitter.

[0149] Thus, to transmit four analog values ​​902-908 over transmission medium 34 to a receiver (having a corresponding decoder), the following technique is used. Each analog value will be modulated by each chip in the representation 944 of the corresponding code; for example, value 902, i.e., .3, is modulated 948 sequentially in time by each chip in the representation 944 of code 932. Modulation 948 may be a multiplication operator. Thus, the result of modulating .3 by code 932 is ".3,.3,.3,.3". Modulating .7 by code 934 becomes ".7,.7,-.7,-.7"; the value "0" becomes "0,0,0,0"; and the value "1" becomes "1,-1,1,-1". Typically, the first chip of each code modulates its corresponding analog value, and then the next chip of each code modulates its analog value, although an implementation may also modulate a particular analog value by all chips of its code before moving on to the next analog value.

[0150] Each time interval, the modulated analog values ​​are then summed at 951 (perceived vertically in the figure) to obtain analog output levels 952-958; for example, the sum of the modulated values ​​for these time intervals results in output levels of 2, 0, .6, -1.4. These analog output levels 952-958 can be further normalized or amplified to conform to the voltage limitations of the transmission line, and can then be transmitted sequentially in time on the electromagnetic path (e.g., differential twisted pair) of the transmission medium 34 in the order in which they were generated. The receiver then receives those output levels 952-958 in sequence and then decodes them using the same codebook 920 using a scheme that is the opposite of the encoding scheme shown here. The resulting pixel voltages 902-908 can then be displayed in a frame of a display at the receiving end according to the convention used. Therefore, the analog values ​​902-908 are effectively synchronously encoded and transmitted on a single electromagnetic path in a sequential sequence of L analog output levels 952-958. Many encoders and electromagnetic channels can also be used, as shown and described herein. Furthermore, the number of N samples that can be encoded in this manner depends on the number of orthogonal codes used in the codebook.

[0151] Advantageously, even though the use of robust SSDS techniques (such as spread spectrum codes) would result in a significant reduction in bandwidth, the use of mutually orthogonal codes, modulating each sample by the chip of its corresponding code, summing, and transmitting N samples in parallel using L output levels can result in significant bandwidth gains. Compared to conventional CDMA techniques that serially encode binary digits and then sum, the present invention first modulates the entire sample (i.e., the entire analog or digital value, rather than a single bit) by each chip in the corresponding code, and then sums these modulations at each time interval of the code to obtain a composite analog voltage level for each specific time interval, thereby utilizing the amplitude of the composite waveform. It is these analog output levels that are sent across the transmission medium, rather than representations of binary digits. In addition, the present invention facilitates sending analog voltages from one video source to another video receiver, i.e., from endpoint to endpoint, unlike CDMA techniques that allow multiple access by different people, different devices, or different sources and send to multiple receivers. In addition, the transmission of sample values ​​does not require compression.

[0152] Fig.11 This new encoding technique is shown to be applied to signal samples as digital values. Here, digital values ​​902'-908' are digital representations of voltages. Using another example of voltages, value 902' is "1101", value 904' is "0011", value 906' is "0001", and value 908' is "1000". Each digital value is modulated (digitally multiplied) by the representation 944 of each code, i.e., modulated by "1" or by "-1", depending on the code chip of the code corresponding to the digital value to be modulated. Considering only the first time interval 940 of each code, and adding the most significant bit (MSB) as a sign bit, modulation "1101" results in "01101" (MSB "0" represents a positive value), modulation "0011" results in "00011", modulation "0001" results in "00001", and modulation "1000" results in "01000". These modulated values ​​are shown as being marked on the first time interval. (Although not shown, modulation by a -1 chip produces negative values ​​which can be represented in binary using a suitable binary representation.)

[0153] Digitally summed, the modulation values ​​in these first time intervals produce the digital value 952'"011001" (again, the MSB is the sign bit); the other digital values ​​954'-958' are not shown in this example, but are calculated in the same way. Considering this base 10 summation, it can be verified that the sum of the modulation values ​​13, 3, 1, and 8 is indeed 25. Although not shown in this example, since the sum may require more than five bits, typically additional MSBs will be available for the resulting levels 952'-958'. For example, if the values ​​902'-908' are represented by 4 bits, then with 64 codes (adding the log2 of 64 bits), the levels 952'-958' may be represented by as many as 10 bits. Alternatively, if 32 modulation values ​​are added, an additional 5 bits will be added. The number of bits required for the output level depends on the number of codes.

[0154] The output levels 950' may first be normalized to accommodate the input requirements of the DAC and then sequentially fed into the DAC 959, which converts each digital value into a corresponding analog value for transmission over the EM path. The DAC 959 may be a MAX5857 RFDAC (including a clock multiplication PLL / VCO and a 14-bit RF DAC core, and the complex path may be bypassed to directly access the RFDAC core), followed by a bandpass filter and then a variable gain amplifier (VGA), not shown. In some cases, the level 950' uses a greater number of bits than the DAC 959 allows, for example, the level 952' is represented by 10 bits, but the DAC 959 is an 8-bit DAC. In this case, an appropriate number of LSBs are discarded and the remaining MSBs are processed by the DAC without loss of visual quality of the resulting image at the display.

[0155] Advantageously, the entire digital value is modulated and then these entire modulated digital values ​​are digitally summed to produce a digital output level for conversion and transmission. This technique differs from CDMA, which modulates each binary digit of the digital value and then adds these modulated bits to produce an output. For example, assuming that each digital value has B bits, for CDMA, there will be a total of B*L output levels to be sent, while using this new digital (or analog) encoding technique, there are only a total of L output levels to be sent, so it is advantageous.

[0156] Fig.12 Shows the use of Fig.10Decoding of analog input levels encoded by an encoder. As shown, L input levels 950 have been received on a single electromagnetic path of a transmission medium 34. As described herein and previously, codebook 920 includes N orthogonal codes 932-938, which will be used to decode input levels 950 to produce an output vector of N analog values ​​902-908 (i.e., the same analog values ​​902-908 encoded above). In order to perform decoding, as shown by the vertical arrows, each input level 952-958 is modulated 961 by each code chip of each code corresponding to a specific index in the output vector 902-908. Considering that the levels 952-958 are modulated by the first code 932, this modulation produces a series of modulation values ​​"2, 0, .6, -1.4". The levels 952-958 are modulated by the second code 934, producing a series of modulation values ​​"2, 0, -.6, 1.4". Modulation by the third code 936 generates “2, 0, -.6, -1.4”, and modulation by the fourth code 938 generates “2, 0, .6, 1.4”.

[0157] Next, as indicated by the horizontal arrows, the modulated values ​​of each series are added to produce one of the analog values ​​902-908. For example, summing the first series results in an analog value of "1.2" (which becomes ".3" after normalization using a scaling factor of 4). In a similar manner, the modulated values ​​of the other three series are added to produce analog values ​​"2.8", "0", and "4" and, after normalization, an output vector of analog values ​​902-908. Each code can modulate the input level and then sum the series, or all codes can modulate the input level before summing each series. Thus, an output vector of N analog values ​​902-908 is transmitted in parallel using L output levels.

[0158] Examples of decoding the digital input levels are not shown in these examples, but those skilled in the art will find that such decoding can be performed directly after reading the digital value encoding in the above description.

[0159] Fig.13A , 13B and 13C show that the encoder and decoder can work on analog samples or digital samples; various analog and digital encoders and decoders have been described above. As mentioned above, there may be more than one EM path, and accordingly there may be more than one encoder / decoder pair and a corresponding number of DACs or ADCs, as the case may be.

[0160] Fig.13AThe use of an analog encoder and a corresponding analog decoder is shown. Input to the analog encoder 900 is an analog sample 970 or a digital sample 971 that has been converted to analog by a DAC 972 located at the analog encoder. In this way, the analog or digital samples arriving at the analog encoder can be encoded for transmission through an electromagnetic path on a transmission medium 34. The analog decoder 900' decodes the encoded analog samples to produce analog samples 970 for output. The analog samples 970 can be used as is, or can be converted to digital samples using an ADC (not shown).

[0161] Fig. 13B The use of a digital encoder and a corresponding analog decoder is shown. Input to the digital encoder 901 is a digital sample 971 or an analog sample 970 that has been converted to digital by an ADC 973 located at the digital encoder. Since the encoder is digital, a DAC 959 located at the encoder converts the encoded sample to analog before transmission through the electromagnetic path. In this way, the analog or digital samples arriving at the digital encoder can be encoded for transmission through the electromagnetic path on the transmission medium 34. The analog decoder 900' decodes the encoded analog sample to produce an analog sample 970 for output. The analog sample 970 can be used as is, or can be converted to a digital sample using an ADC (not shown).

[0162] Fig. 13C The use of a digital decoder to decode the encoded analog signal arriving via the electromagnetic path on the transmission medium 34 is shown. The encoded analog signal can be transmitted using the analog encoder or the digital encoder described above. The ADC 974 located at the digital decoder 976 receives the encoded analog samples sent via the electromagnetic path and converts the samples to digital. These encoded digital samples are then decoded by the digital decoder 976 into digital samples 978 (corresponding to the values ​​of the input vector of the original encoded samples before transmission through the electromagnetic path). The digital samples 978 can be used as is, or can be converted into analog samples using a DAC.

[0163] Fig.14 A simulation (similar to an idealized oscilloscope trace) of an SSVT waveform 602 sent through an electromagnetic path after being output from an analog encoder (or after being digitally encoded and then converted by a DAC) is shown. The vertical scale is voltage and the horizontal scale is the 100ps oscilloscope measurement time interval. Note that the SSVT signal 602 is an analog waveform and not a digital signal (i.e., the signal does not represent binary digits), and can transmit a voltage range from about -15V to about +15V in this embodiment. The voltage values ​​of the analog waveform are (or at least can be) completely analog. In addition, the voltage is not limited to some maximum value, although high values ​​are impractical.

[0164] As previously described, analog voltage levels are sent sequentially through electromagnetic paths, with each level being the sum of the modulated samples per time interval, such as the analog output levels 952-958 above or the digital output levels 952'-958' above (after passing through the DAC). When sent, these output levels are then presented as waveforms, such as waveform 602. In particular, voltage level 980 represents the sum of the modulated samples (i.e., the output level) within a particular time interval. Using a simple example, sequential voltage levels 980-986 represent the transmission of four output levels. In this example, 32 codes are used, which means that 32 samples can be transmitted in parallel. Therefore, voltage levels 980-986 (followed by a plurality of subsequent voltage levels, depending on the number of chips in the code, L) form a parallel transmission of 32 encoded samples (such as pixel voltages from a video source). After this transmission, the next set of L voltage levels of waveform 602 represents the transmission of the next 32 samples. In general, waveform 602 represents encoding analog or digital values ​​into analog output levels, and transmitting these levels in discrete time intervals to form a composite analog waveform.

[0165] Each electromagnetic path degrades the electromagnetic signal propagating through it due to phenomena such as attenuation, reflections caused by impedance mismatches, and impingement attack signals, so there is always an error in the input level measured at the receiving end compared to the corresponding output level available at the transmitting end. Therefore, the input level at the receiver can be scaled (or the output level at the transmitter can be normalized or amplified) to compensate, as is known in the art. In addition, due to processing gain (i.e., due to the increase in L, the electroelasticity is also increased), the decoded input level at the decoder is normalized by using a scaling factor of the code length to recover the transmission output level, as is known in the art.

[0166] OFDM video transmission

[0167] Techniques and related improvements combining spread spectrum video transmission (SSVT) techniques with orthogonal frequency division multiplexing (OFDM) are described above to provide more resilient sample transmission. It is further recognized that OFDM transmission without SSVT has significant advantages and sufficient resiliency, especially when its related improvements (such as improved symbol mapping of digital and analog samples, real output of IFFT, etc.) are introduced or when used to transmit video samples. Embodiments of these new OFDM transmission techniques are described below.

[0168] For example, this OFDM video transmission can be used to wirelessly send video to a display, TV, or monitor over relatively long distances. OFDM video transmission can be used to send video over high-frequency wireless channels, such as 60 GHz, where 2 GHz bandwidth is possible, although the wireless channel may require dynamic equalization due to channel variations. Digital transmission requires error correction codes to address these issues; OFDM video transmission does not require these error correction codes.

[0169] One advantage of using OFDM transmission in the context of image capture and display is that images are traditionally measured on intrinsically error-prone sensors, displayed on intrinsically noisy LED arrays, and viewed by the extremely complex and robust human visual system. Therefore, the communication requirements for video are very different from those for traditional digital artifacts such as spreadsheets and email, where bit-perfect transmission is required. However, traditional video transmission treats the video signal as just another (digital) document. However, with OFDM video transmission, the video signal is transmitted in an electrically robust manner. One of the advantages of OFDM video transmission is that any uncompensated errors that occur in the measurement of the EM signal at the receiver appear as broad-spectrum temporal and spatial noise in the reconstructed image. This white noise is much more perceptible to humans than the blank screens, repeated images, and block compression artifacts produced by traditional bit-serial transmission.

[0170] Fig.15 The transmission of digital video samples from a video source to a video receiver using an OFDM transmitter and an OFDM receiver is shown. Shown is a video source 802 that generates digital video samples 812. The video source includes an image sensor array 804, one or more analog-to-digital converters 806, an optional image signal processor (ISP 808), and an optional video streamer 810 responsible for generating a video sample stream 812. The video source 802 can be any device capable of capturing imaging information, such as, but not limited to, a still camera, a video camera, an infrared imaging device, an ultrasound imaging device, a magnetic resonance imaging (MRI) device, a computed tomography scan, or any other type of imaging device capable of generating video information.

[0171] Image sensor 804 is any device capable of producing an electronic signal proportional to the amount of light being measured. For example, an image sensor is a planar array of photodiodes. Each photodiode represents a pixel position in the planar array, and the number of photodiodes in the planar array can vary widely and depends on the size of the image sensor. For example, a "4K" imaging sensor includes a photodiode array consisting of 3840 horizontal lines by 1080 vertical lines, for a total of 4,147,200 photodiodes. It should be understood that 4K is merely an example of resolution, and image sensor 804 can be any size, including less than 480, 480, 720, 1080, 4K, 8K, or larger.

[0172] During operation, the image sensor 804 continuously repeats sensing intervals at a given refresh rate. During each sensing interval, each photodiode in the array generates a voltage for each pixel location that is inversely proportional to the number of photons generated by the photodiode. As a result, the photodiode array generates a set of voltages that collectively represent a frame. When the image sensor is constantly refreshed at a given frame rate, multiple sets of voltages are continuously generated in succession, each set of voltages representing a frame.

[0173] For each pixel location, a photodiode is placed between a capacitor and ground. Just before the sensing interval, the capacitor is pre-charged. When sensing, the photodiode produces a current that is proportional to the amount of light received. When little or no light is sensed, little or no discharge of the capacitor to ground occurs through the photodiode. Conversely, if a large amount of light is sensed, then most of the voltage on the capacitor is discharged. Therefore, the voltage that remains on the capacitor after the exposure interval is inversely proportional to the amount of light sensed.

[0174] For an image sensor array, there is typically a row of analog-to-digital converters ("ADCs") 806, one for each column. During a given frame interval, all rows of the array 804 are sampled, typically sequentially from top to bottom, sometimes referred to herein as a "row major" order. For each sample, the ADC converts the sensed voltage into a digital value for the pixel location in each column of the array. When all rows of the array have been sampled, the frame is complete. The above process is repeated frame by frame in row major order. The end result is a string of digital values, each representing a pixel location in the frame. The number of bits used to represent each sample can vary greatly. For example, each voltage can be converted by the analog-to-digital converter 806 to an 8-bit or 10-bit value; the number of bits used to represent the pixel voltage value can be greater or less than 8 or 10.

[0175] The image sensor array 804 can be monochrome or color. In the former case, the digital value generated by the ADC represents only one color. For the latter, well-known color techniques such as Bayer filtering are usually applied. Using Bayer filtering, individual photodiodes are selectively covered with filters of predetermined colors (e.g., red, blue, or green). In alternative embodiments, CYGM (cyan, yellow, green, and magenta) or CMY (cyan, magenta, and yellow) filtering can be used. Regardless of which filter is used, the size of the filtered light is measured at each sample position.

[0176] The ISP 808 is arranged to interpolate a string of digital values ​​received from the ADC. By interpolation, the ISP 808 obtains the information contained in the digital values ​​of each pixel measurement and its geometric neighborhood, and defines an estimate of the color of the corresponding pixel. In order to output a full-color image in a specific color space (there are many), the ISP 808 inserts the "missing" color value at each position. That is, given only monochrome measurements of each pixel, the ISP estimates the "missing" color value through an algorithm to create, for example, an RGB or YCbCr representation of the pixel. The ISP 808 thus generates a set of samples for a given pixel of a given frame, each set of samples representing the color value (measured or interpolated) of a given pixel position within the frame.

[0177] Because there are many ways to represent color, the content of a given set of samples may vary. In general, RGB is considered full color, while other spaces such as YCbCr are approximations that transmit smaller full colors. For YCbCr, Y is the brightness component, and Cb and Cr are blue difference chrominance values ​​and red difference chrominance values, respectively. The YCbCr color space is defined by a mathematical coordinate transformation from the associated RGB color space. In another method of representing color, an "alternating" method can be used. For example, every other pixel is represented by its brightness (Y) value, while alternate pixels are represented by Cb (blue) or Cr (red) values. Accordingly, each set of samples includes S sample values ​​that are transmitted in parallel. For RGB, the number of samples in each set of samples is S=3, while for YCbCr, S=2.

[0178] The video streamer 810 generates a sequence of time-ordered sets of samples received from the ISP 808. In general, each set of samples output together represents a measurement of light at one pixel location on the image sensor 804. The value and number of samples generated by the ISP at each pixel location depends on the ISP implementation, in particular the color space of the application. The output of the video streamer 810 is a continuous stream of time-ordered sets of digital video samples 812, each set of samples representing pixels in a row, from left to right, in row-major order, one frame after another, as long as the image sensor 804 is sensing. Once the stream of sets of digital video samples 812 is sent and received at the video receiver 818, the video receiver processes the samples to reconstruct the image sensed by the image sensor array 804 frame by frame.

[0179] Once output from video source 802, digital video samples 812 are input to OFDM transmitter 80 or OFDM transmitter 700a (respectively). Figure 2 and Fig. 7A8 (shown), and then transmitted via OFDM signal 90. The OFDM transmitter may be located in any suitable location: integrated with video source 802, close to video source 802, or remote from video source 802. Once transmitted, OFDM signal 90 may travel any suitable distance before being received.

[0180] In one embodiment, the transmitter does not require a DAC or DACs, and the output signal 90 will be a digital signal. In a corresponding receiver, no ADC is required before the FFT circuit. If the frequency conversion is implemented in the analog domain, an implementation without a DAC or ADC is possible.

[0181] Once transmitted, the OFDM signal 90 is received at an OFDM receiver 814 (which may be a receiver corresponding to the transmitter 80 or the transmitter 700a). After reading this disclosure and understanding the operation of the OFDM transmitter 80 or the OFDM transmitter 700a, those skilled in the art will find that it is straightforward to implement such an OFDM receiver 814. The location of the OFDM receiver 814 can be specified based on the location of the OFDM transmitter and the distance over which the OFDM signal 90 is desired to be transmitted. The OFDM receiver 814 may be very close to the video source, may be located between the video source and the video receiver, or may be located near the video receiver or inside the video receiver. Once the digital video samples 816 are output from the OFDM receiver 814, they are transmitted to the video receiver and displayed on its display panel using techniques known to those skilled in the art.

[0182] Fig.16 The transmission of analog video samples from a video source to a video receiver using an OFDM transmitter and an OFDM receiver is shown. Shown is a video source 822 that generates analog video samples 832. The video source can be any of the video sources described above and includes an image sensor array 824 as previously described. Note that in this embodiment, no analog-to-digital converter (ADC) is required within the video source, thereby reducing the cost, space required, heat generated, and complexity of the video source. An ISP can be added if desired.

[0183] The output of the video source 822 is analog video samples 832. Once the stream of analog video sample sets is transmitted and received at the video receiver 838, the video receiver processes the samples to reconstruct the image sensed by the image sensor array 824 on a frame-by-frame basis.

[0184] Once output from video source 822, analog video samples 832 are input to OFDM transmitter 610 or OFDM transmitter 700b (respectively). Figure 6 and 7B822), and then transmitted via OFDM signal 690. The OFDM transmitter may be located in any suitable location: integrated with video source 822, in close proximity to video source 822, or remote from video source 822. Once transmitted, OFDM signal 690 may travel any suitable distance before being received.

[0185] Once transmitted, the OFDM signal 690 is received at an OFDM receiver 834 (which may be a receiver corresponding to the transmitter 610 or the transmitter 700b). Those skilled in the art, after reading this disclosure and understanding the operation of the OFDM transmitter 610 or the OFDM transmitter 700b, will find that implementing such an OFDM receiver 834 is straightforward. For example, the transmitter 610 or the transmitter 700b inputs and operates on analog input samples, and no DAC is required inside the transmitter. Accordingly, the OFDM receiver 834 does not require an ADC, and it outputs analog video samples corresponding to the analog video samples originally input to the transmitter. In embodiments where digital video samples are required by the video receiver, the analog-to-digital conversion can occur at the receiving end (e.g., within the video receiver), thereby locating the ADC away from the video source and reducing circuit complexity and cost.

[0186] The location of the OFDM receiver 834 can be specified based on the location of the OFDM transmitter and the distance over which the OFDM signal 690 is desired to be transmitted. The OFDM receiver 834 can be located in close proximity to the video source, can be located between the video source and the video receiver, or can be located near or within the video receiver. Once the analog video samples 836 are output from the OFDM receiver 814, they are transmitted to the video receiver and displayed on its display panel using techniques known to those skilled in the art.

[0187] Fig.17 An embodiment is shown in which both the OFDM transmitter and the OFDM receiver are located within a display unit 840, such as a large size television or screen. Signal 854 optionally provides information about the display panel from the display panel 850 to the OFDM transmitter 856 to assist in the generation of the OFDM signal when necessary. The generation of the gate driver power and control signals 860 can be performed by a timing controller (or other specific hardware) based on synchronization information from the source driver. As is known in the art, digital video samples 842 are received at the display unit and processed by the SoC and timing controller (TCON).

[0188] In this embodiment, any number of OFDM transmitters 856 each send an OFDM signal 858 to an OFDM receiver 862 located at each source driver 864 or integrated with the source driver 864, and the source driver 864 generates a source voltage for the display panel. The transmission medium of each signal 858 can be a cable (such as HDMI, a flat cable, a fiber optic cable, a metal cable, a non-metallic carbon rail flexible cable), or it can be wireless. This group of OFDM transmitters 856 may be those transmitters that receive digital inputs (such as transmitters 80 and 700a) or may be transmitters that receive analog inputs (such as transmitters 610 and 700b). In the case of a transmitter that receives an analog input, each transmitter is preceded by a DAC (not shown) that converts the incoming digital video samples into analog samples. Each OFDM receiver 862 can be located on a flexible PCB with each source driver 864, or each receiver can be integrated in each source driver, such as integrated in a single source driver chip. Typically, due to pin count limitations, most display panels with more than about 1024 columns are implemented with an array of source driver chips, with one source driver per chip. For panels with fewer columns, it may be considered that only a single source driver is required. Depending on the OFDM transmitter used, different OFDM receivers and arrangements can be used, as described below.

[0189] In an embodiment where multiple OFDM transmitters 856 are used in a display unit, a method similar to Fig. 9 The distributor of distributor 440 distributes the digital or analog video samples from TCON to the transmitters 856; that is, distributes the incoming stream of digital or analog samples to provide a sample stream for each OFDM transmitter. Any suitable arrangement may be used. Thus, if there are P OFDM transmitters 856 (P being an integer greater than or equal to 1), the samples from TCON will be distributed to P vector streams, one stream for each OFDM transmitter. One or more banks may be used in the distributor, and each output vector stream of the distributor is preferably a serial output of samples for input to its corresponding OFDM transmitter. In a similar manner, if in Fig.15 or Fig.16 If multiple OFDM transmitters are used in , a similar distributor may be used to distribute the incoming samples 812 or 832 to the multiple OFDM transmitters. Fig.15 or Fig.16 If a distributor is used, a corresponding collector can be used after the OFDM receiver 814 or 834 to generate a corresponding sample stream 816 or 836.

[0190] if Fig.17 If the display unit has multiple OFDM transmitters 856, a distributor can be used and can be based on Fig. 9The output of the distributor can be serially entered into each OFDM transmitter. Alternatively, a single or multiple output streams can be multiplexed or unified into a single or multiple transmitters. The number of these channels depends on the resolution and OFDM bandwidth, and a high-resolution video stream can be divided into multiple streams. The bandwidth of each stream will be lower than the bandwidth of a single high-resolution stream, and the samples will be serialized per stream. The number of streams depends on the implementation and can vary depending on the video source resolution, the number of sources, and the available bandwidth of each OFDM channel.

[0191] Fig.18 A digital OFDM receiver with analog outputs located at the source driver is shown. If the OFDM transmitter is a transmitter that inputs digital video samples, such as transmitter 80 or transmitter 700a, an OFDM receiver 814 is used; accordingly, the receiver 814 includes at least one ADC and performs reverse symbol mapping to output the original digital video samples that have been input to the OFDM transmitter. Instead of the two ADCs shown, a single ADC can be placed at the input of the receiver near the antenna; other techniques can also be used to convert the input analog signal to a digital signal before the FFT circuit. A DAC 870 can be added at its output to provide analog video samples to one of the source drivers 864. The source driver 864 that receives analog video samples is described below. Fig.18 is a general schematic diagram of a digital OFDM receiver, corresponding to an OFDM transmitter that inputs digital values. Since there is a digital input at the OFDM transmitter, an ADC is used within the digital OFDM receiver before the FFT.

[0192] Fig.19 An analog OFDM receiver with analog outputs located at the source drivers is shown. Display unit 840 is shown, where OFDM transmitter 856 is a transmitter that inputs analog video samples, such as transmitter 610 or transmitter 700b; accordingly, DAC 880 is added to convert the input digital video samples to analog samples. Since this OFDM transmitter inputs analog video samples, an OFDM receiver such as receiver 834 that performs reverse symbol mapping can be used to output the original analog video samples that were input to the OFDM transmitter and provide these analog video samples to one of the source drivers 864. The source driver 864 that receives the analog video samples is described below.

[0193] Fig. 20An example of a source driver 864 of a display panel 850 receiving analog video samples output from an OFDM receiver is shown. Other source driver architectures are also possible. The source driver 864 typically has 900 to 1000 outputs, or more. There may be multiple instances of this source driver in a display. The analog video samples output from the OFDM receiver are input at an input terminal 890 and then transmitted in parallel to a collector 891, which outputs the analog samples 892 in parallel to a column driver before the analog samples 892 are output 896 to the column, and the column driver typically includes a level shifter 893 and an amplifier 894.

[0194] Amplifier 894 amplifies each analog sample to produce the voltage required for a particular display panel. A polarity signal and a reference voltage (i.e., the rail voltage of the gamma-coded amplifier, used to produce the dynamic voltage range desired or required by the display panel) are provided to each amplifier. Gamma processing and encoding can be performed within the SoC or timing controller chip. Output 896 is output to the display column, i.e., directly to the glass of the display, to drive the source of each pixel, as known in the art. Advantageously, each source driver 864 does not require a DAC to convert pixel data, thereby saving space, reducing required power, etc.

[0195] OFDM video transmission using splitter

[0196] The above describes an OFDM transmission technology. Fig.15 and Fig.16 An OFDM path is shown in Fig.17 Multiple OFDM paths are shown in . An improved technique is described below in which a distributor is incorporated into the transmitter (and a collector into the receiver) to facilitate multiple transmission paths within or to the display unit.

[0197] In a first variation of this embodiment, one or more SAVT signals are generated from one or more video signals and each SAVT signal is then input into an OFDM transmitter for transmission on an EM path for reception at an OFDM receiver and then displayed on a display.

[0198] Fig.21The structure of the transmitter 1140 is shown, which can be external or internal to the display unit. The distributor 1240 shown includes two line buffers 1241, 1242 and a distributor controller 1230, multiple (P) image processors 1250-1259, digital-to-analog converters 260-269 after each image processor, and video sample streams 270-279 output by each DAC. In this example, there are 24 source drivers, which means 24 streams, or P=24. It should be understood that there may be a single EM path (i.e., P=1) or multiple EM paths.

[0199] During operation, a video signal (e.g., RGB) containing time-ordered digital video samples of color values ​​and pixel-related information is received from a video source and transmitted to the transmitter 1140 (via the SoC and TCON if within a display unit). The number and content of the input video samples received from the video source depends on the color space operated at the source (and the samples can be black and white). Regardless of which color space is used, each video sample represents the amount of light sensed or measured in the specified color space.

[0200] Pixel values ​​may appear in row-major order through successive video frames. More than one pixel value may arrive at a time (e.g., two, four, etc.); they are serial because groups of pixels are gradually transmitted from one end of the line to the other. For example, a processing unit, such as an unpacker of a timing controller, may be used to unpack (or expose) these serial pixel values ​​into parallel RGB values. In addition, it should be understood that the exposed color information of each group of samples may be any color information (e.g., Y, C, Cr, Cb, etc.), not limited to RGB. The number of output sample values ​​S in each group of pixel samples is determined by the color space applied by the video source. For RGB, S=3, and for YCbCr, S=2. In other cases, the sample values ​​S in each group of samples may be only 1 or more than 3.

[0201] In general, when input digital video samples of one or more video signals (e.g., RGB) are received within the transmitter 1140 in row major order (e.g.), the input digital video samples are repeatedly (1) assigned to one of the output streams according to a predetermined arrangement (in this case, row major order, i.e., a unit arrangement), (2) optionally processed using standard image processing techniques, such as gamma correction, etc., (3) converted to analog, and (4) output as a video sample stream, one stream per OFDM transmitter, as described below. The OFDM receiver receives each OFDM encoded stream and outputs an analog sample stream to the source driver. At each source driver, samples are received at the input terminals and each analog sample is sequentially assigned to a storage cell of a particular column driver via a sampling circuit using the inverse of the predetermined arrangement used in the transmitter. Once all samples for the source driver are in place, they are driven onto the display panel. In this way, raw time-ordered video samples containing color and pixel related information are transmitted from the video source to the video receiver. The reverse permutation effectively stores the incoming samples as a row in the memory array (for display on the panel) in the same order as the row was received at the distributor.

[0202] In one embodiment, 4 control signals for every 60 video samples are inserted into the sample stream in the distributor to be sent to the source driver. As shown, each input vector 1280 in the line buffer includes a total of 1024 values, wherein every 60 video samples include 4 control signals. Control signals can be inserted into various positions of the input vector, for example, "samples" 960-1023 in the input vectors 1280-1288 can actually be control signals. Any number of control signals in each input vector can be used. In addition, any but limited number of control signals are possible. The more control signals transmitted, the higher the required data transmission rate. Ideally, the number of control signals is limited to the number of blanking periods so that there can be a corresponding relationship between the transmission rate and the display line (thereby reducing the required storage amount, or any additional resynchronization). In addition, the control signal can be inserted into the sample stream at the distributor, or the insertion of the control signal can be performed at another position.

[0203] The distributor 1240 is arranged to receive pixel color information (e.g., R, G, and B values) exposed in a set of input samples. The distributor 1240 obtains the exposed color information and writes a plurality of input vectors 1280-1288 to a first row buffer 1241 (one input vector for each OFDM transmitter) according to a predetermined arrangement. Once the row buffer 1241 is full, each input vector 1280-1288 is read to its corresponding image processor 1250-1259 via its corresponding serial output port 1281-1289. When these input vectors are read from the row buffer 1241 (or once the row buffer 1241 is full), the next row of RGB input samples is written to the input vectors 1290-1298 in the second row buffer 1242. Therefore, once the second row buffer 1242 is full (and the image processor has finished reading the input vector from the first row buffer 1241), the image processor begins reading samples from the second row buffer 1242 via their serial output ports 1291-1299. The process of writing and reading from the first and second row buffers continues in this "ping-pong" fashion as long as input samples arrive at the transmitter.

[0204] The distributor controller 1230 controls the operation and timing of the line buffers. In particular, when constructing the four input vectors, the controller is responsible for defining the arrangement and number of samples N used. In this example, N=1024. The controller 1230 may also include an arrangement controller that controls the allocation of RGB samples to positions in the input vectors. The controller is also responsible for coordinating the clock domain crossing from the first clock frequency to the second clock frequency.

[0205] In one particular embodiment, each line buffer 1241 or 1242 has three input ports for incoming RGB samples, and the samples are clocked at the frequency of FPIXEL; each line buffer also has 24 output ports, such as 1281 or 1291 (in the case of 24 OFDM transmitters, each is sent to one of the 24 source drivers), and samples are serially clocked out from each input vector at the Sampled Analog Video Transport (SAVT) frequency of FSAVT. It is also possible to clock in two R, two G, and two B samples at a time, rather than one at a time, or three at a time, etc. In one embodiment, FSAVT = 663.552 MHz for 24 channels.

[0206] For the purpose of explanation, one possible arrangement is that each input vector contains N samples of color information and control signals. The exposed RGB samples of the sample set in this example are assigned to the input vectors from left to right. In other words, the "R", "G" and "B" values ​​of the first group of samples, and the "R", "G" and "B" values ​​of the next group of samples, etc., are assigned to the input vector 1280 (i.e., RGBRGB, etc.) in this order. Once the input vector 1280 is assigned N samples and control signals, the above process is repeated in sequence for other input vectors until each input vector has N values. The number of N values ​​for each input vector can vary greatly. As shown in this example, this predetermined arrangement maintains the row-major order of the input samples, i.e., the first input vector 1280 includes samples 0 to sample 1023 of the first row in this order, and subsequent input vectors continue this arrangement (including control signals). Therefore, the distributor controller 1230 performs the arrangement by assigning the incoming samples to specific addresses within the row buffer. It should also be understood that the distributor may use any permutation scheme 1230; and, whichever permutation scheme the transmitter uses, its inverse will be used by the control logic in each source driver in order to distribute the incoming samples to the column drivers.

[0207] The image processors 1250-1259 then perform the following operations on each input vector: a) apply gamma correction to each sample; b) level shift each gamma corrected sample, mapping the range (0…255) to (-128…127) to remove the DC component from the signal; c) apply path-specific amplifier variance correction to each gamma corrected, level shifted sample; gain compensate each sample; offset adjust each sample; and demura correct each sample. Other corrections and adjustments may also be performed depending on the target display panel. A separate image processor 1250-1259 can process the sample stream for each serial output (e.g., 1281 and 1291), or a single monolithic image processor can process all serial outputs at once (e.g., 1281 and 1291, 1285 and 1295, etc.). To avoid image processing of control signals in the line buffer, the timing and position of the control signals in the buffer are known so that the logic can determine that image processing of the control signals should not be performed. As discussed above, image processing need not occur within transmitter 1140, but may occur in the SoC or elsewhere.

[0208] After image processing (if any), the modified digital samples of each input vector are serially input into one of the DACs 1260-1269; each DAC converts these modified digital samples at a frequency of FSAVT and outputs a stream of analog samples 1270-1279 to the OFDM transmitters 1290-1299, as described below. Each DAC converts the samples it receives from the digital domain to analog samples (e.g., a differential pair of voltage signals with amplitudes proportional to their incoming digital values); the output of the DAC can range from a maximum voltage to a minimum voltage.

[0209] Although two line buffers are shown in the distributor 1240 (which is preferred), a single line buffer could be used, and as samples from a particular input vector are read to its image processor (or its DAC), the distributor backfills that input vector with the incoming samples, so that there is no pause in the serial transfer of samples from the line buffer to the image processor. Also, and equally less desirable, each DAC could be placed after the distributor and before the image processor (if any), so that image processing is performed on the analog samples.

[0210] In this first variation, each OFDM transmitter 1290-1299 may be a Fig.16 A transmitter, such as transmitter 610 or 700b, is shown that receives analog video samples and transmits OFDM signal 690. Signal 690 is then received at OFDM receiver 834, which outputs the corresponding analog video samples to a video receiver. These samples are then displayed on a display panel. Typically, the OFDM receiver will be combined with a source driver for the panel and may be inside the source driver for the panel. The following figures illustrate embodiments of such a source driver.

[0211] Fig. 22A preferred structure of the source driver is shown, where each distributor amplifier drives adjacent columns and all control signals are processed by a single amplifier. Shown in the figure is an input terminal 1822, which demultiplexes and distributes the pixel data and control signals incoming from the OFDM receiver 834 to the S / H amplifier 1824 (input pixel data numbered from 0 to 14) and the amplifier 1826 that receives the control signal. As described above, the pixel data from the amplifier 1824 is transmitted to the storage array A 1828 or the storage array B 1830, and the control signal is processed by the component 1836 and output at 1838. The pixel data from either storage array is then input into the column driver 1832 and output to the column 1834, as is known in the art. Not shown is the control logic for controlling the timing of the input amplifier, storage array, and column driver. Since the pixel data is received sequentially on a single channel (per chip), it is stored sequentially into the A / B collectors (one Fsavt cycle apart), although it is also possible to store 15 sub-pixels in parallel from the 15 SHA amplifiers into the array.

[0212] Thus, 15 interleaved S / H amplifiers receive incoming pixel data, each driving an adjacent 64 columns, or 64 video tracks, thereby minimizing the span of columns driven by each amplifier. This structure provides 15 blocks of 64 video samples plus one subband channel (control signal) of 64 bits per display row (per source driver). For example, amplifier 0 drives columns 0-63, the second amplifier drives columns 64-127, and so on, the 15th amplifier drives columns 896-959 and amplifier 1826 drives the control signal. Having all the control signals on one channel means that there are no differences in amplitude, delay, or other aspects from one signal to the next (if they were on different channels). It is also possible that the control signal arrives at channel zero (i.e., amplifier 0) instead of amplifier 15; this is advantageous because the control information arrives before the pixel data. Another advantage of this architecture is that control signal extraction only needs to look at one deinterleaved amplifier output, rather than distributing it to all amplifiers, simplifying synchronization.

[0213] In this figure, there are 15 video amplifiers, each driving 64 sub-pixels = 960 sub-pixels / chip. There is a channel dedicated to control, carrying 64 symbols per row (per source driver). As shown, the control channel receives a control signal at amplifier 1826, which is input to comparator 1836, which has a reference voltage of 0V and operates at the 16th of the FSAVT or approximately 41.5MHz. Assuming the control signal is in the range of -.5V to +.5V, the comparator will detect whether the control signal is greater than 0V (meaning a digital 1) or whether the control signal is less than 0V (representing a digital 0). This digital data is then output at 1838, providing one control bit every 16 samples. The control signal provides synchronization and phase alignment, as described below.

[0214] Typically, a display panel may have 24 such source drivers, i.e., P equals 24. Note that no analog-to-digital converter (ADC) is required in the source driver to convert the samples to analog for display. Table 1 shows the parameters, values, and units of the source driver used with an 8K144 display panel. Thus, each of the 24 source drivers drives 960 columns, providing sub-pixels for one row of the display (23040 sub-pixels per row). One of skill in the art will find it straightforward to modify the architecture to accommodate other display sizes and speeds. By reordering the samples in the transmitter, each interleaved S / H amplifier can drive adjacent columns while operating in a rotational manner, as described below.

[0215]

[0216] Table 1

[0217] Fig.23 The source driver inputs of source driver 1820 are shown for interleaving multiple input amplifiers to allow speed requirements to be met. (A single amplifier may be used, but the transmission speed will be reduced.) Shown are input terminals 1822, distribution amplifiers 0-14 1824 and amplifier 1826 and associated switches 1842, which rotate so as to effectively connect one amplifier at a time to receive one of the incoming sub-pixels or control signals, as the case may be. Thus, the inputs are interleaved 16-way and the outputs of the switches are demultiplexed into 16 channels running at 1 / 16 the data rate. Each of the 960 sub-pixels in a row is conveniently grouped into 15 groups of 64 sub-pixels each, and one channel is dedicated to detecting and processing control signals.

[0218] Fig.24 is a summary of pixel transmission sequence 1300, showing how pixels 0-959 and control signals 0-63 are transmitted from the input vector of transmitter 1140 (via one of OFDM transmitters 1290-1299) to Fig. 22 source driver and each assigned amplifier. The figure shows the natural order of sub-pixels transmitted via CEDS (Clock Embedded Differential Signaling), for example, reading the arriving sub-pixels from left to right and then from top to bottom. Due to the 16-way interleaving of the input data at the source driver, the preferred method of transmitting the sub-pixels to the source driver is to start from the upper left corner, from top to bottom, and then from left to right, that is, the sub-pixels (and control signals) transmitted are indexed as 0, 64, 128, etc. Shown is an example of the index of the S / H amplifier 1302, the sub-pixel index 1304 and the control track 1306 of the 16th amplifier.

[0219] In this arrangement, 15 amplifiers (0-14) each drive the sub-pixel values ​​of 64 adjacent columns, while amplifier 15 handles all 64 control signals. This variation minimizes the hardware in the source drivers and also minimizes the wiring load on the input amplifiers. In addition, since no padding is required in the data sequence, this variation allows the slowest possible SAVT (sampled analog video transmission) transmission rate. In order to best display text and other sharp transitions in intensity, it is preferred that the sampling amplifier should be able to settle to a new value every 1 / Fsavt, or approximately 1.5ns per sample. To implement this structure, the sub-pixel index sequence transmitted in the transmitter is: 0, 64, 128, ...832, 896; 1, 65, ...897; ...; 63, 127, 191 ...895, 959.

[0220] Fig.25 is a block diagram of an input vector 1320 of a transmitter having a predetermined arrangement that provides Fig.24 As previously described, when sub-pixels arrive at the distributor 1240, they are distributed into the input vector 1320 according to the order shown. When full, the samples in the input vector are serially output via output port 1321 to the image processor as described above, and then converted and transmitted to the image processor having Fig. 22 The other input vectors to the row buffer are not shown; each input vector will have a similar arrangement, and the other source drivers corresponding to each input vector will have the same Fig. 22 The above structure of source driver 1820 and the above transfer sequence provide the above advantages and preserve the slowest possible SAVT clock rate.

[0221] Fig.26A video transmission system 1700 within a display unit is shown. In a first variation of OFDM transmission with a distributor as shown, the input to the OFDM transmitter is an analog sample and the output of the OFDM receiver is the same analog sample, so advantageously, no DAC or ADC is required inside the transmitter or receiver, and no DAC is required inside the source driver array to convert pixel values. A timing controller 1702 is shown, which outputs a set of color samples as described above, such as sub-pixel values ​​in digital form, representing the brightness values ​​of the image or video to be displayed on the display panel 1710. The samples are input into the transmitter 1704 and transmitted to the source driver array 1708 via a low voltage wiring harness 1706 for display on the display panel 1710.

[0222] The transmitter's distributor includes a row buffer 1720, any number of input vectors (or banks) 1722-1726, and a distributor controller 1728. RGB samples (or black and white, or any other color space) are received continuously at the distributor and distributed into input vectors according to a predetermined arrangement controlled by the distributor controller 1728. In this example, a row-major order arrangement is used, and the first portion of the row of the input video frame (or image) from left to right is stored in the input vector 1722, and so on, and the last portion of the row is stored in the input vector 1726. Therefore, when the row buffer 1720 is full, it contains all the pixel information from the first row of the video frame, which will then be transmitted and displayed in the first line of the video frame on the display panel 1710. Each input vector is read serially to its corresponding DAC 1732-1736, and each sample is converted to analog for OFDM and transmission. As the samples arrive continuously from the timing controller 1702, they are distributed, converted, transmitted, and finally displayed as video on the display panel 710.

[0223] Connecting each OFDM transmitter to the corresponding OFDM receiver is a low voltage wiring harness 1706, which consists of differential pairs, each pair of which transmits a continuous stream of analog samples (electromagnetic signals). Each differential pair of wires terminates at the input 1760 of one of the source drivers 1752-1756. Other transmission media (e.g., cable, wireless, optical) are also possible in place of the differential pairs in the wiring harness.

[0224] Each source driver of the source driver array, such as source driver 1752, includes an input terminal 1760, a collector 1762, and a plurality of column drivers 1764 (corresponding to the number of samples in each input vector, 1024 in this example). The samples are received serially at terminal 1760 and then collected into collector 1762, which can be implemented as one or more one-dimensional storage arrays of length equal to the size of the input vector. Each collector can use Fig. 22Once each collector is full, all collected samples are output in parallel to all column drivers 1764 of all source drivers, amplified to the appropriate high voltage required by the display panel, and output to columns 1766 using a single-ended format. As samples continue to arrive through the harness, each collector continues to collect samples and output them to the display panel, thereby affecting the presentation of the video. In one embodiment, using Fig. 22 Each collector 1762 is implemented with an A / B storage unit. In other words, each column of the collector will have a pair of input samplers. The SHA amplifier can be considered as part of the collector 762.

[0225] In a second variant of OFDM transmission using a distributor, the input digital video samples are kept digital, the input to the OFDM transmitter is the digital samples, and the output from the OFDM receiver is the digital video samples, which can be converted to analog video samples as appropriate. Therefore, to implement this second variant, Fig.21 The transmitter of OFDM is modified to remove DACs 1260-1269 so that the input to each OFDM transmitter is a series of digital video samples from each corresponding input vector. Each transmitter can be implemented as follows Fig.15 In the transmission shown, digital video samples 812 are input to OFDM transmitter 80 or 700a, transmitted to OFDM receiver 814, and then OFDM receiver 814 can output digital video samples 816. Fig.18 As shown, OFDM receiver 814 outputs digital video samples, which can be used directly by a display panel that requires (and has the ability to convert to analog) digital video samples, or a DAC 870 can be included in the OFDM receiver to provide analog video samples required by the source driver of the display panel. If analog video samples are output by the OFDM receiver, then the analog video samples can be used as described above with reference to FIG. Figure 22-25 If this second variant is implemented in a display unit (such as Fig.26 ), DACs 1732 and 1736 are eliminated and the inputs to OFDM transmitters 1290-1299 are digital samples. In contrast, OFDM receiver 834 is implemented as receiver 814 and may include DAC 870 to output analog video samples to each source driver when the source driver requires analog samples.

[0226] In a third variant of OFDM transmission using a splitter, the input video signal comprises analog video samples, namely Fig.21The RGB signal of OFDM consists of analog video samples instead of digital samples. The input of the OFDM transmitter is analog samples, and the output of the OFDM receiver is analog video samples (which can be converted to digital video samples if necessary). Therefore, in order to implement this third variant, Fig.21 The transmitter of OFDM is modified to accept input analog video samples, DAC 1260-1269 is deleted, and the input to each OFDM transmitter 1290-1299 is a series of analog video samples from the corresponding input vector. Each transmitter can be implemented as follows Fig.16 1, where analog video samples 832 are input to OFDM transmitter 610 or 700b, transmitted to OFDM receiver 834, and then OFDM receiver 834 can output analog video samples 836. OFDM receiver 834 outputs analog video samples that can be used directly by the display panel. These analog video samples can be referred to above Figure 22-25 If the third variant (such as Fig.26 As shown), the samples in the RGB signal are analog video samples, DACs 1732 and 1736 are eliminated, and the inputs to OFDM transmitters 1290-1299 are analog samples. OFDM receiver 834 outputs analog video samples to each source driver.

[0227] Other embodiments

[0228] Other embodiments include the following:

[0229] 1. A transmitter for transmitting input digital samples, the transmitter comprising:

[0230] an encoder that continuously inputs an input vector of N digital samples and encodes the N digital samples using N orthogonal spreading codes each of length L to output L digital levels, each of the codes being used with one of the N digital samples and wherein L>=N>=2;

[0231] a symbol mapping circuit that receives the continuous stream of L digital levels from the encoder and maps the L digital levels to points in a constellation to obtain pairs of in-phase (I) and out-of-phase (Q) components and outputs each pair of I and Q components into a bin of an Inverse Fast Fourier Transform (IFFT) block; and

[0232] An orthogonal frequency division multiplexing (OFDM) circuit performs an IFFT on the IFFT block and generates an electromagnetic signal representing the continuous stream of digital levels using OFDM.

[0233] 2. A transmitter as claimed in claim 1, wherein the N digital samples originate from a single source, and wherein the electromagnetic path terminates at a single receiver.

[0234] 3. A transmitter as claimed in claim 1, wherein the electromagnetic path terminates at a display panel of a display unit, and wherein the transmitter is located within the display unit.

[0235] 4. The transmitter of claim 1, wherein the encoder synchronously encodes the N digital samples to the L digital levels, wherein the N digital samples are represented by the L digital levels.

[0236] 5. The transmitter of claim 1, wherein the symbol mapping circuit maps each of the L digital levels to a point in the constellation to obtain the in-phase (I) component and the out-of-phase (Q) component.

[0237] 6. A transmitter as described in claim 1, wherein for each pair of the I and Q components output to the bins of the IFFT block, the complex conjugates of the I and Q components are output to corresponding bins of the IFFT block, the corresponding bins are symmetric with respect to an intermediate frequency of the subcarrier frequencies used in the transmitter, and wherein the output of the IFFT is a real value rather than a complex value.

[0238] 7. A transmitter as described in claim 1, wherein each digital level received by the symbol mapping circuit includes a most significant bit (MSB) and a least significant bit (LSB), wherein for each digital output level received, the symbol mapping circuit assigns the MSB of each digital output level to the MSB of the in-phase (I) component and the MSB of the out-of-phase (Q) component, wherein for each digital output level received, the symbol mapping circuit assigns the LSB of each digital output level to the LSB of the in-phase (I) component and the LSB of the out-of-phase (Q) component, and wherein the symbol mapping circuit outputs the I and Q components as complex numbers into bins of an inverse fast Fourier transform (IFFT) block until the IFFT block is full.

[0239] 8. The transmitter as claimed in claim 1 further comprising:

[0240] A digital-to-analog converter receives the electromagnetic signal and outputs an analog signal on the electromagnetic path.

[0241] 9. The transmitter of claim 1, wherein the transmitter is one of a plurality (P) of transmitters, each of the P transmitters generating an electromagnetic signal representing a media signal from a single source.

[0242] 10. A receiver for outputting digital samples, the receiver comprising:

[0243] an orthogonal frequency division multiplexing (OFDM) circuit that receives the OFDM electromagnetic signal and performs a fast Fourier transform (FFT) on the received OFDM symbols to fill each bin of the FFT block with a complex digital in-phase (I) component and a digital out-of-phase (Q) component for each OFDM symbol;

[0244] a reverse symbol mapping circuit that inputs the I component and the Q component and continuously converts the I component and the Q component into digital input levels according to a symbol mapping circuit of a corresponding OFDM transmitter; and

[0245] A decoder, continuously inputting L of the digital input levels and decoding the L digital input levels using N orthogonal spread spectrum codes, each of which has a length of L, to output an output vector of N digital samples, each of which is used with one of the N digital samples, where L>=N>=2.

[0246] 11. A receiver as claimed in claim 10, wherein the N digital samples originate from a single source, wherein the electromagnetic path terminates at a single receiver.

[0247] 12. A receiver as claimed in claim 10, wherein the electromagnetic path terminates at a display panel of a display unit, wherein the corresponding OFDM transmitter is located within the display unit.

[0248] 13. The receiver of claim 10, wherein the decoder synchronously decodes the L digital input levels into the N digital samples, wherein the N digital samples represent the L digital input levels.

[0249] 14. The receiver of claim 10, wherein the reverse symbol mapping circuit converts each point in a constellation to one of the digital input levels.

[0250] 15. A receiver as described in claim 10, wherein the reverse sign mapping circuit places the most significant bit (MSB) of each pair of digital I component and digital Q component to the MSB of one of the digital input levels, and places the least significant bit (LSB) of each pair to the LSB of the one digital input level.

[0251] 16. A receiver as described in claim 10, wherein the input to the FFT is real valued rather than complex valued, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of the subcarrier frequency used in the receiver, and wherein the bins of the FFT block are symmetrically filled with the complex conjugates of the corresponding I and Q components on the other side of the intermediate frequency, and wherein the reverse sign mapping circuit inputs only the I and Q components from the bins on the one side.

[0252] 17. The receiver of claim 10, wherein the OFDM circuitry includes at least one analog-to-digital converter that produces the digital I and Q components.

[0253] 18. A transmitter for transmitting input analog samples, the transmitter comprising:

[0254] an encoder which continuously inputs an input vector of N analog samples and encodes the N analog samples using N orthogonal codes each of length L to output L analog levels, each of the codes being used with one of the N analog samples and wherein L>=N>=2;

[0255] a switching circuit that receives a continuous stream of L analog levels, wherein for each pair of analog levels received, the switching circuit outputs a first analog level of the pair as an in-phase (I) component and outputs a second analog level of the pair as an out-of-phase (Q) component to a bin of an inverse fast Fourier transform (IFFT) block; and

[0256] An orthogonal frequency division multiplexing (OFDM) circuit receives the I and Q component pairs, performs an IFFT on the IFFT block, and generates an electromagnetic signal representing a continuous input of the analog samples using OFDM.

[0257] 19. A transmitter as claimed in claim 18, wherein the N simulated samples originate from a single source, and wherein the electromagnetic path terminates at a single receiver.

[0258] 20. The transmitter of claim 18, wherein the electromagnetic path terminates at a display panel of a display unit, and wherein the transmitter is located within the display unit.

[0259] 21. The transmitter of claim 18, wherein the encoder synchronously encodes the N analog samples to the L analog levels, wherein the N analog samples are represented by the L analog levels.

[0260] 22. The transmitter of claim 18, wherein the transmitter does not include a constellation for mapping.

[0261] 23. An OFDM transmitter as described in claim 18, wherein for each pair of I and Q components in the bins output to the IFFT block, the complex conjugates of the I and Q components are output to corresponding bins of the IFFT block, the corresponding bins are symmetric with respect to an intermediate frequency of the subcarrier frequencies used in the transmitter, and wherein the output of the IFFT is a real value rather than a complex value.

[0262] 24. The transmitter of claim 18, wherein the transmitter does not include a digital-to-analog converter.

[0263] 25. The transmitter of claim 18, wherein the transmitter is one of a plurality (P) of transmitters, each of the P transmitters generating an electromagnetic signal representing a media signal from a single source.

[0264] 26. A receiver for outputting analog samples, the receiver comprising:

[0265] an orthogonal frequency division multiplexing (OFDM) circuit that receives the OFDM electromagnetic signal and performs a fast Fourier transform (FFT) on the received OFDM symbols to fill each bin of the FFT block with a complex in-phase component (I) and an out-of-phase component (Q); and

[0266] a combining circuit that inputs the I component and the Q component of each bin for each bin and outputs the I and Q components as a first analog level and a second analog level so as to output a continuous stream of analog input levels; and

[0267] A decoder, continuously inputting L of the analog input levels and decoding the L analog input levels using N orthogonal spread spectrum codes, each of which has a length of L, to output an output vector of N analog samples, each of which is used with one of the N analog samples, where L>=N>=2.

[0268] 27. A receiver as claimed in claim 26, wherein the N simulated samples originate from a single source, wherein the electromagnetic path terminates at a single receiver.

[0269] 28. A receiver as claimed in claim 26, wherein the electromagnetic path terminates at a display panel of a display unit, wherein the corresponding OFDM transmitter is located within the display unit.

[0270] 29. The receiver of claim 26, wherein the decoder synchronously decodes the L analog input levels into the N analog samples, wherein the N analog samples represent the L analog input levels.

[0271] 30. The receiver of claim 26, wherein the receiver does not include a constellation for mapping.

[0272] 31. A receiver as claimed in claim 26, wherein the input to the FFT is real valued rather than complex valued, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of the subcarrier frequencies used in the receiver, and wherein the bins of the FFT block are symmetrically filled with the complex conjugates of the corresponding I and Q components on the other side of the intermediate frequency, and wherein the combining circuit inputs only the I and Q components of the bins on the one side.

[0273] 32. A receiver as described in claim 26, wherein the receiver does not include an analog-to-digital converter.

[0274] 32. The receiver of claim 26, wherein the receiver is one of a plurality (P) of receivers, each of the P receivers receiving an electromagnetic signal, the electromagnetic signal representing a media signal from a single source.

[0275] 33. A transmitter for transmitting input digital video samples, the transmitter comprising:

[0276] a serial-to-parallel converter arranged to receive a bit-serial stream of digital video samples and to produce a parallel stream of said digital video samples, said digital video samples originating from an image sensor of a video source;

[0277] a symbol mapping circuit that receives the stream of digital video samples from the serial-to-parallel converter and maps each of the digital video samples to a point in a constellation to obtain an in-phase (I) component and an out-of-phase (Q) component pair, and outputs each pair of I and Q components to a bin of an inverse fast Fourier transform (IFFT) block; and

[0278] An orthogonal frequency division multiplexing (OFDM) circuit performs an IFFT on the IFFT block and generates an electromagnetic signal representing the stream of digital video samples using OFDM.

[0279] 34. A transmitter as claimed in claim 33, wherein the OFDM circuit is further arranged to transmit the electromagnetic signal to a video receiver.

[0280] 35. A transmitter as claimed in claim 33, wherein the transmitter is located within a display unit, and wherein the OFDM circuit is further arranged to transmit the electromagnetic signal to a source driver of a panel of the display unit.

[0281] 36. A transmitter as described in claim 33, wherein for each pair of the I and Q components in the bins output to the IFFT block, the complex conjugates of the I and Q components are output to corresponding bins of the IFFT block, the corresponding bins are symmetric about an intermediate frequency of the subcarrier frequencies used in the transmitter, and wherein the output of the IFFT is a real value rather than a complex value.

[0282] 37. A transmitter as described in claim 33, wherein each digital video sample received by the symbol mapping circuit includes a most significant bit (MSB) and a least significant bit (LSB), wherein for each digital video sample received, the symbol mapping circuit allocates the MSB of each digital video sample to the MSB of an in-phase (I) component and the MSB of an out-of-phase (Q) component, wherein for each digital video sample received, the symbol mapping circuit allocates the LSB of each digital video sample to the LSB of the in-phase (I) component and the LSB of the out-of-phase (Q) component, and wherein the symbol mapping circuit outputs the I and Q components as complex numbers into bins of an inverse fast Fourier transform (IFFT) block until the IFFT block is full.

[0283] 38. A transmitter as described in claim 33, wherein the transmitter is one of a plurality (P) of transmitters, each transmitter receiving a stream of digital video samples, wherein a distributor inputs digital video samples originating from the video source and distributes the digital video samples to the stream of digital video samples.

[0284] 39. A receiver for outputting digital video samples, the receiver comprising:

[0285] an orthogonal frequency division multiplexing (OFDM) circuit that receives an OFDM electromagnetic signal representing a stream of digital video samples and performs a fast Fourier transform (FFT) on the received OFDM symbols to fill each bin of the FFT block with a complex digital in-phase (I) component and a digital out-of-phase (Q) component for each OFDM symbol;

[0286] a reverse symbol mapping circuit that inputs the I component and the Q component and continuously converts the I component and the Q component into a digital video sample stream according to a symbol mapping circuit of a corresponding OFDM transmitter; and

[0287] An output circuit is arranged to output the stream of digital video samples, wherein the digital video samples originate from an image sensor of a video source.

[0288] 40. The receiver of claim 39, further comprising:

[0289] A parallel-to-serial converter is arranged to receive the stream of digital video samples and to produce a bit-serial stream of digital video samples to a video receiver.

[0290] 41. The receiver of claim 39, wherein the receiver is located within a display unit, the receiver further comprising:

[0291] A digital-to-analog converter is arranged to input said stream of digital video samples and to output a stream of analog video samples to a source driver of a panel of said display unit.

[0292] 42. A receiver as claimed in claim 39, wherein the inverse symbol mapping circuit converts each point in the constellation to one of the digital video samples.

[0293] 43. A receiver as described in claim 39, wherein the reverse sign mapping circuit places the most significant bit (MSB) of each pair of digital I component and digital Q component to the MSB of one of the digital video samples, and places the least significant bit (LSB) of each pair to the LSB of the one digital video sample.

[0294] 44. A receiver as claimed in claim 39, wherein the input to the FFT is real valued rather than complex valued, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of the subcarrier frequency used in the receiver, and wherein the bins of the FFT block are symmetrically filled with the corresponding complex conjugates of the I and Q components on the other side of the intermediate frequency, and wherein the reverse sign mapping circuit inputs only the I and Q components from the bins on one side.

[0295] 45. A receiver as described in claim 39, wherein the receiver is one of a plurality (P) of receivers, each outputting a stream of digital video samples, wherein a collector inputs the streams of digital video samples and outputs all of the streams together as a single stream of digital video samples to a display receiver.

[0296] 46. ​​A transmitter for transmitting input analog video samples, the transmitter comprising:

[0297] input circuitry arranged to receive a stream of analog video samples originating from an image sensor of a video source;

[0298] a switching circuit that receives the stream of analog video samples, wherein, for each pair of analog levels received, the switching circuit outputs a first analog level of the pair as an in-phase (I) component and outputs a second analog level of the pair as an out-of-phase (Q) component to a bin of an inverse fast Fourier transform (IFFT) block; and

[0299] An orthogonal frequency division multiplexing (OFDM) circuit receives the I and Q component pairs, performs an IFFT on the IFFT block, and generates an electromagnetic signal representing the stream of analog video samples using OFDM.

[0300] 47. A transmitter as claimed in claim 46, wherein the OFDM circuit is further arranged to transmit the electromagnetic signal to a video receiver.

[0301] 48. The transmitter of claim 46, wherein the transmitter is located within a display unit, the transmitter further comprising:

[0302] A digital-to-analog converter is arranged to input a digital video sample stream and output the analog video sample stream to the input circuit, wherein the OFDM circuit is further arranged to transmit the electromagnetic signal to a source driver of a panel of the display unit.

[0303] 49. A transmitter as claimed in claim 46, wherein the transmitter does not include a constellation for mapping.

[0304] 50. An OFDM transmitter as described in claim 46, wherein for each pair of the I and Q components in the bins output to the IFFT block, the complex conjugates of the I and Q components are output to corresponding bins of the IFFT block, the corresponding bins are symmetric about an intermediate frequency of the subcarrier frequencies used in the transmitter, and wherein the output of the IFFT is a real value rather than a complex value.

[0305] 51. A transmitter as claimed in claim 46, wherein the transmitter does not include a digital to analog converter.

[0306] 52. A transmitter as described in claim 46, wherein the transmitter is one of a plurality (P) of transmitters, each transmitter receiving an analog video sample stream, wherein a distributor inputs analog video samples originating from the video source and distributes the analog video samples to the analog video sample stream.

[0307] 53. A receiver for outputting analog video samples, the receiver comprising:

[0308] an orthogonal frequency division multiplexing (OFDM) circuit that receives an OFDM electromagnetic signal representing an analog video sample stream from an image sensor of a video source and performs a fast Fourier transform (FFT) on the received OFDM symbols to fill each bin of the FFT block with a complex in-phase component (I) and an out-of-phase component (Q); and

[0309] A combining circuit is provided for inputting the I component and the Q component of each bin for each bin and outputting the I and Q components as a first analog video sample and a second analog video sample so as to output a stream of analog video samples, wherein the output stream of analog video samples corresponds to the analog video samples of the image sensor originating from the video source.

[0310] 54. A receiver as claimed in claim 53, further arranged to output the stream of analog video samples to a video receiver.

[0311] 55. A receiver as claimed in claim 53, wherein the receiver is located within a display unit and the receiver is further arranged to output the stream of analog video samples to a source driver of a panel of the display unit.

[0312] 56. A receiver as claimed in claim 53, wherein the receiver does not include a constellation for mapping.

[0313] 57. A receiver as claimed in claim 53, wherein the input to the FFT is real valued rather than complex valued, wherein the bins of the FFT block are filled with the I and Q components on one side of an intermediate frequency of the subcarrier frequencies used in the receiver, and wherein the bins of the FFT block are filled symmetrically on the other side of the intermediate frequency with the complex conjugates of the corresponding I and Q components, and wherein the combining circuit inputs only the I and Q components from the bins on said one side.

[0314] 58. A receiver as described in claim 53, wherein the receiver does not include an analog-to-digital converter.

[0315] 59. A receiver as described in claim 53, wherein the receiver is one of a plurality (P) of receivers, each outputting a stream of analog video samples, wherein a collector inputs the streams of analog video samples and outputs all of the streams together as a single stream of analog video samples to a display receiver.

[0316] Although the above invention has been described in some detail for ease of understanding, it is apparent that certain changes and modifications may be made within the scope of the appended claims. Therefore, the embodiments described should be considered illustrative rather than restrictive, and the invention should not be limited to the details given herein, but should be defined by the following claims and the full scope of their equivalents.

Claims

1. A source driver for a display unit, the source driver comprising: an input terminal configured to receive a serial stream of analog video samples; a storage array comprising a plurality of registers, each register arranged to store one of said analog video samples received from said input terminal; as well as a plurality of amplifiers, each amplifier being arranged to receive one of the analog video samples in parallel from one of the registers, amplify each analog video sample to a voltage within a voltage range expected by a display panel of the display unit, and output each amplified analog video sample to a column of the display panel, wherein the source driver does not include a digital-to-analog converter to convert pixel data of the analog video sample.

2. The source driver of claim 1, wherein the stream of analog video samples is received from an Orthogonal Frequency Division Multiplexing (OFDM) receiver within the display unit. 3 . The source driver according to claim 1 , wherein each of the amplifiers receives a reference voltage from a system on chip or a timing controller of the display unit to provide the voltage range.

4. The source driver of claim 1, wherein the analog video samples are derived from a video source.

5. An apparatus for transmitting input digital video samples, the apparatus comprising: A distributor, inputting digital video samples originating from a video source and distributing the digital video samples into P bitstreams of digital video samples, P>=2; P transmitters, each transmitter receiving one of the bit streams of digital video samples, and each transmitter comprising: a serial to parallel converter arranged to receive one of said bit streams of digital video samples and to produce a parallel stream of digital video samples, a symbol mapping circuit that receives the stream of digital video samples from the serial-to-parallel converter and maps each of the digital video samples to a point in a constellation to obtain an in-phase (I) component and an out-of-phase (Q) component pair, and outputs each pair of I and Q components to a bin of an inverse fast Fourier transform (IFFT) block, and An orthogonal frequency division multiplexing (OFDM) circuit performs an IFFT on the IFFT block and generates an electromagnetic signal representing the bit stream of digital video samples using OFDM.

6. The apparatus of claim 5, wherein the OFDM circuitry of each transmitter is further arranged to transmit the electromagnetic signal to a video receiver.

7. The apparatus of claim 5, wherein the apparatus is located within a display unit, wherein the distributor receives the digital video samples from a TCON of the display unit, and wherein the OFDM circuit of each transmitter is further arranged to transmit the electromagnetic signal to a source driver of a panel of the display unit.

8. A video transmitter, comprising: a distributor arranged to receive a plurality of streams of digital video samples and distribute said digital video samples to a plurality of input vectors according to a predetermined arrangement; a plurality of digital-to-analog converters (DACs), each DAC being arranged to receive digital video samples from one of said input vectors and to convert said digital video samples of said one input vector into a series of analog video samples; as well as A plurality of orthogonal frequency division multiplexing (OFDM) transmitters each receive one of the series of analog video samples and transmit the series of analog video samples as an OFDM signal via an electromagnetic path.

9. The video transmitter of claim 8, wherein the distributor further comprises: A first row buffer storing the plurality of input vectors; as well as a second line buffer storing a plurality of second input vectors, wherein the distributor is further arranged to distribute a line of the digital video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer, wherein the DAC alternately receives from the first line buffer while the distributor writes to the second line buffer, and receives from the second line buffer while the distributor writes to the first line buffer.

10. The video transmitter of claim 8, wherein the digital video samples are distributed into the input vectors at a first frequency, wherein the digital video samples are output from each series of the input vectors at a second frequency different from the first frequency.

11. The video transmitter of claim 8, wherein the predetermined arrangement allows each sampling amplifier of a source driver that receives one of the series of analog video samples to output the analog video samples to consecutive storage locations.

12. The video transmitter of claim 8, wherein each of the OFDM transmitters comprises: a switching circuit that receives said one of said series of analog video samples, wherein for each pair of analog samples received, said switching circuit outputs a first analog level of said pair as an in-phase (I) component and outputs a second analog level of said pair as an out-of-phase (Q) component to a bin of an inverse fast Fourier transform (IFFT) block, wherein each of said OFDM transmitters performs an IFFT on said IFFT block to produce said OFDM signal.

13. The video transmitter of claim 8, wherein each OFDM transmitter does not include a constellation for mapping.

14. The video transmitter of claim 8, wherein each OFDM transmitter does not include a digital-to-analog converter.

15. A video receiver, comprising: an orthogonal frequency division multiplexing (OFDM) receiver arranged to receive the OFDM signal via an electromagnetic path and output a series of analog video samples; a collector arranged to receive the series of analog video samples and to store the series of analog video samples; as well as A plurality of column drivers are arranged to receive the stored series of analog video samples from the collector in parallel and amplify each of the stored analog video samples onto a column of a display panel.

16. The video receiver of claim 15, wherein the collector further comprises: A first storage array and a second storage array, wherein the collector alternately writes the analog video samples to the first storage array or to the second storage array, wherein the column driver alternately reads from the first storage array while the collector writes to the second storage array and reads from the second storage array while the collector writes to the first storage array.

17. The video receiver of claim 15, wherein a predetermined arrangement allows the collector to store the analog video samples into consecutive memory locations.

18. The video receiver of claim 15, wherein the video receiver does not include any digital-to-analog converter (DAC) for converting video samples.

19. The video receiver of claim 15, wherein the OFDM receiver comprises: A combining circuit inputs the I component and the Q component of each bin of the FFT block and outputs the I component and the Q component as a first analog value and a second analog value so as to output a continuous stream of analog video samples.

20. The video receiver of claim 15, wherein the OFDM receiver does not include a constellation for mapping.

21. The receiver of claim 15, wherein the OFDM receiver does not include an analog-to-digital converter.

22. A video transmitter, comprising: a distributor arranged to receive a plurality of video signals comprising digital video samples, distribute said digital video samples of said video signals to a plurality of input vectors according to a predetermined arrangement, and output each of said input vectors as a series of digital video samples; as well as A plurality of orthogonal frequency division multiplexing (OFDM) transmitters each receive one of the series of digital video samples and transmit the series of digital video samples as an OFDM signal over an electromagnetic path.

23. The video transmitter of claim 22, wherein the distributor further comprises: A first row buffer, configured to store the plurality of input vectors; as well as a second line buffer storing a plurality of second input vectors, wherein the distributor is further arranged to distribute a line of the digital video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer, and wherein the OFDM transmitter alternately receives from the first line buffer when the distributor writes to the second line buffer, and receives from the second line buffer when the distributor writes to the first line buffer.

24. The video transmitter of claim 22, wherein the digital video samples are assigned to the input vectors at a first frequency, wherein the digital video samples are serially output from each of the input vectors at a second frequency different from the first frequency.

25. The video transmitter of claim 22, wherein the predetermined arrangement allows each sampling amplifier of a source driver receiving a series of analog video samples to output the analog video samples to consecutive memory locations.

26. The video transmitter of claim 22, wherein each of the OFDM transmitters includes a symbol mapping circuit that maps each of the digital video samples to a point in a constellation to obtain an in-phase (I) component and an out-of-phase (Q) component.

27. The video transmitter of claim 22, wherein each of the OFDM transmitters comprises a symbol mapping circuit, wherein each digital video sample received by the symbol mapping circuit comprises a most significant bit (MSB) and a least significant bit (LSB), wherein for each digital video sample received, the symbol mapping circuit assigns the MSB of the each digital video sample to the MSB of an in-phase (I) component and the MSB of an out-of-phase (Q) component, wherein For each digital video sample received, the symbol mapping circuit allocates the LSB of each digital video sample to the LSB of an in-phase (I) component and the LSB of an out-of-phase (Q) component, and wherein the symbol mapping circuit outputs the I component and the Q component to a bin of an inverse fast Fourier transform (IFFT) block.

28. A video receiver, comprising: an orthogonal frequency division multiplexing (OFDM) receiver arranged to receive the OFDM signal via an electromagnetic path and output a series of digital video samples; a digital-to-analog converter (DAC) that receives the series of digital video samples and outputs a series of analog video samples; a collector arranged to receive the series of analog video samples and to store the series of analog video samples; as well as A plurality of column drivers are arranged to receive the stored series of analog video samples from the collector in parallel and amplify each of the stored analog video samples onto a column of a display panel.

29. The video receiver of claim 28, wherein the collector further comprises: A first storage array and a second storage array, wherein the collector alternately writes the analog video samples to the first storage array or to the second storage array, and wherein the column driver alternately receives from the first storage array when the collector writes to the second storage array and receives from the second storage array when the collector writes to the first storage array.

30. The video receiver of claim 28, wherein a predetermined arrangement allows the collector to store the analog video samples into consecutive memory locations.

31. The video receiver of claim 28, wherein the OFDM receiver includes inverse symbol mapping circuitry to convert each point in a constellation into one of the digital video samples.

32. A video receiver according to claim 28, wherein the OFDM receiver includes a reverse symbol mapping circuit to place the most significant bit (MSB) of each pair of digital I component and digital Q component into the MSB of one of the digital video samples, and to place the least significant bit (LSB) of each pair into the LSB of the one digital video sample.

33. A video transmitter, comprising: a distributor arranged to receive a plurality of video signals comprising analog video samples, distribute said analog video samples of said video signals to a plurality of input vectors according to a predetermined arrangement, and output each of said input vectors as a series of analog video samples; as well as A plurality of orthogonal frequency division multiplexing (OFDM) transmitters each receive one of the series of analog video samples and transmit the series of analog video samples as an OFDM signal via an electromagnetic path.

34. The video transmitter of claim 33, wherein the distributor further comprises: A first row buffer storing the plurality of input vectors; as well as a second line buffer storing a plurality of second input vectors, wherein the distributor is further arranged to distribute the lines of the analog video samples alternately between the input vectors of the first line buffer and the second input vectors of the second line buffer, and wherein the OFDM transmitter alternately receives from the first line buffer when the distributor writes to the second line buffer, and receives from the second line buffer when the distributor writes to the first line buffer.

35. The video transmitter of claim 33, wherein the analog video samples are assigned to the input vectors at a first frequency, and wherein the analog video samples are serially output from each of the input vectors at a second frequency different from the first frequency.

36. The video transmitter of claim 33, wherein the predetermined arrangement allows each sampling amplifier of a source driver receiving a series of analog video samples to output the analog video samples to consecutive memory locations.

37. The video transmitter of claim 33, wherein each of the OFDM transmitters comprises: a switching circuit that receives one of the series of analog video samples, wherein for each pair of analog samples received, the switching circuit outputs a first analog level of the pair as an in-phase (I) component and outputs a second analog level of the pair as an out-of-phase (Q) component to a bin of an inverse fast Fourier transform (IFFT) block, wherein each of the OFDM transmitters performs an IFFT on the IFFT block to generate the OFDM signal.

38. The video transmitter of claim 33, wherein each OFDM transmitter does not include a constellation for mapping.

39. The video transmitter of claim 33, wherein each OFDM transmitter does not include a digital-to-analog converter.

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