Train control system hardware real-time coding method and system

Abstract

The invention relates to / belongs to the technical field of train control, and particularly relates to a train control system hardware real-time coding method and system. The technical problem that in the prior art, safety is insufficient, enough safety redundancy design is lacked, and consequently a system cannot run under the fault condition is solved. The method is used in the FPGA, comprises a first coding module, a second coding module and a DPRAM module, and specifically comprises the following steps: stabilizing an initial transponder message to obtain a stable transponder message; respectively inputting the stable transponder message into a first encoding module and a second encoding module which are parallel to each other, and respectively encoding the stable transponder message in real time by utilizing the first encoding module and the second encoding module based on a control signal sent by an external CPU (Central Processing Unit) to obtain a first encoding message and a second encoding message; and storing the first coded message and the second coded message in a DPRAM module for an external CPU to read.

Description

Technical Field

[0001] The present invention belongs to the technical field of train control, and in particular relates to a method and system for hardware real-time encoding of a train control system. Background Art

[0002] A balise is a device used in railway signalling systems, usually installed beside or embedded in the track, to send specific information to passing trains. This information may include, but is not limited to, the status of the line ahead, speed limits, switch locations, etc. The information sent by the balise needs to be encoded into a format that can be correctly parsed and applied by the onboard equipment.

[0003] In the prior art, wireless transmission of balise information is achieved through the European Train Control System (ETCS), and the balise message coding of the ETCS system specifies the structure and coding method of the balise message to ensure that the train can read standardized information from the balise. In the ETCS system, the ground electronic unit obtains line data from the signal, encodes it, and sends the balise message to the onboard equipment via the active balise, and the onboard equipment decodes and processes the balise message data.

[0004] The prior art has the following technical problems: 1. The existing ETCS system has poor real-time performance in message encoding and does not have efficient real-time encoding capabilities.

[0005] 2. The existing ETCS system is not secure enough and lacks sufficient safety redundancy design, which causes the system to be unable to operate under fault conditions.

[0006] 3. The existing ETCS system cannot support the simultaneous operation of multiple ground electronic unit devices and transponders, and has weak load capacity. Summary of the invention

[0007] The present invention provides a method and system for hardware real-time encoding of a train control system, aiming to solve the technical problems existing in the above-mentioned prior art, such as poor real-time performance in message encoding and lack of efficient real-time encoding capability; insufficient security and lack of sufficient safety redundancy design, which causes the system to be unable to operate under fault conditions; and inability to support the simultaneous operation of multiple ground electronic unit devices and transponders and weak load capacity.

[0008] The technical solution of the present invention to solve the above technical problem is as follows: A method for hardware real-time encoding of a train control system is used in an FPGA, the FPGA includes: a first encoding module, a second encoding module and a DPRAM module, the method includes: Acquire an initial transponder message, and perform stabilization processing on the initial transponder message to obtain a stable transponder message; The stable transponder message is input into two parallel first encoding modules and second encoding modules respectively, and based on the control signal sent by the external CPU, the first encoding module is used to encode the stable transponder message in real time to obtain a first encoded message; and the second encoding module is used to encode the stable transponder message in real time to obtain a second encoded message; The first coded message and the second coded message are stored in a DPRAM module for being read by the external CPU.

[0009] Furthermore, the above also includes: The first encoding module is used to decode the first encoded message to obtain a first decoded message; the second encoding module is used to decode the second encoded message to obtain a second decoded message, and the first decoded message and the second decoded message are sent to the external CPU for verification.

[0010] Furthermore, the FPGA mentioned above also includes a PLL module, specifically: utilizing the PLL module to perform stable processing on the initial responder message.

[0011] Furthermore, the first encoding module includes: a scrambling unit, a replacement unit, a verification unit and a checking unit. Using the first encoding module to perform real-time encoding on the stable transponder message specifically includes: Using the scrambling unit to scramble the stable transponder message to obtain a scrambled message; Using the replacement unit to perform 10-11 replacement processing on the scrambled message to obtain a first replacement message; Calculating a check code of the first replacement message by using the check unit, and appending the check code to the end of the data of the first replacement message to obtain a check message; The checking unit is used to perform a conditional check on the verification message, and if the check passes, the first coded message is obtained.

[0012] Further, the first encoding module further includes: a negation unit, a descrambling unit and a sending unit; and using the first encoding module to decode the first encoded message specifically includes: Using the negation unit to perform a negation operation on each bit in the first coded message to obtain negated data; Using the descrambling unit to descramble the inverted data to obtain descrambled data; Using the replacement unit to perform 11-10 replacement processing on the descrambled data to obtain a first decoded message; The first decoded message is written into the DPRAM module by using the sending unit, and sent to the external CPU for verification.

[0013] Furthermore, the FPGA described above also includes a status self-check module, specifically: The state self-check module is used to detect the state of the first encoding module, the state of the second encoding module and the stability of the stable transponder message in real time to obtain a detection result, and the detection result is sent to the external CPU.

[0014] Furthermore, the above also includes: Acquire a chip select signal, and control the operating state of the first encoding module and the operating state of the second encoding module based on the chip select signal, wherein the chip select signal is generated by the external CPU according to the detection result.

[0015] In a second aspect, in order to solve the above technical problem, the present invention further provides a system for hardware real-time encoding of a train control system, comprising: A PLL module, used for acquiring an initial transponder message, and performing stabilization processing on the initial transponder message to obtain a stable transponder message; A first encoding module, configured to encode the stable transponder message in real time based on a control signal sent by an external CPU to obtain a first encoded message; A second encoding module, configured to encode the stable transponder message in real time based on a control signal sent by an external CPU to obtain a second encoded message; The DPRAM module is used to store the first coded message and the second coded message in the DPRAM module for the external CPU to read.

[0016] Furthermore, the above also includes: The first encoding module is further used to decode the first encoded message to obtain a first decoded message; The second encoding module is further used to decode the second encoded message to obtain a second decoded message; A sending unit is used to send the first decoded message and the second decoded message to the external CPU for verification.

[0017] Furthermore, the above also includes: The state self-check module is used to detect the state of the first encoding module, the state of the second encoding module and the stability of the stable transponder message in real time, obtain the detection result, and send the detection result to the external CPU.

[0018] Compared with the prior art, the present invention has the following advantages: 1. The present invention processes the same data simultaneously through two parallel first encoding modules and second encoding modules, ensuring that even if one module fails, the other module can still work normally. The status self-check module monitors the status of each module in real time. Once a module failure is detected, it can immediately switch to the backup module to ensure the reliability and fault tolerance of the system.

[0019] 2. The real-time encoding and decoding process implemented by the present invention using FPGA can respond quickly, reduce processing time, and ensure the timeliness of data transmission.

[0020] 3. The present invention realizes complex encoding and decoding processes by performing fine module function division and state machine control on FPGA.

[0021] 4. The present invention defines the main stages of the entire encoding or decoding process, such as initialization, encoding, sending, receiving, decoding, etc., to ensure that each stage can be executed correctly.

[0022] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic flow chart of a method for hardware real-time encoding of a train control system according to an embodiment of the present invention is shown; Figure 2 A schematic structural diagram of a system for hardware real-time encoding of a train control system according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] Figure 1A flow chart of a method for hardware real-time encoding of a train control system according to an embodiment of the present invention is shown. Figure 1 As shown, a method for real-time hardware encoding of a train control system according to an embodiment of the present invention is used in an FPGA, wherein the FPGA includes: a first encoding module, a second encoding module and a DPRAM module, and the method includes: Acquire an initial transponder message, and perform stabilization processing on the initial transponder message to obtain a stable transponder message; The stable transponder message is input into two parallel first encoding modules and second encoding modules respectively, and based on the control signal sent by the external CPU, the first encoding module is used to encode the stable transponder message in real time to obtain a first encoded message; and the second encoding module is used to encode the stable transponder message in real time to obtain a second encoded message; In this embodiment, during the data input stage, it also includes a first control signal sent by an external CPU and a second control signal pre-stored in the FPGA. An XOR gate is used to perform control logic judgment on the first control signal and the second control signal, and a control logic result is output. The first encoding module and the second encoding module both receive three inputs: a stable transponder message, a second control signal, and a control logic result.

[0027] The first coded message and the second coded message are stored in a DPRAM module for being read by the external CPU.

[0028] In this embodiment, the DPRAM module includes a DPRAM1 unit located inside the first encoding module and a DPRAM2 unit located inside the second encoding module. The first encoding module stores the processed first encoded message and the first decoded message in the DPRAM1 unit, and the second encoding module stores the processed second encoded message and the second decoded message in the DPRAM2 unit.

[0029] Optionally, also include: The first encoding module is used to decode the first encoded message to obtain a first decoded message; the second encoding module is used to decode the second encoded message to obtain a second decoded message, and the first decoded message and the second decoded message are sent to the external CPU for verification.

[0030] Optionally, the FPGA further includes a PLL module, specifically: utilizing the PLL module to perform stable processing on the initial responder message.

[0031] In this embodiment, the PLL module ensures that all operations within the FPGA are based on a reliable and consistent time reference, which is particularly important for real-time encoding and decoding tasks. If the quality of the initial transponder message is unstable or the frequency is inaccurate, the PLL module can help compensate for these defects and ensure that system performance is not affected. Among them, through the multiple frequency options provided by the PLL module, the FPGA can select the most appropriate clock frequency to perform different tasks as needed, optimize resource usage and improve efficiency.

[0032] Optionally, the first encoding module includes: a scrambling unit, a replacement unit, a verification unit and a checking unit, and using the first encoding module to perform real-time encoding on the stable transponder message specifically includes: Using the scrambling unit to scramble the stable transponder message to obtain a scrambled message; In this embodiment, scrambling is performed to avoid long strings of continuous identical levels (such as a string of 0s or 1s), which helps maintain uniform distribution of the signal spectrum and prevents failure of a clock recovery mechanism at the receiving end.

[0033] Using the replacement unit to perform 10-11 replacement processing on the scrambled message to obtain a first replacement message; In this embodiment, each 10-bit data block is converted into a unique 11-bit code word. This encoding method ensures that even in the worst case (i.e., all 0s or all 1s), there are enough signal changes to maintain synchronization. In this way, redundancy is added to help the receiving end recover the clock and data more easily, while providing additional information for error detection.

[0034] Calculating a check code of the first replacement message by using the check unit, and appending the check code to the end of the data of the first replacement message to obtain a check message; The checking unit is used to perform a conditional check on the verification message, and if the check passes, the first coded message is obtained.

[0035] In this embodiment, the encoding operation steps for obtaining the second coded message are the same as the encoding operation steps for obtaining the first coded message. The stable transponder message is 830 bits of user data, and the first coded message is a 1023 bits transponder message. The maximum encoding time of a stable transponder message does not exceed 200ms.

[0036] Optionally, the first encoding module further includes: a negation unit, a descrambling unit, and a sending unit; and using the first encoding module to decode the first encoded message specifically includes: Using the negation unit to perform a negation operation on each bit in the first coded message to obtain negated data; Using the descrambling unit to descramble the inverted data to obtain descrambled data; Using the replacement unit to perform 11-10 replacement processing on the descrambled data to obtain a first decoded message; The first decoded message is written into the DPRAM module by using the sending unit, and sent to the external CPU for verification.

[0037] Optionally, the FPGA further includes a status self-check module, specifically: The state self-check module is used to detect the state of the first encoding module, the state of the second encoding module and the stability of the stable transponder message in real time to obtain a detection result, and the detection result is sent to the external CPU.

[0038] In this embodiment, the detection results are fed back to the external CPU via control signals, and the external CPU can adjust system parameters or take necessary fault handling measures according to the detection results.

[0039] Optionally, also include: Acquire a chip select signal, and control the operating state of the first encoding module and the operating state of the second encoding module based on the chip select signal, wherein the chip select signal is generated by the external CPU according to the detection result.

[0040] In this embodiment, the status self-check module monitors the status of each module in real time. If the status self-check module detects that the first encoding module has a fault (for example, data transmission error, hardware failure, etc.), it will generate a fault signal. The status self-check module sends the fault signal to the external CPU, and the external CPU adjusts the chip select signal according to the fault signal, for example: the first chip select signal (corresponding to the first encoding module) becomes invalid. The second chip select signal (corresponding to the second encoding module) becomes valid. The subsequent external CPU redirects the data to the second encoding module through the parallel bus. The control signal is also transmitted to the second encoding module through the chip select signal.

[0041] In this embodiment, in the state detection stage, the stable transponder message is input into the frequency divider, and the stable transponder message is frequency-divided by the frequency divider to obtain a frequency-divided signal, and the second control signal and the frequency-divided signal are input into the state self-check module, and the state self-check is performed according to the control signal for state detection sent by the external CPU.

[0042] Based on Figure 1 Based on the same principle as the method shown in , the embodiment of the present invention also provides a system for hardware real-time encoding of a train control system, such as Figure 2 As shown in, including: A PLL module, used for acquiring an initial transponder message, and performing stabilization processing on the initial transponder message to obtain a stable transponder message; A first encoding module, configured to encode the stable transponder message in real time based on a control signal sent by an external CPU to obtain a first encoded message; A second encoding module, configured to encode the stable transponder message in real time based on a control signal sent by an external CPU to obtain a second encoded message; The DPRAM module is used to store the first coded message and the second coded message in the DPRAM module for the external CPU to read.

[0043] Optionally, also include: The first encoding module is further used to decode the first encoded message to obtain a first decoded message; The second encoding module is further used to decode the second encoded message to obtain a second decoded message; A sending unit is used to send the first decoded message and the second decoded message to the external CPU for verification.

[0044] Optionally, the DPRAM module includes: The DPRAM1 unit is located inside the first encoding module and is used to store the first encoded message and the first decoded message; A DPRAM2 unit, located inside the second encoding module, is used to store a second encoded message and a second decoded message; Optionally, also include: The state self-check module is used to detect the state of the first encoding module, the state of the second encoding module and the stability of the stable transponder message in real time, obtain the detection result, and send the detection result to the external CPU.

[0045] The first encoding module includes: The scrambling unit is used to scramble the stable transponder message to obtain a scrambled message. In this embodiment, the scrambling process is used to avoid long strings of continuous identical levels (such as a series of 0s or 1s), which helps to maintain a uniform distribution of the signal spectrum and prevent the clock recovery mechanism at the receiving end from malfunctioning.

[0046] The replacement unit is used to perform 10-11 replacement processing on the scrambled message to obtain a first replacement message; in this embodiment, for each 10-bit data block, it is converted into a unique 11-bit code word. This encoding method ensures that even in the worst case (i.e., all 0s or all 1s), there are enough signal changes to maintain synchronization. In this way, redundancy is added to help the receiving end recover the clock and data more easily, while providing additional information for error detection.

[0047] a verification unit, configured to calculate a verification code of the first replacement message, and append the verification code to the end of the data of the first replacement message to obtain a verification message; A checking unit is used to perform a conditional check on the verification message, and if the check passes, the first coded message is obtained.

[0048] In this embodiment, the stable transponder message is 830 bits of user data, and the first coded message is a 1023 bits transponder message. The maximum coding time of a stable transponder message does not exceed 200 ms.

[0049] Optionally, the first encoding module further includes: a negation unit, used for performing a negation operation on each bit in the first coded message to obtain negated data; a descrambling unit, configured to perform a descrambling process on the negated data to obtain descrambled data; A replacement unit, configured to perform 11-10 replacement processing on the descrambled data to obtain a first decoded message; A sending unit is used to write the first decoded message into the DPRAM module and send it to the external CPU for verification.

[0050] In this embodiment, the structure of the second encoding module is the same as that of the first encoding module, which will not be described again here.

[0051] The above description is only a preferred embodiment of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the disclosure scope involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) by each other.

Claims

1. A method for hardware real-time encoding of a train control system, characterized in that: Used in an FPGA, the FPGA includes: a first encoding module, a second encoding module and a DPRAM module, and the method includes: Acquire an initial transponder message, and perform stabilization processing on the initial transponder message to obtain a stable transponder message; The stable transponder message is input into two parallel first encoding modules and second encoding modules respectively, and based on the control signal sent by the external CPU, the first encoding module is used to encode the stable transponder message in real time to obtain a first encoded message; and the second encoding module is used to encode the stable transponder message in real time to obtain a second encoded message; The first coded message and the second coded message are stored in a DPRAM module for being read by the external CPU.

2. The method for hardware real-time encoding of a train control system according to claim 1, characterized in that: Also includes: Decoding the first encoded message using the first encoding module to obtain a first decoded message; The second encoded message is decoded by the second encoding module to obtain a second decoded message, and the first decoded message and the second decoded message are sent to the external CPU for verification.

3. The method for hardware real-time encoding of a train control system according to claim 1, characterized in that: The FPGA also includes a PLL module, specifically: utilizing the PLL module to perform stable processing on the initial responder message.

4. The method for hardware real-time encoding of a train control system according to claim 2, characterized in that: The first encoding module includes: a scrambling unit, a replacement unit, a verification unit and a checking unit. Using the first encoding module to perform real-time encoding on the stable transponder message specifically includes: Using the scrambling unit to scramble the stable transponder message to obtain a scrambled message; Using the replacement unit to perform 10-11 replacement processing on the scrambled message to obtain a first replacement message; Calculating a check code of the first replacement message by using the check unit, and appending the check code to the end of the data of the first replacement message to obtain a check message; The checking unit is used to perform a conditional check on the verification message, and if the check passes, the first coded message is obtained.

5. The method for hardware real-time encoding of a train control system according to claim 4, characterized in that: The first encoding module further includes: a negation unit, a descrambling unit and a sending unit; and using the first encoding module to decode the first encoded message specifically includes: Using the negation unit to perform a negation operation on each bit in the first coded message to obtain negated data; Using the descrambling unit to descramble the inverted data to obtain descrambled data; Using the replacement unit to perform 11-10 replacement processing on the descrambled data to obtain a first decoded message; The first decoded message is written into the DPRAM module by using the sending unit, and sent to the external CPU for verification.

6. The method for hardware real-time encoding of a train control system according to claim 1, characterized in that: The FPGA also includes a status self-check module, specifically: The state self-check module is used to detect the state of the first encoding module, the state of the second encoding module and the stability of the stable transponder message in real time to obtain a detection result, and the detection result is sent to the external CPU.

7. The method for hardware real-time encoding of a train control system according to claim 6, characterized in that: Also includes: Acquire a chip select signal, and control the operating state of the first encoding module and the operating state of the second encoding module based on the chip select signal, wherein the chip select signal is generated by the external CPU according to the detection result.

8. A system for hardware real-time encoding of a train control system, characterized in that: For use in an FPGA, the system comprises: A PLL module, used for acquiring an initial transponder message, and performing stabilization processing on the initial transponder message to obtain a stable transponder message; A first encoding module, configured to encode the stable transponder message in real time based on a control signal sent by an external CPU to obtain a first encoded message; A second encoding module, configured to encode the stable transponder message in real time based on a control signal sent by an external CPU to obtain a second encoded message; The DPRAM module is used to store the first coded message and the second coded message in the DPRAM module for the external CPU to read.

9. The system of hardware real-time encoding of a train control system according to claim 8, characterized in that: Also includes: The first encoding module is further used to decode the first encoded message to obtain a first decoded message; The second encoding module is further used to decode the second encoded message to obtain a second decoded message; A sending unit is used to send the first decoded message and the second decoded message to the external CPU for verification.

10. The system of hardware real-time encoding of a train control system according to claim 8, characterized in that: Also includes: The state self-check module is used to detect the state of the first encoding module, the state of the second encoding module and the stability of the stable transponder message in real time, obtain the detection result, and send the detection result to the external CPU.

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