Chip testing method and device, equipment and storage medium

Abstract

The invention discloses a chip testing method and device, equipment and a storage medium, and relates to the technical field of integrated circuit testing, and the method comprises the steps: obtaining a first target level inputted by a preset input interface, and carrying out the preset high-speed signal testing of a target chip based on the first target level, so as to obtain a first testing result; adjusting the first target level based on the first test result to obtain a corresponding second target level; and performing preset built-in self-testing on the target chip according to the second target level to obtain a second test result, and determining a target test result corresponding to the target chip based on the first test result and the second test result. Therefore, the target chip can be controlled to perform high-speed signal testing or built-in self testing based on the level input by the preset input interface, final testing of the chip according to needs is realized, the testing time is shortened, the testing efficiency of the chip is improved, and meanwhile, the testing cost of the chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a chip testing method, device, equipment and storage medium. Background Art

[0002] With the development of integrated circuit technology, the complexity and integration of chips are increasing, and the testing process in chip manufacturing has become crucial. Especially in the final test stage of the chip, it is necessary to ensure that all functional modules of the chip can meet the design requirements and operate normally in actual applications. Semiconductor final test (Final Test, FT) is the last test stage after the chip is packaged, and its purpose is to ensure the performance and reliability of the chip in actual applications.

[0003] The existing semiconductor final test solution requires loading the loading board onto the test machine, powering the test machine and applying input signals to configure the test items, and using the machine to detect the output signals to determine whether the chip functions meet the design requirements. The test program is stored in the non-volatile memory in the device under test, such as ROM (Read-Only Memory) or Flash. During the semiconductor final test, the device under test needs to first load the test program from the non-volatile memory, and then start the test program to perform the relevant test items.

[0004] In summary, how to achieve final testing of chips on demand is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a chip testing method, device, equipment and storage medium, which can realize the final test of the chip on demand. The specific scheme is as follows:

[0006] In a first aspect, the present application provides a chip testing method, comprising:

[0007] Acquire a first target level inputted by a preset input interface, and perform a preset high-speed signal test on a target chip based on the first target level to obtain a first test result;

[0008] adjusting the first target level based on the first test result to obtain a corresponding second target level;

[0009] A preset built-in self-test is performed on the target chip according to the second target level to obtain a second test result, and a target test result corresponding to the target chip is determined based on the first test result and the second test result.

[0010] Optionally, acquiring a first target level inputted by a preset input interface, and performing a preset high-speed signal test on a target chip based on the first target level, includes:

[0011] The first target level input by the preset input interface according to the first preset level rule is obtained, and the first target program corresponding to the preset high-speed signal test is loaded from the preset memory based on the first target level, so as to perform the preset high-speed signal test on the target chip based on the first target program.

[0012] Optionally, performing the preset high-speed signal test on the target chip based on the first target program includes:

[0013] Determine each physical layer of the target chip, and use a transmitter in the physical layer to send a preset test pattern based on a preset loopback mode;

[0014] The preset test pattern is received by the receiving end in the physical layer based on the preset loopback mode, and corresponding error detection is performed on the preset test pattern to obtain the first test result.

[0015] Optionally, adjusting the first target level based on the first test result includes:

[0016] If the first test result indicates that the target chip does not meet the preset defective condition, adjusting the first target level inputted by the preset input interface based on the first preset level rule to obtain the corresponding second target level;

[0017] If the first test result indicates that the target chip meets a preset defective condition, the first test result is directly determined as the target test result corresponding to the target chip, and the preset built-in self-test for the target chip is stopped.

[0018] Optionally, performing a preset built-in self-test on the target chip according to the second target level includes:

[0019] A second target program corresponding to the preset built-in self-test is loaded from a preset memory based on the second target level, so as to perform the preset built-in self-test on the target chip based on the second target program.

[0020] Optionally, performing the preset built-in self-test on the target chip based on the second target program includes:

[0021] Determine a first initial test result obtained by performing the preset built-in self-test on the memory of the target chip, and judge whether the target chip meets a preset good product condition based on the first initial test result;

[0022] If the target chip does not meet the preset good product condition, the preset built-in self-test is performed on the memory of the target chip based on a preset error correction technology to obtain a corresponding second initial test result, and the second test result is determined based on the first initial test result and the second initial test result.

[0023] Optionally, determining a target test result corresponding to the target chip based on the first test result and the second test result includes:

[0024] The first test result and the second test result are acquired by using a preset output interface, and the target test result corresponding to the target chip is output through the preset output interface based on a second preset level rule, the first test result and the second test result.

[0025] In a second aspect, the present application provides a chip testing device, comprising:

[0026] A first test result determination module, used for acquiring a first target level inputted from a preset input interface, and performing a preset high-speed signal test on a target chip based on the first target level to obtain a first test result;

[0027] a second target level determination module, configured to adjust the first target level based on the first test result to obtain a corresponding second target level;

[0028] The target test result determination module is used to perform a preset built-in self-test on the target chip according to the second target level to obtain a second test result, and determine a target test result corresponding to the target chip based on the first test result and the second test result.

[0029] In a third aspect, the present application provides an electronic device, including:

[0030] Memory, used to store computer programs;

[0031] The processor is used to execute the computer program to implement the aforementioned chip testing method.

[0032] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned chip testing method is implemented.

[0033] In the present application, the first target level input by the preset input interface is first obtained, and the preset high-speed signal test is performed on the target chip based on the first target level to obtain a first test result; then the first target level is adjusted based on the first test result to obtain a corresponding second target level; finally, the preset built-in self-test is performed on the target chip according to the second target level to obtain a second test result, and the target test result corresponding to the target chip is determined based on the first test result and the second test result. As can be seen from the above, when the first target level input by the preset input interface is obtained, the present application controls the target chip to perform a high-speed signal test, and adjusts the first target level based on the high-speed signal test result to obtain the second target level, so as to control the target chip to perform a built-in self-test according to the second target level, and finally determines the final test result of the target chip according to the high-speed signal test result and the built-in self-test result. In this way, the present application can control the target chip to perform a high-speed signal test or a built-in self-test based on the level input by the preset input interface, so as to realize the final test of the chip on demand. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0035] Figure 1 A chip testing solution system architecture diagram provided for this application;

[0036] Figure 2 A flow chart of a chip testing method provided in this application;

[0037] Figure 3 A specific high-speed signal connection diagram provided for this application;

[0038] Figure 4 A specific built-in self-test flow chart provided for this application;

[0039] Figure 5 A schematic diagram of the structure of a chip testing device provided in this application;

[0040] Figure 6 A structural diagram of an electronic device provided for this application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] The existing semiconductor final test scheme requires loading the loading board onto the test machine, powering the test machine and applying input signals to configure the test items, and using the machine to detect the output signals to determine whether the chip functions meet the design requirements. And the test program is stored in a non-volatile memory in the device under test, such as ROM (Read-Only Memory) or Flash. During the final test of the semiconductor, the device under test needs to first load the test program from the non-volatile memory, and then start the test program to perform related test items. To this end, the present application provides a chip testing scheme that can realize the final test of the chip on demand.

[0043] In the chip testing solution of this application, the system framework used can be specifically referred to Figure 1 As shown, it can specifically include: a test stimulus generation module, a test program loading module, an MBIST test module (MBIST, i.e., memory built-in self-test), a high-speed signal test module, a test result collection module, and a PowerBoard power supply module, wherein the PowerBoard power supply module can replace the machine power supply module to realize offline testing of the chip without the test machine, and at the same time, the present application can support the conversion of the two chip testing modes of offline testing and machine power supply testing. In addition, in the chip testing scheme of the present application, the RAM defect detection and repair function (RAM, i.e., Random Access Memory), the high-speed signal test pattern sending and detection function, and the test result processing function are designed in the software to realize the MBIST test and fault repair of the RAM memory inside the chip, the test pattern loopback and error detection of the high-speed signal, and the dynamic loading of the test code according to the test function and other newly added test functions, and provide the functions of offline debugging of the loading board (i.e., Load board) and offline testing of the chip.

[0044] See also Figure 2 As shown, an embodiment of the present invention discloses a chip testing method, which may include:

[0045] Step S11, obtaining a first target level input by a preset input interface, and performing a preset high-speed signal test on a target chip based on the first target level to obtain a first test result.

[0046] It is understandable that the existing final test technology requires loading the loading board onto the test machine, supplying power to the test machine and applying input signals to configure the test items, and using the machine to detect the output signals to determine whether the chip functions meet the design requirements. However, generally only packaging and testing factories have FT testing capabilities, and renting a test machine requires high testing costs. Therefore, in this embodiment, an independent power supply module is provided, and the loading board can be powered by the power supply board, and the power supply module, the test stimulus generation module and the test result collection module form an independent test system, which can be separated from the test machine for final testing and debugging of the chip.

[0047] It should be noted that the above-mentioned acquisition of the first target level input by the preset input interface and the preset high-speed signal test on the target chip based on the first target level may include: acquiring the first target level input by the preset input interface according to the first preset level rule, and loading the first target program corresponding to the preset high-speed signal test from the preset memory based on the first target level, so as to perform the preset high-speed signal test on the target chip based on the first target program. Specifically, the test stimulus generation module in this embodiment is composed of 4 configurable input GPIOs (i.e., General Purpose Input / Output, general input and output interface), which can output high and low levels through GPIO or read the state of the pin through GPIO as high or low level. GPIO pins can be configured as input or output mode to interact with external hardware. First, the 4 GPIO pins need to be initialized and configured, including setting the direction and level of the pins. In this embodiment, the 4 GPIO pins are configured as input mode to receive test stimulus signals. By inputting high and low level signals to 4 GPIO pins, different excitation signals can be generated, and the excitation signals will be used to control the chip to test various functions. The combination of high and low levels can simulate different external conditions or input signals, thereby comprehensively testing the performance of the chip. In the present embodiment, the test program of each function has been pre-assigned with corresponding addresses and sizes in Flash, and the chip loads the test program according to the test mode input by the GPIO configuration. Since it is necessary to first perform a high-speed signal test on the target chip, the first target level corresponding to the high-speed signal test can be determined according to the first preset level rule, and the corresponding first target level can be input through the GPIO pin. The chip can determine that the high-speed signal test is currently required according to the first target level, and load the first target program corresponding to the high-speed signal test from Flash. In a specific embodiment, it can be set to perform MBIST test when {GPIO0, GPIO1, GPIO2, GPIO3} is {1, 0, 0, 0}.

[0048] It should be pointed out that the existing high-speed signal test solution requires the use of high-speed signal test equipment such as fixtures, oscilloscopes and bit error meters. By training the device under test (DUT) to enter the loopback mode, the test pattern is input to the receiving (Rx) end of the DUT. After receiving the test pattern, the DUT will send the test pattern at the transmitting (Tx) end, and then use the bit error meter or oscilloscope to analyze the signal quality and bit error of the sent pattern. Therefore, the existing high-speed signal test solution cannot be applied to the final test system of the chip. In order to realize the test pattern loopback and bit error detection of high-speed signals, see Figure 3 As shown, the above-mentioned preset high-speed signal test on the target chip based on the first target program may include: determining each physical layer of the target chip, and using the transmitter in the physical layer to send a preset test pattern based on a preset loopback method; using the receiver in the physical layer to receive the preset test pattern based on the preset loopback method, and performing corresponding error detection on the preset test pattern to obtain the first test result. In a specific implementation, the physical layer of the target chip is determined to be PHY0 to PHY35, and each physical layer has a transmitter and a receiver, and the transmitter and the receiver of each physical layer are looped to form 36 independent paths and perform high-speed signal testing. Specifically, the TX end sends the test pattern, and the RX end receives and performs error detection. Among them, the selection of the test pattern is crucial for error detection, and commonly used test patterns include but are not limited to PRBS (Pseudo-Random Binary Sequence), K28.5, 1010, etc. Among them, PRBS is random and can simulate various situations in actual data transmission, so it can effectively detect bit errors. Therefore, PRBS is one of the most commonly used test patterns. The TX end generates a high-speed signal based on the preset test pattern and sends it out through the high-speed interface. The high-speed signal can be SAS3.0 with a transmission rate of 12Gbps and SAS2.0 with a transmission rate of 6Gbps. During the transmission process, it is necessary to ensure that the integrity, timing and performance of the signal meet the high-speed signal test requirements. After that, the RX end receives the test pattern sent by the TX end through the high-speed interface, decodes and verifies the received signal, and compares it with the preset test pattern. If there is a difference between the received signal and the preset test pattern, the bit error is recorded and the corresponding bit error rate is calculated.

[0049] Step S12: adjusting the first target level based on the first test result to obtain a corresponding second target level.

[0050] In this embodiment, the adjusting of the first target level based on the first test result may include: if the first test result indicates that the target chip does not meet the preset poor product condition, adjusting the first target level input by the preset input interface based on the first preset level rule to obtain the corresponding second target level; if the first test result indicates that the target chip meets the preset poor product condition, directly determining the first test result as the target test result corresponding to the target chip, and stopping the preset built-in self-test for the target chip. Specifically, if the target chip is determined not to be a poor product through the high-speed signal test result, it is necessary to perform a built-in self-test on the target chip, so the second target level corresponding to the built-in self-test can be determined according to the first preset level rule, and the corresponding second target level can be input through the GPIO pin. If the target chip is determined to be a poor product through the high-speed signal test result, it is no longer necessary to perform a built-in self-test on the target chip, and the target chip can be directly determined to be a poor product.

[0051] Step S13: performing a preset built-in self-test on the target chip according to the second target level to obtain a second test result, and determining a target test result corresponding to the target chip based on the first test result and the second test result.

[0052] It should be pointed out that the existing FT test program is stored in Flash, and the size of the test program will affect the time of the test loading program. The existing test program usually loads the complete code and cannot load the corresponding code segment on demand according to the test item requirements, so the test time is long and the test efficiency is relatively low. In order to load the chip test program on demand and save test time, in this embodiment, the preset built-in self-test of the target chip according to the second target level may include: loading the second target program corresponding to the preset built-in self-test from the preset memory based on the second target level, so as to perform the preset built-in self-test on the target chip based on the second target program. Specifically, the chip can determine that a built-in self-test is currently required based on the second target level, and load the second target program corresponding to the built-in self-test from Flash.

[0053] It is understandable that the existing MBIST test technology uses a specially designed BIST circuit (BIST, i.e. Built-in Self Test) inside the chip to implement read and write control of the memory: write test vectors, read corresponding data, and output the test results to the outside of the chip through the chip's test pins. However, the existing MBIST test scheme is unable to self-diagnose and correct errors on chips that fail the MBIST test, resulting in chips that can be repaired and passed the test being judged as bad chips. In order to implement MBIST testing and fault repair of RAM memory inside the chip, see Figure 4 As shown, the preset built-in self-test of the target chip based on the second target program may include: determining a first initial test result obtained by performing the preset built-in self-test on the memory of the target chip, and judging whether the target chip meets the preset good product condition based on the first initial test result; if the target chip does not meet the preset good product condition, the preset built-in self-test of the memory of the target chip is performed based on a preset error correction technology to obtain a corresponding second initial test result, and the second test result is determined based on the first initial test result and the second initial test result. Specifically, in order to classify the quality of the chip. First, turn off the ECC error correction (ECC, i.e., ErrorCorrection Code) to perform the MBIST test, which can detect the original performance and quality of the chip without the assistance of the error correction mechanism. If the MBIST test passes at this time, it means that the memory part of the chip itself has no physical defects and the quality is good, and the target chip can be classified as a good product. If the MBIST test fails when the ECC error correction is turned off, turn on the ECC error correction to perform the MBIST test. ECC error correction can detect and correct some errors in the memory. If the MBIST test passes at this time, it means that although there are some problems with the chip, the ECC error correction mechanism can guarantee certain functions and performance, and the target chip can be classified as a substandard product. Substandard products can be used in some scenarios where reliability requirements are not particularly high, or can be processed in some other ways before use. If the MBIST test still fails after turning on ECC error correction, it means that there are serious problems with the memory part of the chip, and even with the error correction mechanism, it cannot guarantee normal operation. The target chip can be classified as a substandard product, and these chips will usually be eliminated or the cause of the failure will be further analyzed. This testing and classification process can more accurately evaluate the quality of the chip, and carry out subsequent processing according to different quality levels, such as direct shipment of good products, special marking or processing of substandard products, and scrapping of substandard products, thereby improving chip production efficiency and product quality control.

[0054] In this embodiment, the determination of the target test result corresponding to the target chip based on the first test result and the second test result may include: obtaining the first test result and the second test result by using a preset output interface, and outputting the target test result corresponding to the target chip through the preset output interface based on a second preset level rule, the first test result and the second test result. Specifically, the test result collection module in this embodiment is composed of 2 configurable output GPIOs and a serial port. After the test is completed, the test result collection module obtains the first test result obtained by performing a high-speed signal test on the target chip and the second test result obtained by performing a built-in self-test on the target chip, and outputs high and low levels through GPIO to represent the final test result. In a specific implementation, it can be set that when {GPIO8, GPIO9} is {0, 1}, it indicates that the high-speed signal test and the built-in self-test pass, and other results indicate failure.

[0055] As can be seen from the above, in this embodiment, the first target level input by the preset input interface is first obtained, and the preset high-speed signal test is performed on the target chip based on the first target level to obtain a first test result; then the first target level is adjusted based on the first test result to obtain a corresponding second target level; finally, the preset built-in self-test is performed on the target chip according to the second target level to obtain a second test result, and the target test result corresponding to the target chip is determined based on the first test result and the second test result. As can be seen from the above, in this embodiment, when the first target level input by the preset input interface is obtained, the target chip is controlled to perform a high-speed signal test, and the first target level is adjusted based on the high-speed signal test result to obtain the second target level, so as to control the target chip to perform a built-in self-test according to the second target level, and finally the final test result of the target chip is determined according to the high-speed signal test result and the built-in self-test result. In this way, this embodiment can control the target chip to perform a high-speed signal test or a built-in self-test based on the level input by the preset input interface, so as to realize the final test of the chip on demand.

[0056] Accordingly, see Figure 5 As shown, the embodiment of the present application also provides a chip testing device, which may include:

[0057] A first test result determination module 11 is used to obtain a first target level input from a preset input interface, and perform a preset high-speed signal test on a target chip based on the first target level to obtain a first test result;

[0058] a second target level determination module 12, configured to adjust the first target level based on the first test result to obtain a corresponding second target level;

[0059] The target test result determination module 13 is used to perform a preset built-in self-test on the target chip according to the second target level to obtain a second test result, and determine a target test result corresponding to the target chip based on the first test result and the second test result.

[0060] As can be seen from the above, in the present application, the first target level input by the preset input interface is first obtained, and the preset high-speed signal test is performed on the target chip based on the first target level to obtain the first test result; then the first target level is adjusted based on the first test result to obtain the corresponding second target level; finally, the preset built-in self-test is performed on the target chip according to the second target level to obtain the second test result, and the target test result corresponding to the target chip is determined based on the first test result and the second test result. As can be seen from the above, when the first target level input by the preset input interface is obtained, the present application controls the target chip to perform a high-speed signal test, and adjusts the first target level based on the high-speed signal test result to obtain the second target level, so as to control the target chip to perform a built-in self-test according to the second target level, and finally determines the final test result of the target chip according to the high-speed signal test result and the built-in self-test result. In this way, the present application can control the target chip to perform a high-speed signal test or a built-in self-test based on the level input by the preset input interface, so as to realize the final test of the chip on demand.

[0061] In some specific implementations, the first test result determination module 11 may include:

[0062] The first target program loading submodule is used to obtain the first target level input by the preset input interface according to the first preset level rule, and load the first target program corresponding to the preset high-speed signal test from the preset memory based on the first target level, so as to perform the preset high-speed signal test on the target chip based on the first target program.

[0063] In some specific implementations, the first target program loading submodule may include:

[0064] A physical layer determination unit, used to determine each physical layer of the target chip, and use a transmitter in the physical layer to send a preset test pattern based on a preset loopback mode;

[0065] The first test result determination unit is used to use the receiving end in the physical layer to receive the preset test code pattern based on the preset loopback mode, and perform corresponding error detection on the preset test code pattern to obtain the first test result.

[0066] In some specific implementations, the second target level determination module 12 may include:

[0067] a second target level determining unit, configured to adjust the first target level inputted by the preset input interface based on the first preset level rule to obtain the corresponding second target level if the first test result indicates that the target chip does not meet the preset defective condition;

[0068] The first target test result determining unit is used to directly determine the first test result as the target test result corresponding to the target chip if the first test result indicates that the target chip meets a preset defective condition, and stop performing the preset built-in self-test on the target chip.

[0069] In some specific implementations, the target test result determination module 13 may include:

[0070] The second target program loading submodule is used to load the second target program corresponding to the preset built-in self-test from the preset memory based on the second target level, so as to perform the preset built-in self-test on the target chip based on the second target program.

[0071] In some specific implementations, the second target program loading submodule may include:

[0072] A first initial test result determination unit, configured to determine a first initial test result obtained by performing the preset built-in self-test on the memory of the target chip, and determine whether the target chip meets a preset good product condition based on the first initial test result;

[0073] A second test result determination unit is used to perform the preset built-in self-test on the memory of the target chip based on a preset error correction technology to obtain a corresponding second initial test result if the target chip does not meet the preset good product condition, and determine the second test result based on the first initial test result and the second initial test result.

[0074] In some specific implementations, the target test result determination module 13 may include:

[0075] The second target test result determination unit is used to obtain the first test result and the second test result by using a preset output interface, and output the target test result corresponding to the target chip through the preset output interface based on a second preset level rule, the first test result and the second test result.

[0076] Furthermore, the present application also discloses an electronic device. Figure 6It is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the chip testing method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0077] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0078] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0079] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the chip testing method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0080] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed chip testing method. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiments, and will not be repeated here.

[0081] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0082] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0083] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0084] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0085] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip testing method, characterized in that: include: Acquire a first target level inputted by a preset input interface, and perform a preset high-speed signal test on a target chip based on the first target level to obtain a first test result; adjusting the first target level based on the first test result to obtain a corresponding second target level; A preset built-in self-test is performed on the target chip according to the second target level to obtain a second test result, and a target test result corresponding to the target chip is determined based on the first test result and the second test result.

2. The chip testing method according to claim 1, characterized in that: The step of obtaining a first target level input from a preset input interface and performing a preset high-speed signal test on a target chip based on the first target level includes: The first target level input by the preset input interface according to the first preset level rule is obtained, and the first target program corresponding to the preset high-speed signal test is loaded from the preset memory based on the first target level, so as to perform the preset high-speed signal test on the target chip based on the first target program.

3. The chip testing method according to claim 2, characterized in that: The performing the preset high-speed signal test on the target chip based on the first target program includes: Determine each physical layer of the target chip, and use a transmitter in the physical layer to send a preset test pattern based on a preset loopback mode; The preset test pattern is received by the receiving end in the physical layer based on the preset loopback mode, and corresponding error detection is performed on the preset test pattern to obtain the first test result.

4. The chip testing method according to claim 2, characterized in that: The adjusting the first target level based on the first test result includes: If the first test result indicates that the target chip does not meet the preset defective condition, adjusting the first target level inputted by the preset input interface based on the first preset level rule to obtain the corresponding second target level; If the first test result indicates that the target chip meets a preset defective condition, the first test result is directly determined as the target test result corresponding to the target chip, and the preset built-in self-test for the target chip is stopped.

5. The chip testing method according to claim 1, characterized in that: The performing a preset built-in self-test on the target chip according to the second target level includes: A second target program corresponding to the preset built-in self-test is loaded from a preset memory based on the second target level, so as to perform the preset built-in self-test on the target chip based on the second target program.

6. The chip testing method according to claim 5, characterized in that: The performing the preset built-in self-test on the target chip based on the second target program includes: Determine a first initial test result obtained by performing the preset built-in self-test on the memory of the target chip, and judge whether the target chip meets a preset good product condition based on the first initial test result; If the target chip does not meet the preset good product condition, the preset built-in self-test is performed on the memory of the target chip based on a preset error correction technology to obtain a corresponding second initial test result, and the second test result is determined based on the first initial test result and the second initial test result.

7. The chip testing method according to any one of claims 1 to 6, characterized in that: The determining a target test result corresponding to the target chip based on the first test result and the second test result includes: The first test result and the second test result are acquired by using a preset output interface, and the target test result corresponding to the target chip is output through the preset output interface based on a second preset level rule, the first test result and the second test result.

8. A chip testing device, characterized in that: include: A first test result determination module, used for acquiring a first target level inputted from a preset input interface, and performing a preset high-speed signal test on a target chip based on the first target level to obtain a first test result; a second target level determination module, configured to adjust the first target level based on the first test result to obtain a corresponding second target level; The target test result determination module is used to perform a preset built-in self-test on the target chip according to the second target level to obtain a second test result, and determine a target test result corresponding to the target chip based on the first test result and the second test result.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the chip testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the chip testing method according to any one of claims 1 to 7.

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