A reference-free low-noise LDO circuit

Abstract

The present invention discloses a reference-free low-noise LDO circuit, which relates to the field of power supply circuits. The connection node of the resistor R1 and the resistor R4 is grounded after passing through the resistor R2, the transistor Q5 and the resistor R3 in sequence, and the control terminal of the transistor Q5 is connected to the connection node of the resistor R2 and the transistor Q5. The voltage input terminal n1 of the error amplifier module is connected to the connection node of the transistor MP6 and the transistor Q3, the voltage input terminal n2 is connected to the connection node of the transistor MP7 and the transistor Q4, the connection terminal ibias is simultaneously connected to the control terminals of the transistor MN7 and the transistor MN5, and the output terminal is connected to the control terminal of the power tube MP_power. The input terminal of the bias current module is connected to the voltage output terminal Vout, and the output terminal is connected to the connection terminal ibias of the error amplifier module. In the present invention, the reference circuit is included in the entire LDO loop, and there is no need to design a separate reference circuit. This can prevent the reference from being directly affected by external circuit interference and affecting the voltage output, and has better noise characteristics in medium and low frequencies.

Description

Technical Field

[0001] The present invention relates to the field of power supply circuits, and in particular to a reference-free low-noise LDO circuit. Background Art

[0002] The LDO circuit, or Low Dropout Regulator, is a power management circuit used to stabilize voltage. Figure 1 and Figure 2 As shown, the current main architecture of LDO circuit is that PMOS device is used as power tube (such as Figure 1 ), one is to use NMOS as the power tube (such as Figure 2 Both of these mainstream LDO architectures consist of a reference voltage circuit, an error amplifier, a power transistor, and a feedback network. However, their reference voltage and the LDO's negative feedback loop are independent of each other. Interference or noise generated by the reference voltage cannot be suppressed by the loop, and the reference noise is directly transmitted to the output, potentially causing significant noise. Summary of the Invention

[0003] The purpose of the present invention is to provide a reference-free low-noise LDO circuit, which aims to overcome the problem in the prior art that interference generated by the reference or noise cannot be suppressed by the loop, and the reference noise will be directly transmitted to the output, which may cause relatively large noise.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A reference-free low-noise LDO circuit includes a voltage input terminal Vbat, an error amplifier module, a voltage output terminal Vout, a power transistor MP_power, a resistor R1, and a resistor R4; one end of the power transistor MP_power is connected to the voltage input terminal Vbat, and a control end is connected to the output end of the error amplifier module; the other end of the power transistor MP_power is connected to the voltage output terminal Vout; the voltage output terminal Vout is grounded via resistors R1 and R4, and further includes a resistor R2, a transistor Q5, and a resistor R3; the connection node between resistors R1 and R4 is grounded via resistor R2, transistor Q5, and resistor R3 in sequence, and the control end of transistor Q5 is connected to the connection node between resistors R2 and Q5;

[0006] Also includes transistor MP7, transistor MP11, transistor Q4, transistor MP8, transistor MP9, transistor MN6, transistor MN7, transistor MP6, transistor Q3, transistor MP10, transistor MP5 and transistor MN5;

[0007] The voltage output terminal Vout is connected to ground via transistor MP7, transistor Q4, and transistor MP11, then to ground via transistor MP8 and transistor MP9, then to ground via transistor MN6 and transistor MN7, then to ground via transistor MP6, transistor Q3, and transistor MP10, then to ground via transistor MP5 and transistor MN5.

[0008] The control terminals of the transistors MP7, MP8, MP6, and MP5 are all connected to the connection node between the transistors MP5 and MN5; the control terminals of the transistors Q3 and Q4 are all connected to the connection node between the transistors MP8 and MP9; the control terminal of the transistor MP11 is connected to the connection node between the transistor Q5 and the resistor R3; the control terminal of the transistor MP9 is connected to the connection node between the transistors MN6 and MN7; the control terminal of the transistor MN6 is connected to the connection node between the transistors MP6 and Q3; and the control terminal of the transistor MP10 is grounded via a resistor.

[0009] The error amplifier module has a voltage input terminal n1 connected to the connection node between transistor MP6 and transistor Q3, a voltage input terminal n2 connected to the connection node between transistor MP7 and transistor Q4, a connection terminal ibias connected to the control terminals of transistors MN7 and MN5, and an output terminal connected to the control terminal of power transistor MP_power.

[0010] Furthermore, the invention also includes a capacitor CL, and the voltage output terminal Vout is grounded after passing through the capacitor CL;

[0011] Furthermore, a capacitor C is included, and the voltage output terminal Vout is connected to a connection node between the transistor MP7 and the transistor Q4 via the capacitor C.

[0012] Furthermore, a resistor R0 is included, and the control end of the power tube MP_power is connected to a connection node between the power tube MP_power and the voltage input end Vbat via the resistor R0.

[0013] Furthermore, the transistor Q3 , the transistor Q4 , and the transistor Q5 are all NPN transistors, and the size ratio of the transistor Q4 to the transistor Q3 is N:1.

[0014] Furthermore, the transistor MP10 and the transistor MP11 are both PMOS transistors.

[0015] Furthermore, the transistor MN6 and the transistor MN7 are both NMOS transistors, and the transistor MP9 is a PMOS transistor.

[0016] Furthermore, a bias current module is included, wherein the input end of the bias current module is connected to the voltage output end Vout, and the output end of the bias current module is connected to the connection end ibias of the error amplifier module.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] In the LDO circuit disclosed in the present invention, the reference circuit is included in the entire LDO loop, eliminating the need to design a separate reference circuit. This can prevent the reference from being directly affected by external circuit interference and affecting the voltage output of the LDO circuit, and can achieve better noise characteristics at medium and low frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is an existing LDO circuit.

[0020] Figure 2 This is another existing LDO circuit.

[0021] Figure 3 Schematic diagram of the circuit of the present invention.

[0022] Figure 4 This is the circuit schematic diagram of the bias current module.

[0023] Figure 5 This is a partial circuit diagram of the voltage output terminal in the present invention.

[0024] Figure 6 This is the small signal model of a part of the circuit in the present invention.

[0025] Figure 7 In the present invention, Figure 6 Bode plot of the small-signal model shown.

[0026] Figure 8 This is a Bode diagram for a zero and pole design scheme in the present invention.

[0027] Figure 9 This is a Bode diagram for another zero and pole design scheme in the present invention. DETAILED DESCRIPTION

[0028] The specific embodiments of the present invention are described below with reference to the accompanying drawings. In order to fully understand the present invention, many details are described below, but for those skilled in the art, the present invention can be implemented without these details.

[0029] like Figure 3 and Figure 4As shown, a reference-less low-noise LDO circuit includes a voltage input terminal Vbat, an error amplifier module, a voltage output terminal Vout, a power transistor MP_power, resistors R1 and R4. One end of the power transistor MP_power is connected to the voltage input terminal Vbat for connection to the power supply VDD. The control terminal of the power transistor MP_power is connected to the output terminal of the error amplifier module, and the other end of the power transistor MP_power is connected to the voltage output terminal Vout for connection to a load. The voltage output terminal Vout is grounded after passing through resistors R1 and R4.

[0030] The power transistor MP_power includes, but is not limited to, an NMOS transistor. Preferably, the control terminal of the power transistor MP_power is connected to the connection node between the power transistor MP_power and the voltage input terminal Vbat via a resistor R0. Resistor R0 can reduce the impedance at the control terminal of the power transistor MP_power, thereby preventing loop instability caused by a too low control terminal of the power transistor MP_power.

[0031] like Figure 3 As shown, the LDO circuit also includes resistor R2, transistor Q5, and resistor R3. The connection node between resistors R1 and R4 is connected to ground via resistor R2, transistor Q5, and resistor R3, respectively. The control terminal of transistor Q5 is connected to the connection node between resistors R2 and Q5. Resistors R1, R4, R2, and R3 form a temperature coefficient and feedback coefficient adjustment network.

[0032] Preferably, the voltage output terminal Vout is grounded after passing through a capacitor CL. Adding a capacitor CL to the load end of the LDO circuit provides a low-frequency pole for the output, thereby improving the stability of the entire loop.

[0033] like Figure 3 As shown, the LDO circuit further includes a transistor MP7, a transistor MP11, a transistor Q4, a transistor MP8, a transistor MP9, a transistor MN6, a transistor MN7, a transistor MP6, a transistor Q3, a transistor MP10, a transistor MP5 and a transistor MN5;

[0034] The voltage output terminal Vout is connected to ground via transistors MP7, Q4, and MP11, then to ground via transistors MP8 and MP9, then to ground via transistors MN6 and MN7, then to ground via transistors MP6, Q3, and MP10, then to ground via transistors MP5 and MN5. Furthermore, the control terminals of transistors MP7, MP8, MP6, and MP5 are all connected to the connection node between transistors MP5 and MN5. The control terminals of transistors Q3 and Q4 are all connected to the connection node between transistors MP8 and MP9. The control terminal of transistor MP11 is connected to the connection node between transistor Q5 and resistor R3. The control terminal of transistor MP9 is connected to the connection node between transistors MN6 and MN7. The control terminal of transistor MN6 is connected to the connection node between transistors MP6 and Q3. The control terminal of transistor MP10 is connected to ground via a resistor.

[0035] Preferably, transistors Q3, Q4, and Q5 are all NPN transistors, and the size ratio of transistor Q4 to transistor Q3 is N:1. These three devices need to be matched during layout drawing. Transistors Q3 and Q5 can be configured as a single device, while the number N of transistors Q4 can be 7, 14, 23, etc. In this way, the three devices can be formed into a square during layout drawing, achieving a better match.

[0036] Preferably, the transistors MP10 , MP11 and MP9 are all PMOS transistors, and the transistors MN6 and MN7 are all NMOS transistors.

[0037] Transistors MN6, MN7, and MP9 provide internal negative feedback for transistor Q3, creating appropriate base potentials for both Q3 and Q4. Transistor Q3's ground terminal (collector) is not directly connected to its control terminal (base) because the current gain β of an NPN transistor in a typical CMOS process is small, resulting in a large base current. This ultimately leads to a significant deviation in the collector currents of transistors Q3 and Q4, deteriorating the temperature characteristics of the LDO circuit.

[0038] like Figure 3 As shown, the voltage input terminal n1 of the error amplifier module is connected to the connection node between transistor MP6 and transistor Q3. The voltage input terminal n2 of the error amplifier module is connected to the connection node between transistor MP7 and transistor Q4. The connection terminal ibias of the error amplifier module is also connected to the control terminals of transistors MN7 and MN5, and the output terminal is connected to the control terminal of power transistor MP_power.

[0039] Preferably, the voltage output terminal Vout is connected to the connection node between the transistor MP7 and the transistor Q4 via a capacitor C. That is, the capacitor C is added between the voltage output terminal Vout and the voltage input terminal n2 and is an internal component of the LDO circuit. The capacitor C provides a zero point for the loop to improve the stability of the loop.

[0040] like Figure 3 As shown, the error amplifier module specifically includes transistors MP1, MP2, MP3, MP4, MN3, MN4, MN11, MN12, MN1, and MN2. Transistor MP4 is connected in series with transistor MN4, and transistor MP3 is connected in series with transistor MN3. Then, transistors MP4 and MP3 are both connected to the voltage output terminal Vout. Transistor MN4 and transistor MN3 are both connected to one end of transistor MN2, and the other end of transistor MN2 is grounded. The control end of transistor MP4 is connected to the connection node between it and transistor MN4, the control end of transistor MP3 is connected to the connection node between it and transistor MN3, the control end of transistor MN4 is the voltage input terminal n2 of the error amplifier module, the control end of transistor MN3 is the voltage input terminal n1 of the error amplifier module, the control end of transistor MN2 is connected to the control end of transistor MN1, and the control end of transistor MN2 is connected to one end of it. The other end of transistor MN2 is grounded. The control terminal of transistor MN1 is connected to the connection terminal ibias, generating a bias voltage. The bias voltage is applied to transistor MN2, causing transistor MN2 to generate a bias current, thereby providing a bias for the error amplifier. Transistors MP2 and MN12 are connected in series between the voltage output terminal Vout and the ground line GND. The control terminal of transistor MP2 is connected to the control terminal of transistor MP3, and the control terminal of transistor MN12 is connected to the connection node between it and transistor MP2. Transistor MP1 and transistor MN11 are connected in series between the voltage input terminal Vbat and the ground line GND. The control terminal of transistor MP1 is connected to the connection node between it and transistor MN11, and is also connected to the control terminal of power transistor MP_power, which serves as the output terminal of the error amplifier. The control terminal of transistor MN11 is connected to the control terminal of transistor MN12.

[0041] like Figure 3 and Figure 4 As shown, the LDO circuit also includes a bias current module, the input end of the bias current module (i.e. Figure 4In the embodiment, the connection node of resistor R1, transistor M2, and transistor M4 is connected to the voltage output terminal Vout, and the output terminal is connected to the connection terminal ibias of the error amplifier module. Therefore, the bias current module uses the voltage output terminal Vout of the LDO as its power source. The circuit structure and principle of the bias current module are relatively simple and will not be described in detail here.

[0042] like Figure 4 As shown, the bias current module specifically includes a resistor R1, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, and a transistor M7. Resistor R1, transistor M1, and transistor M6 are connected in series between the input end of the bias current module and the ground line. Transistors M2, M3, and M7 are also connected in series. The control end of transistor M1 is connected to the control end of transistor M3 and to the connection node between transistors M3 and M7; the control end of transistor M2 is connected to the connection node between resistor R17 and transistor M1; and the control end of transistor M6 is connected to the control end of transistor M7 and to the connection node between transistors M1 and M6. The input end of the bias current module is connected in series with transistors M4 and M5, forming the output end of the bias current module. The control end of transistor M4 is connected to the control end of transistor M2, and the control end of transistor M5 is connected to the connection node between transistors M3 and M7.

[0043] like Figure 3 As shown in the figure, analyzing the entire LDO circuit loop reveals that the feedback introduced by the entire LDO circuit is positive feedback. This is because the equivalent resistance of the LDO circuit as seen from the voltage output terminal Vout and the ground terminal GND is a negative resistance. If the device size of transistor MP2 is large enough and the voltage output terminal Vout increases, the current of transistor MP2 drops rapidly, resulting in the output voltage and current of the LDO circuit at the voltage output terminal Vout being in an anti-phase relationship under small signal conditions. The size of this negative resistance is inversely proportional to the amplification factor of the error amplifier. In other words, the greater the amplification factor of the error amplifier, the smaller the resistance.

[0044] like Figure 3 As shown, the working process of the entire circuit is analyzed below.

[0045] In normal operation, the voltages at voltage input terminals n1 and n2 are essentially the same. The exact difference depends on the overall loop gain. For simplicity, assume that voltage input terminals n1 and n2 are identical, and that the currents (i.e., collector currents) flowing through transistors Q3 and Q4 are identical.

[0046] In normal operation of this LDO circuit, on the one hand, since transistors MP10 and MP11 operate in the saturation region and have the same device size, theoretically, transistors MP10 and MP11 flow the same current and have the same VGS voltage. On the other hand, due to the different sizes of transistors Q3 and Q4, the potential difference between the top terminals (i.e., source terminals) of transistors MP10 and MP11 is ΔVBE (i.e., the difference between the forward bias voltage of transistors MP10 and MP11). Since the control terminal (i.e., gate terminal) of transistor MP10 has a potential of 0, in order to keep the VGS voltages of transistors MP10 and MP11 consistent, the potential of the control terminal (i.e., gate terminal) of transistor MP11 should be ΔV BE .

[0047] The voltage expression of the voltage output terminal Vout is derived below:

[0048] like Figure 5 As shown, according to Ampere's law of resistance, the following expression is obtained:

[0049] The partial current flowing through resistor R3 is:

[0050] The partial current flowing through resistor R4 is:

[0051] Total current:

[0052] The voltage at the voltage output terminal Vout:

[0053] Finally, we get:

[0054]

[0055] Among them, V BE The forward bias voltage of transistor MP11, R1, R2, R 3、 R1, R2, R3, and R4 are the impedances of resistors R1, R2, R3, and R4 respectively. BE is the control terminal (gate terminal) potential of transistor MP11, By setting the appropriate resistance value in this part, a voltage with zero temperature coefficient can be obtained. This part will be explained in detail later and will not be repeated here. When the ratio of the resistors is set properly, a voltage of about 1.2V can be obtained. This part can get an output above 1.2V. This is also a design limitation of this application. Only an LDO output with a voltage greater than 1.2V can be obtained.

[0056] When the output voltage fluctuates, the changes in the entire loop are as follows:

[0057] Assume that the output voltage at voltage output terminal Vout is disturbed and suddenly increases. The output voltage, through resistors R1-R4 and transistor Q5, increases the control terminal (gate) voltage of transistor MP11. At the same time, because the current flowing through transistor MP11 is constant and the voltage VGS remains constant, the increase in the control terminal voltage of transistor MP11 causes the voltage at the top terminal (source) of transistor MP11 to increase, which in turn increases the voltage at the bottom terminal (emitter) of transistor Q4. However, the control terminal (base) voltage of transistor Q4 remains unchanged. In this case, transistor Q4 is connected in a common-base amplifier circuit configuration. The increase in the bottom terminal (emitter) voltage of transistor Q4 causes the voltage at voltage input terminal n2 to increase, while the voltage at voltage input terminal n1 remains essentially unchanged. At this time, the current flowing through transistors MN4 and MP4 increases, causing the current of transistors MN3 and MP3 to decrease. However, the current of transistor MP2 is N times that of transistor MP3. As the current of transistor MP2 decreases, the current of transistor MN11 also decreases, causing the voltage of the control terminal (i.e., the gate) of transistor MP1 and power transistor MP_power to increase, thereby reducing the output current and the output voltage of voltage output terminal Vout. This is achieved until the current of power transistor MP_power just meets the voltage of the node at voltage input terminal n1 and voltage input terminal n2, achieving output voltage stability. When the output voltage of voltage output terminal Vout is suddenly reduced due to interference, the entire process is exactly the opposite of the above process, and the output voltage is finally stabilized to the preset voltage.

[0058] like Figure 3 As shown, disconnect the control terminal (gate) of the power tube MP_power and analyze the loop from the control terminal:

[0059] A large capacitor, CL, connected in parallel with the voltage output terminal Vout creates a relatively low-frequency pole, Pole 1. Since the output resistance is negative, Pole 1 is a right-half-plane pole. As the load resistance decreases, the frequency of Pole 1 decreases (this differs from traditional LDO circuits, where the frequency increases as the load RL decreases). A large parasitic capacitor exists at the control terminal (gate) of transistor MP_power, creating a relatively low-frequency pole, Pole 2, a left-half-plane pole. Both Pole 1 and Pole 2 have relatively low frequencies. If the two pole frequencies are close, the phase is a positive value slightly greater than 0° at low frequencies, increasing with frequency (not exceeding 90°). As the frequency of Pole 2 approaches, the phase begins to decrease. When the phase drops to 0°, if the gain is greater than 1, the loop will be unstable. Especially when the load increases, the gm value of the power tube MP_power will increase, and the equivalent resistance of the output resistor will also increase, the overall loop gain will increase, and the stability will deteriorate. Therefore, when the phase curve passes through zero, it is very likely that the loop gain is still greater than 1, resulting in loop instability. Therefore, a capacitor, namely capacitor C, is added between the voltage input terminal n2 and the voltage output terminal Vout. Capacitor C introduces a zero-pole pair and draws the small signal model of this part of the circuit, which is as follows: Figure 6 shown.

[0060] like Figure 6 and Figure 7 As shown, write the KCL equation in Vo column as follows:

[0061] ;

[0062] ;

[0063] in, is the impedance of capacitor C; is the transconductance of the power tube MP_power;

[0064] The solution is: ;

[0065] Depend on , the frequency of the zero point is:

[0066] Depend on , the frequency of the pole is:

[0067] The zeros and poles here are opposite to the actual situation, because the negative resistance of the equivalent resistance is inversely proportional to Vo / Vi, while the gain of the entire loop is proportional to the negative resistance, so the zeros and poles are opposite. In other words, the frequency of the actual zero point of the loop is: ;The frequency of the actual loop pole is: .

[0068] Through observation, we find that the frequency of the zero point is much smaller than the frequency of the pole. Therefore, the frequency of the pole can be designed to be very high (outside the unity gain bandwidth UGB, no need to consider), and the frequency of the zero point can be designed to be relatively low. In this way, we can get something like Figure 7 The Bode plot is shown below.

[0069] In the Bode plot, sp1 represents the frequency of Pole 1 at the voltage output terminal Vout. Pole 1 is a right-half-plane pole, and its frequency, sp1, barely changes with load changes. When Pole 1 is encountered, the loop gain begins to decrease at a rate of 20dB / dec, while the phase increases.

[0070] sp2 represents the frequency of pole 2 at the control terminal (i.e., gate terminal) of transistor MP_power. Pole 2, sp2, is a left-half-plane pole. Pole 2's frequency, sp2, increases with increasing load current. This deteriorates circuit stability because, when the frequency, sp2, is low, the gain decreases rapidly, reducing the unity-gain bandwidth (UGB). If the frequency, sp2, is too high, the rate of gain decreases, the frequency of the unity-gain bandwidth (UGB) increases, and the phase rises by nearly 90° after reaching the frequency, sp1, of pole 1 before dropping back to nearly 0° at the frequency, sp2, of pole 2. Therefore, at the frequency, sp2, of pole 2, the gain decreases at a rate of 40 dB / dec, and the phase also begins to decrease.

[0071] sz1 represents the frequency of the zero introduced by capacitor C. This zero is a left-half-plane zero, and the frequency of the zero, sz1, remains essentially unchanged. When encountering the zero frequency, sz1, the gain decreases at a rate of 20dB / dec, and the phase recovers.

[0072] After the frequency of the zero point sz1, the frequency of the unity gain bandwidth UGB is reached soon. The various high-frequency poles (such as sp3) or right half-plane zeros generated thereafter will cause a sharp drop in phase. After the gain of the loop is less than 0dB, as long as there is no gain rebound, that is, the gain is no longer greater than 0dB, the subsequent zeros and poles can be ignored.

[0073] Therefore, as long as the frequency of each zero and pole is designed reasonably and the phase margin is not less than the required value before the frequency of the unity gain bandwidth UGB, the entire circuit can work normally.

[0074] Through the above analysis, we further analyze the loop stability under the maximum load state. There are two schemes for the frequency design of zeros and poles.

[0075] like Figure 3 and Figure 8 As shown in the figure, design solution 1: the zero frequency sz1 is designed to be closer to the frequency sp1 of the pole 1. At this time, the frequency sp1 of the pole 1 and the zero frequency sz1 produce a phase shift of +180°. The subsequent design is similar to the design of a three-pole circuit. It is only necessary to design the frequency sp2 of the next pole 2 relatively low to stabilize the entire loop. The Bode plot of this solution is shown below. Figure 8 This design method is relatively simple, but it requires a very low frequency zero point, which requires the capacitor C to be designed to be large, resulting in a large area. In this case, if the phase margin is insufficient, it is only necessary to reduce the frequency of the second pole, sp2, so that the frequency of the second pole, sp2, is far away from other parasitic high-frequency poles to achieve loop stability.

[0076] like Figure 3 and Figure 9 As shown, if the frequency of the zero point sz1 is greater than the frequency of the pole two sp2, through Figure 9 The Bode plot shown clearly shows that the frequency sp1 of pole one can be designed to be higher than that of design scheme one, the required capacitance CL will be smaller, the capacitance C introduced into the zero point can also be designed to be smaller, and the frequency sp2 of pole two can also be designed to be relatively high. What is the specific relationship? The following analysis is made:

[0077] like Figure 3 and Figure 9 As shown, Design Scheme 2: This is a design of a multi-zero and multi-pole system, and the unity gain bandwidth UGB and the frequency of the pole two sp2 change with the load. The design is more flexible. Here is a reference scheme:

[0078] In the above analysis of zero and pole, the frequency of zero sz1 and the frequency of pole 1 sp1 can be flexibly adjusted. Now we first determine the frequency of zero and pole under heavy load conditions. Specifically, through simulation software, adjust the frequency of zero and pole from Figure 9The Bode plot shows that the frequency of the unity-gain bandwidth (UGB) is maximum when the load is maximum. Using simulation software, we first find the frequency of the high-frequency pole. Then, we can determine the frequency of the zero (sz1) based on the ratio of maximum to minimum load currents. The larger the ratio of maximum to minimum load currents, the smaller the frequency of the zero (sz1) is designed, moving it away from the high-frequency pole while remaining within the unity-gain bandwidth (UGB). For example, assuming the high-frequency pole is sp3, the frequency of the unity-gain bandwidth (UGB) is designed to be half the frequency of the high-frequency pole (sp3), and the frequency of the zero (sz1) is designed to be half the frequency of the unity-gain bandwidth (UGB). In this case, the phase shift introduced by the high-frequency pole is 26.5°, while the phase shift compensated by the zero is 63.43°. There is a right-half-plane pole (pole 1), a left-half-plane pole (pole 2), and a left-half-plane zero before the unity-gain bandwidth (UGB). The entire system is stable. The frequency of the unity-gain bandwidth (UGB) can be adjusted by adjusting the load capacitor value. For convenience, the capacitor CL can be directly set as a variable using simulation software, and then a parameter scan can be performed to determine the appropriate value of the capacitor CL. At this time, the frequency sp1 of the pole one is also determined.

[0079] Once the frequency sp1 of pole one and the frequency sz1 of the zero are determined, verification under small load current conditions begins. Adjust the load to the required minimum value, simulate the stability of the loop, and obtain the phase margin value at this time. If the phase margin does not meet the design requirements, the frequency sz1 of the zero can be reduced, and then the circuit can be redesigned according to the previous steps. If it still does not meet the requirements, the frequency of the unit gain bandwidth UGB needs to be designed to be smaller. As mentioned above, the frequency of the unit gain bandwidth UGB is designed to be half of the high-frequency pole. If you want to improve the phase margin, you can continue to appropriately reduce the frequency of the unit gain bandwidth UGB to ensure better stability of the loop.

[0080] Because the entire system consists of multiple zeros and poles, quantitatively analyzing its stability is somewhat challenging. However, it can be seen that as long as the frequency of the unity-gain bandwidth (UGB) is designed to be sufficiently lower than the frequency of the high-frequency poles, the entire loop system is absolutely stable. This is because the phase shifts introduced by the first two poles (Pole 1 and Pole 2) essentially cancel each other out. Furthermore, the phase shift introduced by the preceding zero is greater than that introduced by the subsequent high-frequency poles. Therefore, at the frequency of the unity-gain bandwidth (UGB), the phase will not fall below the 0° boundary. Furthermore, to achieve even better phase margin and faster settling time, the ratio of the high-frequency poles and zeros within the unity-gain bandwidth (UGB) can be further optimized.

[0081] The voltage across resistor R3 is △VBE, which is a positive temperature coefficient voltage. This voltage causes the current flowing through resistors R3, R2 and transistor Q5 to be a positive temperature coefficient current, while the voltage across resistor R4 is the sum of the voltages across resistors R3, R2 and VBE. VBE is a negative temperature coefficient voltage. Although the voltages across resistors R2 and R3 have positive temperature coefficients, as long as the resistance values ​​are designed according to the ratio described above, the voltage across resistor R4 will eventually be a negative temperature coefficient voltage. This voltage will generate a negative temperature coefficient current. After adding the positive temperature coefficient current flowing through resistor R2 and the negative temperature coefficient current flowing through resistor R4, the ratio between resistors R1-R4 can be designed according to the previous method to obtain a positive temperature coefficient current. This current generates a positive temperature coefficient voltage across resistor R1, which cancels out the temperature coefficient of the negative temperature coefficient voltage across resistor R4, resulting in a negative temperature coefficient voltage at the voltage output terminal Vout. A reference voltage with a zero temperature coefficient is obtained, and the voltage output terminal Vout is the output of the LDO circuit. Therefore, Vout is both the reference voltage and the output voltage of the LDO.

[0082] Through the analysis of the entire circuit, we found that in this LDO circuit, the reference circuit is included in the entire LDO loop. There is no need to design a separate reference loop. This can prevent the reference from being directly affected by external circuit interference and affect the LDO output, and can obtain better noise characteristics at medium and low frequencies.

[0083] The above is only a specific implementation of the present invention, but the design concept of the present invention is not limited to this. Any non-substantial changes to the present invention using this concept shall be deemed as an infringement of the protection scope of the present invention.

Claims

1. A reference-less low-noise LDO circuit, comprising a voltage input terminal Vbat, an error amplifier module, a voltage output terminal Vout, a power transistor MP_power, resistors R1 and R4; one end of the power transistor MP_power is connected to the voltage input terminal Vbat, and a control end is connected to the output terminal of the error amplifier module; the other end of the power transistor MP_power is connected to the voltage output terminal Vout; the voltage output terminal Vout is grounded after passing through resistors R1 and R4, and is characterized in that: The device further comprises a resistor R2, a transistor Q5 and a resistor R3, wherein the connection node between the resistor R1 and the resistor R4 is connected to ground via the resistor R2, the transistor Q5 and the resistor R3 in sequence, and the control terminal of the transistor Q5 is connected to the connection node between the resistor R2 and the transistor Q5; Also includes transistor MP7, transistor MP11, transistor Q4, transistor MP8, transistor MP9, transistor MN6, transistor MN7, transistor MP6, transistor Q3, transistor MP10, transistor MP5 and transistor MN5; The voltage output terminal Vout is grounded after passing through transistors MP7, Q4, and MP11, then through transistors MP8 and MP9, then through transistors MN6 and MN7, then through transistors MP6, Q3, and MP10, then through transistors MP5 and MN5; The control terminals of transistors MP7, MP8, MP6, and MP5 are all connected to the connection node between transistor MP5 and transistor MN5; the control terminals of transistors Q3 and Q4 are all connected to the connection node between transistors MP8 and MP9; the control terminal of transistor MP11 is connected to the connection node between transistor Q5 and resistor R3; the control terminal of transistor MP9 is connected to the connection node between transistors MN6 and MN7; the control terminal of transistor MN6 is connected to the connection node between transistors MP6 and Q3; and the control terminal of transistor MP10 is grounded via a resistor. The voltage input terminal n1 of the error amplifier module is connected to the connection node of the transistor MP6 and the transistor Q3, the voltage input terminal n2 is connected to the connection node of the transistor MP7 and the transistor Q4, the connection terminal ibias is simultaneously connected to the control terminals of the transistor MN7 and the transistor MN5, and the output terminal is connected to the control terminal of the power transistor MP_power.

2. The reference-free low-noise LDO circuit according to claim 1, wherein: The capacitor CL is further included, and the voltage output terminal Vout is grounded after passing through the capacitor CL.

3. The reference-free low-noise LDO circuit according to claim 1, wherein: The device further includes a capacitor C, and the voltage output terminal Vout is connected to a connection node between the transistor MP7 and the transistor Q4 via the capacitor C.

4. The reference-free low-noise LDO circuit according to claim 1, wherein: The device further includes a resistor R0 , and the control end of the power tube MP_power is connected to a connection node between the power tube MP_power and the voltage input end Vbat via the resistor R0 .

5. The reference-free low-noise LDO circuit according to any one of claims 1 to 4, wherein: The transistor Q3 , the transistor Q4 , and the transistor Q5 are all NPN-type triodes, and the size ratio of the transistor Q4 to the transistor Q3 is N:

1.

6. The reference-free low-noise LDO circuit according to claim 5, wherein: The transistor MP10 and the transistor MP11 are both PMOS transistors.

7. The reference-free low-noise LDO circuit according to claim 5, wherein: The transistors MN6 and MN7 are both NMOS transistors, and the transistor MP9 is a PMOS transistor.

8. The reference-free low-noise LDO circuit according to any one of claims 1 to 4, wherein: The system further comprises a bias current module, wherein the input end of the bias current module is connected to the voltage output end Vout, and the output end of the bias current module is connected to the connection end ibias of the error amplifier module.

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