Transient enhancement circuit for suppressing overshoot and undershoot applied to LDO

Abstract

The application belongs to the field of integrated circuit power chip design, and particularly relates to a transient enhancement circuit for suppressing overshoot and undershoot of LDO, which is composed of a band gap reference circuit, an error amplifier, a power tube PMOS tube MP1, a second-stage amplification tube NMOS tube MN1, a resistor R4, a load resistor R L , an in-chip load capacitor C L , an adaptive zero module composed of a resistor R3, a capacitor C1 and an NMOS tube MN2, a feedback network of LDO composed of a resistor R1 and a resistor R2, and a module for suppressing overshoot and undershoot of output voltage. The application realizes effective suppression of overshoot and undershoot generated when the load is suddenly changed, shortens the recovery time of overshoot and undershoot voltage, and the overshoot suppression circuit only generates a small amount of static current consumption, and the undershoot suppression circuit does not generate additional static consumption under the whole LDO working state due to the effect of the capacitor.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuit power chip design, and particularly relates to a transient enhancement circuit for suppressing overshoot and undershoot of LDO. BACKGROUND

[0002] In the selection of power chips, a low dropout regulator (LDO) is widely used due to its simple structure, low ripple, small EMI noise and other advantages. In order to facilitate integration, a no-capacitor LDO emerges as the times require, and its output capacitor is usually within 1 pF to 200 pF, which is more easily integrated into the chip, and thus becomes a research hotspot. However, the no-capacitor LDO has poor transient response due to the reduction of the output capacitor, and thus enhancing the transient response becomes a factor that must be considered.

[0003] The transient response refers to the maximum output voltage change allowed when the load current changes in steps, which reflects the response speed and stability of the LDO circuit to the load current change. In modern electronic systems, the load current change is normal, and if the transient response characteristic of the LDO circuit is poor, a large output voltage fluctuation (i.e. overshoot or undershoot) may occur when the load changes, thereby affecting the performance and stability of the entire electronic system. Therefore, good transient response characteristic is one of the important performance indicators of the LDO circuit. The design goal of the transient enhancement circuit mainly focuses on improving the response speed and stability of the circuit to the load change, and reducing the fluctuation of the output voltage, so that the LDO circuit has good transient response.

[0004] Figure 1 A schematic diagram of a traditional transient enhancement circuit is shown in FIG. 1. The transient enhancement circuit is composed of an error amplifier EA, a buffer Buffer, a slew rate enhancement module SER, a power PMOS transistor M P , a resistor feedback network R1, R2, an output capacitor C OUT , a load resistor R L , an on-chip load capacitor C L , and a power transistor gate capacitor C P , wherein V FB is the output voltage of the resistor feedback network, V REF is the bandgap reference output voltage. Due to the negative feedback, the feedback voltage V FB will eventually stabilize at the reference voltage V REF , that is, the LDO output voltage V OUT will eventually stabilize at formula (1).

[0005]

[0006] Figure 2 This is a specific circuit diagram of a traditional transient enhancement circuit. M1 to M11 form the error amplifier EA, M12 and M13 form the buffer, M14 to M18 form the slew rate enhancement module SER, M19 is the power transistor, resistors R1 and R2 form the feedback network, RL is the load resistor, COUT is the output capacitor, CC is the compensation capacitor, and Vb1 to Vb5 are the bias voltages.

[0007] Overshoot analysis: When an LDO transitions from a heavy load to a light load, i.e., the load current decreases, the output voltage V... OUT The voltage rises, and this rise is fed back to the error amplifier EA through the feedback network, causing the error amplifier's output voltage to rise. This rise is then transmitted through the buffer and the power transistor M. P The gate-source voltage decreases, thereby reducing the output current and the output capacitor C. OUT Discharge reduces the output voltage. Due to the negative feedback, the feedback voltage VFB will eventually stabilize at the reference voltage VREF, that is, the LDO output voltage will stabilize at formula (1).

[0008] Undershoot suppression analysis: When the LDO changes from light load to heavy load, i.e., the load current increases, the output voltage V... OUT The voltage drop is fed back to the error amplifier EA through the feedback network, causing the output voltage of the error amplifier to drop. This drop is then transmitted through the buffer and the power transistor M. P The gate-source voltage increases, thereby increasing the output current's impact on the output capacitor C. OUT Charging is performed to increase the output voltage. Meanwhile, as... Figure 3 The decrease in the output voltage of the error amplifier will simultaneously increase the transient current I of the transient enhancement module. boost That is, the gate voltage of transistor M18 will decrease as the source voltage of transistor M12 decreases, and the current I flowing through M14 is determined by the current mirrors M14 to M17. boost The increase in voltage leads to a decrease in the current flowing through transistor M12, further lowering the source voltage of transistor M12, which in turn lowers the gate voltage of power transistor M19. P As the gate-source voltage increases further, the output current also increases further, accelerating the degradation of the output capacitor C. OUT Charging is performed to raise the output voltage, enhance the transient response of the LDO, and suppress the undershoot of the output voltage. Similarly, due to the negative feedback and undershoot suppression, the output voltage will eventually stabilize at the formula (1).

[0009] As can be seen, the introduction of the transient boost module increases the current consumption, the LDO quiescent current increases, and the static consumption of the circuit increases. In addition, the traditional transient boost circuit can only reduce the output voltage undershoot and shorten the recovery time when the load current suddenly increases, but it has no effect on the output voltage overshoot caused by the sudden decrease of the load current.

[0010] In summary, traditional transient boosting circuits increase the overall quiescent current of the LDO circuit by introducing excess current, thereby increasing circuit power consumption. Transient boosting modules can only reduce the output voltage undershoot and shorten the recovery time when the load current suddenly increases, but cannot improve the output voltage overshoot caused by the sudden decrease in load current. Summary of the Invention

[0011] To address the aforementioned technical problems, this invention provides a transient enhancement circuit for suppressing overshoot and undershoot in an LDO, comprising: a bandgap reference circuit BG, an error amplifier EA, a power PMOS transistor MP1, amplifier NMOS transistors MN1 and MN2, resistors R1-4, and a load resistor R. L On-chip load capacitor C L Capacitor C1, undershoot suppression module Reduce Undershoot and overshoot suppression module Reduce Overshoot;

[0012] The bandgap reference circuit BG is connected to the positive input of the error amplifier EA to provide a reference voltage VREF, and its inverting input is connected to the feedback voltage VFB.

[0013] The output terminal of the error amplifier EA is connected to one end of the resistor R3 and the gates of the second-stage amplifier transistors NMOS transistors MN1 and MN2;

[0014] The other end of the resistor R3 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the drain of the NMOS transistor MN2.

[0015] The source of the amplifying transistor NMOS transistor MN2 is grounded;

[0016] The source of the second-stage amplifier transistor NMOS transistor MN1 is grounded, and its drain is connected to one end of the resistor R4 and the gate of the power transistor PMOS transistor MP1.

[0017] The other end of the resistor R4 serves as the input terminal of the overall circuit and is connected to the source of the power transistor PMOS MP1.

[0018] The drain of the power transistor PMOS transistor MP1 serves as the output terminal of the overall circuit and is connected to the load resistor R. L One end, on-chip load capacitor C LOne end of the resistor R1, one end of the resistor R1, the input of the Reduce Undershoot module, and the output of the Reduce Overshoot module;

[0019] The load resistor R L The other end is grounded and connected to the on-chip load capacitor C. L The other end, one end of resistor R2;

[0020] The other end of R1 is connected to the other end of the resistor R2 and the input terminal of the overshoot suppression module ReduceOvershoot, and outputs a feedback voltage VFB.

[0021] The output of the Reduce Undershoot module is connected to the error amplifier EA.

[0022] The beneficial effects of this invention are:

[0023] This invention provides a transient enhancement circuit for suppressing overshoot and undershoot in LDOs. The circuit effectively suppresses overshoot and undershoot caused by load changes and shortens the recovery time of overshoot and undershoot voltages through overshoot suppression circuit and undershoot suppression circuit. The overshoot suppression circuit generates only a small amount of static current consumption, and the undershoot suppression circuit does not generate any additional static current consumption throughout the entire LDO operating state due to the effect of the capacitor.

[0024] This invention can effectively reduce the overshoot and undershoot of the output voltage when the load current jumps, and significantly shorten the voltage settling time, thus ensuring the fast transient response of the LDO circuit.

[0025] This invention improves transient response by adding an undershoot suppression circuit that does not generate additional static power consumption, and an overshoot suppression circuit that generates only a small amount of static current. This solves the problem of excessive static power consumption in traditional transient enhancement circuits, reduces the static power consumption of the circuit, and improves the circuit efficiency.

[0026] Instruction manual illustrations

[0027] Figure 1 This is a schematic diagram of a traditional transient enhancement circuit.

[0028] Figure 2 This is a schematic diagram of a traditional transient enhancement circuit.

[0029] Figure 3 This is a schematic diagram of the circuit framework of the present invention;

[0030] Figure 4 The circuit schematic diagram for this invention is obtained;

[0031] Figure 5This is a simulation diagram of the load transient response of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] A transient enhancement circuit for suppressing overshoot and undershoot in an LDO includes: a bandgap reference circuit BG, an error amplifier EA, a power PMOS transistor MP1, amplifier NMOS transistors MN1 and MN2, resistors R1-4, and a load resistor R. L On-chip load capacitor C L Capacitor C1, undershoot suppression module Reduce Undershoot and overshoot suppression module Reduce Overshoot;

[0034] The bandgap reference circuit BG is connected to the positive input of the error amplifier EA to provide a reference voltage VREF, and its inverting input is connected to the feedback voltage VFB.

[0035] The output terminal of the error amplifier EA is connected to one end of the resistor R3 and the gates of the second-stage amplifier transistors NMOS transistors MN1 and MN2;

[0036] The other end of the resistor R3 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the drain of the NMOS transistor MN2.

[0037] The source of the amplifying transistor NMOS transistor MN2 is grounded;

[0038] The source of the second-stage amplifier transistor NMOS transistor MN1 is grounded, and its drain is connected to one end of the resistor R4 and the gate of the power transistor PMOS transistor MP1.

[0039] The other end of the resistor R4 serves as the input terminal of the overall circuit and is connected to the source of the power transistor PMOS MP1.

[0040] The drain of the power transistor PMOS transistor MP1 serves as the output terminal of the overall circuit and is connected to the load resistor R. L One end, on-chip load capacitor C L One end of the resistor R1, one end of the resistor R1, the input of the Reduce Undershoot module, and the output of the Reduce Overshoot module;

[0041] The load resistor R L The other end is grounded and connected to the on-chip load capacitor C. L The other end, one end of resistor R2;

[0042] The other end of R1 is connected to the other end of the resistor R2 and the input terminal of the overshoot suppression module ReduceOvershoot, and outputs a feedback voltage VFB.

[0043] The output of the Reduce Undershoot module is connected to the error amplifier EA.

[0044] A block diagram of a transient enhancement circuit for suppressing overshoot and undershoot in an LDO is shown below. Figure 3 As shown, the circuit consists of a bandgap reference circuit BG, an error amplifier EA, a power PMOS transistor MP1, a second-stage amplifier NMOS transistor MN1, a resistor R4 providing bias current to MN1, and a load resistor R. L On-chip load capacitor C L The system consists of an adaptive zero-point module composed of resistor R3, capacitor C1, and NMOS transistor MN2; a feedback network for the LDO composed of resistors R1 and R2; and modules ReduceOvershoot and ReduceUndershoot to suppress output voltage overshoot and undershoot, respectively. EA_OUT is the output voltage of the error amplifier EA. A bandgap reference circuit BG provides a reference voltage VREF to the error amplifier EA, which is compared with the feedback voltage VFB generated by the feedback network to generate a voltage signal EA_OUT. This voltage signal controls the gate voltage of transistor MN1, thereby generating current flowing through resistor R4 to control the gate voltage signal of power transistor MP1. This allows the feedback network to sense output voltage fluctuations, which are then stabilized by the error amplifier and power transistor. The ReduceOvershoot module senses the feedback voltage VFB generated by the feedback network and sends a signal to the LDO output to suppress overshoot; the ReduceUndershoot module senses the LDO output voltage OUT and sends a signal to the error amplifier EA module to suppress undershoot. When a light load suddenly changes to a heavy load, i.e. a sudden increase in load current causes an undershoot in the output voltage, the undershoot suppression module Reduce Undershoot is activated to slow down the undershoot and shorten the recovery time. When a heavy load suddenly changes to a light load, i.e. a sudden decrease in load current causes an overshoot in the output voltage, the overshoot suppression module Reduce Overshoot is activated to slow down the overshoot and shorten the recovery time.

[0045] The schematic diagram of the transient enhancement circuit for suppressing overshoot and undershoot in LDO designed in this invention is shown below. Figure 4As shown, resistors R5 and R6 and capacitor C2 constitute the undershoot suppression circuit module; NMOS transistors MN9 to MN11, and PMOS transistors MP6 and MP7, due to the width-to-length ratio (W / L) of PMOS transistors MP6 and MP7. MP6 (W / L) MP7 =n:2 (n≥4) The equivalent offset voltage Vos, resistor R4, and fixed bias current I1 constitute the overshoot suppression circuit module; NMOS transistors MN3 and MN4, PMOS transistors MP4 and MP5, and fixed bias current I2 form the first stage of error amplifier EA; PMOS transistors MP2 and MP3 and NMOS transistors MN5 to MN8 forming the current mirrors of MP4 and MP5 constitute the second stage of error amplifier; EA_OUT is the output voltage of error amplifier.

[0046] Overshoot suppression analysis: When the load changes abruptly from heavy load to light load, i.e. the load current drops suddenly and the output voltage rises suddenly, since the circuit loop response takes a certain amount of time, a voltage overshoot will occur at this time, and the feedback voltage VFB will also rise accordingly, i.e. the source-gate voltage of PMOS transistor MP6 decreases, resulting in a decrease in the leakage current of MP6. The current is replicated through current mirrors MN9 and MN10. At this time, the leakage current of PMOS transistor MP7 is greater than the leakage current of MP6, i.e. the current flowing through MN10, which raises the drain voltage of MP7, i.e. the gate voltage of MN11 is raised, MN11 is turned on, and the output voltage VOUT is pulled down. Finally, due to the effect of negative feedback and overshoot suppression, the output voltage will stabilize at the value shown in equation (1), achieving the effect of slowing down the output overshoot, shortening the overshoot recovery time, and enhancing the transient response of the circuit.

[0047] When the load remains constant in a steady state, due to the width-to-length ratio (W / L) of PMOS transistors MP6 and MP7... MP6 (W / L) MP7 =n:2 (n≥4) will introduce an equivalent offset voltage Vos, ensuring that when the overshoot suppression circuit is not working, i.e., there is no sudden change in load, the drain current of the MOSFET is proportional to the width-to-length ratio, and the drain current of the MP6 transistor is I. D6 Greater than the drain current I of MP7 transistor D7 At this time, the leakage current of MP6 is always greater than the leakage current of MP7 after the effect of the current mirror, ensuring that the leakage voltage of MN10, i.e. the gate voltage of MN11, is at a low potential. At this time, the gate-source voltage of MN11 is less than the threshold voltage, and MN11 is turned off. That is, no current flows through MN11 at this time, the overshoot suppression circuit does not work and only generates a static current of 100nA. In other words, the overshoot suppression circuit only generates a small amount of static current.

[0048] Based on the above analysis, when I D7 ≥I D6The time comparator flips, turning on transistor MN11 and thus activating the overshoot suppression circuit. The flip point, I, will be analyzed next. D7 =I D6 At this time, since the comparator is provided with a static current by a fixed bias current source I1, i.e., I D7 +I D6 =I1, so at this time both MP6 and MP7 are working in the saturation region and the current is I1 / 2. According to the formula (2) for the drain current of the MOSFET when it is in the saturation region, we can get I at the switching point. D7 and I D6 The respective current values ​​are expressed as equation (3), where it is assumed that MP6 and MP7 are identical except for the width-to-length ratio of n:2.

[0049]

[0050] Where, μ p Where is the electron mobility of the PMOS transistor, and Cox is the gate oxide capacitance per unit area. The aspect ratio of the MP6 tube. V7 is the width-to-length ratio of the MP7 transistor, VA is the source voltage of the MP6 and MP7 transistors, and VTH is the threshold voltage of the PMOS transistors MP6 and MP7.

[0051] From equation (3) I D7 The source voltage V of MP7 at the flip point can be obtained from the current expression. A Equation (4):

[0052]

[0053] According to equation (3), I D6 The current expression and the source voltage V in equation (4) A The expression can be used to obtain the MP6 gate voltage, i.e., the feedback voltage V, at the flip point. FB The voltage value is given by equation (5), that is, when an overshoot occurs, the voltage V increases with the output voltage V. OUT The rise of the feedback voltage V FB When the value rises to the value of equation (5), the comparator flips and turns on the MN11 transistor, thereby activating the overshoot suppression circuit.

[0054]

[0055] Therefore, the width-to-length ratio (W / L) of PMOS transistors MP6 and MP7 can be determined. MP6 (W / L) MP7 The values ​​of n in the expression = n:2 (n≥4) are discussed below:

[0056] (1) n should not be too small. If n is too small, the width-to-length ratio n:2 will be close to 1:1. According to equation (5), VFB is equal to VREF at the inversion point. At this time, due to the system imbalance of the circuit, the MN11 transistor is easily turned on by accident when the LDO circuit is stable, which will cause the overshoot suppression module to be turned on in advance. When overshoot occurs, the module will not play the role of suppressing overshoot. In addition, the turn-on of the MN11 transistor will introduce an extra static current I. D11 As shown in equation (6), the static cost of the LDO is increased;

[0057]

[0058] Where Ron is the on-resistance of the MN11 transistor when it is working normally.

[0059] (2) n should not be too large. If n is too large, as shown in equation (5), as n increases, the value of VFB required for the overshoot suppression module to be turned on will increase, that is, the overshoot voltage required for VOUT to be reached will increase, which will cause the overshoot suppression module to be triggered too late when overshoot occurs, and the overshoot suppression effect will be worse.

[0060] (3) In the width-to-length ratio n:2, the value of n is generally taken as an even number greater than 4, such as 4 or 6, in order to facilitate layout matching design.

[0061] Undershoot Suppression Analysis: When the load abruptly changes from light to heavy load, i.e., the load current suddenly increases and the output voltage suddenly decreases, a voltage undershoot occurs because the circuit loop response takes a certain amount of time. The feedback voltage VFB also decreases accordingly. We know that the error amplifier EA will first react to this feedback voltage. That is, the gate-source voltage of NMOS transistor MN3 decreases, the current flowing through MP4 decreases, and after being mirrored by the current mirror, it flows through NMOS transistor MN6. Similarly, the current in NMOS transistor MN4 flows through the PMOS transistor MP3 after passing through the current mirror. At this time, ID3 > ID6, so the output voltage VEA_OUT of the error amplifier EA is raised. Figure 3That is, the gate voltage of NMOS transistor MN1 is raised, thereby pulling down the gate voltage of power transistor MP1, increasing the output current to charge the output capacitor, and thus raising the output voltage. The undershoot suppression circuit adds resistors R5, R6 and capacitor C2 to the error amplifier EA. It can be seen that when the output voltage VOUT drops suddenly and generates an undershoot, since the voltage across capacitor C2 cannot change abruptly, in order to keep the voltage across C2 constant, the gate voltage of MN7 also generates an undershoot. At this time, the drain current of MN7 is further reduced, that is, after being replicated by the current mirror, the current flowing through NMOS transistor MN6 is further reduced. At this time, the output voltage of the error amplifier is further raised, that is, the output voltage can be raised better. Similarly, due to the negative feedback and overshoot suppression, the output voltage will be stabilized at the value shown in equation (1), achieving the effect of slowing down the output voltage undershoot, shortening the undershoot recovery time, and enhancing the transient response of the circuit. Similarly, it can be seen that due to the effect of the capacitor blocking DC and passing AC, the undershoot suppression circuit will not generate additional static DC current, that is, it will not generate additional static consumption.

[0062] pass Figure 5 The simulation results clearly show this phenomenon. When the load current jumps from 10mA to 200mA, the output voltage exhibits a significant undershoot, and when the load current jumps from 200mA to 10mA, the output voltage exhibits a significant overshoot. After adding the transient enhancement module designed in this invention, namely the overshoot suppression circuit and the undershoot suppression circuit, the undershoot is reduced by 90mV and the overshoot is reduced by 150mV. Furthermore, the undershoot settling time is shortened by 70µs and the overshoot settling time is shortened by 152µs. This effectively suppresses both overshoot and undershoot phenomena and significantly shortens the settling time, achieving the effect of enhancing the transient response of the circuit. Moreover, only the overshoot suppression circuit generates a small amount of static current, while the undershoot suppression circuit does not generate additional current consumption, thereby reducing static consumption and improving the efficiency of the circuit.

[0063] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A transient enhancement circuit for suppressing overshoot and undershoot in an LDO, characterized in that, This includes a bandgap reference circuit BG, an error amplifier EA, a power PMOS transistor MP1, amplifier NMOS transistors MN1 and MN2, resistors R1-R4, and a load resistor R. L On-chip load capacitor C L Capacitor C1, undershoot suppression module Reduce Undershoot and overshoot suppression module Reduce Overshoot; The bandgap reference circuit BG is connected to the positive input of the error amplifier EA to provide a reference voltage VREF, and its inverting input is connected to the feedback voltage VFB. The output terminal of the error amplifier EA is connected to one end of the resistor R3 and the gates of the second-stage amplifier transistors NMOS transistors MN1 and MN2; The other end of the resistor R3 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the drain of the NMOS transistor MN2. The source of the amplifying transistor NMOS transistor MN2 is grounded; The source of the second-stage amplifier transistor NMOS transistor MN1 is grounded, and its drain is connected to one end of the resistor R4 and the gate of the power transistor PMOS transistor MP1. The other end of the resistor R4 serves as the input terminal of the overall circuit and is connected to the source of the power transistor PMOS MP1. The drain of the power transistor PMOS transistor MP1 serves as the output terminal of the overall circuit and is connected to the load resistor R. L One end, on-chip load capacitor C L One end of the resistor R1, one end of the resistor R1, the input of the Reduce Undershoot module, and the output of the Reduce Overshoot module; The load resistor R L The other end is grounded and connected to the on-chip load capacitor C. L The other end, one end of resistor R2; The other end of resistor R1 is connected to the other end of resistor R2 and the input terminal of the overshoot suppression module ReduceOvershoot, and outputs a feedback voltage VFB. The output of the Reduce Undershoot module is connected to the error amplifier EA. The Reduce Overshoot module includes: NMOS transistors MN9 to MN11, PMOS transistors MP6 and MP7, equivalent offset voltage Vos, resistor R4, reference voltage VREF, and fixed bias current I1. The source terminals of PMOS transistors MP6 and MP7 are connected to a fixed bias current I1. The gate connection equivalent offset voltage Vos of PMOS transistor MP6; The drain of PMOS transistor MP6 is connected to the drain and gate of NMOS transistor MN9 and the gate of NMOS transistor MN10. The gate of PMOS transistor MP7 is connected to the reference voltage VREF, and its drain is connected to the drain of NMOS transistor MN10 and the gate of NMOS transistor MN11. The source of NMOS transistor MN9 is connected to the sources of NMOS transistors MN10 and MN11 and then grounded. The drain of NMOS transistor MN11 is connected to one end of resistor R4; The other end of resistor R4 is connected to the undershoot suppression module Reduce Undershoot; The undershoot suppression module, Reduce Undershoot, includes: resistors R5 and R6 and capacitor C2; One end of resistor R5 is connected to the Reduce Overshoot module as the output voltage OUT. The other end of resistor R5 is connected to one end of capacitor C2; The other end of capacitor C2 is connected to one end of resistor R6; The other end of resistor R6 is connected to error amplifier EA.

2. The transient enhancement circuit for suppressing overshoot and undershoot applied to an LDO according to claim 1, characterized in that, The adaptive zero-point module composed of resistor R3, capacitor C1 and NMOS transistor MN2, and the feedback network of LDO composed of resistor R1 and resistor R2; The bandgap reference circuit BG provides a reference voltage VREF to the error amplifier EA. It is compared with the feedback voltage VFB generated by the feedback network to generate a voltage signal EA_OUT to control the gate voltage of transistor MN1. This generates a current that flows through resistor R4 to generate a voltage signal that controls the gate of power transistor MP1. This allows the output voltage fluctuation to be sensed through the feedback network and then stabilized by the error amplifier and power transistor. The overshoot suppression module Reduce Overshoot senses the feedback voltage VFB generated by the feedback network and sends a signal to the LDO output to suppress overshoot; the undershoot suppression module Reduce Undershoot senses the LDO output voltage OUT and sends a signal to the error amplifier EA module to suppress undershoot.

3. A transient enhancement circuit for suppressing overshoot and undershoot applied to an LDO according to claim 1, characterized in that, When the transient enhancement circuit suddenly changes from a light load to a heavy load, i.e., the load current surge causes the output voltage to undershoot, it activates the undershoot suppression module Reduce Undershoot to slow down the output voltage undershoot and shorten the recovery time.

4. A transient enhancement circuit for suppressing overshoot and undershoot applied to an LDO according to claim 1, characterized in that, When the transient enhancement circuit suddenly changes from heavy load to light load, i.e., the load current drops suddenly, causing the output voltage to surge, it activates the overshoot suppression module Reduce Overshoot to slow down the output voltage surge and shorten the recovery time.

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