A micro-power linear power supply foldback current limit protection circuit and method

Abstract

The application relates to the technical field of power management integrated circuits, and discloses a micro-power-consumption linear power supply return type current-limiting protection circuit and method, wherein the circuit structure error amplifier can accurately control the conduction degree of the eighteenth P-type transistor M P18 by comparing a reference voltage VREF with a feedback voltage, so as to adjust the output voltage VOUT to a set value. The closed-loop feedback mechanism greatly improves the stability of the power supply, and ensures that the output voltage can be kept constant under various load conditions. The return type current-limiting protection circuit can rapidly respond and act on the input end of the error amplifier when the output current exceeds a set threshold value by monitoring the output current, adjust the output signal of the error amplifier, and then reduce the conduction degree of the eighteenth P-type transistor M P18 , so as to realize current-limiting protection. The return type current-limiting mechanism can effectively prevent the power supply from being damaged or short-circuited due to overcurrent.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power management integrated circuit, in particular to a micro-power linear power supply foldback current limiting protection circuit and method. BACKGROUND

[0002] With the rapid development of semiconductor technology, the integration of linear voltage regulator is increasing, and the power density is rapidly increasing. In actual application, if the load current of the voltage regulator is too large or in a short circuit state, and the current of the power transistor is large, then local hot spots and electrical migration of the internal interconnection metal of the chip will occur, resulting in damage or burning of the power transistor of the voltage regulator and functional failure, which seriously threatens the normal work of the powered system.

[0003] The current limiting circuit of the linear voltage regulator ensures that the voltage regulating device is in a safe operating area. The conventional current limiting circuit is divided into two types: foldback current limiting voltage and constant current limiting circuit. The static current of each analog branch is in the microampere level. The principle of the foldback current limiting circuit is that the limiting current is controlled by a certain voltage signal of the circuit. When the load of the voltage regulator is too heavy and the output current is greater than the threshold current I MAX , the output current of the voltage regulator is quickly adjusted to the short circuit current by the current limiting circuit, reducing the power consumption of the voltage regulator. If the transient state requires a current greater than the current limiting protection threshold, the output voltage function of the voltage regulator is abnormal. The principle of the constant current limiting circuit is that the maximum output current of the voltage regulator is always the current limiting threshold I MAX . In the overcurrent or short circuit application state, the power of the voltage regulator is very large, and there is a potential risk of damage or failure. If the existing two current limiting protection circuit technical solutions are used, the application range of the linear voltage regulator is limited. In the low voltage difference application process of the voltage regulator, the output transient current of the voltage regulator is too large, and the output function of the voltage regulator is not normal. SUMMARY

[0004] In order to overcome the defects of the prior art, the purpose of the present application is to provide a micro-power linear power supply foldback current limiting protection circuit and method to solve the technical problem of the abnormal output function of the voltage regulator in the low voltage difference and large output current application state of the voltage regulator in the prior art.

[0005] The present application is realized by the following technical solutions:

[0006] In a first aspect, the present application provides a micro-power linear power supply foldback current limiting protection circuit, which comprises an error amplifier, a foldback current limiting protection circuit, a buffer, an eighteenth P-type transistor M P18 , a first resistor R1 and a second resistor R2.

[0007] The positive input end of the error amplifier is connected to a reference voltage V REF , and the power supply end of the error amplifier is connected to an input voltage V INThe output end of the error amplifier is connected to the gate of the eighteenth P-type transistor M P18 through a buffer; the source and substrate of the eighteenth P-type transistor M P18 are connected to an input voltage V IN ; the drain of the eighteenth P-type transistor M P18 is connected to ground through a first resistor R1 and a second resistor R2 in sequence; the negative input end of the error amplifier is connected between the first resistor R1 and the second resistor R2 in parallel;

[0008] The output voltage V P18 is set between the drain of the eighteenth P-type transistor M OUT and the first resistor R1.

[0009] The output end of the buffer is provided with a first test node a1; the input end of the buffer is provided with a second test node a2.

[0010] The turn-back type current limiting protection circuit is provided with three branches, one branch is connected to an input voltage V IN , one branch is connected to the second test node a2, and one branch is connected to V OUT .

[0011] Preferably, the turn-back type current limiting protection circuit comprises a current limiting mode control circuit and a power transistor gate-source voltage limiting circuit.

[0012] One end of the current limiting mode control circuit and the power transistor gate-source voltage limiting circuit is connected to an input voltage V IN .

[0013] The other end of the current limiting mode control circuit and the power transistor gate-source voltage limiting circuit is set to ground.

[0014] The output end of the current limiting mode control circuit is connected to the input end of the power transistor gate-source voltage limiting circuit, and the output end of the power transistor gate-source voltage limiting circuit is connected to the second test node a2.

[0015] Further, the current limiting mode control circuit comprises a first limiting amplifier circuit, a second limiting amplifier circuit, a third limiting amplifier circuit, a fourth limiting amplifier circuit, a fifth limiting amplifier circuit, a sixth limiting amplifier circuit, a seventh limiting amplifier circuit and an eighth limiting amplifier circuit.

[0016] The first limiting amplifier circuit, the second limiting amplifier circuit, the third limiting amplifier circuit, the fourth limiting amplifier circuit, the fifth limiting amplifier circuit, the sixth limiting amplifier circuit, the seventh limiting amplifier circuit and the eighth limiting amplifier circuit are all connected in parallel, and a plurality of voltage measuring points are provided on each limiting amplifier circuit and connected through the plurality of voltage measuring points.

[0017] One end of the first limiting circuit, the second limiting circuit, the fourth limiting circuit, the sixth limiting circuit is connected to the input voltage V IN ; the other end of the first limiting circuit, the second limiting circuit, the fourth limiting circuit, the fifth limiting circuit, the sixth limiting circuit is grounded; wherein the first limiting circuit is connected to the first bias voltage V B1 ; the second limiting circuit and the fourth limiting circuit are provided with the second bias voltage V B2 ;

[0018] One end of the third limiting circuit is connected to the output voltage V OUT , and the other end is grounded;

[0019] One end of the seventh limiting circuit is connected to the input voltage V IN ; the other end is connected to the measuring point circuit; one end of the measuring point circuit is sequentially connected to the output voltage V OUT through the sixth limiting circuit, the fifth limiting circuit and the fourth limiting circuit; the other end is connected to the eighth limiting circuit;

[0020] One end of the eighth limiting circuit is connected to the input voltage V IN ; the other end is connected to the input end of the power transistor gate-source voltage limiting circuit.

[0021] Further, the first limiting circuit is provided with a first P-type transistor M P1 , a second P-type transistor M P2 , a third P-type transistor M P3 , a first N-type transistor M N1 , a first voltage measuring point b1, a second voltage measuring point b2 and a third voltage measuring point b3;

[0022] The source and substrate of the first P-type transistor M P1 are connected to the input voltage V IN , and the gate and drain are connected to the first voltage measuring point b1; the source of the second P-type transistor M P2 is connected to the first voltage measuring point b1, the substrate is connected to the input voltage V IN , and the gate and drain are connected to the second voltage measuring point b2; the source of the third P-type transistor M P3 is connected to the second voltage measuring point b2, the substrate is connected to the input voltage V IN , and the gate and drain are connected to the third voltage measuring point b3; the source and substrate of the first N-type transistor M N1 are grounded, the gate is connected to the first bias voltage V B1 , and the drain is connected to the third voltage measuring point b3;

[0023] The second limiting circuit is provided with a fourth P-type transistor M P4 , a second N-type transistor M N2, the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , the fourth voltage measuring point b4, the fifth voltage measuring point b5, the sixth voltage measuring point b6 and the seventh voltage measuring point b7;

[0024] the fourth P-type transistor M P4 , the source and the substrate of the fourth P-type transistor M IN are connected with an input voltage V B2 , the gate is connected with a second bias voltage V N2 , and the drain is connected with the fourth voltage measuring point b4; the source of the second N-type transistor M N3 is connected with the fifth voltage measuring point b5, the substrate is connected with ground, and the gate and the drain are connected with the fourth voltage measuring point b4; the source of the third N-type transistor M N4 is connected with the sixth voltage measuring point b6, the substrate is connected with ground, and the gate and the drain are connected with the fifth voltage measuring point b5; the source of the fourth N-type transistor M N5 is connected with the seventh voltage measuring point b7, the substrate is connected with ground, and the gate and the drain are connected with the sixth voltage measuring point b6; the source and the substrate of the fifth N-type transistor M N6 are connected with ground, and the gate and the drain are connected with the seventh voltage measuring point b7;

[0025] the sixth N-type transistor M N7 , the seventh N-type transistor M N8 , the eighth N-type transistor M N9 , the ninth N-type transistor M N10 , the tenth N-type transistor M 10 , the ninth voltage measuring point b9, the tenth voltage measuring point b 11 , the eleventh voltage measuring point b 12 and the twelfth voltage measuring point b N6 ;

[0026] the source and the substrate of the sixth N-type transistor M OUT are connected with the ninth voltage measuring point b9, the gate is connected with the fourth voltage measuring point b4, and the drain is connected with an output voltage V N7 ; the source of the seventh N-type transistor M 10 is connected with the tenth voltage measuring point b N8 , the substrate is connected with ground, and the gate and the drain are connected with the ninth voltage measuring point b9; the source of the eighth N-type transistor M 11 is connected with the eleventh voltage measuring point b 10 , the substrate is connected with ground, and the gate and the drain are connected with the tenth voltage measuring point b N9 ; the source of the ninth N-type transistor M 12 is connected with the twelfth voltage measuring point b 11 , the substrate is connected with ground, and the gate and the drain are connected with the eleventh voltage measuring point b N10The source and substrate of the fifth P-type transistor M 12 ;

[0027] The fourth limiting circuit is provided with a fifth P-type transistor M P5 , an eleventh N-type transistor M N11 , a twelfth N-type transistor M N12 , a thirteenth voltage measuring point b 13 , and a fourteenth voltage measuring point b 14 ; the source and substrate of the fifth P-type transistor M P5 are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , and the drain is connected to the thirteenth voltage measuring point b 13 ; the source and substrate of the eleventh N-type transistor M N11 are connected to the fourteenth voltage measuring point b 14 , the gate is connected to the third voltage measuring point b3, and the drain is connected to the thirteenth voltage measuring point b 13 ; the source and substrate of the twelfth N-type transistor M N12 are connected to the ground, the gate is connected to the ninth voltage measuring point b9, and the drain is connected to the fourteenth voltage measuring point b 14 ;

[0028] The fifth limiting circuit is provided with a sixth P-type transistor M P6 and a Zener diode D z1 ; the source of the sixth P-type transistor M P6 is connected to the output voltage V OUT , the drain is connected to the eighteenth voltage measuring point b 18 , and the substrate is connected to the input voltage V IN ; the gate is connected to the third voltage measuring point b3; the cathode of the Zener diode D z1 is connected to the fourteenth voltage measuring point b 14 , and the anode is connected to the ground;

[0029] The sixth limiting circuit is provided with a seventh P-type transistor M P7 , a thirteenth N-type transistor M N13 , and a fifteenth voltage measuring point b 15 ; the source and substrate of the seventh P-type transistor M P7 are connected to the input voltage V IN , the gate is connected to the thirteenth voltage measuring point b 13 , and the drain is connected to the fifteenth voltage measuring point b 15 ; the source and substrate of the thirteenth N-type transistor M N13 are connected to the ground, the gate is connected to the fourteenth voltage measuring point b 14 , and the drain is connected to the fifteenth voltage measuring point b 15 ;

[0030] The seventh limiting circuit is provided with an eighth P-type transistor M P8 , a ninth P-type transistor M P9 , and a tenth P-type transistor M P10 ; 16 ; 17 ; 18 ;

[0031] The eighth P-type transistor M P8 has its source and substrate connected to an input voltage V IN , and its gate and drain connected to a sixteenth voltage measuring point b 16 ; The ninth P-type transistor M P9 has its source connected to the sixteenth voltage measuring point b 16 , its substrate connected to the input voltage V IN , and its gate and drain connected to a seventeenth voltage measuring point b 17 ; The tenth P-type transistor M P10 has its source connected to the seventeenth voltage measuring point b 17 , its substrate connected to the input voltage V IN , and its gate and drain connected to an eighteenth voltage measuring point b 18 ; The eighteenth voltage measuring point b 18 is arranged on the measuring point circuit;

[0032] The eighth limiting circuit is provided with an eleventh P-type transistor M P11 ; The eleventh P-type transistor M P11 has its source and substrate connected to the input voltage V IN , its gate connected to the eighteenth voltage measuring point b 18 , and its drain connected to an input end of the power transistor gate-source voltage limiting circuit 200.

[0033] Further, the power transistor gate-source voltage limiting circuit comprises a ninth limiting circuit, a tenth limiting circuit, and an eleventh limiting circuit;

[0034] The ninth limiting circuit, the tenth limiting circuit, and the eleventh limiting circuit are arranged in parallel; each limiting circuit is provided with a plurality of voltage measuring points, and is connected through the plurality of voltage measuring points;

[0035] One end of the ninth limiting circuit is connected to a drain of the eleventh P-type transistor M P11 , and the other end is grounded;

[0036] One end of the tenth limiting circuit is connected to the input voltage V IN , and the other end is grounded;

[0037] One end of the eleventh limiting circuit is connected to the input voltage V IN , and the other end is connected to a second test node a2.

[0038] Further, the ninth limiting circuit is provided with a twelfth P-type transistor M P12 , a thirteenth P-type transistor M P13 , a fourteenth P-type transistor M P14 , a fifteenth P-type transistor M P15 , a sixteenth P-type transistor M P16 , a fourteenth N-type transistor M N14 , a nineteenth voltage measuring point b 19 , a twentieth voltage measuring point b 20 , a twenty-first voltage measuring point b 21 , a twenty-second voltage measuring point b 22 , and a twenty-third voltage measuring point b 23 ; the source and substrate of the twelfth P-type transistor M P12 are connected to the nineteenth voltage measuring point b 19 , the gate is connected to the fifteenth voltage measuring point b 15 , and the drain is connected to the twentieth voltage measuring point b 20 ; the source and substrate of the thirteenth P-type transistor M P13 are connected to the twentieth voltage measuring point b 20 ; the gate and the drain are connected to the twenty-first voltage measuring point b 21 ; the source and substrate of the fourteenth P-type transistor M P14 are connected to the twenty-first voltage measuring point b 21 , and the gate and the drain are connected to the twenty-second voltage measuring point b 22 ; the source and substrate of the fifteenth P-type transistor M P15 are connected to the nineteenth voltage measuring point b 19 , and the gate and the drain are connected to the twenty-second voltage measuring point b 22 ; the source and substrate of the sixteenth P-type transistor M P16 are connected to the twenty-second voltage measuring point b 22 , and the gate and the drain are connected to the twenty-third voltage measuring point b 23 ; the source and substrate of the fourteenth N-type transistor M N14 are connected to the ground, the gate is connected to the first bias voltage V B1 , and the drain is connected to the twenty-third voltage measuring point b 23 ;

[0039] The tenth limiting circuit is provided with a seventeenth P-type transistor M P17 , a twenty-fourth voltage measuring point b 24 , and an LP-type transistor Q LP1 ;

[0040] The source and substrate of the seventeenth P-type transistor M P17 are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2, the drain is connected to the twenty-fourth voltage measuring point b 24 ; the collector of the LP type transistor Q LP1 is grounded, and the base is connected to the twenty-third voltage measuring point b 23 , and the emitter is connected to the twenty-fourth voltage measuring point b 24 ;

[0041] The eleventh limiting circuit is provided with an N type transistor Q n1 ; the collector of the N type transistor Q n1 is connected to the input voltage V IN , the base is connected to the twenty-fourth voltage measuring point b 24 , and the emitter is connected to the second test node a2.

[0042] In a second aspect, the present application further provides a micro-power linear power supply return type current limiting protection method, which is based on the above-mentioned micro-power linear power supply return type current limiting protection circuit and comprises the following processes:

[0043] The input and output voltages of the buffer are set to be equal, i.e. the voltages of the first test node a1 and the second test node a2 are equal, and the maximum limiting current is determined according to the state of the voltage stabilizer in the working mode of the current limiting mode control circuit by using the power transistor gate-source voltage limiting circuit in the return type current limiting protection circuit, so as to perform the micro-power linear power supply return type current limiting protection.

[0044] Preferably, the working mode of the current limiting mode control circuit comprises a low voltage difference working state non-current limiting working mode, a normal working voltage difference constant current limiting working mode and an output short circuit protection working mode.

[0045] Preferably, when the voltage stabilizer is in the low voltage difference application state, the current limiting protection is closed, and the maximum output current of the voltage stabilizer is determined by the W / L of the power transistor; when the output of the voltage stabilizer is short-circuited to the ground, the current limiting protection circuit is opened, and the maximum output current of the voltage stabilizer is determined by the width-length ratio and threshold voltage of the fourteenth P type transistor M P14 , the fifteenth P type transistor M P15 and the sixteenth P type transistor M P16 , wherein the maximum output current I OMAX =170mA; when the voltage stabilizer is in the normal working mode, the current limiting protection circuit is opened, and the maximum output current of the voltage stabilizer is determined by the width-length ratio and threshold voltage of the fifteenth P type transistor M P15 and the sixteenth P type transistor M P16 , wherein the maximum output current I OMAX =510mA.

[0046] Preferably, when the voltage stabilizer is in the low voltage difference application state, the input and output voltage difference is less than 0.8V; and when the voltage stabilizer is in the normal working mode, the input and output voltage difference is greater than 1V.

[0047] Compared with the prior art, the present application has the following beneficial technical effects:

[0048] The present application provides a micro-power linear power supply foldback current limiting protection circuit. The error amplifier can accurately control the conduction degree of the eighteenth P-type transistor M P18 , thereby adjusting the output voltage VOUT to a set value. This closed-loop feedback mechanism greatly improves the stability of the power supply, ensuring that the output voltage remains constant under various load conditions. The foldback current limiting protection circuit monitors the output current and, when the output current exceeds a set threshold, quickly responds to the input of the error amplifier and adjusts its output signal, thereby reducing the conduction degree of the eighteenth P-type transistor M P18 , achieving current limiting protection. This foldback current limiting mechanism can effectively prevent power supply damage or short circuit failure caused by overcurrent.

[0049] Further, the current limiting mode control circuit can monitor the size of the output current in real time and trigger the current limiting mode when the current exceeds the preset threshold. By accurately controlling the input signal of the power transistor gate-source voltage limiting circuit, the output current can be accurately limited, preventing circuit damage or failure caused by overcurrent. The main function of the power transistor gate-source voltage limiting circuit is to limit the gate-source voltage of the power transistor, thereby protecting it from excessive voltage. When the output current is too large, the circuit can quickly respond and reduce the gate-source voltage, thereby reducing the power consumption and heat generation of the power transistor, prolonging its service life. The foldback current limiting protection circuit can maintain the stability of the power supply system by accurately controlling the output current and gate-source voltage. In the case of load mutation or input voltage fluctuation, the circuit can quickly adjust the output current and voltage, ensuring stable operation of the system under various conditions.

[0050] The present application also provides a micro-power linear power supply foldback current limiting protection method, which adopts a current limiting mode control circuit to realize three current limiting protection working modes: low voltage difference working state without current limiting, normal working voltage difference constant current limiting, and output short circuit protection. The power transistor gate-source voltage limiting circuit design realizes the maximum limiting current of the voltage stabilizer in the normal working voltage difference constant current limiting mode and the output short circuit protection mode. The circuit design is simple and can be applied to linear voltage stabilizers based on BiCMOS and BCD process design. Users can meet the high reliability of voltage stabilizers in different application scenarios by reasonable use and configuration, while effectively protecting the voltage stabilizer from damage. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1Structure schematic diagram of micro-power-consumption linear power supply turn-back type current limiting protection circuit in the embodiment of the present application;

[0052] Figure 2 Structure schematic diagram of micro-power-consumption turn-back type current limiting protection circuit in the embodiment of the present application;

[0053] In the figure: 1, error amplifier; 2, turn-back type current limiting protection circuit; 3, buffer; V IN , input voltage; V REF , reference voltage; V OUT , output voltage; R1, first resistor; R2, second resistor; 100, current limiting mode control circuit; 200, power transistor gate-source voltage limiting circuit; a1, first test node; a2, second test node; M P1 , first P-type transistor; M P2 , second P-type transistor; M P3 , third P-type transistor; M P4 , fourth P-type transistor; M P5 , fifth P-type transistor; M P6 , sixth P-type transistor; M P7 , seventh P-type transistor; M P8 , eighth P-type transistor; M P9 , ninth P-type transistor; M P10 , tenth P-type transistor; M P11 , eleventh P-type transistor; M P12 , twelfth P-type transistor; M P13 , thirteenth P-type transistor; M P14 , fourteenth P-type transistor; M P15 , fifteenth P-type transistor; M P16 , sixteenth P-type transistor; M P17 , seventeenth P-type transistor; M P18 , eighteenth P-type transistor; M N1 , first N-type transistor; M N2 , second N-type transistor; M N3 , third N-type transistor; M N4 , fourth N-type transistor; M N5 , fifth N-type transistor; M N6 , sixth N-type transistor; M N7 , seventh N-type transistor; M N8 , eighth N-type transistor; M N9 , ninth N-type transistor; M N10 , tenth N-type transistor; M N11 , eleventh N-type transistor; M N12 , twelfth N-type transistor; M N13, thirteenth N-type transistor; M N14 , fourteenth N-type transistor; b1, first voltage measuring point; b2, second voltage measuring point; b3, third voltage measuring point; b4, fourth voltage measuring point; b5, fifth voltage measuring point; b6, sixth voltage measuring point; b7, seventh voltage measuring point; b9, ninth voltage measuring point; b 10 , tenth voltage measuring point; b 11 , eleventh voltage measuring point; b 12 , twelfth voltage measuring point; b 13 , thirteenth voltage measuring point; b 14 , fourteenth voltage measuring point; b 15 , fifteenth voltage measuring point; b 16 , sixteenth voltage measuring point; b 17 , seventeenth voltage measuring point; b 18 , eighteenth voltage measuring point; b 19 , nineteenth voltage measuring point; b 20 , twentieth voltage measuring point; b 21 , twenty-first voltage measuring point; b 22 , twenty-second voltage measuring point; b 23 , twenty-third voltage measuring point; b 24 , twenty-fourth voltage measuring point; D z1 , Zener diode; V B1 , first bias voltage; V B2 , second bias voltage; Q n1 , N-type transistor; Q LP1 , LP-type transistor. DETAILED DESCRIPTION

[0054] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person of ordinary skill in the art without making creative labor should belong to the protection scope of the present application.

[0055] The purpose of the present application is to provide a micro-power linear power supply foldback current limiting protection circuit and method, to solve the technical problem of abnormal output function of the voltage stabilizer in the application state of large output current of low voltage difference of the voltage stabilizer in the prior art.

[0056] The present application will be described in further detail below in combination with the drawings:

[0057] Embodiment 1

[0058] Referring to Figure 1In one embodiment of the present invention, a low-power linear power supply foldback current limiting protection circuit is provided, including an error amplifier 1, a foldback current limiting protection circuit 2, a buffer 3, and an eighteenth P-type transistor M. P18 The first resistor R1 and the second resistor R2; the positive input terminal of the error amplifier 1 is connected to the reference voltage V. REF The power supply terminal of error amplifier 1 is connected to the input voltage V. IN The output of error amplifier 1 is connected to the eighteenth P-type transistor M via buffer 3. P18 The gate of the eighteenth P-type transistor M; P18 The source and substrate are connected to the input voltage V. IN The eighteenth P-type transistor M P18 The drain of the transistor is grounded after passing through a first resistor R1 and a second resistor R2 in sequence; the negative input terminal of the error amplifier 1 is connected in parallel between the first resistor R1 and the second resistor R2; the eighteenth P-type transistor M P18 The output voltage V is set between the drain and the first resistor R1. OUT The output terminal of the buffer 3 is provided with a first test node a1; the input terminal of the buffer 3 is provided with a second test node a2; the foldback current limiting protection circuit 2 has three branches, one of which is connected to the input voltage V. IN One branch is connected to the second test node a2; the other branch is grounded after passing through the first resistor R1 and the second resistor R2.

[0059] Specifically, according to Figure 2 As shown, the foldback current limiting protection circuit 2 includes a current limiting mode control circuit 100 and a power transistor gate-source voltage limiting circuit 200; one end of the current limiting mode control circuit 100 and the power transistor gate-source voltage limiting circuit 200 are connected to the input voltage V. IN The other end of the current limiting mode control circuit 100 and the power transistor gate-source voltage limiting circuit 200 is grounded; the output terminal of the current limiting mode control circuit 100 is connected to the input terminal of the power transistor gate-source voltage limiting circuit 200, and the output terminal of the power transistor gate-source voltage limiting circuit 200 is connected to the second test node a2.

[0060] Among them, according to Figure 2As shown, the current-limiting mode control circuit 100 includes a first limiting circuit, a second limiting circuit, a third limiting circuit, a fourth limiting circuit, a fifth limiting circuit, a sixth limiting circuit, a seventh limiting circuit, and an eighth limiting circuit. All the first, second, third, fourth, fifth, sixth, seventh, and eighth limiting circuits are connected in parallel. Each limiting circuit has several voltage measurement points, which are connected together. One end of each of the first, second, fourth, and sixth limiting circuits is connected to an input voltage V. IN The other ends of the first, second, fourth, fifth, and sixth limiting circuits are grounded; the first limiting circuit is connected to the first bias voltage V. B1 A second bias voltage V is provided between the second limiting circuit and the fourth limiting circuit. B2 One end of the third limiting circuit is connected to the output voltage V. OUT The other end is grounded; one end of the seventh limiting circuit is connected to the input voltage V. IN The other end is connected to the measuring point circuit; one end of the measuring point circuit is connected to the output voltage V via the sixth limiting circuit, the fifth limiting circuit, and the fourth limiting circuit in sequence. OUT The other end is connected to the eighth limiting circuit; one end of the eighth limiting circuit is connected to the input voltage V. IN The other end is connected to the input of the power transistor gate-source voltage limiting circuit 200.

[0061] Among them, according to Figure 2 As shown, the first limiting circuit is equipped with a first P-type transistor M. P1 The second P-type transistor M P2 Third P-type transistor M P3 The first N-type transistor M N1 The first voltage measuring point b1, the second voltage measuring point b2, and the third voltage measuring point b3; the first P-type transistor M P1 The source and substrate are connected to the input voltage V. IN The gate and drain are connected to the first voltage measurement point b1; the second P-type transistor M P2 The source is connected to the first voltage measurement point b1, and the substrate is connected to the input voltage V. IN The gate and drain are connected to the second voltage measurement point b2; the third P-type transistor M P3 The source is connected to the second voltage measurement point b2, and the substrate is connected to the input voltage V. IN The gate and drain are connected to the third voltage measurement point b3; the first N-type transistor M N1 The source and substrate are grounded, and the gate is connected to the first bias voltage V. B1, the drain of the third P-type transistor M P4 , the source of the second N-type transistor M N2 , the source of the third N-type transistor M N3 , the source of the fourth N-type transistor M N4 , the source of the fifth N-type transistor M N5 , the fourth voltage measuring point b4, the fifth voltage measuring point b5, the sixth voltage measuring point b6 and the seventh voltage measuring point b7; the source and the substrate of the fourth P-type transistor M P4 are connected with an input voltage V IN , the gate is connected with a second bias voltage V B2 , and the drain is connected with the fourth voltage measuring point b4; the source of the second N-type transistor M N2 is connected with the fifth voltage measuring point b5, the substrate is connected with the ground, and the gate and the drain are connected with the fourth voltage measuring point b4; the source of the third N-type transistor M N3 is connected with the sixth voltage measuring point b6, the substrate is connected with the ground, and the gate and the drain are connected with the fifth voltage measuring point b5; the source of the fourth N-type transistor M N4 is connected with the seventh voltage measuring point b7, the substrate is connected with the ground, and the gate and the drain are connected with the sixth voltage measuring point b6; the source and the substrate of the fifth N-type transistor M N5 are connected with the ground, and the gate and the drain are connected with the seventh voltage measuring point b7; the sixth N-type transistor M N6 , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 , the ninth voltage measuring point b9, the tenth voltage measuring point b 10 , the eleventh voltage measuring point b 11 and the twelfth voltage measuring point b 12 ; the source and the substrate of the sixth N-type transistor M N6 are connected with the ninth voltage measuring point b9, the gate is connected with the fourth voltage measuring point b4, and the drain is connected with an output voltage V OUT ; the source of the seventh N-type transistor M N7 is connected with the tenth voltage measuring point b 10 , the substrate is connected with the ground, and the gate and the drain are connected with the ninth voltage measuring point b9; the source of the eighth N-type transistor M N8 is connected with the eleventh voltage measuring point b 11 , the substrate is connected with the ground, and the gate and the drain are connected with the tenth voltage measuring point b 10 ; the source of the ninth N-type transistor M N9 is connected with the twelfth voltage measuring point b 12 , the substrate is connected with the ground, and the gate and the drain are connected with the eleventh voltage measuring point b 11 ; the source of the tenth N-type transistor M N10The source and substrate are grounded, and the gate and drain are connected to the twelfth voltage measurement point b. 12 The fourth limiting circuit is equipped with a fifth P-type transistor M. P5 11th N-type transistor M N11 Twelfth N-type transistor M N12 Thirteenth voltage measurement point b 13 and the fourteenth voltage measurement point b 14 ; Fifth P-type transistor M P5 The source and substrate are connected to the input voltage V. IN The gate is connected to the second bias voltage V. B2 The drain is connected to the thirteenth voltage measurement point b. 13 ; Eleventh N-type transistor M N11 The source and substrate are connected to the fourteenth voltage measurement point b. 14 The gate is connected to the third voltage measurement point b3, and the drain is connected to the thirteenth voltage measurement point b. 13 ; Twelfth N-type transistor M N12 The source and substrate are grounded, the gate is connected to the ninth voltage measurement point b9, and the drain is connected to the fourteenth voltage measurement point b. 14 The fifth limiting circuit is equipped with a sixth P-type transistor M. P6 and Zener diode D z1 The sixth P-type transistor M P6 The source is connected to the output voltage V OUT The drain is connected to the thirteenth voltage measurement point b. 13 The substrate is connected to the input voltage V. IN The source is connected to the third voltage measurement point b3; Zener diode D z1 The cathode is connected to the fourteenth voltage measuring point b. 14 The anode is grounded; the sixth limiting circuit is equipped with a seventh P-type transistor M. P7 Thirteenth N-type transistor M N13 and the fifteenth voltage measurement point b 15 ; Seventh P-type transistor M P7 The source and substrate are connected to the input voltage V. IN The gate is connected to the thirteenth voltage measurement point b. 13 The drain is connected to the fifteenth voltage measurement point b. 15 ; Thirteenth N-type transistor M N13 The source and substrate are grounded, and the gate is connected to the fourteenth voltage measurement point b. 14 The drain is connected to the fifteenth voltage measurement point b. 15 The seventh limiting circuit is equipped with an eighth P-type transistor M. P8 Ninth P-type transistor M P9 10th P-type transistor M P10 Sixteenth voltage measurement point b 16 Seventeenth voltage measurement point b17 and the eighteenth voltage measuring point b 18 ; the eighth P-type transistor M P8 has its source and substrate connected to the input voltage V IN , and its gate and drain connected to the sixteenth voltage measuring point b 16 ; the ninth P-type transistor M P9 has its source connected to the sixteenth voltage measuring point b 16 , and its substrate connected to the input voltage V IN , and its gate and drain connected to the seventeenth voltage measuring point b 17 ; the tenth P-type transistor M P10 has its source connected to the seventeenth voltage measuring point b 17 , and its substrate connected to the input voltage V IN , and its gate and drain connected to the eighteenth voltage measuring point b 18 ; wherein the eighteenth voltage measuring point b 18 is arranged on the measuring point circuit; the eighth limiting circuit is provided with an eleventh P-type transistor M P11 ; the eleventh P-type transistor M P11 has its source and substrate connected to the input voltage V IN , and its gate connected to the eighteenth voltage measuring point b 18 , and its drain connected to the input end of the power transistor gate-source voltage limiting circuit 200.

[0062] According to the power transistor gate-source voltage limiting circuit 200 shown in Figure 2 , the power transistor gate-source voltage limiting circuit 200 comprises a ninth limiting circuit, a tenth limiting circuit and an eleventh limiting circuit; the ninth limiting circuit, the tenth limiting circuit and the eleventh limiting circuit are arranged in parallel; each limiting circuit is provided with a plurality of voltage measuring points and is connected by the plurality of voltage measuring points; one end of the ninth limiting circuit is connected to the drain of the eleventh P-type transistor M P11 , and the other end is grounded; one end of the tenth limiting circuit is connected to the input voltage V IN , and the other end is grounded; one end of the eleventh limiting circuit is connected to the input voltage V IN , and the other end is connected to the second test node a2.

[0063] According to the power transistor gate-source voltage limiting circuit 200 shown in Figure 2 , the ninth limiting circuit is provided with a twelfth P-type transistor M P12 , a thirteenth P-type transistor M P13 , a fourteenth P-type transistor M P14 , a fifteenth P-type transistor M P15 , a sixteenth P-type transistor M P16 , a fourteenth N-type transistor M N14 , a nineteenth voltage measuring point b 19 , a twentieth voltage measuring point b 20 , a twenty-first voltage measuring point b21 22nd voltage measurement point b 22 and the twenty-third voltage measurement point b 23 ; Twelfth P-type transistor M P12 The source and substrate are connected to the nineteenth voltage measurement point b. 19 The gate is connected to the fifteenth voltage measurement point b. 15 The drain is connected to the twentieth voltage measurement point b. 20 ; Thirteenth P-type transistor M P13 The source and substrate are connected to the twentieth voltage measurement point b. 20 The gate and drain are connected to the twenty-first voltage measurement point b. 21 The fourteenth P-type transistor M P14 The source and substrate are connected to the twenty-first voltage measurement point b. 21 The gate and drain are connected to the twenty-second voltage measurement point b. 22 The fifteenth P-type transistor M P15 The source and substrate are connected to the nineteenth voltage measurement point b. 19 The gate and drain are connected to the twenty-second voltage measurement point b. 22 The sixteenth P-type transistor M P16 The source and substrate are connected to the twenty-second voltage measurement point b. 22 The gate and drain are connected to the twenty-third voltage measurement point b. 23 ; Fourteenth N-type transistor M N14 The source and substrate are grounded, and the gate is connected to the first bias voltage V. B1 The drain is connected to the twenty-third voltage measurement point b. 23 The tenth limiting circuit is equipped with a seventeenth P-type transistor M. P17 24th voltage measurement point b 24 and LP-type transistor Q LP1 ; Seventeenth P-type transistor M P17 The source and substrate are connected to the input voltage V. IN The gate is connected to the second bias voltage V. B2 The drain is connected to the twenty-fourth voltage measurement point b. 24 LP-type transistor Q LP1 The collector is grounded, and the base is connected to the twenty-third voltage measurement point b. 23 The emitter is connected to the twenty-fourth voltage measurement point b. 24 The eleventh limiting circuit is equipped with an N-type transistor Q. n1 The N-type transistor Q n1 The collector is connected to the input voltage V IN The base is connected to the twenty-fourth voltage measurement point b. 24 The emitter is connected to the second test node a2.

[0064] Example 2

[0065] The embodiment 2 provides a micro-power linear power supply foldback current limit protection method based on the micro-power linear power supply foldback current limit protection circuit.

[0066] The input and output voltages of the buffer are equal, that is, the voltages of the first test node a1 and the second test node a2 are equal, the current limit circuit compares the sizes of the input voltage and the output voltage, and when the voltage stabilizer is in heavy load, the output voltage of the error amplifier in the voltage stabilizer loop is limited, so that the gate-source voltage V P18 of the eighteenth P-type transistor M GS is adjusted, and the working current of the power transistor is limited. P18 When V OUT =0V, 3V≤V IN ≤11.5V (the input voltage is a normal working voltage), V IN -V a1 =V X , V GSMP1 = V X , and the working current of the power transistor is 170mA; when 1.25V≤V OUT ≤11.0V, 3V≤V IN ≤11.5V (the input voltage is a normal working voltage), V IN -V OUT ≥1V, V IN -V a1 = V Y , V GSMP1 = V Y , and the working current of the power transistor is 510mA; when 1.25V≤V OUT ≤11.0V, 3V≤V IN ≤11.5V (the input voltage is a normal working voltage), V IN -V OUT ≤0.8V, V GSMP1 = V Z , the foldback current limit protection circuit is in an open circuit state, the output node voltage of the error amplifier in the voltage stabilizer loop is not controlled by the foldback current limit protection circuit, the output current capacity of the power transistor is determined by the width-length ratio of the power transistor itself, and the output current I OUT is generally designed to be about 1A; when the voltage stabilizer is in different three working modes, V X ≤V Y ≤V Z .

[0067] The static current of each analog branch in the embodiment is in the order of nanoampere. Three working states are adopted without affecting the normal working of the voltage stabilizer. The first low voltage difference working state is adopted. In this state, the current limiting protection circuit does not limit the output current. The second voltage stabilizer output is short-circuited to the ground. In this state, the output circuit is limited to 170 mA. The third normal working state is adopted. The output current is limited to 510 mA.

[0068] The micro-power consumption foldback current limiting protection circuit in the embodiment is composed of a current limiting mode control circuit 100 and a power transistor gate-source voltage limiting circuit 200. The output voltage of the error amplifier in the voltage stabilizer loop is limited by comparing the sizes of the input voltage and the output voltage, so as to control the adjusting device such as the Figure 1 The gate-source voltage V P18 of the eighteenth P-type transistor M GS is shown. The working current of the eighteenth P-type transistor M P18 is limited.

[0069] Specifically, the principle of the current limiting mode control circuit 100 is as follows. The first P-type transistor M P1 , the second P-type transistor M P2 , the third P-type transistor M P3 , and the first N-type transistor M N1 form a first limiting circuit. The difference between the third voltage measuring point b3 voltage and the input voltage V IN is V GSMP1 + V GSMP2 + V GSMP3 . The first N-type transistor M N1 is a current mirror transistor. V B1 is the first bias voltage. When 7V≤VIN≤11.5, the first N-type transistor M N1 suffers a high voltage between the source and the drain. The first P-type transistor M P1 , the second P-type transistor M P2 , the third P-type transistor M P3 , and the first N-type transistor M N1 are thin gate oxide source-drain high voltage devices. The second N-type transistor M N2 , the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , and the fourth P-type transistor M P4 form a second limiting circuit. The difference between the fourth voltage measuring point b4 voltage and GND is V GSMN2 + V GS MN3 + V GS GS MN4 +V GS GS MN5 . The fourth P-type transistor M P4 is a current mirror transistor. VB2 For the second bias voltage, when 7V≤VIN≤11.5, the fourth P-type transistor M P4 The transistor source-drain bears a higher voltage, the second N-type transistor M N2 , the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , the fourth P-type transistor M P4 It is a thin gate oxide source-drain high voltage device; the sixth N-type transistor M N6 , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 The signal transmission circuit is composed of, in normal operation, the ninth voltage measuring point b9 voltage is equal to the output voltage V OUT , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 The third limiting circuit is composed of transistors, and the difference between the ninth voltage measuring point b9 voltage and GND is V GSMN7 + V GS MN8 + V GS GS MN9 + V GS GS MN10 When 7V≤VIN≤11.5V, the sixth N-type transistor M N6 The source-drain bears a higher voltage, the sixth N-type transistor M N6 , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 The transistor is a thin gate oxide source-drain high voltage device; the fifth P-type transistor M P5 , the eleventh N-type transistor M N11 , the eleventh N-type transistor M N12 The common source amplifier circuit is composed of transistors, and the fifth P-type transistor M P5 It is a current mirror to the transistor, V B2 It is a second bias voltage, an isolation common gate device, which separates the thirteenth voltage measuring point b 13 And the fourteenth voltage measuring point b 14 When 7V≤V IN ≤11.5V, the eleventh N-type transistor M N11 The source-drain bears a larger voltage, the twelfth N-type transistor M N12 It is an input transistor of the common source amplifier, and the fifth P-type transistor M P5Eleventh N-type transistor M N11 Twelfth N-type transistor M N12 is a thin gate oxide high voltage transistor; seventh P-type transistor M P7 and thirteenth N-type transistor M N13 comprise a common source amplifier, seventh P-type transistor M P7 is a bias current source, thirteenth N-type transistor M N13 is an input transistor, seventh P-type transistor M P7 and thirteenth N-type transistor M N13 is a thin gate oxide high voltage transistor.

[0070] Specifically, the power transistor gate-source voltage limiting circuit 200 works as follows: when the eleventh P-type transistor M P11 is turned on, the twelfth P-type transistor M P12 is turned off, the voltage at the twenty-third voltage measuring point b 23 is V IN -V GSMP15 -V GSMP16 , the fourteenth N-type transistor M N14 is a current mirror transistor, when 7V≤V IN ≤11.5V, the fourteenth N-type transistor M N14 suffers a high voltage between its source and drain, the LP-type transistor Q LP1 , N-type transistor Q n1 comprise a voltage shooting structure, the voltage at the second test node a2 is equal to the voltage at the twenty-third voltage measuring point b 23 , i.e. V IN -V GSMP15 -V GSMP16 ; when the eleventh P-type transistor M P11 is turned on, the twelfth P-type transistor M P12 is turned on, the voltage at the twenty-third voltage measuring point b 23 is V IN -V GSMP14∥GSMP15 -V GSMP16 , the fourteenth N-type transistor M N14 is a current mirror transistor, when 7V≤V IN ≤11.5V, the fourteenth N-type transistor M N14 suffers a high voltage between its source and drain, the LP-type transistor Q LP1 , N-type transistor Q n1 comprise a voltage shooting structure, the voltage at the second test node a2 is equal to the voltage at the twenty-third voltage measuring point b 23 , i.e. V IN -V GSMP14∥GSMP15 -V GSMP16In this condition, the fourteenth P-type transistor M P14 and the fifteenth P-type transistor M P15 are simultaneously in the on state.

[0071] When V OUT = 0V, 3V≤V IN ≤11.5V (normal operating voltage of the input voltage), V IN -V OUT ≥V SGMP11 , the sixth P-type transistor M P6 is turned on, the voltage of the eighteenth voltage measuring point b 18 equals the output voltage V OUT , the eleventh P-type transistor M P11 is turned on, the voltage of the nineteenth voltage measuring point b 19 equals the input voltage V IN , the voltage of the ninth voltage measuring point b9 equals V OUT = 0V, the twelfth N-type transistor M N12 is turned off, the voltage of the fourteenth voltage measuring point b 14 equals V IN -V GSMP1 - V GSMP2 -V GSMP3 -V GSMN11 , the Zener diode D Z1 limits the voltage of the fourteenth voltage measuring point b 14 to be no more than V DZ (the reverse breakdown voltage of the Zener diode), the thirteenth N-type transistor is turned on, the voltage of the fifteenth voltage measuring point b 15 approaches 0V, the twelfth P-type transistor M P12 is turned on, the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 , and the sixteenth P-type transistor M P16 are in the saturation operating state, and the voltage of the twenty-third voltage measuring point b 23 is as shown in equation (1).

[0072] (1)

[0073] K P is the current transfer factor of the PMOS transistor.

[0074] The P-type transistor Q LP1 and the N-type transistor Q n1 are in the snapback structure, the voltage of the first test node a2 equals the voltage of the twenty-third voltage measuring point b 23 , and the maximum driving voltage of the voltage regulator is as shown in equation (2).

[0075] (2)

[0076] In the output short-circuit current limiting mode, the maximum output current of the voltage regulator is determined by the width-length ratio and threshold voltage of the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 , the sixteenth P-type transistor M P16 and the seventeenth P-type transistor M OMAX . The maximum output current I =170mA.

[0077] When 1.25V≤V OUT ≤11.0V, V IN -V OUT ≥V SGMP11 , 3V≤V IN ≤11.5V (normal working voltage of the input voltage), the sixth P-type transistor M P6 is turned on, the voltage of the eighteenth voltage measuring point b 18 is equal to the output voltage V OUT , the eleventh P-type transistor M P11 is turned on, the voltage of the nineteenth voltage measuring point b 19 is equal to the input voltage V IN , the voltage of the ninth voltage measuring point b9 is equal to the output voltage V OUT , the twelfth N-type transistor M N12 is turned on, the voltage of the fourteenth voltage measuring point b 14 is equal to 0, the Zener diode D Z1 limits the voltage of the fourteenth voltage measuring point b 14 to be not greater than V DZ (the reverse breakdown voltage of the Zener diode), the thirteenth N-type transistor M N13 is turned off, the voltage of the fifteenth voltage measuring point b 15 is close to the input voltage V IN , the twelfth P-type transistor M P12 is turned off, the fourteenth P-type transistor M P14 is turned off, the fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 are in the saturation working state, and the voltage of the twenty-third voltage measuring point b 23 is shown in equation (3).

[0078] (3)

[0079] K P is the current transfer factor of the PMOS transistor.

[0080] LP-type transistor Q LP1 and N-type transistor Q n1The voltage of the second test node a2 is equal to the voltage of the twenty-third voltage measuring point b 23 The voltage of the second test node a2 is equal to the voltage of the twenty-third voltage measuring point b

[0081] (4)

[0082] In the normal application working current limiting mode, the maximum output current of the voltage stabilizer is determined by the width-length ratio and threshold voltage of the fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 The maximum output current I OMAX =510mA is obtained by design adjustment.

[0083] When 1.25V≤V OUT ≤11.0V, V IN -V OUT ≤V SGMP11 , 3V≤V IN ≤11.5V (the input voltage is the normal working voltage), the eleventh P-type transistor M P11 is cut off, the fourteenth N-type transistor M N14 is the current mirror in normal working state, the voltage of the nineteenth voltage measuring point b 19 is equal to 0, the voltage of the twenty-third voltage measuring point b 23 is 0, and the voltage of the twenty-fourth voltage measuring point b24 is V BE In the normal application mode, the N-type transistor Q n1 is cut off, and the current limiting protection circuit is in high resistance state and does not have the current limiting protection function.

[0084] In the low voltage difference application state of the voltage stabilizer, the current limiting protection does not work, and the maximum output current of the voltage stabilizer is determined by the W / L of the power transistor.

[0085] In summary, the micro-power linear power supply foldback current limiting protection circuit and method provided by the application can accurately control the conduction degree of the eighteenth P-type transistor MP18 by comparing the reference voltage VREF with the feedback voltage, so as to adjust the output voltage VOUT to the set value. The closed-loop feedback mechanism greatly improves the stability of the power supply and ensures that the output voltage can remain constant under various load conditions. The foldback current limiting protection circuit can quickly respond and act on the input end of the error amplifier when the output current exceeds the set threshold value, adjust the output signal of the error amplifier, and then reduce the conduction degree of the eighteenth P-type transistor MP18, thereby realizing current limiting protection. The foldback current limiting mechanism can effectively prevent the power supply from being damaged or short-circuit failure due to overcurrent.

[0086] The application adopts a current limiting mode control circuit to realize three current limiting protection working modes, a low voltage difference working state non-current limiting working mode, a normal working voltage difference constant current limiting working mode and an output short circuit protection working mode; the maximum limiting current of the voltage stabilizer in the normal working voltage difference constant current limiting working mode and the output short circuit protection working mode is realized by using a power transistor gate-source voltage limiting circuit design; the circuit design is simple and can be popularized and applied to linear voltage stabilizers designed based on BiCMOS and BCD processes; users can meet the high reliability of the working of the voltage stabilizer in different application scenarios by reasonably using the configuration, and at the same time, the voltage stabilizer is effectively protected from damage.

[0087] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, but not to limit it, although the present application has been described in detail with reference to the above examples, those skilled in the art should understand that: the specific embodiments of the present application can still be modified or replaced by the equivalent, without departing from the spirit and scope of the present application. Any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A low-power linear power supply foldback current limiting protection circuit, characterized in that, Includes an error amplifier (1), a foldback current limiting protection circuit (2), a buffer (3), and an eighteenth P-type transistor M. P18 The first resistor R1 and the second resistor R2; The positive input terminal of the error amplifier (1) is connected to the reference voltage V. REF The power supply terminal of the error amplifier (1) is connected to the input voltage V. IN The output of the error amplifier (1) is connected to the eighteenth P-type transistor M via a buffer (3). P18 The gate of the eighteenth P-type transistor M; P18 The source and substrate are connected to the input voltage V. IN The eighteenth P-type transistor M P18 The drain of the amplifier is grounded after passing through the first resistor R1 and the second resistor R2 in sequence; the negative input terminal of the error amplifier (1) is connected in parallel between the first resistor R1 and the second resistor R2. The eighteenth P-type transistor M P18 The output voltage V is set between the drain and the first resistor R1. OUT ; The output end of the buffer (3) is provided with a first test node a1; the input end of the buffer (3) is provided with a second test node a2; The foldback current limiting protection circuit (2) has three branches, one of which is connected to the input voltage V. IN One branch is connected to the second test node a2; another branch is connected to V. OUT ; The foldback current limiting protection circuit (2) includes a current limiting mode control circuit (100) and a power transistor gate-source voltage limiting circuit (200). One end of the current limiting mode control circuit (100) and the power transistor gate-source voltage limiting circuit (200) is connected to the input voltage V. IN ; The other end of the current limiting mode control circuit (100) and the power transistor gate-source voltage limiting circuit (200) is grounded; The output of the current limiting mode control circuit (100) is connected to the input of the power transistor gate-source voltage limiting circuit (200), and the output of the power transistor gate-source voltage limiting circuit (200) is connected to the second test node a2. The current limiting mode control circuit (100) includes a first limiting circuit, a second limiting circuit, a third limiting circuit, a fourth limiting circuit, a fifth limiting circuit, a sixth limiting circuit, a seventh limiting circuit, and an eighth limiting circuit; The first, second, third, fourth, fifth, sixth, seventh, and eighth limiting circuits are all connected in parallel. Each limiting circuit has several voltage measurement points, which are connected together. One end of the first, second, fourth, and sixth limiting circuits is connected to the input voltage V. IN The other ends of the first, second, fourth, fifth, and sixth limiting circuits are grounded; the first limiting circuit is connected to the first bias voltage V. B1 A second bias voltage V is provided between the second limiting circuit and the fourth limiting circuit. B2 ; One end of the third limiting circuit is connected to the output voltage V. OUT The other end is grounded; One end of the seventh limiting circuit is connected to the input voltage V. IN The other end is connected to the measuring point circuit; wherein, the measuring point circuit is the circuit for detecting the output voltage VUOT; one end of the measuring point circuit is connected to the output voltage VUOT via the sixth limiting circuit, the fifth limiting circuit, and the fourth limiting circuit in sequence. OUT The other end is connected to the eighth limiting circuit; One end of the eighth limiting circuit is connected to the input voltage V. IN The other end is connected to the input of the power transistor gate-source voltage limiting circuit (200).

2. The low-power linear power supply foldback current limiting protection circuit according to claim 1, characterized in that, The first limiting circuit is provided with a first P-type transistor M P1 The second P-type transistor M P2 Third P-type transistor M P3 The first N-type transistor M N1 The first voltage measuring point b1, the second voltage measuring point b2, and the third voltage measuring point b3; The first P-type transistor M P1 The source and substrate are connected to the input voltage V. IN The gate and drain are connected to the first voltage measurement point b1; the second P-type transistor M P2 The source is connected to the first voltage measurement point b1, and the substrate is connected to the input voltage V. IN The gate and drain are connected to the second voltage measurement point b2; the third P-type transistor M P3 The source is connected to the second voltage measurement point b2, and the substrate is connected to the input voltage V. IN The gate and drain are connected to the third voltage measurement point b3; the first N-type transistor M N1 The source and substrate are grounded, and the gate is connected to the first bias voltage V. B1 The drain is connected to the third voltage measurement point b3; The second limiting circuit is equipped with a fourth P-type transistor M. P4 The second N-type transistor M N2 The third N-type transistor M N3 The fourth N-type transistor M N4 Fifth N-type transistor M N5 The fourth voltage measuring point b4, the fifth voltage measuring point b5, the sixth voltage measuring point b6, and the seventh voltage measuring point b7; The fourth P-type transistor M P4 The source and substrate are connected to the input voltage V. IN The gate is connected to the second bias voltage V. B2 The drain is connected to the fourth voltage measurement point b4; the second N-type transistor M N2 The source is connected to the fifth voltage measurement point b5, the substrate is grounded, and the gate and drain are connected to the fourth voltage measurement point b4; the third N-type transistor M N3 The source is connected to the sixth voltage measurement point b6, the substrate is grounded, and the gate and drain are connected to the fifth voltage measurement point b5; the fourth N-type transistor M N4 The source is connected to the seventh voltage measurement point b7, the substrate is grounded, and the gate and drain are connected to the sixth voltage measurement point b6. Fifth N-type transistor M N5 The source and substrate are grounded, and the gate and drain are connected to the seventh voltage measurement point b7; The third limiting circuit is equipped with a sixth N-type transistor M. N6 The seventh type N transistor M N7 The eighth N-type transistor M N8 Ninth type N transistor M N9 Type N transistor M N10 Ninth voltage measuring point b9, tenth voltage measuring point b 10 Eleventh voltage measurement point b 11 and the twelfth voltage measurement point b 12 ; The sixth N-type transistor M N6 The source and substrate are connected to the ninth voltage measurement point b9, the gate is connected to the fourth voltage measurement point b4, and the drain is connected to the output voltage V. OUT ; Seventh N-type transistor M N7 The source is connected to the tenth voltage measurement point b. 10 The substrate is grounded, and the gate and drain are connected to the ninth voltage measurement point b9; the eighth N-type transistor M N8 The source is connected to the eleventh voltage measurement point b. 11 The substrate is grounded, and the gate and drain are connected to the tenth voltage measurement point b. 10 ; Ninth type N transistor M N9 The source is connected to the twelfth voltage measurement point b. 12 The substrate is grounded, and the gate and drain are connected to the eleventh voltage measurement point b. 11 Type 10 N transistor M N10 The source and substrate are grounded, and the gate and drain are connected to the twelfth voltage measurement point b. 12 ; The fourth limiting circuit is equipped with a fifth P-type transistor M. P5 11th N-type transistor M N11 Twelfth N-type transistor M N12 Thirteenth voltage measurement point b 13 and the fourteenth voltage measurement point b 14 ; Fifth P-type transistor M P5 The source and substrate are connected to the input voltage V. IN The gate is connected to the second bias voltage V. B2 The drain is connected to the thirteenth voltage measurement point b. 13 ; Eleventh N-type transistor M N11 The source and substrate are connected to the fourteenth voltage measurement point b. 14 The gate is connected to the third voltage measurement point b3, and the drain is connected to the thirteenth voltage measurement point b. 13 ; Twelfth N-type transistor M N12 The source and substrate are grounded, the gate is connected to the ninth voltage measurement point b9, and the drain is connected to the fourteenth voltage measurement point b. 14 ; The fifth limiting circuit is equipped with a sixth P-type transistor M. P6 and Zener diode D z1 The sixth P-type transistor M P6 The source is connected to the output voltage V OUT The drain is connected to the eighteenth voltage measurement point b. 18 The substrate is connected to the input voltage V. IN The gate is connected to the third voltage measurement point b3; Zener diode D z1 The cathode is connected to the fourteenth voltage measuring point b. 14 Anode grounding is installed; The sixth limiting circuit is equipped with a seventh P-type transistor M. P7 Thirteenth N-type transistor M N13 and the fifteenth voltage measurement point b 15 ; Seventh P-type transistor M P7 The source and substrate are connected to the input voltage V. IN The gate is connected to the thirteenth voltage measurement point b. 13 The drain is connected to the fifteenth voltage measurement point b. 15 ; Thirteenth N-type transistor M N13 The source and substrate are grounded, and the gate is connected to the fourteenth voltage measurement point b. 14 The drain is connected to the fifteenth voltage measurement point b. 15 ; The seventh limiting circuit is equipped with an eighth P-type transistor M. P8 Ninth P-type transistor M P9 10th P-type transistor M P10 Sixteenth voltage measurement point b 16 Seventeenth voltage measurement point b 17 and the eighteenth voltage measurement point b 18 ; Eighth P-type transistor M P8 The source and substrate are connected to the input voltage V. IN The gate and drain are connected to the sixteenth voltage measurement point b. 16 ; Ninth P-type transistor M P9 The source is connected to the sixteenth voltage measurement point b. 16 The substrate is connected to the input voltage V. IN The gate and drain are connected to the seventeenth voltage measurement point b. 17 ; The tenth P-type transistor M P10 The source is connected to the seventeenth voltage measurement point b. 17 The substrate is connected to the input voltage V. IN The gate and drain are connected to the eighteenth voltage measurement point b. 18 Among them, the eighteenth voltage measuring point b 18 Set on the measuring point circuit; The eighth limiting circuit is equipped with an eleventh P-type transistor M. P11 ; Eleventh P-type transistor M P11 The source and substrate are connected to the input voltage V. IN The gate is connected to the eighteenth voltage measurement point b. 18 The drain is connected to the input terminal of the power transistor gate-source voltage limiting circuit (200).

3. The low-power linear power supply foldback current limiting protection circuit according to claim 2, characterized in that, The power transistor gate-source voltage limiting circuit (200) includes a ninth limiting circuit, a tenth limiting circuit, and an eleventh limiting circuit; The ninth, tenth, and eleventh limiting circuits are all connected in parallel; each limiting circuit is equipped with several voltage measurement points, which are connected together. One end of the ninth limiting circuit is connected to the eleventh P-type transistor M. P11 One end is the drain, and the other end is grounded; One end of the tenth limiting circuit is connected to the input voltage V. IN The other end is grounded; One end of the eleventh limiting circuit is connected to the input voltage V. IN The other end is connected to the second test node a2.

4. The low-power linear power supply foldback current limiting protection circuit according to claim 3, characterized in that, The ninth limiting circuit is equipped with a twelfth P-type transistor M. P12 Thirteenth P-type transistor M P13 Fourteenth P-type transistor M P14 The fifteenth P-type transistor M P15 The sixteenth P-type transistor M P16 Fourteenth N-type transistor M N14 19th voltage measurement point b 19 20th voltage measurement point b 20 21st voltage measurement point b 21 22nd voltage measurement point b 22 and the twenty-third voltage measurement point b 23 ; Twelfth P-type transistor M P12 The source and substrate are connected to the nineteenth voltage measurement point b. 19 The gate is connected to the fifteenth voltage measurement point b. 15 The drain is connected to the twentieth voltage measurement point b. 20 ; Thirteenth P-type transistor M P13 The source and substrate are connected to the twentieth voltage measurement point b. 20 The gate and drain are connected to the twenty-first voltage measurement point b. 21 The fourteenth P-type transistor M P14 The source and substrate are connected to the twenty-first voltage measurement point b. 21 The gate and drain are connected to the twenty-second voltage measurement point b. 22 The fifteenth P-type transistor M P15 The source and substrate are connected to the twentieth voltage measurement point b. 20 The gate and drain are connected to the twenty-second voltage measurement point b. 22 The sixteenth P-type transistor M P16 The source and substrate are connected to the twenty-second voltage measurement point b. 22 The gate and drain are connected to the twenty-third voltage measurement point b. 23 ; Fourteenth N-type transistor M N14 The source and substrate are grounded, and the gate is connected to the first bias voltage V. B1 The drain is connected to the twenty-third voltage measurement point b. 23 ; The tenth limiting circuit is equipped with a seventeenth P-type transistor M. P17 24th voltage measurement point b 24 and LP transistor Q LP1 ; The seventeenth P-type transistor M P17 The source and substrate are connected to the input voltage V. IN The gate is connected to the second bias voltage V. B2 The drain is connected to the twenty-fourth voltage measurement point b. 24 LP-type transistor Q LP1 The collector is grounded, and the base is connected to the twenty-third voltage measurement point b. 23 The emitter is connected to the twenty-fourth voltage measurement point b. 24 ; The eleventh limiting circuit is equipped with an N-type transistor Q. n1 The N-type transistor Q n1 The collector is connected to the input voltage V IN The base is connected to the twenty-fourth voltage measurement point b. 24 The emitter is connected to the second test node a2.

5. A method for foldback current limiting protection of a low-power linear power supply, based on the low-power linear power supply foldback current limiting protection circuit according to any one of claims 1-4, characterized in that, The process includes the following: The input and output voltages of the buffer (3) are set to be equal, that is, the voltages of the first test node a1 and the second test node a2 are equal. In the foldback current limiting protection circuit (2), the power transistor gate source voltage limiting circuit (200) limits the maximum current according to the state of the regulator in the working mode adopted by the current limiting mode control circuit (100) to perform low power linear power supply foldback current limiting protection.

6. The low-power linear power supply foldback current limiting protection method according to claim 5, characterized in that, The operating modes adopted by the current limiting mode control circuit (100) include low differential pressure working state without current limiting mode, normal working differential pressure constant current limiting mode and output short circuit protection mode.

7. A low-power linear power supply foldback current limiting protection method according to claim 5, characterized in that, When the voltage regulator is in a low-dropout application, the current limiting protection is off, and the maximum output current of the voltage regulator is determined by the W / L ratio of the power transistor. When the voltage regulator output is short-circuited to ground, the current limiting protection circuit is on, and the maximum output current of the voltage regulator is determined by the fourteenth P-type transistor M. P14 The fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 The aspect ratio and threshold voltage determine the maximum output current I. OMAX =170mA; When the regulator is in normal operating mode, the current limiting protection circuit is activated, and the maximum output current of the regulator is controlled by the fifteenth P-type transistor M. P15 and the sixteenth P-type transistor M P16 The aspect ratio and threshold voltage determine the maximum output current I. OMAX =510mA.

8. A low-power linear power supply foldback current limiting protection method according to claim 7, characterized in that, When the voltage regulator is in low-dropout application mode, the input-output voltage difference is less than 0.8V; when the voltage regulator is in normal operating mode, the input-output voltage difference is greater than 1V.

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