A control method of a storage device, a storage device, and an electronic device

Abstract

The application discloses a kind of control method of storage device, storage device and electronic equipment, control method includes: in response to the data to be written sent by host end, data to be written is written into storage unit according to target mode;Wherein, target mode at least includes first mode and / or second mode, first mode includes first type of storage unit is stored first, then migrates to second type of storage unit;Second mode includes directly with second type of storage unit is stored;According to target mode, target erase number of times is counted;Target erase number of times is less than the sum of the actual erase number of times of two types of storage units;In response to target erase number of times greater than erase number of times threshold, close first mode;That is, in the present application, data is written by target mode, corresponding target erase number of times is obtained, and writing mode is controlled based on target erase number of times, improve the write performance of storage device, can also effectively reduce erase amplification, prolong the life of storage device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage devices, and in particular to a control method of a storage device, a storage device and an electronic device. BACKGROUND

[0002] In the application process of the storage device, in order to improve the write performance of the storage device, the write data is usually written by the cache write mode.

[0003] In the actual operation process, the present application found that the write data is written by the cache write mode, which will produce more times of erase and write, and then produce larger erase amplification, which reduces the service life of the storage device. SUMMARY

[0004] The technical problem solved by the present application is to provide a control method of a storage device, a storage device and an electronic device, which combines the cache write mode and the direct write mode, obtains the target erase and write times, and controls the write mode based on the target erase and write times, thereby improving the write performance of the storage device while effectively reducing the erase amplification and prolonging the service life of the storage device.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a control method of a storage device, comprising: in response to the host sending the to-be-written data, writing the to-be-written data into the storage unit according to a target mode; wherein the target mode at least includes a first mode and / or a second mode, the first mode includes storing in a first type of storage unit first, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in a second type of storage unit; wherein the storable data amount of each first type of storage unit is less than the storable data amount of each second type of storage unit; counting the target erase and write times according to the target mode; wherein the target erase and write times is less than the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit; in response to the target erase and write times being greater than an erase and write times threshold, closing the first mode.

[0006] In an embodiment of the present application, the counting of the target erase and write times according to the target mode comprises: obtaining the first wear-out coefficient, wherein the first wear-out coefficient is determined by the first error bit number corresponding to the first type of storage unit and the second error bit number corresponding to the second type of storage unit; wherein the first wear-out coefficient is a positive number less than 1; determining the product of the first wear-out coefficient and the actual erase and write times of the first type of storage unit, and determining the sum of the product and the actual erase and write times of the second type of storage unit as the target erase and write times.

[0007] In an embodiment of the present application, the first wear-out coefficient is obtained by: performing the same number of times of erasing and writing on the storage units of the first type and the storage units of the second type, obtaining a first number of error bits corresponding to the storage units of the first type and a second number of error bits corresponding to the storage units of the second type; and determining the first wear-out coefficient according to the first number of error bits and the second number of error bits.

[0008] In an embodiment of the present application, the writing of the to-be-written data into the storage units according to the target mode comprises: writing the to-be-written data into the storage units according to a first mode with a first erase state threshold voltage and / or a first program state threshold voltage; wherein the first erase state threshold voltage is greater than a second erase state threshold voltage corresponding to the first wear-out coefficient, and the first program state threshold voltage is less than a second program state threshold voltage corresponding to the first wear-out coefficient; the counting of the target number of times of erasing and writing according to the target mode comprises: obtaining a second wear-out coefficient, wherein the second wear-out coefficient is determined by the first erase state threshold voltage and / or the first program state threshold voltage; wherein the second wear-out coefficient is less than the first wear-out coefficient; the first wear-out coefficient is determined by a first number of error bits corresponding to the storage units of the first type and a second number of error bits corresponding to the storage units of the second type; the first wear-out coefficient is a positive number less than 1; and a product of the second wear-out coefficient and an actual number of times of erasing and writing of the storage units of the first type is determined, and a sum of the product and an actual number of times of erasing and writing of the storage units of the second type is determined as the target number of times of erasing and writing.

[0009] In an embodiment of the present application, the first erase state threshold voltage is 0.2-0.3V higher than the second erase state threshold voltage, and the first program state threshold voltage is 0.2-0.3V lower than the second program state threshold voltage.

[0010] In an embodiment of the present application, the writing the to-be-written data into the storage unit according to the target mode comprises: writing the to-be-written data into the storage unit according to a first mode based on a first erase starting voltage and / or a first program starting voltage; wherein the first erase starting voltage is smaller than a second erase starting voltage corresponding to the first wear-out coefficient, and the first program starting voltage is smaller than a second program starting voltage corresponding to the first wear-out coefficient; the counting the target erase-write times according to the target mode comprises: obtaining a third wear-out coefficient, wherein the third wear-out coefficient is determined by the first erase starting voltage and / or the first program starting voltage; wherein the third wear-out coefficient is smaller than the first wear-out coefficient; the first wear-out coefficient is determined by a first number of error bits corresponding to a first type of storage unit and a second number of error bits corresponding to a second type of storage unit; the first wear-out coefficient is a positive number smaller than 1; and a product of the third wear-out coefficient and an actual erase-write time of the first type of storage unit is determined, and a sum of the product and an actual erase-write time of the second type of storage unit is determined as the target erase-write times.

[0011] In an embodiment of the present application, the writing the to-be-written data into the storage unit according to the target mode comprises: writing the to-be-written data into the storage unit according to a first mode based on a first erase step value and / or a first program step value; wherein the first erase step value is smaller than a second erase step value corresponding to the first wear-out coefficient, and the first program step value is smaller than a second program step value corresponding to the first wear-out coefficient; the counting the target erase-write times according to the target mode comprises: obtaining a fourth wear-out coefficient, wherein the fourth wear-out coefficient is determined by the first erase step value and / or the first program step value; wherein the fourth wear-out coefficient is smaller than the first wear-out coefficient; the first wear-out coefficient is determined by a first number of error bits corresponding to a first type of storage unit and a second number of error bits corresponding to a second type of storage unit; the first wear-out coefficient is a positive number smaller than 1; a product of the fourth wear-out coefficient and an actual erase-write time of the first type of storage unit is determined, and a sum of the product and an actual erase-write time of the second type of storage unit is determined as the target erase-write times.

[0012] In an embodiment of the present application, the writing the to-be-written data into the storage unit according to the target mode comprises: obtaining available space of the storage device, wherein the storage device comprises a plurality of storage units; in response to the available space of the storage device being greater than or equal to a preset space, writing the to-be-written data into the storage device according to the first mode; and in response to the available space of the storage device being smaller than the preset space, writing the to-be-written data into the storage device according to the second mode.

[0013] To solve the above technical problems, another technical solution adopted by the present application is to provide a storage device, which comprises a processor and a storage unit, the processor is coupled with the storage unit and a host end, and executes instructions in operation to realize the control method.

[0014] To solve the above technical problems, another technical solution adopted by the present application is to provide a storage device, which comprises a processor and a storage unit, the processor is coupled with the storage unit and a host end, and executes instructions in operation to realize the control method.

[0015] Distinguished from the current technology, the control method of the storage device provided by the present application comprises: in response to the data to be written sent by the host end, writing the data to be written into the storage unit according to a target mode; wherein the target mode at least includes a first mode and / or a second mode, the first mode includes storing in the first type of storage unit first, and then migrating the data stored in the first type of storage unit to the second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the storable data amount of each first type of storage unit is less than the storable data amount of each second type of storage unit; counting the target erase-write times according to the target mode; wherein the target erase-write times is less than the sum of the actual erase-write times of the first type of storage unit and the actual erase-write times of the second type of storage unit; in response to the target erase-write times being greater than an erase-write times threshold, closing the first mode. That is, in the present application, the data to be written is written into the storage unit through the target mode containing the first mode and / or the second mode, the corresponding target erase-write times are obtained, and the writing mode is controlled based on the target erase-write times, which can improve the writing performance of the storage device, effectively reduce the erase amplification, and prolong the service life of the storage device. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. Among them:

[0017] Figure 1 is a flowchart of the first embodiment of the control method of the storage device of the present application;

[0018] Figure 2 is a flowchart of an embodiment of step S11;

[0019] Figure 3 is a flowchart of the second embodiment of the control method of the storage device in the present application;

[0020] Figure 4is a relationship diagram of the number of erasing and writing times and the number of error bits corresponding to the first type of storage unit and the second type of storage unit;

[0021] Figure 5 is a flow diagram of a third embodiment of the control method of the storage device in the present application;

[0022] Figure 6 is a threshold voltage diagram of the first type of storage unit and the second type of storage unit in the prior art;

[0023] Figure 7 is a threshold voltage diagram of the first type of storage unit in the third embodiment of the present application;

[0024] Figure 8 is a flow diagram of a fourth embodiment of the control method of the storage device in the present application;

[0025] Figure 9 is a flow diagram of a fifth embodiment of the control method of the storage device in the present application;

[0026] Figure 10 is a principle flow diagram of writing data to be written into a storage unit in the present application;

[0027] Figure 11 is a structural diagram of an embodiment of the storage device in the present application;

[0028] Figure 12 is a structural diagram of an embodiment of the electronic device in the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0030] The phrase "embodiment" in the present application means that the specific features, structures or characteristics described in combination with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0031] The steps in the embodiments of the present application do not necessarily have to be processed in the order of the described steps, and the steps can be selectively rearranged, deleted, or added according to requirements. The step description in the embodiments of the present application is only an optional sequence combination, and does not represent all sequence combinations of the embodiments of the present application. The sequence of steps in the embodiments cannot be considered as a limitation of the present application.

[0032] The terms "first", "second", and the like in the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed or can optionally include other steps or units inherent to such processes, methods, products, or devices.

[0033] In the current technology, in order to improve the write performance of the storage device, the cache write (WB feature) is usually used to write the to-be-written data to the storage device, that is, the to-be-written data is first written to the flash memory, and then the corresponding data is moved to other storage units. Because the writing rate of the flash memory is fast, the write performance of the storage device is improved. However, for the same amount of data writing, the number of flash memory blocks occupied by the writing to the flash memory is much larger than the number of flash memory blocks occupied by the direct writing, and after writing to the flash memory, the data needs to be moved to other storage units, thereby generating a large number of side write times, and then generating a large erase amplification, thereby reducing the service life of the storage device.

[0034] Therefore, the present application provides a control method of a storage device, which writes to-be-written data to a storage unit through a target mode including a first mode and / or a second mode, obtains a corresponding target erase-write times, and controls the writing mode based on the target erase-write times, thereby improving the write performance of the storage device while effectively reducing the erase amplification and prolonging the service life of the storage device.

[0035] Please refer to Figure 1 , Figure 1 is a flowchart of the first embodiment of the control method of the storage device of the present application.

[0036] As shown in Figure 1 , the control method of the storage device of the present application includes the following steps:

[0037] S11, in response to the host sent to write data, write data to be written to the storage unit according to the target mode; wherein the target mode comprises at least the first mode and / or the second mode, the first mode comprises first with the first type of storage unit for storage, then the first type of storage unit stored in the data to the second type of storage unit; the second mode comprises directly with the second type of storage unit for storage; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit.

[0038] Wherein, the host can be a communication device capable of sending commands, such as mobile phones, tablets, computers, etc.; the data to be written can be various types of data that need to be stored, such as text, numbers, images, audio, video, etc.

[0039] In some embodiments, the storage device can include a plurality of storage units, which can be a part of the storage unit as the first type of storage unit, and the other part of the storage unit as the second type of storage unit; it can also be that a single storage unit is a first type of storage unit in one time period and a second type of storage unit in another time period, which can be set according to actual conditions.

[0040] Wherein, the first type of storage unit as a buffer area, the second type of storage unit as a normal storage area.

[0041] In some embodiments, the target mode can be separately including the first mode, or separately including the second mode, or including the first mode and the second mode.

[0042] Referring to Figure 2 , Figure 2 is a flowchart of an embodiment of step S11.

[0043] As Figure 2 shown, including:

[0044] S111, obtain the available space of the storage device.

[0045] Wherein, the available space of the storage device includes the available space of the storage unit to be stored, and determines the available space corresponding to each storage unit.

[0046] S112, in response to the available space of the storage device being greater than or equal to the preset space, write the data to be written to the storage device according to the first mode.

[0047] In order to ensure the normal operation of the first mode, a threshold value needs to be set, that is, the preset space is set, so that the data to be written is written to the storage unit in the first mode, and sufficient available space is used for caching and carrying.

[0048] Specifically, when it is detected that the available space of the storage device is greater than or equal to the preset space, the data to be written is written into the storage device according to the first mode, that is, the target mode can be the first mode alone, and then in the first mode, the host sends the data to be written to the storage device, and after the storage device receives the data to be written, the storage device stores the data to be written in the first type of storage unit in response to the action, and when the device is idle or the available bandwidth is sufficient, the data cached in the first type of storage unit is moved to the second type of storage unit, and the moving can be in the form of direct writing, that is, the data cached in the first type of storage unit is refreshed to the second type of storage unit, and the related data of the first type of storage unit is invalidated, so that more space is released.

[0049] S113, in response to the available space of the storage device being less than the preset space, the data to be written is written into the storage device according to the second mode.

[0050] Specifically, when it is detected that the available space of the storage device is less than the preset space, the data to be written is written into the storage device according to the second mode, that is, the target mode can be the second mode alone, and then in the second mode, the host sends the data to be written to the storage device, and after the storage device receives the data to be written, the storage device stores the data to be written in the second type of storage unit in response to the action, that is, directly stores the data to be written into the normal storage area.

[0051] In some embodiments, the target mode can include the first mode and the second mode, for example, in the early stage of the storage process, the available space of the storage device is greater than or equal to the preset space, and in the later stage of the storage process, the available space of the storage device is less than the preset space, that is, in the case of a large amount of data to be stored in one storage process, a mixed mode of the first mode and the second mode is adopted. Then in the case of mixing the first mode and the second mode, the available space of the storage device is compared with the preset space in real time, in the stage of the available space of the storage device being greater than or equal to the preset space, the first mode is adopted to write the data to be written into the storage device, and in the stage of the available space of the storage device being less than the preset space, the second mode is adopted to write the data to be written into the storage device.

[0052] S12, according to the target mode, the target erase-write times are counted; wherein the target erase-write times are less than the sum of the actual erase-write times of the first type of storage unit and the actual erase-write times of the second type of storage unit.

[0053] The erase-write times are the number of times of erasing and writing when the to-be-written data is written into the storage unit, and the target erase-write times are the erase-write times corresponding to the target mode when the to-be-written data is written into the storage unit according to the target mode; the actual erase-write times of the storage unit of the first type are the erase-write times when the to-be-written data is stored in the storage unit of the first type, and the actual erase-write times of the storage unit of the second type are the erase-write times when the to-be-written data is stored in the storage unit of the second type.

[0054] Specifically, after the to-be-written data is written into the storage unit according to the target mode, the target erase-write times corresponding to the target mode are counted, and the sum of the actual erase-write times of the storage unit of the first type and the actual erase-write times of the storage unit of the second type are counted. Since the target erase-write times are less than the sum of the actual erase-write times of the two types of storage units, the erase amplification is effectively reduced, and the service life of the storage device is prolonged.

[0055] For example, the capacity of the storage unit of the first type is 1 GB, the capacity of the storage unit of the second type is 3 GB, and 3 GB of to-be-written data is written into the storage unit according to the second mode. In this case, the 3 GB of to-be-written data is directly written into the storage unit of the second type by using the direct writing mode, and one erase-write is needed for the storage unit of the second type during the writing process, and the erase amplification coefficient is 1 / 1=1. When 3 GB of to-be-written data is written into the storage unit according to the first mode, the 3 GB of to-be-written data is first written into three storage units of the first type with a capacity of 1 GB, and the host end is quickly returned. When the system is idle or has sufficient bandwidth, the 3 GB of data stored in the three storage units of the first type is moved to the storage unit of the second type with a capacity of 3 GB. The storage efficiency is accelerated by storing data in the storage unit of the first type. However, each 1 GB storage unit of the first type needs to be erased and written once, and the storage unit of the second type needs to be erased and written once when the data is moved to the storage unit of the second type. Therefore, the erase-write times of the first mode are four times, and the erase amplification coefficient is 4 / 1=4. That is, the sum of the actual erase-write times of the storage unit of the first type and the actual erase-write times of the storage unit of the second type is 3+1=4, and the target erase-write times counted at present are less than 4. Therefore, the erase amplification is effectively reduced, and the service life of the storage device is prolonged.

[0056] S13, in response to the target erase-write times being greater than the erase-write times threshold, the first mode is closed.

[0057] In order to determine whether the service life of the storage unit is exhausted, it is necessary to set the erase-write times threshold.

[0058] Specifically, the erase-write times threshold is determined according to the erasable times of the storage unit in the storage device, after the data to be written is written into the storage unit according to the target mode and the target erase-write times is counted, the target erase-write times is compared with the erase-write times threshold, when the target erase-write times is greater than the erase-write times threshold, it indicates that the service life of the storage unit is exhausted, therefore, the first mode needs to be closed to end the erase-write work of the storage unit.

[0059] In the embodiment, the data to be written is written into the storage unit through the target mode including the first mode and / or the second mode, the target erase-write times is obtained, and the target erase-write times is set to be less than the sum of the actual erase-write times of the first type of storage unit and the actual erase-write times of the second type of storage unit, so as to reduce the erase amplification, that is, the control of the writing mode based on the target erase-write times can improve the writing performance of the storage device while effectively reducing the erase amplification and prolonging the service life of the storage device.

[0060] In order to further reduce the erase amplification, the wear coefficient can also be set according to the wear coefficient.

[0061] Referring to Figure 3 , Figure 3 is a flowchart of the second embodiment of the control method of the storage device in the present application.

[0062] As Figure 3 shown, the method comprises the following steps:

[0063] S21, in response to the data to be written sent by the host, the data to be written is written into the storage unit according to the target mode; wherein the target mode at least includes the first mode and / or the second mode, the first mode includes storing in the first type of storage unit first, and then migrating the data stored in the first type of storage unit to the second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the storable data amount of each first type of storage unit is less than the storable data amount of each second type of storage unit.

[0064] The same parts as the first embodiment are not described.

[0065] S22, the first wear coefficient is obtained, wherein the first wear coefficient is determined by the first error bit number corresponding to the first type of storage unit and the second error bit number corresponding to the second type of storage unit; wherein the first wear coefficient is a positive number less than 1.

[0066] The first wear-out coefficient is an internal operation parameter corresponding to the first type of storage unit for erasing and writing, used for managing the service life of the storage device and adjusting the erase amplification. In the same erasing and writing condition, the fail bit count (FBC) caused by the first type of storage unit is less than that caused by the second type of storage unit.

[0067] In some embodiments, the first wear-out coefficient can be obtained in advance in the following way.

[0068] Specifically, the first type of storage unit and the second type of storage unit are subjected to the same number of erasing and writing, and the first error bit count corresponding to the first type of storage unit and the second error bit count corresponding to the second type of storage unit are obtained respectively, and then the first wear-out coefficient is determined according to the first error bit count and the second error bit count.

[0069] As shown in FIG. 1, Figure 4 Figure 4 is a relationship diagram of the number of erasing and writing and the error bit count corresponding to the first type of storage unit and the second type of storage unit.

[0070] As shown in FIG. 1, Figure 4 , the second error bit count corresponding to the second type of storage unit is twice the first error bit count corresponding to the first type of storage unit in the same number of erasing and writing, and therefore the first wear-out coefficient is 1 / 2 = 0.5.

[0071] S23, multiplying the first wear-out coefficient and the actual number of erasing and writing of the first type of storage unit to obtain a product, and adding the product and the actual number of erasing and writing of the second type of storage unit to determine the target number of erasing and writing.

[0072] The first wear-out coefficient needs to be brought into the calculation of the target number of erasing and writing.

[0073] Specifically, the first wear-out coefficient and the actual number of erasing and writing of the first type of storage unit are multiplied to obtain a product, and the product and the actual number of erasing and writing of the second type of storage unit are added, and the obtained sum is the target number of erasing and writing.

[0074] ​Then, the first wear-out coefficient is 0.5, the actual erase-write times of the storage unit of the first type is k, the actual erase-write times of the storage unit of the second type is m, and the target erase-write times is n, then n=k*0.5+m; for example, the capacity of the storage unit of the first type is 1 GB, the capacity of the storage unit of the second type is 3 GB, the data to be written is 3 GB, when the data is written in the first mode, the actual erase-write times of the storage unit of the first type is 3, the actual erase-write times of the storage unit of the second type is 1, and the target erase-write times n=3*0.5+1=2.5, which is less than the sum of the actual erase-write times of the storage unit of the first type and the actual erase-write times of the storage unit of the second type, i.e. 4; that is, the erase amplification is modified from 4 to 2.5, which is reduced by 37.5% compared with the original 4 times of erase amplification.

[0075] S24, in response to the target erase-write times being greater than the erase-write times threshold, the first mode is closed.

[0076] The same parts as the first embodiment are not described herein.

[0077] In this embodiment, the data to be written is written into the storage unit through the target mode including the first mode and / or the second mode, the corresponding target erase-write times is obtained, the first wear-out coefficient affecting the target erase-write times is obtained, so that the target erase-write times is less than the sum of the actual erase-write times of the storage unit of the first type and the actual erase-write times of the storage unit of the second type, so as to reduce the erase amplification, that is, the control of the writing mode based on the target erase-write times can improve the writing performance of the storage device while effectively reducing the erase amplification and prolonging the service life of the storage device.

[0078] In order to further reduce the erase amplification, the wear-out coefficient can also be set according to the erase state threshold voltage and the programming state threshold voltage, so as to further reduce the erase amplification.

[0079] Referring to Figure 5 , Figure 5 is a flowchart of the third embodiment of the control method of the storage device in the present application.

[0080] As Figure 5 shown, the method comprises the following steps:

[0081] S31, in response to the data to be written sent by the host, the data to be written is written into the storage unit in the first mode with the first erase state threshold voltage and / or the first programming state threshold voltage; wherein the first erase state threshold voltage is greater than the second erase state threshold voltage corresponding to the first wear-out coefficient, and the first programming state threshold voltage is less than the second programming state threshold voltage corresponding to the first wear-out coefficient.

[0082] In the determination of the first wear-out coefficient, there are corresponding second erase state threshold voltage and second program state threshold voltage, the second erase state threshold voltage is the voltage of the erase state corresponding to the first wear-out coefficient, and the second program state threshold voltage is the voltage of the program state corresponding to the first wear-out coefficient.

[0083] Because the number of error bits increases with the increase of the number of erase-write times, the reason is that the electron tunneling causes the degradation of the tunneling oxide layer of the storage unit, and the degradation degree depends on the electron tunneling rate.

[0084] Referring to Figure 6 and Figure 7 , Figure 6 is a schematic diagram of threshold voltages corresponding to the first type of storage unit and the second type of storage unit in the prior art; Figure 7 is a schematic diagram of threshold voltages corresponding to the first type of storage unit in the third embodiment of the present application.

[0085] As shown in Figure 6 , the program state (L1-L7) threshold voltage of the first type of storage unit is high, and the erase state (L0) threshold voltage is low, so the amount of electron tunneling is high, and the loss to the storage unit is also high; as shown in Figure 7 , the threshold voltage corresponding to the first type of storage unit in the prior art is SLC, and the threshold voltage corresponding to the first type of storage unit in the third embodiment is the optimized SLC, and as Figure 7 can be seen, the read window corresponding to the optimized SLC is smaller than the read window of SLC.

[0086] In some embodiments, the first erase state threshold voltage is 0.2-0.3V higher than the second erase state threshold voltage, and the first program state threshold voltage is 0.2-0.3V lower than the second program state threshold voltage, for example, the range of the second erase state threshold voltage is 0-0.5V, the range of the second program state threshold voltage is 2.0-2.5V, the range of the first erase state threshold voltage is 0.2-0.8V, and the range of the first program state threshold voltage is 1.8-2.2V.

[0087] S32, obtaining a second wear-out coefficient, wherein the second wear-out coefficient is determined by the first erase state threshold voltage and / or the first program state threshold voltage, and the second wear-out coefficient is less than the first wear-out coefficient.

[0088] In which, the erase state threshold voltage and the wear-out coefficient are negatively correlated, and the program state threshold voltage and the wear-out coefficient are positively correlated; the first wear-out coefficient is determined by the first error bit number corresponding to the first type of storage unit and the second error bit number corresponding to the second type of storage unit; the first wear-out coefficient is a positive number less than 1.

[0089] Specifically, the first erase state threshold voltage greater than the second erase state threshold voltage and / or the first program state threshold voltage less than the second program state threshold voltage can achieve the goal of lower electron tunneling amount, so that the second wear-out coefficient corresponding to the first erase state threshold voltage and / or the first program state threshold voltage is less than the first wear-out coefficient, that is, the second wear-out coefficient is less than 0.5, thus further reducing erase amplification and improving the service life of the storage device.

[0090] S33, determine the product of the second wear-out coefficient and the actual erase-write times of the storage unit of the first type, and determine the sum of the product and the actual erase-write times of the storage unit of the second type as the target erase-write times.

[0091] S34, in response to the target erase-write times being greater than the erase-write times threshold, turn off the first mode.

[0092] The same parts as the first and second embodiments are not repeated.

[0093] In this embodiment, by increasing the erase state threshold voltage and / or reducing the program state threshold voltage, the electron tunneling amount is reduced, and the corresponding second wear-out coefficient is also less than the first wear-out coefficient, further reducing erase amplification and improving the service life of the storage device.

[0094] In order to further reduce the erase amplification, the wear-out coefficient can also be set according to the erase starting voltage and the program starting voltage, thereby reducing the erase amplification.

[0095] Referring to Figure 8 , Figure 8 is a flowchart of the fourth embodiment of the control method of the storage device in the present application.

[0096] As Figure 8 shown, the method comprises the following steps:

[0097] S41, in response to the data to be written sent by the host, write the data to be written into the storage unit according to the first mode based on the first erase starting voltage and / or the first program starting voltage; wherein the first erase starting voltage is less than the second erase starting voltage corresponding to the first wear-out coefficient, and the first program starting voltage is less than the second program starting voltage corresponding to the first wear-out coefficient.

[0098] Wherein, in the conversion process between the program state and the erase state, multiple pulses are required; when determining the first wear-out coefficient, there are corresponding second erase state threshold voltage, second program state threshold voltage, second erase starting voltage and second program starting voltage, the second erase starting voltage is the starting voltage corresponding to the first wear-out coefficient from the program state to the erase state, and the second program starting voltage is the starting voltage corresponding to the first wear-out coefficient from the erase state to the program state.

[0099] The lower erase starting voltage and / or program starting voltage can reduce the degradation speed of the tunnel oxide layer of the memory cell, which depends on the electron tunneling rate. The higher the erase starting voltage and the program starting voltage, the higher the electron tunneling rate, and the higher the damage to the memory cell.

[0100] S42, a third wear-out coefficient is obtained, wherein the third wear-out coefficient is determined by the first erase starting voltage and / or the first program starting voltage, and wherein the third wear-out coefficient is less than the first wear-out coefficient.

[0101] The erase starting voltage and the program starting voltage are positively correlated with the wear-out coefficient. The first wear-out coefficient is determined by the first number of error bits corresponding to the memory cells of the first type and the second number of error bits corresponding to the memory cells of the second type. The first wear-out coefficient is a positive number less than 1.

[0102] Therefore, the first erase starting voltage less than the second erase starting voltage and / or the first program starting voltage less than the second program starting voltage can achieve the goal of reducing the electron tunneling rate, so that the third wear-out coefficient corresponding to the first erase starting voltage and / or the first program starting voltage is less than the first wear-out coefficient, i.e., the third wear-out coefficient is less than 0.5. Therefore, the erase amplification is further reduced, and the service life of the storage device is improved.

[0103] S43, a product of the third wear-out coefficient and the actual erase-write times of the memory cells of the first type is determined, and a sum of the product and the actual erase-write times of the memory cells of the second type is determined as the target erase-write times.

[0104] S44, in response to the target erase-write times being greater than the erase-write times threshold, the first mode is turned off.

[0105] The same parts as the first embodiment and the second embodiment are not described again.

[0106] In some embodiments, the first erase state threshold voltage and the first program state threshold voltage can also be used while the first erase starting voltage and the first program starting voltage are used, so that the corresponding wear-out coefficient is further reduced, and the erase amplification is further reduced, and the service life of the storage device is improved.

[0107] In this embodiment, by reducing the erase starting voltage and / or the program starting voltage, the electron tunneling rate is reduced, and the corresponding third wear-out coefficient is less than the first wear-out coefficient, and the erase amplification is further reduced, and the service life of the storage device is improved.

[0108] In order to further reduce the erase amplification, the wear-out coefficient can also be set according to the erase step value and the program step value, and the erase amplification is further reduced.

[0109] Referring to Figure 9 , Figure 9 is a flowchart of a fifth embodiment of a control method of a storage device in the present application.

[0110] As Figure 9 shown, comprising the following steps:

[0111] S51, in response to the host sent to be written data, according to the first mode, with the first erase step value and / or the first programming step value to be written data is written into the storage unit; wherein, the first erase step value is less than the first wear coefficient corresponding to the second erase step value, the first programming step value is less than the first wear coefficient corresponding to the second programming step value.

[0112] Wherein, in the conversion process of programming state and erase state, the need for multiple pulse; in determining the first wear coefficient, there is corresponding second erase threshold voltage, second programming threshold voltage, second erase starting voltage, second programming starting voltage, second erase step value and second programming step value, the second erase step value is the first wear coefficient corresponding to the voltage difference between the adjacent pulse from programming state to erase state, the second programming step value is the first wear coefficient corresponding to the voltage difference between the adjacent pulse from erase state to programming state.

[0113] Degradation speed depends on the electron tunneling rate, erase step value and programming step value is high, the high electron tunneling amount, the loss caused by the storage unit is also higher; lower erase step value and / or programming step value, can reduce the storage unit tunneling oxide layer degradation speed.

[0114] S52, the fourth wear coefficient is obtained, wherein, the fourth wear coefficient is determined by the first erase step value and / or the first programming step value, wherein, the fourth wear coefficient is less than the first wear coefficient.

[0115] Wherein, the erase step value and the wear coefficient is positive correlation, the programming step value and the wear coefficient is positive correlation; the first wear coefficient is determined by the first type of storage unit corresponding to the first error bit number and the second type of storage unit corresponding to the second error bit number; the first wear coefficient is a positive number less than 1.

[0116] Therefore, to a first erase step value less than the second erase step value and / or a first programming step value less than the second programming step value, can achieve the goal of lower electron tunneling amount, so that the first erase step value and / or the first programming step value corresponding to the fourth wear coefficient is less than the first wear coefficient, that is, the fourth wear coefficient is less than 0.5, therefore, further reduces the erase amplification, improves the life of the storage device.

[0117] S53, determining a product of the fourth wear-out coefficient and the actual erase-write times of the storage unit of the first type, and determining a sum of the product and the actual erase-write times of the storage unit of the second type as the target erase-write times.

[0118] S54, in response to the target erase-write times being greater than the erase-write times threshold, turning off the first mode.

[0119] The same parts as the first and second embodiments are not repeated.

[0120] In some embodiments, the first erase-state threshold voltage and the first program-state threshold voltage can also be adopted while the first erase step value and the first program step value are adopted, so that the corresponding wear-out coefficient is further reduced, and the erase amplification is further reduced, and the life of the storage device is improved.

[0121] In other embodiments, the first erase starting voltage and the first program starting voltage can also be adopted while the first erase step value and the first program step value are adopted, so that the corresponding wear-out coefficient is further reduced, and the erase amplification is further reduced, and the life of the storage device is improved.

[0122] In still other embodiments, the first erase starting voltage, the first program starting voltage, the first erase-state threshold voltage and the first program-state threshold voltage can also be adopted while the first erase step value and the first program step value are adopted, so that the corresponding wear-out coefficient is further reduced, and the erase amplification is further reduced, and the life of the storage device is improved.

[0123] In the present embodiment, by reducing the erase step value and / or the program step value, the electron tunneling amount is reduced, and the corresponding fourth wear-out coefficient is also less than the first wear-out coefficient, the erase amplification is further reduced, and the life of the storage device is improved.

[0124] In order to represent the entire writing process, the following Figure 10 is represented.

[0125] Figure 10 is the principle flowchart of writing data to be written into the storage unit in the present application.

[0126] As Figure 10As shown, the target number of erase / write cycles is set to n, the total number of erase / write cycles of the storage device is N, the number of erase / write cycles for the first type of storage cell is k, the number of erase / write cycles for the second type of storage cell is m, and the wear factor is a. When writing data begins, Cycle n = 0, SLC cycle k = 0, TLC cycle m = 0, and the entire storage device is written to once. If the first mode is used for writing, i.e., SLC mode, then k = K + 1, m = m, and the target number of erase / write cycles is n = k * a + m. When n is greater than N, the flash memory block corresponding to the storage cell has exhausted its lifespan, and the WriteBooster function is turned off, i.e., the first mode is turned off. If the second mode is used for writing, then k = k, m = m + 1, and the target number of erase / write cycles is n = k * a + m.

[0127] See Figure 11 , Figure 11 This is a schematic diagram of the structure of an embodiment of the storage device of this application.

[0128] like Figure 11 As shown, the storage device 600 includes a processor 610 and a storage unit 620. The processor 610 is coupled to the storage unit 620 and the host, and executes instructions during operation to implement the aforementioned control method for the storage device.

[0129] See Figure 12 , Figure 12 This is a schematic diagram of the structure of an embodiment of the electronic device of this application.

[0130] like Figure 12 As shown, the electronic device 70 includes a processing device 71 and a storage device 600. The processor is coupled to the storage device 600 and executes instructions during operation to implement the above-mentioned control method for the storage device.

[0131] The above technical solution provides a control method of a storage device, in response to the to-be-written data sent by a host, the to-be-written data is written into a storage unit according to a target mode; wherein the target mode at least includes a first mode and / or a second mode, the first mode includes storing in a first type of storage unit first, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit; the target erase-write times are counted according to the target mode; wherein the target erase-write times are less than the sum of the actual erase-write times of the first type of storage unit and the actual erase-write times of the second type of storage unit; in response to the target erase-write times being greater than an erase-write times threshold, the first mode is closed. That is, in the present application, the to-be-written data is written into the storage unit through the target mode including the first mode and / or the second mode, the corresponding target erase-write times are obtained, and the target erase-write times are set to be less than the sum of the actual erase-write times of the first type of storage unit and the actual erase-write times of the second type of storage unit, so as to reduce erase amplification, that is, the control of the writing mode is based on the target erase-write times, which can improve the writing performance of the storage device, effectively reduce erase amplification, and prolong the service life of the storage device.

[0132] In several embodiments provided in the present application, it should be understood that the disclosed storage device, electronic device and method can be implemented in other manners. For example, the above described embodiments are merely schematic. Taking the division of the modules or units as an example, the division can be changed in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0133] The above only describes the embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation based on the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A control method of a storage device, characterized by, The method comprises: writing, in response to data to be written sent by a host, the data to be written into storage units according to a target mode; wherein the target mode comprises at least a first mode and / or a second mode, the first mode comprises storing first type storage units first and then migrating data stored in the first type storage units to second type storage units, and the second mode comprises directly storing second type storage units; wherein the amount of data that can be stored in each first type storage unit is less than the amount of data that can be stored in each second type storage unit; counting a target erase-write number according to the target mode; wherein the target erase-write number is less than the sum of the actual erase-write number of the first type storage units and the actual erase-write number of the second type storage units; in response to the target erase-write number being greater than an erase-write number threshold, closing the first mode.

2. The control method according to claim 1, wherein: the counting of the target erase-write number according to the target mode comprises: obtaining a first wear-out coefficient, wherein the first wear-out coefficient is determined by a first error bit number corresponding to the first type storage units and a second error bit number corresponding to the second type storage units; wherein the first wear-out coefficient is a positive number less than 1; determining the product of the first wear-out coefficient and the actual erase-write number of the first type storage units, and determining the sum of the product and the actual erase-write number of the second type storage units as the target erase-write number.

3. The control method according to claim 2, wherein: the first wear-out coefficient is obtained by: performing the same number of erase-writes on the first type storage units and the second type storage units to obtain the first error bit number corresponding to the first type storage units and the second error bit number corresponding to the second type storage units; and determining the first wear-out coefficient according to the first error bit number and the second error bit number.

4. The control method according to claim 1, wherein: the writing of the data to be written into storage units according to a target mode comprises: writing, in a first mode, the data to be written into storage units using a first erase state threshold voltage and / or a first programming state threshold voltage; wherein the first erase state threshold voltage is greater than a second erase state threshold voltage corresponding to a first wear-out coefficient, and the first programming state threshold voltage is less than a second programming state threshold voltage corresponding to the first wear-out coefficient; the counting of a target erase-write number according to the target mode comprises: obtaining a second wear-out coefficient, wherein the second wear-out coefficient is determined by the first erase state threshold voltage and / or the first programming state threshold voltage; wherein the second wear-out coefficient is less than the first wear-out coefficient; the first wear-out coefficient is determined by a first error bit number corresponding to the first type storage units and a second error bit number corresponding to the second type storage units; and the first wear-out coefficient is a positive number less than 1. determining a product of the second wear-out coefficient and the actual erase-write times of the storage cells of the first type, and determining a sum of the product and the actual erase-write times of the storage cells of the second type as the target erase-write times.

5. The control method according to claim 4, wherein the first erase state threshold voltage is higher than the second erase state threshold voltage by 0.2-0.3V, and the first program state threshold voltage is lower than the second program state threshold voltage by 0.2-0.3V.

6. The control method according to claim 1, wherein the writing of the data to be written into the storage cells according to the target mode comprises: writing the data to be written into the storage cells according to a first mode based on a first erase starting voltage and / or a first program starting voltage, wherein the first erase starting voltage is lower than a second erase starting voltage corresponding to a first wear-out coefficient, and the first program starting voltage is lower than a second program starting voltage corresponding to the first wear-out coefficient; the counting of the target erase-write times according to the target mode comprises: obtaining a third wear-out coefficient, wherein the third wear-out coefficient is determined by the first erase starting voltage and / or the first program starting voltage, and the third wear-out coefficient is lower than the first wear-out coefficient, and the first wear-out coefficient is determined by a first number of error bits corresponding to the storage cells of the first type and a second number of error bits corresponding to the storage cells of the second type, and the first wear-out coefficient is a positive number lower than 1; determining a product of the third wear-out coefficient and the actual erase-write times of the storage cells of the first type, and determining a sum of the product and the actual erase-write times of the storage cells of the second type as the target erase-write times.

7. The control method according to claim 1, wherein the writing of the data to be written into the storage cells according to the target mode comprises: writing the data to be written into the storage cells according to a first mode based on a first erase step value and / or a first program step value, wherein the first erase step value is lower than a second erase step value corresponding to a first wear-out coefficient, and the first program step value is lower than a second program step value corresponding to the first wear-out coefficient; the counting of the target erase-write times according to the target mode comprises: obtaining a fourth wear-out coefficient, wherein the fourth wear-out coefficient is determined by the first erase step value and / or the first program step value, and the fourth wear-out coefficient is lower than the first wear-out coefficient, and the first wear-out coefficient is determined by a first number of error bits corresponding to the storage cells of the first type and a second number of error bits corresponding to the storage cells of the second type, and the first wear-out coefficient is a positive number lower than 1; determining a product of the fourth wear-out coefficient and the actual erase-write times of the storage cells of the first type, and determining a sum of the product and the actual erase-write times of the storage cells of the second type as the target erase-write times.

8. The control method according to claim 1, wherein the writing of the data to be written into the storage cells according to the target mode comprises: acquiring available space of the storage device, wherein the storage device comprises a plurality of storage units; in response to the available space of the storage device being greater than or equal to a preset space, writing the to-be-written data into the storage device according to the first mode; or in response to the available space of the storage device being less than the preset space, writing the to-be-written data into the storage device according to the second mode.

9. A storage device, comprising: The storage device comprises a processor and a storage unit, the processor is coupled with the storage unit and a host end, and in operation, the processor executes instructions to implement the control method according to any one of claims 1 to 8.

10. An electronic device, comprising: The storage device comprises a processor and a storage unit, the processor is coupled with the storage unit and a host end, and in operation, the processor executes instructions to implement the control method according to any one of claims 1 to 8.

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