Computing system and method of correlator supporting three levels

Abstract

The invention relates to the technical field of communication system design, is also applicable to a 7 * 7 basic arithmetic unit applied to a convolutional neural network, and discloses a computing system and method of correlators supporting three levels, and the system comprises the following steps: configuring eight paths of identical correlators on one side of a receiver; the receiver locally stores a three-level local code with a preset length, and moves the received signal into a shift register with the same length as the preset length; the shift register stores a signal with the same length as the preset length as an input signal; the correlator performs selection and XOR operation on the local code and the input signal to obtain a multiplication result; according to the invention, the three-level local codes stored by the receiver and the input signals stored by the shift register are subjected to selection and XOR operation through the correlator supporting the three levels, so that the consumption of hardware resources is reduced, and the performance of the receiver is improved. And a counter is adopted to accumulate and sum all multiplication results, so that the consumption of hardware resources is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of communication system design, and is also applicable to a 7x7 basic operation unit applied to a convolutional neural network, and specifically to a computing system and method supporting a three-level correlator. Background Art

[0002] In the design of communication systems based on the spread spectrum principle, the design of the receiver's correlator is an important part of the receiving process. The correlator needs to complete the following tasks:

[0003] Assume that the local spreading code length is N, and the local spreading code sequence is: C n , n=0,1,2,...,N-1.

[0004] The receiver has a shift register of length N, which stores the latest received sampling point: S n , n=0,1,2,...,N-1.

[0005] The relevant operations are:

[0006] The above-mentioned related operations are required in multiple stages of the receiving process of the spread spectrum receiver.

[0007] In the capture phase, the received signal needs to be captured by the chip phase, and the corresponding chip phase is the position where the receiver's local code phase and the received signal's code phase are aligned. Assuming the signal spread spectrum sequence length is N, and the signal is sampled twice, there are 2N code phases in one spread spectrum sequence period, that is, 2N correlation operations of N sampling points are required to complete the maximum value search and capture on a code phase.

[0008] In the signal tracking stage, in order to achieve tracking on the code phase, it is necessary to output the correlation results of at least two code phases around the maximum code phase to complete the phase detection and loop tracking of the code phase.

[0009] In applications based on ultra-wideband receivers, the receiver needs to always maintain channel estimation within the entire chip length range, that is, the correlation operation of the code phase of a certain window length must be completed during the entire receiving process.

[0010] In the above applications, especially in the capture phase, the receiver needs to complete the correlation operation of N sampling points every time a new sampling point is received, which places high demands on hardware resources. Therefore, how to optimize the correlator so that it occupies as little hardware resources as possible has become an urgent problem to be solved. Summary of the invention

[0011] In view of this, the present invention provides a computing system and method supporting a three-level correlator to solve the problem of occupying as few hardware resources as possible.

[0012] In a first aspect, the present invention provides a computing system supporting a three-level correlator, the system comprising: a receiver, a correlator, a shift register and a (7, 3) counter, wherein:

[0013] 8 identical correlators are configured on the receiver side for parallel processing;

[0014] The receiver locally stores a three-level local code of a preset length, and shifts the received signal into a shift register having the same length as the preset length;

[0015] The shift register stores a signal having the same length as the preset length as an input signal;

[0016] The correlator selects and performs an XOR operation on the local code and the input signal to obtain a multiplication result;

[0017] The (7, 3) counter is used to perform a sum operation on all multiplication results to obtain a calculation result.

[0018] The present invention adopts a correlator supporting three levels to select and perform an XOR operation on the three-level local code stored in the receiver and the input signal stored in the shift register, thereby replacing the direct multiplication of the three-level local code and the input signal, reducing the consumption of hardware resources, and adopts a (7, 3) counter to accumulate and sum all multiplication results, so as to further reduce the consumption of hardware resources by the correlator.

[0019] In a second aspect, the present invention provides a calculation method for a correlator supporting three levels, the method comprising:

[0020] Perform selection and exclusive OR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result;

[0021] The (7, 3) counter is used to sum all the multiplication results to obtain the calculation result.

[0022] The present invention adopts a correlator supporting three levels to select and perform an XOR operation on the three-level local code stored in the receiver and the input signal stored in the shift register, thereby replacing the direct multiplication of the three-level local code and the input signal, reducing the consumption of hardware resources, and adopts the addition of a (7, 3) counter to accumulate and sum all multiplication results, so as to further reduce the consumption of hardware resources by the correlator.

[0023] In an optional implementation manner, the selecting and XORing the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result includes:

[0024] When the amplitude bit of the local code is zero, the multiplication result is 4'b0000;

[0025] When the amplitude bit of the local code is one, the sign bit of the local code is XORed with the bit of the input signal, and when the sign bit of the local code is one, the multiplication result is the addition result of the XOR result and 1'b1.

[0026] The present invention selects and performs an XOR operation on a three-level local code and an input signal to replace the existing multiplication operation, thereby reducing the consumption of hardware resources.

[0027] In an optional implementation, performing an XOR operation on the sign bit of the local code and the bit bit of the input signal includes:

[0028] Expanding the sign bit of the local code to a 4-bit signal;

[0029] Perform an XOR operation on the 4-bit signal and the 4-bit input signal bit by bit.

[0030] The present invention expands the sign bit of the local code and performs an XOR operation on the 4-bit signal and the 4-bit input signal bit by bit, so that before the local code and the input signal are selected and XORed, the local code and the input signal have the same number of bits, which facilitates the selection and XOR operation of the local code and the input signal.

[0031] In an optional implementation manner, the method of using a (7, 3) counter to sum all multiplication results to obtain a calculation result includes:

[0032] Put all the multiplication results into groups of seven and calculate the sum of each bit separately;

[0033] According to the position of the bit, the calculated sum of each bit is shifted and added, and the accumulated sum is determined as the calculation result.

[0034] The present invention sums up the multiplication results in groups of seven, and then performs shift and addition operations on the sum of each bit obtained, thereby replacing the existing hierarchical sequential addition method, thereby reducing resource consumption and solving the problem of tight timing.

[0035] In an optional implementation, before using the (7, 3) counter to perform a sum operation on all multiplication results to obtain a calculation result, the method further includes:

[0036] Perform the two's complement to original code conversion operation on all multiplication results;

[0037] According to the maximum length supported by the correlator, the result of the complement code conversion operation is padded with zeros.

[0038] The present invention performs a complement-to-original code conversion operation on the multiplication result to meet the requirement that the input data is in the original code format. According to the maximum length supported by the correlator, the complement-to-original code conversion operation result is padded with zeros, and the operation result is expanded to ensure the length consistency of all data, so as to facilitate subsequent data processing.

[0039] In a third aspect, the present invention provides a computing device supporting a three-level correlator, the device comprising:

[0040] The first calculation module is used to select and perform an XOR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result;

[0041] The second calculation module is used to use the (7, 3) counter to perform a sum operation on all multiplication results to obtain a calculation result.

[0042] In a fourth aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the calculation method of a correlator supporting three levels according to the second aspect or any corresponding embodiment thereof by executing the computer instructions.

[0043] In a fifth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the calculation method for a correlator supporting three levels according to the second aspect or any corresponding embodiment thereof.

[0044] In a sixth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the calculation method for a correlator supporting three levels according to the second aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1is an overall framework of a correlator in a computing system supporting a three-level correlator according to an embodiment of the present invention;

[0047] Figure 2 is a flow chart of a calculation method of a correlator supporting three levels according to an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of a multiplication process of a signal and code multiplication unit according to an embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of a summing process based on a summing method of a (7, 3) counter according to an embodiment of the present invention;

[0050] Figure 5 is a schematic diagram of a summing process based on another summing method of a (7, 3) counter according to an embodiment of the present invention;

[0051] Figure 6 is a schematic diagram of a functional module of a (7, 3) counter according to an embodiment of the present invention;

[0052] Figure 7 is a schematic diagram of an implementation process of a (7, 3) counter according to an embodiment of the present invention;

[0053] Figure 8 is a schematic diagram of another implementation process of the (7, 3) counter according to an embodiment of the present invention

[0054] Fig. 9 is a schematic diagram of an optimization solution for a (7, 3) counter of an FPGA according to an embodiment of the present invention;

[0055] Fig.10 is a structural block diagram of a computing device supporting a three-level correlator according to an embodiment of the present invention;

[0056] Fig.11 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0058] In related operations, there are two forms of local codes. One is a 2-level code, that is, the local code has only two values ​​0 and 1, which can be represented by 1 bit. The other is a 3-level code, that is, the local code has three values ​​-1, 0, and +1. For this 3-level code, only 2 bits can be used to represent it, where the high bit represents the sign bit and the low bit represents the amplitude bit. The mapping relationship is as follows:

[0059] Local Code Mapping Bits -1 11 0 00 +1 01

[0060] Obviously, if three-level codes are used, the hardware resource usage of the correlator will increase significantly. In the fields of pulse radar, pulse ultra-wideband receiver, etc., due to the existence of 0 values ​​in the local code, designing a correlator that supports three levels becomes a necessary requirement.

[0061] A three-level code requires 2 bits to represent a code. Compared with a two-level code that only requires 1 bit to represent, the hardware scale of subsequent multiplication and addition operations will increase by about 1 times. To this end, an embodiment of the present invention provides a computing system that supports a three-level correlator, which is suitable for a 7x7 basic computing unit applied to a convolutional neural network. The system includes: a receiver, a correlator, a shift register, and a (7, 3) counter.

[0062] For high-speed sampling receiving systems, the sampling frequency of the input signal to the correlator is often much higher than the working clock. Each working clock needs to process 8 output sampling points, that is, it is necessary to implement 8 correlation operations with a length of N points and output 8 code phase correlation results. Therefore, on the receiver side, 8 completely identical correlators need to be configured for parallel processing. The implementation of the 8 correlators required for each working clock is exactly the same, such as Figure 1 As shown, Figure 1 The figure is a schematic diagram of the overall block diagram of one of the correlators.

[0063] The receiver locally stores a local code of length N, which is a three-level code. The received signal is shifted into a shift register of length N. The shift register stores a signal of length N as the input signal. The operation of the correlator is to select and perform an XOR operation on the local code of length N and the input signal of length N stored in the shift register to obtain N 4-bit multiplication results M. n , using addition based on (7, 3) counter, for N multiplication results M n Sum them and get the calculation result.

[0064] The three-level correlator can support both direct sequence spread spectrum and pulse sequence spread spectrum spread spectrum systems, and can support coherent reception of pulse radar by configuring a local chip sequence.

[0065] By adopting a correlator supporting three levels, the three-level local code stored in the receiver and the input signal stored in the shift register are selected and XORed, replacing the direct multiplication of the three-level local code and the input signal, thereby reducing the consumption of hardware resources. A (7, 3) counter is used to accumulate and sum all multiplication results, so as to further reduce the consumption of hardware resources by the correlator.

[0066] According to an embodiment of the present invention, an embodiment of a calculation method supporting a three-level correlator is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0067] In this embodiment, a calculation method for a correlator supporting three levels is provided, which is executed by the correlator. Figure 2 is a flow chart of a calculation method of a correlator supporting three levels according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0068] Step S201, performing a selection and exclusive OR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result.

[0069] In the embodiment of the present invention, the three-level local code C stored in the receiver n , the shift register stores the input signal S n , the correlator is used for the local code C n and the 4-bit quantized input signal S n Perform selection and XOR operation to obtain N 4-bit multiplication results M n .

[0070] Step S202, using the (7, 3) counter to perform a sum operation on all multiplication results to obtain a calculation result.

[0071] In the embodiment of the present invention, a (7, 3) counter is used to implement the multiplication of N 4-bit results M n =C n ×S n The embodiment of the present invention adopts a combination of several (7, 3) counters to replace the existing summation operation. Since the (7, 3) counter can be implemented using four 1-bit full adders, the consumption of hardware resources can be reduced to the maximum extent.

[0072] The calculation method of the correlator supporting three levels provided in this embodiment uses a correlator supporting three levels to select and perform an XOR operation on the three-level local code stored in the receiver and the input signal stored in the shift register, thereby replacing the direct multiplication of the three-level local code and the input signal, thereby reducing the consumption of hardware resources, and using the addition of a (7, 3) counter to accumulate and sum all multiplication results, thereby further reducing the consumption of hardware resources by the correlator.

[0073] In this embodiment, a calculation method for a correlator supporting three levels is provided, and the process includes the following steps:

[0074] Step S301, performing a selection and exclusive OR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result.

[0075] Specifically, the above step S301 includes:

[0076] Step S3011, when the amplitude bit of the local code is zero, the multiplication result is 4'b0000.

[0077] Step S3012, when the amplitude bit of the local code is 1, perform an XOR operation on the sign bit of the local code and the bit of the input signal, and when the sign bit of the local code is 1, the multiplication result is the addition result of the XOR operation result and 1'b1.

[0078] In the embodiment of the present invention, the first step of the correlator is to realize the multiplication of the input signal and the three-level local code. The embodiment of the present invention adopts the selection and XOR operation to realize the multiplication of each input signal and the three-level local code. The implementation block diagram is as follows: Figure 3 shown.

[0079] First, the input signal 4bit signal S n With 2-bit local code C n Perform multiplication operation, the result of multiplication is 4-bit X n , the embodiment of the present invention converts the multiplication operation into a selective XOR operation, that is, when the local code C n When the amplitude bit is 0, the multiplication result is 4'b0000, and 4'b0000 is directly output; when the local code C n When the amplitude bit is 1, the multiplication operation is converted into an XOR operation, and the local code C n The sign bit is respectively related to the input signal S n The four bits of the XOR operation are performed, and when the local code C n When the sign bit of is 1, add 1'b1 to the XOR operation result to get the multiplication result X n .

[0080] The existing multiplication operation is replaced by selecting and performing an XOR operation on the three-level local code and the input signal, so as to reduce the consumption of hardware resources.

[0081] Specifically, the above step S3012 includes:

[0082] Step S30121, expanding the sign bit of the local code to a 4-bit signal.

[0083] Step S30122, performing an XOR operation on the 4-bit signal and the 4-bit input signal bit by bit.

[0084] In the embodiment of the present invention, since the input signal S n 4-bit signal, local code C n is a 2-bit signal. When the local code C n When the amplitude bit of the spread spectrum code sequence is 1, the multiplication operation is converted into an XOR operation, and the local code C n The sign bit is extended to 4 bits {~C n1 ,C n1 ,C n1 ,C n1}, and then bitwise AND the input signal S n The 4 bits are XORed and finally converted into the original code.

[0085] Since the scheme requires the input data to be in the original code format, but the actual input data is in the complement code format, in the first step of the summation operation, the N multiplication results are converted from the complement code format to the original code format.

[0086] By expanding the sign bit of the local code, the 4-bit signal is bit-wise XORed with the 4-bit input signal, so that before the local code and the input signal are selected and XORed, the number of bits of the local code and the input signal are made the same, which facilitates the selection and XOR operation of the local code and the input signal.

[0087] Step S302, performing a two's complement to original code conversion operation on all multiplication results.

[0088] Step S303: pad the result of the complementary code conversion operation with zeros according to the maximum length supported by the correlator.

[0089] In the embodiment of the present invention, the N multiplication results are subjected to a two's complement to original code conversion operation:

[0090]

[0091] Since the maximum length N supported by the correlator is 1024, when summing, the N multiplication results are first The tail of is padded with 0, and the value is expanded to 1029=7×7×3.

[0092] The correlator performs a summation operation based on a (7, 3) counter on 1029 4-bit data. After the calculation is completed, a K value is subtracted to convert the original code result into a complement code, where K=1029×8.

[0093] After completing the above operations, since the above-mentioned XOR operation is used instead of multiplication, only the inversion operation is performed on the local code of -1, and the actual multiplication of negative numbers is to invert the original value and add 1. Therefore, each local code of -1 here will be less by one 1. Therefore, these 1s are added back in the final sum result at once, that is, a number L needs to be added, and the value of L that needs to be added is the number of -1 in the local code.

[0094] Right now:

[0095] It should be noted that in order to optimize the above process, the multiplication operation and the operation of converting the complement code to the original code are combined, that is, adding 4'b1000, to unify them to reduce resource usage. Therefore, the actual process of the operation is: when the local code C n When the amplitude bit is 0, directly output 4'b1000; when the local code C n When the amplitude bit is 1, the multiplication operation is converted into an XOR operation, and C n The sign bit is extended to 4 bits {~C n1 ,C n1 ,C n1 ,C n1}, bitwise AND S n The four bits of the XOR operation are performed, and finally the original code is converted to the original code minus 1029*4'b1000. n When the sign bit of is 1, the operation of adding 1'b1 to the XOR result is performed together. Let the result of the sum after (7, 3)-counter be SUM, and the number of -1 in the spread spectrum code sequence be NEG_NUM. The actual cumulative sum is:

[0096] S=SUM-1029*4'b1000+NEG_NUM

[0097] In addition, if there are multiple channels for parallel processing, for C n1 The inversion operation can be processed uniformly before being sent to each channel. Input {~C n1 ,C n1 ,C n0} to each channel; similarly, the number of -1 NEG_NUM in the frequency code sequence can also be calculated uniformly before being sent to each channel, and then input into each channel. Finally, each channel performs its own selection and conversion to the original code. This process can minimize resource usage.

[0098] The multiplication result is converted to the original code by performing a complement-code conversion operation to meet the requirement that the input data is in the original code format. According to the maximum length supported by the correlator, the complement-code conversion operation result is padded with zeros and the operation result is expanded to ensure the length consistency of all data, so as to facilitate subsequent data processing.

[0099] Step S304: Use the (7, 3) counter to perform a sum operation on all multiplication results to obtain a calculation result.

[0100] Specifically, the above step S304 includes:

[0101] Step S3041, group all the multiplication results into groups of seven and calculate the sum of each bit.

[0102] Step S3042, shift and add the calculated sum of each bit according to the position of the bit, and determine the accumulated sum as the calculation result.

[0103] In the embodiment of the present invention, after the correlator performs the XOR operation, it is necessary to use the (7, 3) counter to accumulate and sum all the multiplication results. The length of the accumulation operation is 1024. If the 4-bit X is hierarchically summed according to the existing method, n Adding them one by one will consume a lot of resources and have a tight time sequence. Therefore, a summation method based on (7, 3)-counter is adopted. The main function of the summation based on (7, 3)-counter is to accumulate the multiplication results after N XORs together. In the embodiment of the present invention, a 4-stage pipeline method is adopted, and its block diagram is as follows: Figure 5 As shown. The following is an example of an accumulation operation length of 1024, with a total of 4 levels, to achieve the addition of 1029 numbers. For the accumulation of 1023 numbers, the last few local codes are set to 0.

[0104] For 4-bit X with a length of 1024 n Calculate the sum of each bit in groups of 7. After calculating the sum, shift the bits according to their positions and then add them up to get the cumulative sum.

[0105] First, add 7 1-bit numbers to get a maximum value of 3 bits, specifically:

[0106] 1'b1+1'b1+1'b1+1'b1+1'b1+1'b1+1'b1=3'b111

[0107] Therefore, no bits are wasted in the addition operation.

[0108] Specifically, there are the following two accumulation schemes based on the addition of the (7, 3) counter.

[0109] The first option is Figure 4 As shown, the descriptions of the 4-level pipeline are as follows:

[0110] First level: sum of 7 4-bit numbers, the maximum value is 15*105, that is, 7'b1101001, and the output is 7 bits;

[0111] Second level: sum of 7 7-bit numbers, the maximum value is: 105*7=735, that is, 10'b1011011111, the output is 10 bits;

[0112] Level 3: Sum 7 10-bit numbers, the maximum value is: 735*7=5145, that is, 13'1010000011001, the output is 13 bits;

[0113] Fourth level: sum of 3 13 bits, the maximum value is: 5145*3=15435, that is, 15'11110001001011, and the output is 15 bits.

[0114] The second option is Figure 5 As shown, 7 single bits are added vertically, and finally X is obtained by shift addition. n The cumulative sum can maximize the use of data resources. Since the minimum cumulative unit is 7, to calculate the accumulation of 1024 lengths, 7*7*7*3=1029 lengths are used. The part exceeding 1024 is C n Set to 2'b00, one of the calculation units is 7*7*7=343. Because the final shift addition involves the problem of sign bit extension, the 1029-length S n Convert the complement code to the original code by adding 4'b1000, and then subtract 1029*4'b1000 from the accumulated sum.

[0115] Taking a basic calculation unit of 7*7*7=343 as an example, the first level calculates 7 adjacent X n The same bit of the 7 adjacent 3-bit values ​​in the second level is calculated, and 7*7*4=196 3-bit numbers are obtained. The second level also calculates the same bit of the 7 adjacent 3-bit values ​​in the vertical direction, and 7*4*3=84 3-bit numbers are obtained. The third level continues to calculate the same bit of the 7 adjacent 3-bit values ​​in the vertical direction, and 4*3*3=36 3-bit numbers are obtained. Finally, these 36 3-bit numbers are shifted and added according to the number of bits at the time of calculation, and the 343-length 4-bit X is obtained. n The cumulative sum of 4*3*3=36 3-bit numbers is level 3 n , n=0,1,2...35, then level3n According to the number of bits in the calculation, first add the same left shift level operation to get level 4 n ,n=0,1,2...7; finally level4 n Shift left and add the corresponding series to get the final result.

[0116] level3 0 Shift left by 0 bits;

[0117] level3 139 Shift left 1 bit in total;

[0118] level3 246101218 Shift left 2 places in total;

[0119] level3 57111315192127 Shift left 3 places in total;

[0120] level3 814162022242830 Shift left 4 bits in total;

[0121] level3 172325293133 Shift left 5 bits in total;

[0122] level3 263234 Shift left 6 places in total;

[0123] level3 35 A total of 7 bits are shifted left.

[0124] By instantiating three of these calculation units, we can calculate the 4-bit X of length 1029 n The cumulative sum of is:

[0125] SUM=level3 0 +sum(level3 139 )×2+sum(level3 246101218 )×4

[0126] +sum(level3 57111315192127 )×8+sum(level3 814162022242830 )

[0127] ×16+sum(level3 172325293133 )×32+sum(level3 263234 )×64

[0128] After all the data are accumulated, the summation result is finally corrected according to the above correction method:

[0129] S=SUM-1029*4'b1000+NEG_NUM

[0130] Specifically, the implementation process of the (7, 3) counter is as follows:

[0131] (7,3) The counter is the smallest processing unit of the accumulator. Its basic functional block diagram is as follows: Figure 6 As shown, input 7 bits and output the number of 1s in the 7 bits.

[0132] As the smallest unit of the accumulator, this module only needs to use 4 single-bit full adders to implement it. The scheme of using full adders is as follows: Figure 7 shown.

[0133] Another way to implement the (7, 3) counter is to use a lookup table directly to save gate-level circuits by using memory. Figure 8 shown.

[0134] The solution of using full adder is more suitable for ASIC design, but it is different in FPGA implementation. Since the basic unit in FPGA is configurable logic block (CLB), which is composed of several functional units such as LUT, MUX, CARRY, FF, etc., the following solutions can be used for targeted optimization on the FPGA platform, such as Fig. 9 shown.

[0135] In the specific implementation, the primitives on the FPGA are used to implement this function, and three LUT6s are instantiated. The values ​​of each bit of the sum are obtained by looking up the table, and then the sum of the 6 input bits is obtained. The lookup tables of the three LUT6s are set in order from low to high according to the result bits:

[0136] 64'b0110100110010110100101100110100110010110011010010110100110010110,

[0137] 64'b1000000100010111000101110111111000010111011111100111111011101000,

[0138] 64'b1111111011101000111010001000000011101000100000001000000000000000,

[0139] The remaining 1-bit input is implemented through the CARRY4 carry chain, that is, the output results s[2:0] of the three LUT6s are input as the input number of CARRY4, and the 7th input bit is used as the carry bit, and the final result is obtained by the carry chain.

[0140] CARRY8 can be divided into two CARRY4s through configuration. By performing the same operation, half of the CARRY8 resources can be saved, thereby reducing the occupation of the FPGA's smallest unit CLB, and ultimately realizing the (7,3) counter operation. Each (7,3) counter occupies three LUT6s and half of the CARRY8 of the FPGA.

[0141] The above-mentioned optimization is specifically performed for FPGA to maximize the application of fixed resources such as LUT, CARRY8, DSP and MUX in FPGA.

[0142] The calculation method of the correlator supporting three levels provided in this embodiment sums the multiplication results in groups of seven, and then shifts and adds the sums of each bit obtained, thereby replacing the existing hierarchical addition method, thereby reducing resource consumption and solving the problem of tight timing.

[0143] In this embodiment, a computing device supporting a three-level correlator is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are not repeated here. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0144] This embodiment provides a computing device supporting a three-level correlator, such as Fig.10 As shown, including:

[0145] The first calculation module 1001 is used to select and perform an XOR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result.

[0146] The second calculation module 1002 is used to use the (7, 3) counter to perform a sum operation on all multiplication results to obtain a calculation result.

[0147] In some optional implementations, the first calculation module 1001 includes:

[0148] The first calculation unit is configured to calculate, when the amplitude bit of the local code is zero, a multiplication result of 4'b0000.

[0149] The second calculation unit is used to perform an XOR operation on the sign bit of the local code and the bit bit of the input signal when the amplitude bit of the local code is one, and when the sign bit of the local code is one, the multiplication result is the addition result of the XOR operation result and 1'b1.

[0150] In some optional implementations, the second computing unit includes:

[0151] The bit expansion unit is used to expand the sign bit of the local code into a 4-bit signal.

[0152] The calculation subunit is used to perform an XOR operation on the 4-bit signal and the 4-bit input signal bit by bit.

[0153] In some optional implementations, the second calculation module 1002 includes:

[0154] The third calculation unit is used to calculate the sum of each bit of all the multiplication results in groups of seven.

[0155] The fourth calculation unit is used to perform shift and addition operations on the sum of each bit obtained by calculation according to the position of the bit, and determine the accumulated sum as the calculation result.

[0156] In some optional embodiments, the device further comprises:

[0157] The transcoding module is used to convert the complement code to the original code of all multiplication results.

[0158] The zero-filling module is used to fill the result of the complement code conversion operation with zeros according to the maximum length supported by the correlator.

[0159] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0160] In this embodiment, the computing device supporting the three-level correlator is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0161] The embodiment of the present invention also provides a computer device having the above Fig.10 A computing device supporting a three-level correlator is shown.

[0162] See also Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.11As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.11 A processor 10 is taken as an example.

[0163] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0164] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0165] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0166] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0167] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Fig.11 The example of connecting through bus is taken in the following.

[0168] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, etc. The output device 40 can include a display device, etc.

[0169] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0170] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0171] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope of the present application.

Claims

1. A computing system supporting a three-level correlator, characterized in that: The system includes a receiver, a correlator, a shift register and a (7, 3) counter, wherein: 8 identical correlators are configured on the receiver side for parallel processing; The receiver locally stores a three-level local code of a preset length, and shifts the received signal into a shift register having the same length as the preset length; The shift register stores a signal having the same length as the preset length as an input signal; The correlator selects and performs an XOR operation on the local code and the input signal to obtain a multiplication result; The (7, 3) counter is used to perform a sum operation on all multiplication results to obtain a calculation result.

2. A calculation method for a correlator supporting three levels, characterized in that: The method comprises: Perform selection and exclusive OR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result; The (7, 3) counter is used to sum all the multiplication results to obtain the calculation result.

3. The method according to claim 2, characterized in that The method of selecting and performing an XOR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result includes: When the amplitude bit of the local code is zero, the multiplication result is 4'b0000; When the amplitude bit of the local code is one, the sign bit of the local code is XORed with the bit of the input signal, and when the sign bit of the local code is one, the multiplication result is the addition result of the XOR result and 1'b1.

4. The method according to claim 3, characterized in that The performing an XOR operation on the sign bit of the local code and the bit bit of the input signal comprises: Expanding the sign bit of the local code to a 4-bit signal; Perform an XOR operation on the 4-bit signal and the 4-bit input signal bit by bit.

5. The method according to claim 2, characterized in that: The (7, 3) counter is used to perform a sum operation on all multiplication results to obtain a calculation result, including: Put all the multiplication results into groups of seven and calculate the sum of each bit separately; According to the position of the bit, the calculated sum of each bit is shifted and added, and the accumulated sum is determined as the calculation result.

6. The method according to claim 2, characterized in that Before using the (7, 3) counter to sum all multiplication results to obtain the calculation result, the method further includes: Perform the two's complement to original code conversion operation on all multiplication results; According to the maximum length supported by the correlator, the result of the complement code conversion operation is padded with zeros.

7. A computing device supporting a three-level correlator, characterized in that: The device comprises: The first calculation module is used to select and perform an XOR operation on the three-level local code stored in the receiver and the input signal stored in the shift register to obtain a multiplication result; The second calculation module is used to use the (7, 3) counter to perform a sum operation on all multiplication results to obtain a calculation result.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the calculation method of the correlator supporting three levels according to any one of claims 2 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the calculation method of the correlator supporting three levels according to any one of claims 2 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the calculation method of the correlator supporting three levels according to any one of claims 2 to 6.

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