Binary translation method, translator, electronic device and readable storage medium

Abstract

An embodiment of the present invention provides a binary translation method, a translator, an electronic device, and a readable storage medium. The method includes: when translating a direct jump instruction in a first basic block, identifying whether a second basic block to which the direct jump instruction jumps spans pages; if it is determined that the second basic block spans pages, inserting a target instruction sequence before an unoptimized instruction sequence after the translation of the direct jump instruction, where the target instruction sequence is used to detect whether the direct jump instruction meets an optimization condition, and when it is detected that the direct jump instruction meets the optimization condition, performing a jump through a link instruction sequence; the optimization condition includes: the virtual-to-physical address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache. The embodiment of the present invention optimizes the execution of the direct jump instruction when it is determined that the optimization condition is met, which can improve the program running efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a binary translation method, a translator, an electronic device, and a readable storage medium. Background Art

[0002] Binary translation can convert binary code of one ISA (Instruction Set Architecture) into binary code of another instruction set architecture. Through binary translation technology, an application program of one ISA (source architecture) can run on another ISA (target architecture).

[0003] Binary translation is performed in units of basic blocks (Translation Blocks, TBs). A basic block is a sequence of instructions that are sequentially executed in a program and has a single entry point and a single exit point. Once the program enters a basic block, all the instructions therein will be sequentially executed until the exit of the basic block, and there will be no control flow branches inside the basic block (except for sequentially executing to the last instruction). The entry point is the first instruction of the basic block; the exit point is the last instruction of the basic block, and the last instruction can be a jump instruction, a function call instruction, a program termination instruction, etc.

[0004] When a basic block ends with a jump instruction, when the program executes to this jump instruction, it is necessary to jump the control flow from the current basic block to another basic block, which involves the search operation of the basic block. This process usually requires a relatively high cost and affects the program execution efficiency. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a binary translation method that can overcome the above problems or at least partially solve the above problems, and can optimize the execution of direct jump instructions under the condition of determining that the optimization conditions are met, thereby improving the program running efficiency.

[0006] Correspondingly, embodiments of the present invention also provide a binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a system-level binary translator, and the method includes:

[0008] When translating to a direct jump instruction in a first basic block, identifying whether the second basic block to which the direct jump instruction jumps spans pages;

[0009] If it is determined that the second basic block spans pages, a target instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction. The target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and in the case where it is detected that the direct jump instruction meets the optimization conditions, a jump is made through a link instruction sequence; the optimization conditions include: the virtual-to-physical address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0010] In a second aspect, an embodiment of the present invention discloses a system-level binary translator, which includes:

[0011] A translation recognition module, configured to, when translating a direct jump instruction in a first basic block, recognize whether the second basic block to which the direct jump instruction jumps spans pages;

[0012] A translation optimization module, configured to, if it is determined that the second basic block spans pages, insert a target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction. The target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and in the case where it is detected that the direct jump instruction meets the optimization conditions, a jump is made through a link instruction sequence; the optimization conditions include: the virtual-to-physical address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0013] In a third aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method as described in any one of the foregoing.

[0014] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, it can implement the binary translation method as described in any one of the foregoing.

[0015] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program. When the computer program is executed by a processor, it performs the steps of the binary translation method as described in any one of the foregoing.

[0016] The embodiments of the present invention have the following advantages:

[0017] In the embodiment of the present invention, during the dynamic binary translation process, when translating a direct jump instruction in the first basic block, it is identified whether the second basic block to which the direct jump instruction jumps spans pages. According to whether the second basic block spans pages and whether the virtual-to-physical address mapping relationship changes in the case where the second basic block spans pages, the optimization operation performed on the direct jump instruction is refined. In the case where the second basic block does not span pages, or in the case where the second basic block spans pages but the virtual-to-physical address mapping relationship of the second basic block does not change, the execution of the direct jump instruction in the first basic block can be optimized, and the jump is performed through a linked instruction sequence, directly jumping to the starting address of the translated basic block corresponding to the second basic block in the code cache, avoiding the basic block search operation performed by the unoptimized instruction sequence, which can improve the jump efficiency and thus improve the program running efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a binary translation architecture of the present invention;

[0019] Figure 2 is a flowchart of the steps of an embodiment of a binary translation method of the present invention;

[0020] Figure 3 is a schematic diagram of an exemplary binary translation method flow of the present invention;

[0021] Figure 4 is a block diagram of the structure of an embodiment of a system-level binary translator of the present invention;

[0022] Figure 5 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In the embodiments of the present invention, the term "plurality" refers to two or more, and other quantifiers are similar.

[0025] Binary translation technology can solve the problem of application programs running across instruction set architectures at the binary level. Specifically, binary translation technology can convert an instruction sequence in one instruction set architecture into an instruction sequence in another instruction set architecture.

[0026] Refer to Figure 1 , which shows a schematic diagram of the dynamic binary translation architecture. As Figure 1 shown, dynamic binary translation adopts the "translate and run while" method, translating the instructions of the client architecture into the instructions of the host architecture and running them on the host at runtime. After the translator reads the binary file of the target program (client program), it translates and executes at the granularity of basic blocks (TranslationBlock, TB). A basic block usually ends with a control flow change instruction (such as an indirect jump instruction, a function call instruction, etc.). Before executing a basic block, first look it up in the code cache. If the translated basic block is found, execute the basic block. If the translated basic block is not found in the code cache, translate the basic block and put the translated basic block into the code cache, and then execute the translated basic block. After executing a basic block, look for the next basic block in the code cache, and so on in a loop until the program execution ends.

[0027] Dynamic binary translators can be divided into user-level binary translators and system-level binary translators, and their application scopes are different. The application scope of user-level binary translators is mainly limited to the execution of a single user-mode program, which is suitable for executing target programs on different architectures without running the entire operating system, and is commonly used in software compatibility solutions that cross architectures but not operating systems. System-level binary translators, on the other hand, cover the operation of the entire system, including the operating system kernel and user-mode programs, and can simulate a complete computer system on different architectures. They are usually used in software compatibility solutions that cross both architectures and operating systems. System-level binary translators can also be used in scenarios such as virtualization, embedded development, and operating system migration.

[0028] The present invention provides a binary translation method, which is applied to a system-level binary translator and can be used to optimize the translation and execution of direct jump instructions.

[0029] Some concepts involved in the embodiments of the present invention are explained below.

[0030] Guest Virtual Address (GVA) is the virtual address space allocated by the guest operating system for its processes or applications.

[0031] Guest Physical Address (GPA) is the address obtained by the guest operating system after converting the GVA through its Memory Management Unit (MMU), and it is the "physical address" considered by the guest operating system or runtime environment. The guest operating system maps the GVA to the GPA, but these addresses are not real physical addresses and are further mapped to the host's address space by the binary translator or virtualization layer.

[0032] Host Virtual Address (HVA) is the virtual address used by the host operating system for its own processes and the guest.

[0033] In user-level binary translation, a basic block can be uniquely identified using the GVA. Specifically, the user-level binary translator mainly translates the binary code of a single user process. In the context of a single process, the Guest Virtual Address GVA provides an independent and continuous virtual address space for the process. The GVA used by each process is unique, and the code and data within the process are organized and accessed according to the GVA. Therefore, in this relatively independent process environment, using the GVA can uniquely identify a basic block.

[0034] In system-level binary translation, both GVA and GPA are required to uniquely identify a basic block. Specifically, system-level binary translation involves the entire operating system and multiple processes managed by it. Different processes may have the same GVA, but their actual positions in physical memory are different. The guest physical address GPA represents the physical memory address from the perspective of the guest operating system, which can reflect the actual position of the basic block in physical memory. Therefore, relying solely on GVA cannot uniquely identify a basic block, and GPA needs to be combined to distinguish different basic blocks corresponding to the same GVA in different processes. Therefore, in system-level binary translation, both GVA and GPA are required to uniquely identify a basic block.

[0035] Since the guest program runs in the host environment, the physical memory of the guest program is actually simulated by the virtual memory of the host. Therefore, a mapping relationship between GPA and HVA needs to be established. This mapping relationship is maintained by the binary translation system to ensure that the physical memory accessed by the guest can be correctly mapped to the virtual memory space of the host. The relationship between GVA and HVA is indirect and requires GPA as an intermediate bridge. First, GVA is converted to GPA, and then GPA is mapped to HVA. Although GPA and HVA belong to different address spaces of the guest and the host respectively, they actually point to the same physical memory resource. For example, when the guest program accesses the memory corresponding to a certain GPA, the binary translation system will map it to an HVA, and these two addresses correspond to the same actual memory data.

[0036] Since there is a one-to-one mapping relationship between the guest physical address GPA and the host virtual address HVA in system-level binary translation, using either GPA or HVA in the present invention can achieve the same purpose. For the convenience of description, in the embodiments of the present invention, the guest physical address GPA and the host virtual address HVA are uniformly described as the actual address. That is, in the embodiments of the present invention, the actual address corresponding to the guest virtual address GVA can be the guest physical address GPA or the host virtual address HVA. In the embodiments of the present invention, the guest physical address GPA is mainly used as an example for description. It can be understood that the guest physical address GPA in the description can be replaced by the host virtual address HVA, and the purpose of the present invention can also be achieved.

[0037] Refer to Figure 2 , which shows a flowchart of the steps of an embodiment of a binary translation method of the present invention. The method is applied to a system-level binary translator, and the method may include the following steps:

[0038] Step 101, when translating a direct jump instruction in the first basic block, identify whether the second basic block to which the direct jump instruction jumps spans pages;

[0039] Step 102: If it is determined that the second basic block spans pages, then insert a target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction. The target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and in the case where it is detected that the direct jump instruction meets the optimization conditions, perform a jump through a link instruction sequence; the optimization conditions include: the virtual-to-real address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0040] In system-level binary translation, it is necessary to use both the guest virtual address GVA and the actual address (guest physical address GPA or host virtual address HVA) to uniquely identify a basic block.

[0041] In the memory management of an operating system, to effectively manage memory, the memory is divided into pages of fixed size, and a page is the basic unit of memory management.

[0042] For ease of description, in the embodiments of the present invention, the system-level binary translator is also simply referred to as the translator. Before executing the first basic block in a certain page, the translator checks whether the virtual-to-real address mapping relationship of this page is correct. The virtual-to-real address mapping relationship refers to the mapping relationship between the guest virtual address GVA and the actual address. This is because the operating system may perform various operations on the memory, such as page replacement, memory allocation adjustment, etc., which may cause the virtual-to-real address mapping relationship to change. If the virtual-to-real address mapping relationship is correct (has not changed), it means that all address accesses within this page are predictable and secure. When executing subsequent basic blocks in this page, there is no need to repeatedly check the virtual-to-real address mapping relationship of this page.

[0043] In the embodiments of the present invention, the first basic block refers to the basic block ending with a direct jump instruction. The second basic block refers to the basic block to which the direct jump instruction in the first basic block jumps.

[0044] The direct jump instruction clearly specifies the jump target address. At the program compilation or assembly stage, the jump target address of the direct jump instruction has been determined, and unless the program code is modified, the jump target will not change. The jump target address is carried in the direct jump instruction, and this jump target address points to the first instruction of the basic block to which it jumps. It can be understood that the address of a certain basic block described in the embodiments of the present invention refers to the address of the first instruction in this basic block. For example, the guest virtual address GVA of basic block B refers to the guest virtual address GVA of the first instruction in basic block B.

[0045] Since the jump target address of a direct jump instruction is fixed, unlike the jump target address of an indirect jump instruction which can only be determined during execution, in the embodiments of the present invention, when translating a direct jump instruction, the translation of the direct jump instruction is optimized by inserting a target instruction sequence. This target instruction sequence is used to optimize the execution of the direct jump instruction when it is determined that the direct jump instruction meets the optimization condition during the execution of the direct jump instruction. It directly jumps through the link instruction sequence, reducing the search operation of basic blocks during the program execution while ensuring the correct jump, and improving the program execution efficiency.

[0046] Further, the target instruction sequence is also used to not optimize the execution of the direct jump instruction when it is detected that the direct jump instruction does not meet the optimization condition, jump to the unoptimized instruction sequence, perform basic block search according to the original process, and then perform the jump to ensure the correct jump.

[0047] In an example, the first basic block is denoted as basic block A, and the last instruction of basic block A is a direct jump instruction, and the second basic block to which this direct jump instruction jumps is denoted as basic block B.

[0048] During the translation stage, when translating the direct jump instruction in the first basic block (such as basic block A), it can be translated into an unoptimized instruction sequence, and this unoptimized instruction sequence is used to jump to the target search code, and the target search code is used to perform the following operations:

[0049] Search for the translated basic block corresponding to the second basic block in the code cache. If found, obtain the starting address of the translated basic block corresponding to the second basic block in the code cache and jump to the execution at this starting address; if not found, translate the second basic block and save the translated basic block corresponding to the second basic block to the code cache after the translation is completed.

[0050] The target search code is used to execute the slow search logic, that is, to search for the host virtual address HVA of the translated basic block corresponding to the second basic block according to the client virtual address GVA of the second basic block (basic block B). The host virtual address HVA of the translated basic block corresponding to the second basic block refers to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0051] Specifically, first, look up the translated basic block corresponding to the second basic block in the code cache. If found, obtain the starting address of the translated basic block corresponding to the second basic block in the code cache, and jump to that starting address for execution; if not found, exit the execution process, enter the translation context, translate the second basic block, and after the translation is completed, save the translated basic block corresponding to the second basic block to the code cache, and jump to the starting address of the translated basic block corresponding to the second basic block in the code cache for execution.

[0052] During the execution phase, when the direct jump instruction (client instruction) in basic block A is executed, the translated unoptimized instruction sequence (host instruction) will be executed, that is, the above-mentioned target search code will be executed to complete the search for the starting address of the translated basic block corresponding to basic block B in the code cache and jump to basic block B.

[0053] During the program running process, a basic block may be executed multiple times. If the above-mentioned target search code has to be executed every time the direct jump instruction in basic block A is executed, it will affect the program execution efficiency.

[0054] Performing basic block linking on the first basic block and the second basic block can optimize the execution of the direct jump instruction. Specifically, for the first basic block ending with a direct jump instruction, when the first basic block is executed for the first time, the first basic block is in an unlinked state. When the direct jump instruction is executed, it will exit to the translation context, translate the second basic block to which it jumps, and perform basic block linking on the first basic block and the second basic block after the translation is completed.

[0055] The process of performing basic block linking on the first basic block and the second basic block can be as follows:

[0056] During the translation phase, when the direct jump instruction in the first basic block is translated, it can be translated into an unoptimized instruction sequence, and a placeholder instruction sequence is inserted before the unoptimized instruction sequence. The placeholder instruction sequence can include at least one no-operation instruction (such as the NOP instruction of the host architecture). The placeholder instruction sequence is used to reserve a position for subsequent basic block linking. The NOP instruction (No Operation) is an instruction widely used in computer architecture, and its function is "no operation". When the CPU executes the NOP instruction, it will not have any substantial impact on registers, memory, or program state, but simply consume one or more clock cycles and then continue to execute the next instruction.

[0057] When the direct jump instruction in the first basic block is executed for the first time, the basic block chaining operation has not been performed on the first basic block, and the first basic block is in an unchained state. At this time, the placeholder instruction sequence is still the NOP instruction, so it will be sequentially executed to the unoptimized instruction sequence, and then the target search code will be executed. After the target search code is executed, since the starting address of the translated basic block corresponding to the second basic block in the code cache has been obtained, the placeholder instruction sequence can be replaced with a linking instruction sequence, and the linking instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache. Thus, the basic block chaining operation for the first basic block and the second basic block is completed. At this time, the first basic block is in a chained state. Among them, the starting address of the translated basic block corresponding to the second basic block in the code cache is the host virtual address HVA of the translated basic block corresponding to the second basic block.

[0058] When the direct jump instruction in the first basic block is executed for the Nth (N≥2) time, the first basic block is in a chained state, and the placeholder instruction sequence has been replaced with a linking instruction sequence. Therefore, the linking instruction sequence will be executed, and then directly jump to the starting address (HVA) of the translated basic block corresponding to the second basic block in the code cache, and the subsequent target search code will not be executed, which can avoid executing the target search code each time to find the starting address (HVA) of the translated basic block corresponding to the second basic block in the code cache according to the GVA of the second basic block, and can improve the program running efficiency.

[0059] However, during the program running process, there may be two situations. One is that the second basic block and the first basic block are in the same page, which is called the second basic block does not cross pages; the other is that the second basic block and the first basic block are not in the same page, which is called the second basic block crosses pages.

[0060] Before the translator executes the first basic block in a certain page, it will check whether the virtual-to-physical address mapping relationship of this page is correct. In the above example, regardless of whether the first basic block (such as basic block A) is the first basic block in its page, when the direct jump instruction in the first basic block is executed, the virtual-to-physical address mapping relationship of the page where the first basic block is located has been checked for correctness, that is, the virtual-to-physical address mapping relationship of this page has not changed. However, for the second basic block (such as basic block B) to which the direct jump instruction is to jump, the virtual-to-physical address mapping relationship of the page where the second basic block is located has not been checked for changes.

[0061] For the case where the second basic block does not cross pages, that is, jumping within the same page, since the virtual-to-physical address mapping relationship of this page has been checked before executing the first basic block, directly jumping from the first basic block to the second basic block can ensure correct execution.

[0062] For the case where the second basic block spans multiple pages, that is, the first basic block and the second basic block are on different pages. Since the virtual-to-physical address mapping relationship of the page where the second basic block is located has not been checked for correctness, directly jumping from the first basic block to the second basic block may cause execution errors.

[0063] In specific implementation, for the case where the second basic block does not span multiple pages, the execution of the direct jump instruction in the first basic block can be optimized using basic block linking. For the case where the second basic block spans multiple pages, to ensure the correctness of the basic block jump behavior, the basic block linking operations for the first basic block and the second basic block can be discarded, and the unoptimized instruction sequence is still executed.

[0064] Specifically, when translating to the direct jump instruction in the first basic block, it can be identified whether the second basic block to which the direct jump instruction is to jump spans multiple pages. If it is determined that the second basic block does not span multiple pages, the execution of the direct jump instruction is optimized, and the jump is performed through the linked instruction sequence. If it is determined that the second basic block spans multiple pages, the execution of the direct jump instruction is not optimized, and the jump is still performed through the unoptimized instruction sequence.

[0065] During the translation phase, the GVA addresses of the first basic block and the second basic block are known. Therefore, the GVA addresses of the pages where the first basic block and the second basic block are located are also known. By determining whether the GVA address of the page where the first basic block is located is the same as the GVA address of the page where the second basic block is located, it can be determined whether the second basic block spans multiple pages. If the GVA address of the page where the first basic block is located is different from the GVA address of the page where the second basic block is located, it is determined that the second basic block spans multiple pages.

[0066] Furthermore, the embodiments of the present invention have found through research that the virtual-to-physical address mapping relationship of the page where the second basic block is located is mostly in a stable state without change. Completely discarding the optimization operation using basic block linking when the second basic block spans multiple pages results in sacrificing part of the performance of the translator. To further improve the performance of the translator and further improve the program running efficiency, the embodiments of the present invention further optimize the jump in the case where the second basic block spans multiple pages.

[0067] Specifically, when translating a direct jump instruction in the first basic block, it is identified whether the second basic block to which the direct jump instruction jumps spans pages; if it is determined that the second basic block spans pages, a target instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction. The target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and in the case where it is detected that the direct jump instruction meets the optimization conditions, the execution of the direct jump instruction can still be optimized, and the jump is performed through a linked instruction sequence. The optimization conditions include: the virtual-to-physical address mapping relationship of the second basic block has not changed, that is, the actual address corresponding to the client virtual address of the second basic block remains the same before and after the basic block is linked.

[0068] In the embodiment of the present invention, in the case where the second basic block spans pages, it is further determined whether the virtual-to-physical address mapping relationship of the second basic block has changed. If it has not changed and directly jumping from the first basic block to the second basic block can ensure correct execution, it is considered that the direct jump instruction in the first basic block still meets the optimization conditions and can be jumped through a linked instruction sequence, further improving the performance of the translator on the premise of ensuring the correctness of cross-page jumps.

[0069] Further, inserting the target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction may include:

[0070] Inserting a placeholder instruction sequence before the unoptimized instruction sequence, and inserting the target instruction sequence before the placeholder instruction sequence.

[0071] In the embodiment of the present invention, the target instruction sequence is inserted before the placeholder instruction sequence. The target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions when the execution reaches the direct jump instruction in the first basic block, and in the case where it is detected that the direct jump instruction meets the optimization conditions, the jump is performed through a linked instruction sequence, so as to directly jump to the starting address of the translated basic block corresponding to the second basic block in the code cache, and the unoptimized instruction sequence is no longer executed, which can avoid the slow search logic of the target search code. If it is detected that the direct jump instruction does not meet the optimization conditions, the unoptimized instruction sequence is still executed to ensure correct jumping.

[0072] In an alternative embodiment of the present invention, the target instruction sequence may include:

[0073] The first instruction sequence is used to read the client virtual address of the second basic block recorded when the basic block is linked; continue to execute sequentially;

[0074] A second instruction sequence, which is used to jump to the unoptimized instruction sequence when it is determined that the value pointed to by the client virtual address of the second basic block read is empty; if not empty, continue to execute sequentially;

[0075] A third instruction sequence, which is used to read the actual address corresponding to the client virtual address of the second basic block recorded when the basic block is linked; continue to execute sequentially;

[0076] A fourth instruction sequence, which is used to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; continue to execute sequentially;

[0077] A fifth instruction sequence, which is used to jump to the unoptimized instruction sequence when it is determined that the actual address during the current execution queried is inconsistent with the actual address when the basic block is linked; if consistent, it is determined that the optimization condition is met, and continue to execute sequentially.

[0078] It should be noted that the inserted target instruction sequence is an instruction sequence under the host architecture. The embodiments of the present invention do not limit the form of the target instruction sequence, and there may be different manifestations under different host architectures. For example, any one of the above inserted first instruction sequence to fifth instruction sequence may include one or more instructions under the host architecture in different host architectures.

[0079] In the translation stage of the embodiments of the present invention, when translating the direct jump instruction in the first basic block, if it is recognized that the second basic block to which the jump is to be made spans pages, the target instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction. Specifically, the target instruction sequence is inserted before the placeholder instruction sequence before the unoptimized instruction sequence.

[0080] After inserting the target instruction sequence, when the direct jump instruction in the first basic block is first executed, the target instruction sequence will be executed first. Specifically, the first instruction sequence is executed first to read the client virtual address of the second basic block recorded when the basic block link is read. Then the second instruction sequence is executed to determine whether the value pointed to by the client virtual address of the second basic block recorded when the basic block link is read is empty. Since this is the first execution, the value is empty, so it jumps to the unoptimized instruction sequence, and then the target search code is executed. The target search code searches in the code cache for the translated basic block corresponding to the second basic block that does not exist. Therefore, the second basic block will be translated. After the translation is completed, the translated basic block corresponding to the second basic block is saved to the code cache, jumps to the start address of the translated basic block corresponding to the second basic block in the code cache for execution, and replaces the placeholder instruction sequence with the link instruction sequence, and records the client virtual address of the second basic block (denoted as GVA1) and the actual address corresponding to the client virtual address (denoted as GPA1).

[0081] It should be noted that since the target instruction sequence inserted in the embodiment of the present invention is before the placeholder instruction sequence, and the placeholder instruction sequence is before the unoptimized instruction sequence, therefore, in the embodiment of the present invention, the basic block link of the first basic block and the second basic block can be performed when the direct jump instruction is first executed, and the placeholder instruction sequence is replaced with the link instruction sequence. When the direct jump instruction in the first basic block is executed again, it is possible to control whether to execute the link instruction sequence or the unoptimized instruction sequence by determining whether the direct jump instruction meets the optimization conditions in the target instruction sequence.

[0082] When the direct jump instruction in the first basic block is executed for the Nth (N≥2) time, the target instruction sequence is still executed first. Taking the second execution as an example, specifically, the first instruction sequence is executed first to read the client virtual address (such as GVA1) of the second basic block recorded during basic block linking. Then the second instruction sequence is executed. Since the value pointed to by GVA1 recorded during basic block linking is not null, the execution continues sequentially. Next, the third instruction sequence is executed to read the actual address (such as GPA1) corresponding to the client virtual address (GVA1) of the second basic block recorded during basic block linking. Next, the fourth instruction sequence is executed to query the actual address (such as GPA2) corresponding to the client virtual address (GVA1) of the second basic block during this execution based on the read client virtual address (GVA1) of the second basic block. Finally, the fifth instruction sequence is executed. If it is determined that the actual address (GPA2) during this execution queried is inconsistent with the actual address (GPA1) during basic block linking, then jump to the unoptimized instruction sequence. If it is determined that GPA2 is consistent with GPA1 and the optimization condition is satisfied, the execution continues sequentially, and the linked instruction sequence after replacing the placeholder instruction sequence will be executed, and then a direct jump will be made.

[0083] Among them, the fourth instruction sequence queries the actual address corresponding to the client virtual address of the second basic block during this execution based on the read client virtual address of the second basic block, and can be queried through an address translation lookaside buffer; exemplarily, it is queried through a software address translation lookaside buffer; the software address translation lookaside buffer is used to store the mapping relationship of the most recently used GVA to GPA to accelerate the address conversion process. Therefore, by querying the software address translation lookaside buffer based on GVA, the GPA corresponding to this GVA can be obtained.

[0084] In the translation stage of the embodiment of the present invention, when translating to the direct jump instruction in the first basic block, if it is recognized that the second basic block to which the direct jump instruction jumps spans pages, a target instruction sequence is inserted before the unoptimized instruction sequence after the direct jump instruction is translated. When the direct jump instruction is executed for the first time, the unoptimized instruction sequence is executed, and basic block linking is performed on the first basic block and the second basic block, and the client virtual address and the corresponding actual address of the second basic block are recorded. Thus, when the direct jump instruction is executed again subsequently, the execution flow can be controlled through the target instruction sequence, such as controlling whether to adopt the optimization strategy of basic block linking. Specifically, when the direct jump instruction meets the optimization condition (the virtual-to-real address mapping relationship of the second basic block has not changed), a jump is made through the linked instruction sequence. When the direct jump instruction does not meet the optimization condition (the virtual-to-real address mapping relationship of the second basic block has changed), a jump is made through the unoptimized instruction sequence to ensure the correctness of the execution.

[0085] In an alternative embodiment of the present invention, the method may further include:

[0086] During the translation stage of the target basic block, record the actual address corresponding to the client virtual address of the target basic block in the structure of the target basic block; the target basic block includes the first basic block or the second basic block;

[0087] When performing basic block linking on the first basic block and the second basic block, read the client virtual address and the corresponding actual address of the second basic block from the structure of the second basic block and record them in the structure of the first basic block.

[0088] In a specific implementation, the structure of each basic block contains the client virtual address (GVA) of the basic block to identify the basic block. In an embodiment of the present invention, when translating each basic block, the actual address (such as GPA) corresponding to the client virtual address (GVA) of the basic block is additionally recorded in the structure of the basic block. Thus, when performing basic block linking on the first basic block and the second basic block, by querying the structure of the second basic block, the client virtual address (GVA) of the second basic block and the corresponding actual address (such as GPA) recorded therein can be obtained. Furthermore, the client virtual address (GVA) of the second basic block and the corresponding actual address (such as GPA) during basic block linking can be recorded for use by the target instruction sequence during the next execution process.

[0089] In an embodiment of the present invention, when performing basic block linking on the first basic block and the second basic block, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block are recorded. Further, in an embodiment of the present invention, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block are recorded in the structure of the first basic block. Thus, when the direct jump instruction in the first basic block is executed next time, the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block recorded during basic block linking can be directly read from the structure of the first basic block, which can improve the reading speed.

[0090] Of course, in an embodiment of the present invention, there is no limitation on the position where the client virtual address (GVA) and the corresponding actual address (GPA) of the second basic block are recorded. For example, it can also be recorded in the structure of the second basic block.

[0091] In the embodiment of the present invention, when translating each basic block, the client virtual address (GVA) and the corresponding physical address (GPA) of the basic block are recorded in the structure of the basic block. Further, when performing basic block linking on the first basic block and the second basic block, the client virtual address (GVA) and the corresponding physical address (GPA) of the second basic block during basic block linking can be additionally recorded in the structure of the first basic block. Thus, when the direct jump instruction in the first basic block is executed next time, the target instruction sequence can directly read the client virtual address (GVA) and the corresponding physical address (GPA) of the second basic block recorded during basic block linking from the structure of the first basic block, which can accelerate the data reading speed.

[0092] If, when performing basic block linking on the first basic block and the second basic block, the client virtual address (GVA) and the corresponding physical address (GPA) of the second basic block are recorded in the structure of the second basic block. When the direct jump instruction in the first basic block is executed next time, the target instruction sequence needs to first obtain the structure pointer of the second basic block, then find the structure of the second basic block according to the structure pointer of the second basic block, and further read the client virtual address (GVA) and the corresponding physical address (GPA) of the second basic block recorded during basic block linking from the structure of the second basic block. It can be understood that the embodiment of the present invention does not limit the position where the client virtual address (GVA) and the corresponding physical address (GPA) of the second basic block are recorded during basic block linking, as long as they can be obtained when the target instruction sequence is executed.

[0093] In a specific implementation, the direct jump instruction may include an unconditional jump instruction and a conditional jump instruction. An unconditional jump instruction refers to an instruction that, regardless of any conditions, the program will immediately jump to the specified target address and continue execution. Once the unconditional jump instruction is executed, the program will directly jump to the address specified in the instruction. A conditional jump instruction refers to an instruction that determines whether to jump to the specified target address based on specific conditions.

[0094] A conditional jump instruction has two jump branches: taken or not taken. When the condition of the conditional jump instruction is satisfied, the program will jump to the specified target address and continue execution, and this situation is called taken, that is, the jump operation is executed. When the condition of the conditional jump instruction is not satisfied, the program will not perform a jump but continue to sequentially execute the next instruction, and this situation is called not taken, that is, the jump operation is not executed.

[0095] Therefore, a direct jump instruction may have one jump target or two jump targets. For an unconditional jump instruction, there is only one jump target. For a conditional jump instruction, there are two jump targets.

[0096] In an alternative embodiment of the present invention, the unoptimized instruction sequence may include a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to the jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is satisfied; the second jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is not satisfied.

[0097] For ease of description, in the embodiments of the present invention, the first jump instruction sequence is denoted as I_link0, the second jump instruction sequence is denoted as I_link1, and the unoptimized instruction sequence is denoted as I_exit. It should be noted that the first jump instruction sequence, the second jump instruction sequence, and the unoptimized instruction sequence are all translated host instruction sequences.

[0098] When linking the first basic block and the second basic block, the placeholder instruction sequence in the first basic block is replaced with a link instruction sequence. When the direct jump instruction in the first basic block is an unconditional jump instruction, the link instruction sequence is the first jump instruction sequence. When the direct jump instruction in the first basic block is a conditional jump instruction, if the condition is satisfied, the link instruction sequence is the first jump instruction sequence; if the condition is not satisfied, the link instruction sequence is the second jump instruction sequence. The first jump instruction sequence and the second jump instruction sequence are used to jump to the corresponding second basic block.

[0099] Further, the unoptimized instruction sequence may only contain a single instruction (denoted as I_exit), and this instruction is used to jump to the target search code. Since the target search code needs to perform operations in multiple steps and contains a relatively large number of instructions, the target search code can be used as common code and stored in a common basic block. I_exit is used to jump to this common basic block to execute this common code.

[0100] It should be noted that in the embodiments of the present invention, during the execution phase, the first basic block and the second basic block refer to the basic blocks under the translated host instruction architecture. During the translation phase, the first basic block and the second basic block refer to the basic blocks under the client instruction architecture before translation. The unoptimized instruction sequence, the link instruction sequence, the target instruction sequence, the placeholder instruction sequence, and the target search code are all instruction sequences under the host instruction architecture.

[0101] Refer to Figure 3 , which shows a schematic flow diagram of an exemplary binary translation method of the present invention, and specifically may include the following steps:

[0102] Step A1: When translating the target basic block, record the actual address (GPA or HVA) corresponding to the client virtual address (GVA) of the target basic block in the structure of the target basic block; the target basic block includes the first basic block or the second basic block.

[0103] Step A2: When translating the direct jump instruction in the first basic block, determine whether the second basic block that the first jump instruction sequence I_link0 is to jump to spans pages. If it does not span pages, execute Step A4; if it spans pages, insert the following target instruction sequence before the first jump instruction sequence I_link0:

[0104] The first instruction sequence is used to read the client virtual address of the second basic block recorded during basic block linking; continue to execute sequentially;

[0105] The second instruction sequence is used to jump to the unoptimized instruction sequence when it is determined that the value pointed to by the read client virtual address of the second basic block is empty; if not empty, continue to execute sequentially;

[0106] The third instruction sequence is used to read the actual address corresponding to the client virtual address of the second basic block recorded during basic block linking; continue to execute sequentially;

[0107] The fourth instruction sequence is used to query the actual address corresponding to the client virtual address of the second basic block during this execution based on the read client virtual address of the second basic block; continue to execute sequentially;

[0108] The fifth instruction sequence is used to jump to the unoptimized instruction sequence when it is determined that the actual address during this execution queried is inconsistent with the actual address during basic block linking read; if consistent, it is determined that the optimization condition is met, and continue to execute sequentially.

[0109] Step A3: When performing basic block linking on the first basic block and the second basic block, record the client virtual address (GVA) of the second basic block and the corresponding actual address (GPA).

[0110] Step A4: Determine whether there is a second jump instruction sequence I_link1. If there is, determine whether the second basic block that the second jump instruction sequence I_link1 is to jump to spans pages. If it spans pages, insert the above target instruction sequence before the second jump instruction sequence I_link1; if it does not span pages, continue to execute sequentially.

[0111] In summary, in the process of dynamic binary translation according to the embodiments of the present invention, when translating a direct jump instruction in a first basic block, it is identified whether a second basic block to which the direct jump instruction jumps spans pages. According to whether the second basic block spans pages and whether the virtual-to-physical address mapping relationship changes in the case where the second basic block spans pages, the optimization operation performed on the direct jump instruction is refined. In the case where the second basic block does not span pages, or in the case where the second basic block spans pages but the virtual-to-physical address mapping relationship of the second basic block does not change, the execution of the direct jump instruction in the first basic block can be optimized, and the jump is performed through a linked instruction sequence directly to the starting address of the translated basic block corresponding to the second basic block in the code cache, avoiding the basic block search operation performed by the unoptimized instruction sequence, which can improve the jump efficiency and thus improve the program running efficiency.

[0112] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0113] Refer to Figure 4 , which shows a structural block diagram of an embodiment of a system-level binary translator according to the present invention. The system-level binary translator may include:

[0114] A translation recognition module 401, configured to identify whether a second basic block to which a direct jump instruction jumps spans pages when translating a direct jump instruction in a first basic block;

[0115] A translation optimization module 402, configured to, if it is determined that the second basic block spans pages, insert a target instruction sequence before the unoptimized instruction sequence after the direct jump instruction is translated. The target instruction sequence is used to detect whether the direct jump instruction meets the optimization condition, and in the case where it is detected that the direct jump instruction meets the optimization condition, perform a jump through a linked instruction sequence; the optimization condition includes: the virtual-to-physical address mapping relationship of the second basic block does not change; the linked instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache.

[0116] Optionally, the target instruction sequence includes:

[0117] A first instruction sequence, configured to read the client virtual address of the second basic block recorded when the basic blocks are linked; continue to execute sequentially;

[0118] A second instruction sequence, which is used to jump to the unoptimized instruction sequence when it is determined that the value pointed to by the client virtual address of the read second basic block is empty; if not, continue to execute sequentially;

[0119] A third instruction sequence, which is used to read the actual address corresponding to the client virtual address of the second basic block recorded when linking basic blocks; continue to execute sequentially;

[0120] A fourth instruction sequence, which is used to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; continue to execute sequentially;

[0121] A fifth instruction sequence, which is used to jump to the unoptimized instruction sequence when it is determined that the actual address during the current execution queried is inconsistent with the actual address when linking basic blocks; if they are consistent, it is determined that the optimization condition is met, and continue to execute sequentially.

[0122] Optionally, the target instruction sequence is further used to jump to the unoptimized instruction sequence when it is detected that the direct jump instruction does not meet the optimization condition.

[0123] Optionally, the unoptimized instruction sequence is used to jump to target search code, and the target search code performs the following operations:

[0124] Search for the translated basic block corresponding to the second basic block in the code cache. If found, obtain the starting address of the translated basic block corresponding to the second basic block in the code cache, and jump to the execution at that starting address; if not found, translate the second basic block, and after the translation is completed, save the translated basic block corresponding to the second basic block to the code cache.

[0125] Optionally, the translation optimization module is specifically used for:

[0126] Insert a placeholder instruction sequence before the unoptimized instruction sequence, and insert the target instruction sequence before the placeholder instruction sequence;

[0127] The system-level binary translator further includes:

[0128] A basic block linking module, which is used to replace the placeholder instruction sequence with the link instruction sequence after obtaining the starting address of the translated basic block corresponding to the second basic block in the code cache during the first execution of the direct jump instruction in the first basic block.

[0129] Optionally, the unoptimized instruction sequence includes a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to the jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is satisfied; the second jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is not satisfied.

[0130] Optionally, the system-level binary translator further includes:

[0131] A first recording module, configured to record, in the translation stage of a target basic block, the actual address corresponding to the client virtual address of the target basic block in the structure of the target basic block; the target basic block includes the first basic block or the second basic block;

[0132] A second recording module, configured to, when performing basic block linking on the first basic block and the second basic block, read the client virtual address and the corresponding actual address of the second basic block from the structure of the second basic block and record them into the structure of the first basic block.

[0133] Optionally, the system-level binary translator further includes:

[0134] A non-page-crossing jump module, configured to, if it is determined that the second basic block does not cross a page, perform a jump through the link instruction sequence.

[0135] In the system-level binary translator provided by the embodiments of the present invention, during the dynamic binary translation process, when translating a direct jump instruction in the first basic block, it is identified whether the second basic block to which the direct jump instruction is to jump crosses a page, and according to whether the second basic block crosses a page and whether the virtual-to-physical address mapping relationship changes in the case where the second basic block crosses a page, the optimization operation performed on the execution of the direct jump instruction is refined. In the case where the second basic block does not cross a page, or in the case where the second basic block crosses a page but the virtual-to-physical address mapping relationship of the second basic block does not change, the execution of the direct jump instruction in the first basic block can be optimized, and a jump is performed through the link instruction sequence directly to the starting address of the translated basic block corresponding to the second basic block in the code cache, avoiding the basic block search operation performed by the unoptimized instruction sequence, which can improve the jump efficiency and thus improve the program running efficiency.

[0136] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference may be made to the partial description of the method embodiments.

[0137] Refer to Figure 5 , which is a schematic structural diagram of an electronic device provided by the embodiments of the present invention. AsFigure 5 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method in the foregoing embodiments.

[0138] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a program or a processor of a terminal, the terminal can execute the steps of the binary translation method in the foregoing embodiments.

[0139] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0140] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a binary translator, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0141] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0142] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal devices to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0143] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one process or multiple processes and / or one block or multiple blocks. Figure 1 one process or multiple processes and / or blocks Figure 1 steps for the functions specified in one block or multiple blocks.

[0144] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0145] Specific examples are used in this article to illustrate the principles and implementation modes of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A binary translation method, characterized in that, Applied to a system-level binary translator, the method includes: When translating a direct jump instruction in a first basic block, identifying whether a second basic block that the direct jump instruction is to jump to spans pages; If it is determined that the second basic block spans pages, insert a target instruction sequence before an unoptimized instruction sequence after the translation of the direct jump instruction, where the target instruction sequence is used to detect whether the direct jump instruction meets an optimization condition, and in the case where it is detected that the direct jump instruction meets the optimization condition, perform a jump through a link instruction sequence; the optimization condition includes: the virtual-to-physical address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the second basic block in the code cache; The target instruction sequence includes: A first instruction sequence for reading the client virtual address of the second basic block recorded when linking basic blocks; continue to execute sequentially; A second instruction sequence for, when determining that the value pointed to by the read client virtual address of the second basic block is empty, jumping to the unoptimized instruction sequence; if not empty, continue to execute sequentially; A third instruction sequence for reading the physical address corresponding to the client virtual address of the second basic block recorded when linking basic blocks; continue to execute sequentially; A fourth instruction sequence for querying the physical address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; continue to execute sequentially; A fifth instruction sequence for, when determining that the physical address during the current execution queried is inconsistent with the physical address when linking basic blocks read, jumping to the unoptimized instruction sequence; if consistent, determine that the optimization condition is met and continue to execute sequentially.

2. The method according to claim 1, characterized in that, The target instruction sequence is further used to jump to the unoptimized instruction sequence in the case where it is detected that the direct jump instruction does not meet the optimization condition.

3. The method according to claim 1, characterized in that, The unoptimized instruction sequence is used to jump to target search code, and the target search code performs the following operations: Search for the translated basic block corresponding to the second basic block in the code cache, and if found, obtain the starting address of the translated basic block corresponding to the second basic block in the code cache and jump to and execute at that starting address; If not found, translate the second basic block and save the translated basic block corresponding to the second basic block to the code cache after the translation is completed.

4. The method according to claim 1, wherein Inserting the target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction includes: Inserting a placeholder instruction sequence before the unoptimized instruction sequence, and inserting the target instruction sequence before the placeholder instruction sequence; The method further includes: During the first execution of the direct jump instruction in the first basic block, after obtaining the starting address of the translated basic block corresponding to the second basic block in the code cache, replacing the placeholder instruction sequence with the link instruction sequence.

5. The method according to claim 1, wherein The unoptimized instruction sequence includes a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to the jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is satisfied; The second jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is not satisfied.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: In the translation stage of the target basic block, record the actual address corresponding to the client virtual address of the target basic block in the structure of the target basic block; the target basic block includes the first basic block or the second basic block; When performing basic block linking on the first basic block and the second basic block, read the client virtual address and the corresponding actual address of the second basic block from the structure of the second basic block and record them in the structure of the first basic block.

7. The method according to any one of claims 1 to 5, characterized in that, The method further includes: If it is determined that the second basic block does not span pages, perform a jump through the link instruction sequence.

8. A system-level binary translator, characterized in that, The system-level binary translator includes: A translation recognition module, configured to, when translating a direct jump instruction in a first basic block, recognize whether the second basic block that the direct jump instruction is to jump to spans pages; A translation optimization module, configured to, if it is determined that the second basic block spans pages, insert a target instruction sequence before the unoptimized instruction sequence after the translation of the direct jump instruction, where the target instruction sequence is used to detect whether the direct jump instruction meets the optimization conditions, and in the case where it is detected that the direct jump instruction meets the optimization conditions, perform a jump through the link instruction sequence; the optimization conditions include: the virtual-to-physical address mapping relationship of the second basic block has not changed; the link instruction sequence is used to jump to the start address of the translated basic block corresponding to the second basic block in the code cache; The target instruction sequence includes: A first instruction sequence, configured to read the client virtual address of the second basic block recorded during basic block linking; continue to execute sequentially; A second instruction sequence, configured to, when determining that the value pointed to by the read client virtual address of the second basic block is empty, jump to the unoptimized instruction sequence; if not empty, continue to execute sequentially; A third instruction sequence, configured to read the actual address corresponding to the client virtual address of the second basic block recorded during basic block linking; continue to execute sequentially; A fourth instruction sequence, configured to query the actual address corresponding to the client virtual address of the second basic block during the current execution based on the read client virtual address of the second basic block; continue to execute sequentially; A fifth instruction sequence, configured to, when determining that the actual address during the current execution queried is inconsistent with the actual address read during basic block linking, jump to the unoptimized instruction sequence; if consistent, determine that the optimization conditions are met and continue to execute sequentially.

9. The system-level binary translator according to claim 8, wherein The target instruction sequence is further configured to, in the case where it is detected that the direct jump instruction does not meet the optimization conditions, jump to the unoptimized instruction sequence.

10. The system-level binary translator according to claim 8, wherein The unoptimized instruction sequence is used to jump to target search code, and the target search code performs the following operations: Search for the translated basic block corresponding to the second basic block in the code cache. If found, obtain the starting address of the translated basic block corresponding to the second basic block in the code cache and jump to that starting address for execution; If not found, translate the second basic block and save the translated basic block corresponding to the second basic block to the code cache after the translation is completed.

11. The system-level binary translator according to claim 8, wherein The translation optimization module is specifically configured to: Insert a placeholder instruction sequence before the unoptimized instruction sequence, and insert the target instruction sequence before the placeholder instruction sequence; The system-level binary translator further includes: A basic block linking module, configured to, during the first execution of the direct jump instruction in the first basic block, after obtaining the starting address of the translated basic block corresponding to the second basic block in the code cache, replace the placeholder instruction sequence with the linking instruction sequence.

12. The system-level binary translator according to claim 8, wherein The unoptimized instruction sequence includes a first jump instruction sequence and / or a second jump instruction sequence; the first jump instruction sequence is used to jump to the jump target of an unconditional jump instruction, or the first jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is satisfied; The second jump instruction sequence is used to jump to the jump target of a conditional jump instruction when the condition is not satisfied.

13. The system-level binary translator according to any one of claims 8 to 12, characterized in that The system-level binary translator further includes: A first recording module, configured to record the actual address corresponding to the client virtual address of the target basic block in the structure of the target basic block during the translation stage of the target basic block; the target basic block includes the first basic block or the second basic block; A second recording module, configured to, when performing basic block linking between the first basic block and the second basic block, read the client virtual address and the corresponding actual address of the second basic block from the structure of the second basic block and record them in the structure of the first basic block.

14. The system-level binary translator according to any one of claims 8 to 12, characterized in that The system-level binary translator further includes: A non-page-crossing jump module, configured to, if it is determined that the second basic block does not cross pages, perform a jump through the linking instruction sequence.

15. An electronic device, characterized in that, Includes: A processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete mutual communication through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method according to any one of claims 1 to 7.

16. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, the steps of the binary translation method according to any one of claims 1 to 7 are implemented.

17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, the steps of the binary translation method according to any one of claims 1 to 7 are implemented.

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