Basic block linking method, translator, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a basic block linking method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: in the process of executing a target search code, judging whether a jump source basic block meets a de-linking condition or not; the target search code is used for searching an initial address of the translated basic block corresponding to the jump target basic block in the code cache; the jump target basic block is a basic block to which the jump source basic block is to jump; the unlinking conditions comprise that the jump target basic block crosses pages, the virtual-real address mapping relation of the jump target basic block is changed, and the jump source basic block is in a linked state; if it is determined that the jump source basic block meets the unlinking condition, basic block unlinking is carried out on the jump source basic block; and carrying out basic block linking on the unlinked jump source basic block again. According to the embodiment of the invention, the number of times of searching the jump target basic block when the direct jump instruction is executed can be reduced, and the efficiency of executing the application program by the translator is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a basic block linking method, a translator, an electronic device and a readable storage medium. Background Art

[0002] Binary translation can convert the binary code of one ISA (Instruction Set Architecture) into the binary code of another instruction set architecture. Through binary translation technology, an application of one ISA (source architecture) can run on another ISA (target architecture).

[0003] Binary translation is performed in units of basic blocks (TB). A basic block is a set of instruction sequences executed sequentially in a program, with a single entry point and a single exit point. Once a program enters a basic block, all instructions in it will be executed sequentially until the exit of the basic block is reached. There will be no branching of control flow within the basic block (except for the sequential execution to the last instruction). The entry point is the first instruction of the basic block; the exit point is the last instruction of the basic block. The last instruction can be a jump instruction, a function call instruction, or a program termination instruction.

[0004] When a basic block ends with a jump instruction and the program executes to the jump instruction, the control flow needs to jump from the current basic block to another basic block, which involves a basic block search operation. This process usually requires a relatively high cost and affects the program execution efficiency. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide a basic block linking method that overcomes the above problems or at least partially solves the above problems, which can reduce the number of times the jump target basic block is searched when executing a direct jump instruction and improve the efficiency of the translator in executing the application.

[0006] Correspondingly, an embodiment of the present invention also provides a system-level binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses a basic block linking method, which is applied to a system-level binary translator. The method comprises: In the process of executing the target search code, it is determined whether the jump source basic block meets the unlinking condition; the target search code is used to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block to which the jump source basic block is to be jumped; the unlinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; If it is determined that the jump source basic block meets the delinking condition, delinking the jump source basic block; The delinked jump source basic block is relinked.

[0008] In a second aspect, an embodiment of the present invention discloses a system-level binary translator, the system-level binary translator comprising: A conditional judgment module is used to judge whether a jump source basic block meets a delinking condition during the execution of a target search code; the target search code is used to find the starting address of a translated basic block corresponding to the jump target basic block in a code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is a basic block to which the jump source basic block is to be jumped; the delinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; A delinking module, configured to delink the jump source basic block if it is determined that the jump source basic block satisfies the delinking condition; The linking module is used to re-link the jump source basic block after delinking.

[0009] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the basic block linking method as described in any of the above.

[0010] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the basic block linking method as described in any of the above can be implemented.

[0011] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the basic block linking methods described above.

[0012] The embodiments of the present invention include the following advantages: The embodiment of the present invention improves the execution process of the original target search code, and determines whether the jump source basic block meets the unlinking condition, and the unlinking condition includes: the jump target basic block crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state. In the case of determining that the jump source basic block meets the unlinking condition, the jump source basic block is unlinked, so that the jump source basic block can be re-linked with the correct jump address (such as the second starting address), so that when the jump crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, the execution of the direct jump instruction can also be optimized, and a direct jump is performed through a correct link instruction sequence (such as the second link instruction sequence), avoiding the need to execute an unoptimized instruction sequence for slow search each time, and reducing the number of times the jump target basic block is searched when executing a direct jump instruction, thereby improving the efficiency of the translator in executing the application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a binary translation architecture of the present invention; Figure 2 is a flowchart of a basic block linking method embodiment of the present invention; Figure 3 is a structural block diagram of an embodiment of a system-level binary translator of the present invention; Figure 4 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0016] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0017] Reference Figure 1 , shows a schematic diagram of the architecture of dynamic binary translation. Figure 1 As shown in the figure, dynamic binary translation adopts the "translate while running" method to translate the instructions of the client architecture into the instructions of the host architecture at runtime and run them on the host. After the translator reads the binary file of the target program (client program), it translates and executes it according to the granularity of basic blocks (TranslationBlock, TB). A basic block usually ends with a control flow change instruction (such as an indirect jump instruction, a function call instruction, etc.). Before executing a basic block, it first searches in the code cache. If a translated basic block is found, it executes the basic block. If a translated basic block is not found in the code cache, it translates the basic block and puts the translated basic block into the code cache, and then executes the translated basic block. After executing a basic block, it searches for the next basic block in the code cache, and repeats this cycle until the program execution ends.

[0018] Dynamic binary translators can be divided into user-level binary translators and system-level binary translators, and their application scopes are different. The application scope of user-level binary translators is mainly limited to the operation of a single user-mode program. They are suitable for executing target programs on different architectures without running the entire operating system. They are often used in software compatibility solutions that are cross-architecture but not cross-operating systems. System-level binary translators cover the operation of the entire system, including the operating system kernel and user-mode programs. They can simulate a complete computer system on different architectures and are usually used in software compatibility solutions that are both cross-architecture and cross-operating systems. System-level binary translators can also be used in scenarios such as virtualization, embedded development, and operating system migration.

[0019] The present invention provides a basic block linking method, which is applied to a system-level binary translator and can be used to optimize the execution of direct jump instructions.

[0020] Some concepts involved in the embodiments of the present invention are explained below.

[0021] The guest virtual address (GVA) is the virtual address space allocated by the guest operating system to its process or application.

[0022] The guest physical address (GPA) is the address obtained by the client operating system after converting the GVA through its memory management unit (MMU). It is the "physical address" considered by the client operating system or runtime environment. The client operating system maps the GVA to the GPA, but these addresses are not real physical addresses, but are further mapped to the address space of the host by the binary translator or virtualization layer.

[0023] The host virtual address (HVA) is the virtual address used by the host operating system for its own processes and the client.

[0024] GVA can be used to uniquely identify a basic block in user-level binary translation. Specifically, the user-level binary translator mainly translates the binary code of a single user process. In the context of a single process, the client virtual address GVA provides an independent and continuous virtual address space for the process. The GVA used by each process is unique, and the code and data within the process are organized and accessed according to the GVA. Therefore, in this relatively independent process environment, a basic block can be uniquely identified using GVA.

[0025] In system-level binary translation, both GVA and GPA need to be used to uniquely identify a basic block. Specifically, system-level binary translation involves the entire operating system and multiple processes it manages. Different processes may have the same GVA, but their actual locations in physical memory are different. The client physical address GPA represents the physical memory address from the perspective of the client operating system, which can reflect the actual location of the basic block in physical memory. Therefore, GVA alone cannot uniquely identify a basic block, and GPA needs to be combined to distinguish different basic blocks corresponding to the same GVA in different processes. Therefore, in system-level binary translation, both GVA and GPA need to be relied upon to uniquely identify a basic block.

[0026] Since the client program runs in the host environment, the physical memory of the client program is actually simulated by the virtual memory of the host. Therefore, it is necessary to establish a mapping relationship between GPA and HVA. This mapping relationship is maintained by the binary translation system to ensure that the physical memory accessed by the client can correctly correspond to the virtual memory space of the host. The relationship between GVA and HVA is indirect, and GPA is needed as an intermediate bridge. First, GVA is converted to GPA, and then GPA is mapped to HVA. Although GPA and HVA belong to different address spaces of the client and host respectively, they actually point to the same physical memory resource. For example, when the client program accesses the memory corresponding to a GPA, the binary translation system will map it to an HVA, and these two addresses correspond to the same actual memory data.

[0027] Since there is a one-to-one mapping relationship between the client physical address GPA and the host virtual address HVA in the system-level binary translation, the actual address corresponding to the client virtual address GVA can be the client physical address GPA or the host virtual address HVA.

[0028] Reference Figure 2 , shows a flowchart of a basic block linking method embodiment of the present invention, the method is applied to a system-level binary translator, and the method may include the following steps: Step 101: during the execution of the target search code, determine whether the jump source basic block meets the unlinking condition; the target search code is used to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block to which the jump source basic block is to be jumped; the unlinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; Step 102: If it is determined that the jump source basic block meets the delinking condition, then delink the jump source basic block; Step 103: relink the delinked jump source basic block.

[0029] In system-level binary translation, both the guest virtual address GVA and the actual address (guest physical address GPA or host virtual address HVA) are needed to uniquely identify a basic block.

[0030] In the memory management of the operating system, in order to effectively manage the memory, the memory is divided into pages of fixed size, which are the basic units of memory management. The page refers to a virtual page.

[0031] For ease of description, the system-level binary translator is also referred to as a translator in the embodiments of the present invention. Before executing the first basic block in a page, the translator checks whether the virtual-to-real address mapping relationship of the page is correct. The virtual-to-real address mapping relationship refers to the mapping relationship between the client virtual address GVA and the actual address. This is because the operating system may perform various operations on the memory, such as page replacement, memory allocation adjustment, etc., which may cause the virtual-to-real address mapping relationship to change. If the virtual-to-real address mapping relationship is correct (no change), it means that all address accesses in the page are predictable and safe. When executing subsequent basic blocks in the page, there is no need to repeatedly check the virtual-to-real address mapping relationship of the page.

[0032] In the embodiment of the present invention, the jump source basic block refers to a basic block ending with a direct jump instruction. The jump target basic block refers to a basic block to which the direct jump instruction in the jump source basic block is to jump.

[0033] The direct jump instruction explicitly specifies the jump target address. During the program compilation or assembly stage, the jump target address of the direct jump instruction has been determined, and the jump target will not change unless the program code is modified. The direct jump instruction carries the jump target address, which points to the first instruction of the basic block to be jumped to (jump target basic block). It can be understood that the address of a basic block described in the embodiment of the present invention refers to the address of the first instruction in the basic block. For example, the client virtual address GVA of basic block B refers to the client virtual address GVA of the first instruction in basic block B.

[0034] During program execution, there may be two situations: one is that the jump target basic block and the jump source basic block are in the same page, which is called the jump target basic block does not cross pages; the other is that the jump target basic block and the jump source basic block are not in the same page, which is called the jump target basic block crosses pages.

[0035] Since the jump target address of a direct jump instruction is fixed, unlike the jump target address of an indirect jump instruction which can only be determined during execution, when translating a direct jump instruction, if it is determined that the jump target basic block crosses pages, the translation of the direct jump instruction can be optimized and a target instruction sequence can be inserted. The target instruction sequence is used to optimize the execution of the direct jump instruction when executing the direct jump instruction. The jump is directly performed through a link instruction sequence. Under the premise of ensuring the correct cross-page jump, the search operation of the basic block during program operation is reduced, thereby improving the program operation efficiency. The link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache.

[0036] Furthermore, the target instruction sequence is also used to not optimize the execution of the direct jump instruction when it is detected that the direct jump instruction does not meet the optimization conditions, jump to the non-optimized instruction sequence, perform basic block search according to the original process, and then jump to ensure the correct jump.

[0037] Among them, the optimization conditions include: the jump target basic block crosses pages and the virtual-to-real address mapping relationship of the jump target basic block across pages has not changed, that is, when the direct jump instruction in the jump source basic block is executed this time, although the jump target basic block crosses pages, the virtual-to-real address mapping relationship of the jump target basic block has not changed compared with the virtual-to-real address mapping relationship during the first cross-page link.

[0038] However, if when executing a direct jump instruction in the jump source basic block, if the jump target basic block crosses pages and the virtual-to-real address mapping relationship changes, then each subsequent execution of the direct jump instruction in the jump source basic block can only jump to the unoptimized instruction sequence for jumping. The unoptimized instruction sequence needs to jump to the target search code to execute slow search logic, affecting the operating efficiency of the application.

[0039] Among them, the mapping relationship between the virtual and real addresses of the jump target basic block changes, which means that when the direct jump instruction in the jump source basic block is executed this time, when jumping to the jump target basic block, the actual address (such as GPA2) corresponding to the client virtual address (such as GVA1) of the jump target basic block changes relative to the actual address (such as GPA1) corresponding to the client virtual address (such as GVA1) of the jump target basic block when the jump source basic block is linked to the jump target basic block.

[0040] The target search code is used to execute the slow search logic, that is, to search the host virtual address HVA of the translated basic block corresponding to the jump target basic block according to the client virtual address GVA of the jump target basic block (such as basic block 2). The host virtual address HVA of the translated basic block corresponding to the jump target basic block refers to the starting address of the translated basic block corresponding to the jump target basic block in the code cache.

[0041] In order to optimize the execution of direct jump instructions and reduce the number of times the slow search logic is executed when the jump target basic block crosses pages and the virtual-to-real address mapping relationship changes, the embodiment of the present invention adds judgment and processing operations in the slow search logic (i.e., the target search code). It is judged whether the jump source basic block meets the delinking condition. The delinking condition includes: the jump target basic block crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state.

[0042] In one example, basic block 1 (jump source basic block) ends with a direct jump instruction, which is to jump to basic block 2 (jump target basic block).

[0043] In the translation stage, when translating to the direct jump instruction in basic block 1, if it is recognized that basic block 2 crosses pages, a placeholder instruction sequence is inserted before the unoptimized instruction sequence after the direct jump instruction is translated, and a target instruction sequence is inserted before the placeholder instruction sequence. The target instruction sequence is an instruction sequence under the host machine architecture. The embodiment of the present invention does not limit the form of the target instruction sequence, and different host machine architectures may have different forms of expression. The target instruction sequence may include a single or multiple instructions under the host machine architecture in different host machine architectures.

[0044] The placeholder instruction sequence may include at least one empty instruction (such as the NOP instruction of the host architecture). The placeholder instruction sequence is used to reserve a position for the subsequent execution of the basic block link. The NOP instruction (No Operation) is an instruction widely used in computer architecture, and its function is "no operation". When the CPU executes the NOP instruction, it will not have any substantial impact on the register, memory or program state, but simply consumes one or more clock cycles and then continues to execute the next instruction.

[0045] When the direct jump instruction in basic block 1 is executed for the first time, basic block 1 is in an unlinked state, and the unoptimized instruction sequence is executed. The unoptimized instruction sequence will jump to the target search code to find the starting address of the translated basic block corresponding to basic block 2 in the code cache. If the translated basic block corresponding to basic block 2 is found in the code cache, basic block 1 and basic block 2 are linked, and the jump is made to the starting address of the translated basic block corresponding to basic block 2 in the code cache; if not found, the translation process is exited, basic block 2 is translated, and the translated basic block corresponding to basic block 2 is stored in the code cache after the translation is completed, and basic block 1 and basic block 2 are linked, and the jump is made to the starting address of the translated basic block corresponding to basic block 2 in the code cache. In addition, the virtual-real address mapping relationship of basic block 2 during linking is recorded, that is, the client virtual address (such as GVA1) and the corresponding real address (such as GPA1) of basic block 2 are recorded.

[0046] After the basic block is linked, the jump source basic block is in a linked state, and the placeholder instruction sequence is replaced by the link instruction sequence. Therefore, when the direct jump instruction in the jump source basic block is executed next time, if the target instruction sequence is determined to meet the optimization conditions, the link instruction sequence is directly executed, and then directly jumps to the starting address (HVA) of the translated basic block corresponding to the jump target basic block in the code cache, and the target search code will not be executed again. This can avoid the process of searching the starting address (HVA) of the translated basic block corresponding to the jump target basic block in the code cache according to the GVA of the jump target basic block each time the target search code is executed, which can improve the program running efficiency.

[0047] In a specific implementation, basic block linking is performed on a jump source basic block (such as basic block 1) and a jump target basic block (such as basic block 2), which means replacing a placeholder instruction sequence with a link instruction sequence, where the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache.

[0048] In the above example, the first basic block linking of basic block 1 and basic block 2 is called the first cross-page linking, that is, replacing the placeholder instruction sequence with the first linking instruction sequence. The first linking instruction sequence is used to jump to the first starting address of the translated basic block corresponding to basic block 2 in the code cache. For ease of description, in the embodiment of the present invention, the starting address of the translated basic block corresponding to the jump target basic block found during the first cross-page linking is called the first starting address; and the linking instruction sequence generated during the first cross-page linking is called the first linking instruction sequence.

[0049] When the direct jump instruction in basic block 1 is executed for the Nth time (N≥2), the target instruction sequence will be executed. The target instruction sequence determines whether the direct jump instruction meets the optimization conditions. If the optimization conditions are met, that is, the virtual-to-real address mapping relationship of basic block 2 has not changed, that is, the actual address corresponding to the client virtual address GVA1 of basic block 2 is still GPA1 during this execution, then the jump can be performed through the first link instruction sequence; if the optimization conditions are not met, that is, the virtual-to-real address mapping relationship of basic block 2 has changed, that is, the actual address corresponding to the client virtual address GVA1 of basic block 2 is not GPA1 during this execution, if it becomes GPA2, then the jump is performed by executing the non-optimized instruction sequence.

[0050] Since the jump target basic block (such as basic block 2) crosses pages and the virtual-real address mapping relationship changes, each subsequent execution can only use the unoptimized instruction sequence to implement the jump. The unoptimized instruction sequence needs to jump to the target search code to execute slow search logic, affecting the running efficiency of the application.

[0051] The embodiment of the present invention optimizes the execution process of the target search code, so that when executing the target instruction sequence, if it is determined that the direct jump instruction does not meet the optimization conditions, the jump is jumped to the unoptimized instruction sequence and then the target search code is executed. The jump source basic block that meets the unlinking conditions can be unlinked, and then the unlinked jump source basic block can be re-linked. In this way, when the jump target basic block crosses pages and the virtual-to-real address mapping relationship changes, the execution optimization of the direct jump instruction in the jump source basic block can be achieved by unlinking and relinking.

[0052] Specifically, by performing basic block unlinking on the jump source basic block (such as basic block 1), the previous first link instruction sequence can be cancelled. The first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to basic block 2 in the code cache. Since the virtual-to-real address mapping relationship of basic block 2 may change during subsequent execution, if the first link instruction sequence is still used to jump, it may jump to an incorrect address in the case of change. Therefore, in the embodiment of the present invention, the jump source basic block (such as basic block 1) that meets the unlinking condition is unlinked to cancel the previous first link instruction sequence, and the starting address of the translated basic block corresponding to basic block 2 in the code cache is re-searched, which is called the second starting address. The second starting address is the correct address obtained after the virtual-to-real address mapping relationship of basic block 2 changes. The jump source basic block (such as basic block 1) is re-linked using the correct address (second starting address), such as generating a second link instruction sequence, and the second link instruction sequence can be used to jump to the correct address after the virtual-to-real address mapping relationship of basic block 2 changes.

[0053] Therefore, by performing basic block unlinking on the jump source basic block that meets the unlinking condition, and then using the correct address to re-link the unlinked jump source basic block, when the direct jump instruction in the jump source basic block is subsequently executed, the relinked link instruction sequence (such as the second link instruction sequence) can be executed, and then directly jump to the starting address (HVA) of the translated basic block corresponding to the jump target basic block in the code cache, without having to execute the target search code again, and can avoid executing the target search code each time. The process of searching the starting address (HVA) of the translated basic block corresponding to the jump target basic block in the code cache according to the GVA of the jump target basic block can improve the program running efficiency.

[0054] In practical applications, after the jump source basic block and the cross-page jump target basic block are first linked, the virtual-to-real address mapping relationship of the jump target basic block may change, but usually does not change frequently. Therefore, through the embodiment of the present invention, after the virtual-to-real address mapping relationship of the jump target basic block changes, the second link instruction sequence generated by relinking can be used to perform a direct jump, which can improve the program running efficiency.

[0055] In an optional embodiment of the present invention, the operation of performing basic block linking on any jump source basic block may include: Step S11, determining whether the jump target basic block corresponding to the jump source basic block crosses pages; Step S12: If it is determined that the jump target basic block crosses pages, determine whether the jump source basic block is the first cross-page link; Step S13: If it is determined that the jump source basic block is linked across pages for the first time, the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual-real address mapping relationship of the jump target basic block during the first cross-page linking is recorded; Step S14: If it is determined that the jump source basic block is not the first cross-page link, the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page link that has been recorded is updated.

[0056] In a specific implementation, if the jump target basic block does not cross pages, that is, the jump target basic block and the jump source basic block are on the same virtual page, it is called a non-cross-page jump. For the case of a non-cross-page jump, the execution of the direct jump instruction can also be optimized by basic block linking. For example, basic block 3 ends with a direct jump instruction, and the direct jump instruction is to jump to basic block 4, and basic block 3 and basic block 4 are on the same virtual page. When the direct jump instruction in basic block 3 is executed for the first time to jump to basic block 4, basic block 3 and basic block 4 can be basic block linked, so that subsequent executions can use the link instruction sequence to perform direct jumps.

[0057] In order to realize cross-page jump and optimize the execution of direct jump instructions through basic block linking when the virtual-to-real address mapping relationship of the jump target basic block changes, an embodiment of the present invention improves the original basic block linking process of the translator, and the improved process is shown in steps S11 to S14.

[0058] Since the embodiment of the present invention optimizes the cross-page jump situation, when a jump source basic block is linked to a basic block, it is first determined whether the jump target basic block corresponding to the jump source basic block crosses pages. If it is determined that the jump target basic block crosses pages, it is further determined whether the jump source basic block is linked across pages for the first time.

[0059] If it is determined that the jump source basic block is linked across pages for the first time, the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page linking is recorded, such as recording the client virtual address (such as GVA1) and the corresponding real address (such as GPA1) of the jump target basic block. The purpose of recording the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page linking is to determine whether the virtual-to-real address mapping relationship of the jump target basic block has changed during the next execution.

[0060] It should be noted that what is replaced during the first cross-page link is the placeholder instruction sequence generated during the translation phase. For example, in the above example, during the translation phase, when translating to the direct jump instruction in basic block 1, a placeholder instruction sequence is inserted before the translated non-optimized instruction, and a target instruction sequence is inserted before the placeholder instruction sequence. When basic block 1 and basic block 2 are linked across pages for the first time, the placeholder instruction sequence is replaced with a first link instruction sequence, which is used to jump to the first starting address of the translated basic block corresponding to basic block 2 in the code cache.

[0061] The next time a direct jump instruction in basic block 1 is executed, the target instruction sequence will be executed. If the target instruction sequence determines that basic block 2 crosses pages and the virtual-to-real address mapping relationship changes, the unoptimized instruction sequence will be executed, and then jump to the target search code to execute step 101. Step 101 determines whether basic block 1 meets the unlinking condition; since basic block 2 crosses pages and the virtual-to-real address mapping relationship changes, and basic block 1 is in a linked state, it is determined that basic block 1 meets the unlinking condition, and basic block 1 can be unlinked.

[0062] Since the virtual-to-real address mapping relationship of basic block 2 changes during this execution, the first starting address to which the first link instruction sequence generated during the first cross-page link may jump may point to an incorrect address. Therefore, basic block 1 is unlinked to cancel the first link instruction sequence and disconnect the link between basic block 1 and an incorrect jump address.

[0063] Furthermore, the step of unlinking the jump source basic block may include: The first link instruction sequence in the jump source basic block is replaced with a placeholder instruction sequence; the first link instruction sequence is generated when the jump source basic block is linked across pages for the first time, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

[0064] In the embodiment of the present invention, the basic block linking operation is to replace the placeholder instruction sequence with the linking instruction sequence. Conversely, the basic block unlinking operation is to replace (restore) the linking instruction sequence with the placeholder instruction sequence.

[0065] Since the first starting address pointed to by the first link instruction sequence generated during the first cross-page link may change during the subsequent execution process due to the change in the virtual-to-real address mapping relationship of the jump target basic block, the embodiment of the present invention, when determining that the jump source basic block meets the unlinking conditions, performs basic block unlinking on the jump source basic block and restores the first link instruction sequence to a placeholder instruction sequence.

[0066] After the basic block 1 is delinked, the basic block 1 is in an unlinked state, and the delinked basic block 1 may be relinked.

[0067] In step S14, if it is determined that the jump source basic block is not the first cross-page link, that is, it is a basic block link re-performed after the jump source basic block is unlinked, then the jump source basic block is linked using the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache, and the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page link that has been recorded is updated.

[0068] For example, after the basic block 1 is unlinked, the basic block 1 is relinked, and this basic block link is not the first cross-page link. Since the virtual-to-real address mapping relationship of basic block 2 has changed, it is necessary to use the second starting address of the translated basic block corresponding to the basic block 2 found this time in the code cache to relink the basic block 1. The second starting address is the starting address of the translated basic block corresponding to the basic block 2 found in the code cache when the direct jump instruction in basic block 1 is executed this time, after the virtual-to-real address mapping relationship of basic block 2 changes. Therefore, the second starting address is a correct jump address. Relinking the basic block 1 using the second starting address can ensure that it jumps to the correct address the next time it is executed.

[0069] In addition, since the virtual-to-real address mapping relationship of the jump target basic block is recorded during the first cross-page link, in the subsequent execution process, whether the virtual-to-real address mapping relationship of the jump target basic block has changed is determined by comparing it with the virtual-to-real address mapping relationship of the jump target basic block recorded during the first cross-page link. Therefore, when re-performing cross-page linking, it is necessary to update the virtual-to-real address mapping relationship of the jump target basic block recorded during the first cross-page link. Therefore, in the subsequent execution process, it can be compared with the updated record, and the correctness of the process can be guaranteed.

[0070] Furthermore, the re-linking of the jump source basic block after delinking may include: The second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is obtained, and the placeholder instruction sequence in the jump source basic block is replaced with a second link instruction sequence, where the second link instruction sequence is used to jump to the second starting address.

[0071] It should be noted that the starting address of the translated basic block corresponding to the jump target basic block in the code cache can be found through the target search code. Specifically, the target search code first searches the code cache for whether there is a translated basic block corresponding to the jump target basic block. If so, it is directly found; if not, the current process is exited and the translation process is entered to translate the jump target basic block. After the translation is completed, the translated basic block corresponding to the jump target basic block is stored in the code cache, and the starting address of the translated basic block corresponding to the jump target basic block in the code cache is obtained.

[0072] It can be understood that, in the process of re-linking the jump source basic block after delinking, the placeholder instruction sequence in the jump source basic block is replaced with the second link instruction sequence, and the placeholder instruction sequence is restored when the jump source basic block is delinked.

[0073] The next time the direct jump instruction in basic block 1 is executed, the target instruction sequence is executed. The target instruction sequence can read the recorded virtual-to-real address mapping relationship of basic block 2 during the first cross-page link, and compare it with the virtual-to-real address mapping relationship of basic block 2 during this execution. Since the recorded virtual-to-real address mapping relationship has been updated to the changed virtual-to-real address mapping relationship during relinking, the target instruction sequence detects that the virtual-to-real address mapping relationship of basic block 2 has not changed during this execution, and can use the link instruction sequence to jump directly, specifically, jump directly to the second starting address through the second link instruction sequence.

[0074] If the target instruction sequence detects that the virtual-to-real address mapping relationship of basic block 2 has changed during this execution, it can jump to the unoptimized instruction sequence and then enter the target search code, that is, execute step 101. If it is determined that the unlinking conditions are met, the basic block can be unlinked again, and the basic block linking process can be re-performed.

[0075] The embodiment of the present invention improves the execution process of the original target search code. When it is determined that the unlinking condition is met, the jump source basic block is unlinked, so that the jump source basic block can be re-linked using the correct jump address (such as the second starting address). When the jump occurs across pages and the virtual-to-real address mapping relationship of the jump target basic block changes, the execution of the direct jump instruction can also be optimized. A fast jump is performed through a correct link instruction sequence (such as the second link instruction sequence), avoiding the use of an unoptimized instruction sequence for slow search each time, thereby improving the efficiency of the translator in executing the application.

[0076] In a specific implementation, direct jump instructions may include unconditional jump instructions and conditional jump instructions. An unconditional jump instruction is an instruction that causes the program to immediately jump to a specified target address to continue execution regardless of any conditions. Once an unconditional jump instruction is executed, the program will directly jump to the address specified in the instruction. A conditional jump instruction is an instruction that determines whether to jump to a specified target address based on specific conditions.

[0077] The conditional jump instruction has two jump branches: the branch is taken or not taken. When the condition of the conditional jump instruction is met, the program will jump to the specified target address to continue execution. This situation is called the branch is taken, that is, the jump operation is executed. When the condition of the conditional jump instruction is not met, the program will not jump, but continue to execute the next instruction sequentially. This situation is called the branch is not taken, that is, the jump operation is not executed.

[0078] Therefore, a direct jump instruction may have one jump target or two jump targets. For an unconditional jump instruction, there is only one jump target. For a conditional jump instruction, there are two jump targets.

[0079] In an embodiment of the present invention, the jump target basic block may include a first jump target basic block or a second jump target basic block; the first jump target basic block is the jump target of an unconditional jump instruction, or the jump target (taken) of a conditional jump instruction when a condition is met; the second jump target basic block is the jump target (not taken) of a conditional jump instruction when the condition is not met.

[0080] In an optional embodiment of the present invention, the structure of each basic block may include a first variable, the initial value of the first variable is empty, and the method may further include: Step S21: If it is determined that the jump target basic block crosses pages, a pointer to the structure of the jump target basic block is recorded in a first variable in the structure of the jump source basic block; Step S22: During the execution of the target search code, determine whether the jump source basic block is in a linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty.

[0081] In the embodiment of the present invention, a first variable is added to the structure of each basic block. The first variable may be a pointer variable, which is used to record the pointer of the structure of the linked jump target basic block in the structure of the jump source basic block. The initial value of the first variable is null, indicating that the jump source basic block has no linked jump target basic block.

[0082] When the embodiment of the present invention executes step S12, if it is determined that the jump target basic block crosses pages, the pointer of the structure of the jump target basic block is recorded in the first variable in the structure of the jump source basic block. For example, the pointer of the structure of basic block 2 is recorded in the first variable in the structure of basic block 1, and the pointer points to the structure of basic block 2.

[0083] Furthermore, a direct jump instruction may have one jump target or two jump targets, so two first variables may be used to record two different jump targets respectively. For example, the first variable next_tb0 is used to record the pointer of the structure of the first jump target basic block, and the first variable next_tb1 is used to record the pointer of the structure of the second jump target basic block.

[0084] In the process of executing step 101, when it is determined that the jump target basic block crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, it is also necessary to determine whether the jump source basic block is in a linked state. At this time, the value of the first variable in the structure of the jump source basic block can be read, and the value points to the structure of the linked jump target basic block. If the value of the read first variable is empty, it means that the jump source basic block has no linked jump target basic block and is in an unlinked state; if the value of the read first variable is not empty, it means that the jump source basic block is in a linked state.

[0085] The embodiment of the present invention can quickly determine whether the jump source basic block is in a linked state during the execution of the target search code by adding a first variable in the structure of the basic block.

[0086] In an optional embodiment of the present invention, the structure of each basic block may include a second variable, the initial value of the second variable is a first value, and the determining whether the jump source basic block is the first cross-page link may include: The value of the second variable in the structure of the jump source basic block is read. If the value of the second variable is a first value, it is determined that the jump source basic block is linked across pages for the first time; if the value of the second variable is a second value, it is determined that the jump source basic block is not linked across pages for the first time.

[0087] In the embodiment of the present invention, a second variable is added to the structure of each basic block. The second variable may be a Boolean variable used to identify whether the basic block has been linked across pages for the first time.

[0088] The initial value of the second variable is the first value (such as false), indicating that the basic block has not been linked across pages for the first time. If the value of the second variable in the structure of a basic block is the second value (such as true), it indicates that the basic block has been linked across pages for the first time.

[0089] When executing step S12, the value of the second variable in the structure of the jump source basic block can be read, and according to whether the value of the read second variable is the first value or the second value, if the value of the read second variable is the first value, it means that the jump source basic block has not been linked across pages for the first time, and the basic block linking performed on the jump source basic block this time is the first cross-page link. If the value of the read second variable is the second value, it means that the jump source basic block has been linked across pages for the first time, and the basic block linking performed on the jump source basic block this time is not the first cross-page link, but a re-cross-page link.

[0090] Furthermore, the method may also include: When it is determined that the jump source basic block is linked across pages for the first time, after basic block linking is performed on the jump source basic block, the value of the second variable in the structure of the jump source basic block is set to a second value.

[0091] Specifically, after step S13 is executed, the value of the second variable in the structure of the jump source basic block is set to the second value, indicating that the jump source basic block has been linked across pages for the first time.

[0092] The embodiment of the present invention adds a second variable to the structure of the basic block, and can quickly determine whether the jump source basic block is linked across pages for the first time during the execution of basic block linking.

[0093] The structure of a basic block is a data structure used in an interpreter to represent and store basic block information. It is understandable that the embodiment of the present invention does not limit the positions of the first variable and the second variable in the structure of a basic block.

[0094] It should be noted that, in the embodiment of the present invention, in the execution stage, the jump source basic block and the jump target basic block refer to the basic blocks under the translated host machine instruction architecture. In the translation stage, the jump source basic block and the jump target basic block refer to the basic blocks under the client machine instruction architecture before translation. The unoptimized instruction sequence, the link instruction sequence (including the first link instruction sequence and the second link instruction sequence), the target instruction sequence, the placeholder instruction sequence, and the target search code are all instruction sequences under the host machine instruction architecture.

[0095] In a specific implementation, for a jump source basic block ending with a direct jump instruction, when the jump source basic block is executed for the first time, the jump source basic block is in an unlinked state. When the direct jump instruction is executed, the current process is exited and the translation context is entered to translate the jump target basic block. After the translation is completed, the jump source basic block and the jump target basic block are linked.

[0096] In one example, the embodiment of the present invention refers to the original basic block linking logic of the translator as the basic linking logic. The embodiment of the present invention adds the following steps A1 to A4 before the basic linking logic: A1, determine whether the jump target basic block crosses pages. If not, execute A5; if so, execute A2; A2. In the first variable of the structure of the jump source basic block, record the pointer of the structure of the jump target basic block; execute A3; A3, read the value of the second variable in the structure of the jump source basic block. If the value of the second variable is the first value, it means that this is the first cross-page link of the jump source basic block, then set the value of the second variable to the second value, and execute A5; if the value of the second variable is the second value, it means that this is the relink of the jump source basic block, then execute A4; A4, obtaining the second starting address of the translated basic block corresponding to the jump target basic block in the code cache, using the second starting address to replace the placeholder instruction sequence generated during the delinking process, and updating the recorded virtual-real address mapping relationship of the jump target basic block during the first cross-page link; exiting the current basic block linking process; A5. Execute basic link logic.

[0097] The basic link logic includes: replacing the placeholder instruction sequence with the first link instruction sequence, and recording the virtual-real address mapping relationship of the jump target basic block during the first cross-page link.

[0098] In a specific implementation, since the target search code needs to perform multiple steps of operations and contains a large number of instructions, the target search code can be used as a common code and stored in a common basic block. There are many reasons for entering the target search code. For example, when executing the target instruction sequence, if it is detected that the jump target basic block crosses pages and the virtual-to-real address mapping relationship changes, it jumps to the unoptimized instruction sequence and then executes the target search code. For example, when executing a direct jump instruction in a jump source basic block, the jump source basic block is in an unlinked state, then the target search code is executed to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache. For example, when executing a direct jump instruction in a jump source basic block, the jump target basic block corresponding to the direct jump instruction is invalidated due to code self-modification, then the target search code is executed to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache.

[0099] In one example, the embodiment of the present invention refers to the operation performed by the original target search code of the translator as a slow search logic. The embodiment of the present invention adds the following steps B1 to B4 to the slow search logic: B1, determine whether the jump target basic block crosses pages. If so, execute B2; if not, execute B5; B2, read the first variable from the structure of the jump source basic block. If the value of the first variable is empty, it means that the jump source basic block is in an unlinked state, and execute B5; if the value of the first variable is not empty, it means that the jump source basic block is in a linked state, and execute B3; B3, determine whether the virtual-to-real address mapping relationship of the jump target basic block has changed. If not, execute B5; if changed, execute B4; B4, determining that the jump source basic block meets the unlinking condition, unlinking the jump source basic block, and replacing the first link instruction sequence with a placeholder instruction sequence; B5. Execute slow search logic.

[0100] Furthermore, the embodiment of the present invention can record the client virtual address and the corresponding actual address of the jump target basic block when basic block linking is performed on any basic block. The step of judging whether the virtual-to-real address mapping relationship of the jump target basic block has changed in B3 may include: reading the client virtual address and the corresponding actual address of the jump target basic block recorded when the basic block is linked, querying the actual address corresponding to the client virtual address of the jump target basic block during this execution based on the read client virtual address of the jump target basic block, judging whether the queried actual address during this execution is consistent with the actual address read during basic block linking, if they are consistent, judging that the virtual-to-real address mapping relationship of the jump target basic block has not changed; if they are inconsistent, judging that the virtual-to-real address mapping relationship of the jump target basic block has changed.

[0101] Wherein, based on the read client virtual address of the jump target basic block, the actual address corresponding to the client virtual address of the jump target basic block during this execution is queried, which can be queried through the software address translation lookaside buffer; exemplary, the query is performed through the software address translation lookaside buffer; the software address translation lookaside buffer is used to store the mapping relationship between the most recently used GVA and GPA to accelerate the address translation process. Therefore, based on the GVA, the software address translation lookaside buffer can be queried to obtain the GPA corresponding to the GVA.

[0102] The slow search logic in B5 may include: searching for the translated basic block corresponding to the jump target basic block in the code cache, and if found, obtaining the starting address of the translated basic block corresponding to the jump target basic block in the code cache, and jumping to the starting address for execution; if not found, entering the translation process, translating the jump target basic block, and after the translation is completed, saving the translated basic block corresponding to the jump target basic block to the code cache, obtaining the starting address of the translated basic block corresponding to the jump target basic block in the code cache, and jumping to the starting address for execution.

[0103] It should be noted that the embodiment of the present invention does not limit the positions of the inserted B1 to B4, and they can be inserted at any position such as before or after the slow search logic.

[0104] In summary, the embodiment of the present invention improves the execution process of the original target search code to determine whether the jump source basic block meets the unlinking condition, and the unlinking condition includes: the jump target basic block crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state. In the case of determining that the jump source basic block meets the unlinking condition, the jump source basic block is unlinked, so that the jump source basic block can be re-linked with the correct jump address (such as the second starting address), so that when the jump crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, the execution of the direct jump instruction can also be optimized, and a direct jump is performed through a correct link instruction sequence (such as the second link instruction sequence), avoiding the need to execute an unoptimized instruction sequence for slow search every time, which can reduce the number of times the jump target basic block is searched when executing a direct jump instruction, and improve the efficiency of the translator in executing the application.

[0105] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0106] Reference Figure 3 , shows a structural block diagram of an embodiment of a system-level binary translator of the present invention, and the system-level binary translator may include: The condition judgment module 201 is used to judge whether the jump source basic block meets the delinking condition during the execution of the target search code; the target search code is used to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block to which the jump source basic block is to be jumped; the delinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; The delinking module 202 is configured to delink the jump source basic block if it is determined that the jump source basic block satisfies the delinking condition; The linking module 203 is used to re-link the delinked jump source basic block.

[0107] Optionally, the link module includes: The first judgment submodule is used to judge whether the jump target basic block corresponding to the jump source basic block crosses pages; A second judgment submodule is used to judge whether the jump source basic block is linked across pages for the first time if it is determined that the jump target basic block crosses pages; A first linking submodule is used to perform basic block linking on the jump source basic block using the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache if it is determined that the jump source basic block is linked across pages for the first time, and record the virtual-real address mapping relationship of the jump target basic block during the first cross-page linking; The second linking submodule is used to perform basic block linking on the jump source basic block if it is determined that the jump source basic block is not the first cross-page link, using the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache, and updating the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page link that has been recorded.

[0108] Optionally, the structure of each basic block includes a first variable, the initial value of the first variable is empty, and the system-level binary translator further includes: A pointer recording module, configured to record a pointer of a structure of the jump target basic block in a first variable in a structure of the jump source basic block if it is determined that the jump target basic block crosses pages; The state judgment module is used to determine whether the jump source basic block is in a linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty during the execution of the target search code.

[0109] Optionally, the structure of each basic block includes a second variable, the initial value of the second variable is a first value, and the second judgment submodule is specifically used to: Reading the value of a second variable in the structure of the jump source basic block, and if the value of the second variable is a first value, determining that the jump source basic block is the first cross-page link; if the value of the second variable is a second value, determining that the jump source basic block is not the first cross-page link; The system-level binary translator also includes: The variable value updating module is used to set the value of the second variable in the structure of the jump source basic block to a second value after basic block linking is performed on the jump source basic block when it is determined that the jump source basic block is linked across pages for the first time.

[0110] Optionally, the denaturing module is specifically used for: The first link instruction sequence in the jump source basic block is replaced with a placeholder instruction sequence; the first link instruction sequence is generated when the jump source basic block is linked across pages for the first time, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

[0111] Optionally, the link module is specifically used to: The second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is obtained, and the placeholder instruction sequence in the jump source basic block is replaced with a second link instruction sequence, where the second link instruction sequence is used to jump to the second starting address.

[0112] Optionally, the jump target basic block includes a first jump target basic block or a second jump target basic block; the first jump target basic block is the jump target of an unconditional jump instruction, or the jump target of a conditional jump instruction when a condition is met; the second jump target basic block is the jump target of a conditional jump instruction when the condition is not met.

[0113] Optionally, the system-level binary translator further includes: An optimization execution module is used to execute a target instruction sequence when executing a direct jump instruction in the jump source basic block, if it is determined that the jump target basic block crosses pages; the target instruction sequence is the content inserted when translating the direct jump instruction and determining that the jump target basic block crosses pages; the target instruction sequence is used to jump through a link instruction sequence when it is detected that the direct jump instruction meets the optimization condition, otherwise jump through a non-optimized instruction sequence; the optimization condition includes: the virtual-to-real address mapping relationship of the jump target basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the non-optimized instruction sequence is used to jump to the target search code.

[0114] The embodiment of the present invention provides a system-level binary translator, which improves the execution process of the original target search code, and determines whether the jump source basic block meets the unlinking condition, and the unlinking condition includes: the jump target basic block crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state. In the case of determining that the jump source basic block meets the unlinking condition, the jump source basic block is unlinked, so that the jump source basic block can be re-linked with the correct jump address (such as the second starting address), so that when the jump crosses pages and the virtual-to-real address mapping relationship of the jump target basic block changes, the execution of the direct jump instruction can also be optimized, and the direct jump is performed through the correct link instruction sequence (such as the second link instruction sequence), avoiding the need to execute the unoptimized instruction sequence for slow search every time, and reducing the number of times the jump target basic block is searched when executing the direct jump instruction, thereby improving the efficiency of the translator in executing the application program.

[0115] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0116] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the basic block linking method of the aforementioned embodiment.

[0117] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or processor of a terminal, the terminal is enabled to execute the steps of the basic block linking method of the aforementioned embodiment.

[0118] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0119] Those skilled in the art will appreciate that the embodiments of the embodiments of the present invention may be provided as methods, binary translators, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0120] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0121] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0122] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0123] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0124] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A basic block linking method, characterized in that: Applied to a system-level binary translator, the method comprises: In the process of executing the target search code, it is determined whether the jump source basic block meets the unlinking condition; the target search code is used to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block to which the jump source basic block is to be jumped; the unlinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; If it is determined that the jump source basic block meets the delinking condition, delinking the jump source basic block; The delinked jump source basic block is relinked.

2. The method according to claim 1, characterized in that The basic block linking operation is performed on any jump source basic block, including: Determine whether the jump target basic block corresponding to the jump source basic block crosses pages; If it is determined that the jump target basic block crosses pages, then determining whether the jump source basic block is linked across pages for the first time; If it is determined that the jump source basic block is linked across pages for the first time, the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual-real address mapping relationship of the jump target basic block during the first cross-page linking is recorded; If it is determined that the jump source basic block is not the first cross-page link, the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page link that has been recorded is updated.

3. The method according to claim 2, characterized in that The structure of each basic block includes a first variable, and the initial value of the first variable is empty. The method further includes: If it is determined that the jump target basic block crosses pages, the pointer of the structure of the jump target basic block is recorded in the first variable in the structure of the jump source basic block; In the process of executing the target search code, it is determined whether the jump source basic block is in a linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty.

4. The method according to claim 2, characterized in that: The structure of each basic block includes a second variable, the initial value of the second variable is a first value, and the determining whether the jump source basic block is the first cross-page link includes: Reading the value of a second variable in the structure of the jump source basic block, and if the value of the second variable is a first value, determining that the jump source basic block is the first cross-page link; if the value of the second variable is a second value, determining that the jump source basic block is not the first cross-page link; The method further comprises: When it is determined that the jump source basic block is linked across pages for the first time, after basic block linking is performed on the jump source basic block, the value of the second variable in the structure of the jump source basic block is set to a second value.

5. The method according to any one of claims 1 to 4, characterized in that: The step of performing basic block unlinking on the jump source basic block comprises: The first link instruction sequence in the jump source basic block is replaced with a placeholder instruction sequence; the first link instruction sequence is generated when the jump source basic block is linked across pages for the first time, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

6. The method according to any one of claims 1 to 4, characterized in that: The re-linking of the jump source basic block after delinking comprises: The second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is obtained, and the placeholder instruction sequence in the jump source basic block is replaced with a second link instruction sequence, where the second link instruction sequence is used to jump to the second starting address.

7. The method according to any one of claims 1 to 4, characterized in that: The jump target basic block includes a first jump target basic block or a second jump target basic block; the first jump target basic block is a jump target of an unconditional jump instruction, or a jump target of a conditional jump instruction when a condition is met; The second jump target basic block is the jump target of the conditional jump instruction when the condition is not satisfied.

8. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: When executing a direct jump instruction in the jump source basic block, if it is determined that the jump target basic block crosses pages, a target instruction sequence is executed; the target instruction sequence is the content inserted when translating the direct jump instruction and determining that the jump target basic block crosses pages; the target instruction sequence is used to jump through a link instruction sequence when it is detected that the direct jump instruction meets the optimization conditions, otherwise it jumps through a non-optimized instruction sequence; the optimization conditions include: the virtual-to-real address mapping relationship of the jump target basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the non-optimized instruction sequence is used to jump to the target search code.

9. A system-level binary translator, characterized in that: The system-level binary translator comprises: A conditional judgment module is used to judge whether a jump source basic block meets a delinking condition during the execution of a target search code; the target search code is used to find the starting address of a translated basic block corresponding to the jump target basic block in a code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is a basic block to which the jump source basic block is to be jumped; the delinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; A delinking module, configured to delink the jump source basic block if it is determined that the jump source basic block satisfies the delinking condition; The linking module is used to re-link the jump source basic block after delinking.

10. The system-level binary translator according to claim 9, characterized in that: The link module comprises: The first judgment submodule is used to judge whether the jump target basic block corresponding to the jump source basic block crosses pages; A second judgment submodule is used to judge whether the jump source basic block is linked across pages for the first time if it is determined that the jump target basic block crosses pages; A first linking submodule is used to perform basic block linking on the jump source basic block using the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache if it is determined that the jump source basic block is linked across pages for the first time, and record the virtual-real address mapping relationship of the jump target basic block during the first cross-page linking; The second linking submodule is used to perform basic block linking on the jump source basic block if it is determined that the jump source basic block is not the first cross-page link, using the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache, and updating the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page link that has been recorded.

11. The system-level binary translator according to claim 10, characterized in that: The structure of each basic block includes a first variable, the initial value of the first variable is empty, and the system-level binary translator further includes: A pointer recording module, configured to record a pointer of a structure of the jump target basic block in a first variable in a structure of the jump source basic block if it is determined that the jump target basic block crosses pages; The state judgment module is used to determine whether the jump source basic block is in a linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty during the execution of the target search code.

12. The system-level binary translator according to claim 10, characterized in that: The structure of each basic block includes a second variable, the initial value of the second variable is a first value, and the second judgment submodule is specifically used to: Reading the value of a second variable in the structure of the jump source basic block, and if the value of the second variable is a first value, determining that the jump source basic block is the first cross-page link; If the value of the second variable is a second value, it is determined that the jump source basic block is not the first cross-page link; The system-level binary translator also includes: The variable value updating module is used to set the value of the second variable in the structure of the jump source basic block to a second value after basic block linking is performed on the jump source basic block when it is determined that the jump source basic block is linked across pages for the first time.

13. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The depolymerization module is specifically used for: The first link instruction sequence in the jump source basic block is replaced with a placeholder instruction sequence; the first link instruction sequence is generated when the jump source basic block is linked across pages for the first time, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

14. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The link module is specifically used for: The second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is obtained, and the placeholder instruction sequence in the jump source basic block is replaced with a second link instruction sequence, where the second link instruction sequence is used to jump to the second starting address.

15. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The jump target basic block includes a first jump target basic block or a second jump target basic block; the first jump target basic block is a jump target of an unconditional jump instruction, or a jump target of a conditional jump instruction when a condition is met; The second jump target basic block is the jump target of the conditional jump instruction when the condition is not satisfied.

16. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The system-level binary translator also includes: An optimization execution module is used to execute a target instruction sequence when executing a direct jump instruction in the jump source basic block, if it is determined that the jump target basic block crosses pages; the target instruction sequence is the content inserted when translating the direct jump instruction and determining that the jump target basic block crosses pages; the target instruction sequence is used to jump through a link instruction sequence when it is detected that the direct jump instruction meets the optimization condition, otherwise jump through a non-optimized instruction sequence; the optimization condition includes: the virtual-to-real address mapping relationship of the jump target basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the non-optimized instruction sequence is used to jump to the target search code.

17. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the basic block linking method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the basic block linking method as described in any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the basic block linking method according to any one of claims 1 to 8 are implemented.

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