Resource scheduling method and device of data center, storage medium and electronic equipment

Abstract

The invention provides a resource scheduling method and device for a data center, and the method comprises the steps: carrying out the initial resource division after an application is started; periodically measuring the number of single-core cycle instructions of the application; calculating a real-time parallelizable proportion value of the application according to the current single-core cycle instruction number and the number of processor cores; according to the real-time parallelizable proportion value, calculating a period instruction number increment value after the application distributes the processor core; and preferentially distributing the processor core to the application with the maximum increment value of the cycle instruction number. Correspondingly, the invention further provides a storage medium and electronic equipment. Therefore, resource management and throughput improvement of the application in the data center can be realized.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a resource scheduling method, device, storage medium and electronic equipment for a data center. Background Art

[0002] Data centers are an important infrastructure for cloud computing, but they often have difficulty coping with the problems of low system resource utilization and difficulty in ensuring the service quality of hybrid applications. In order to fully utilize the rich resources of data centers (such as processor cores, last-level cache, memory bandwidth, etc.), data centers often run various types of applications at the same time. These applications share system resources. Resource sharing brings greater uncertainty to application performance, making it difficult to ensure the service quality of hybrid applications.

[0003] Data center loads vary, and can be roughly divided into two types: latency critical (LC) and best efforts (BE). LC applications (such as online service applications such as web queries and social networks) use tail latency as a performance indicator. BE applications (such as big data mining applications) use IPC (Instructions Per Cycle) as a performance indicator. In data centers, the tail latency of LC applications is related to user experience and has a higher priority, while BE applications are mostly batch processing applications with a relatively low priority. However, the load of LC applications usually changes over time, and in many cases existing resources cannot be fully utilized. In order to improve resource utilization, data centers usually adopt a mixed application deployment method to place multiple applications on a real machine or virtual machine. In order to solve the interference between applications, resource scheduling strategies are needed to allocate resources.

[0004] In summary, the existing technology obviously has inconveniences and defects in practical use, so it is necessary to improve it. Summary of the invention

[0005] In view of the above-mentioned defects, the object of the present invention is to provide a data center resource scheduling method, device, storage medium and electronic device, which can realize resource management and throughput improvement of applications in the data center.

[0006] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0007] In a first aspect, an embodiment of the present invention provides a resource scheduling method for a data center, the method comprising:

[0008] After starting the application, perform initial resource allocation;

[0009] periodically measuring the number of single-core cycle instructions of the application;

[0010] Calculating a real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores;

[0011] Calculating, according to the real-time parallelizable ratio value, an incremental value of the number of cycle instructions after the application is allocated to a processor core;

[0012] The processor core is preferentially allocated to the application having the largest increment value of cycle instruction number.

[0013] According to the resource scheduling method for a data center of the present invention, the step of periodically measuring the number of single-core cycle instructions of the application includes:

[0014] The single-core cycle instruction number is measured periodically, the number of available processor cores for the application is limited to 1 during operation, the number of executed instructions and the number of cycles within a predetermined time period are measured, and the ratio is calculated to obtain the single-core cycle instruction number.

[0015] According to the resource scheduling method for a data center of the present invention, the step of calculating the real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores includes:

[0016] Calculating the real-time parallelizable ratio value of the application according to the following formula (1);

[0017] Formula (1)

[0018] Among them, S A, NA Indicates that it has N A The ratio of the number of instructions per cycle when there are 2 processor cores to the number of instructions per cycle when there are 1 processor core, that is, S is the speedup ratio, and F is the parallelization ratio value.

[0019] According to the resource scheduling method for a data center of the present invention, the step of calculating the incremental value of the number of cycle instructions after the application is allocated a processor core according to the real-time parallelizable ratio value comprises:

[0020] The increment of the number of cycle instructions is calculated by the following formula (2). For application A, IPC A, n Indicates that application A is in N A The number of instructions per cycle that can be achieved by a processor core is A Under the premise of adding one processor core, the incremental value of the number of cycle instructions that can be obtained by adding one processor core to application A is:

[0021] Formula (2)

[0022] Formula (3)

[0023] Among them, S A, NA Indicates that application A is in N A The speedup ratio of the cores compared to the single core is F A is the parallelizable ratio of application A, which is determined by the multi-core speedup ratio and the corresponding number of cores.

[0024] According to the resource scheduling method for a data center of the present invention, the step of preferentially allocating the processor core to the application with the largest increment value of the number of cycle instructions comprises:

[0025] After calculating the incremental value of the number of cycle instructions of each application in the shared area, sorting the incremental value of the number of cycle instructions of each application;

[0026] Selecting an application with the smallest increment value of the number of cycle instructions among the applications whose number of cycle instructions is greater than a predetermined lower limit of the processor core allocation as a victim application;

[0027] Selecting the application with the largest increment value of the number of cycle instructions among the applications that have not reached the predetermined upper limit of processor core allocation as the beneficiary application;

[0028] If both the victim application and the beneficiary application are found, the processor core is preferentially allocated to the application with the largest cycle instruction count increment value, otherwise the cycle instruction count increment value of each application is recalculated.

[0029] According to the resource scheduling method for a data center of the present invention, the step of preferentially allocating the processor core to the application with the largest increment value of the number of cycle instructions comprises:

[0030] The scheduling round number increases by one;

[0031] Determine whether the current scheduling round number reaches a predetermined scheduling round number threshold;

[0032] If so, the application is terminated, otherwise the process returns to the step of periodically measuring the number of single-core cycle instructions of the application.

[0033] According to the resource scheduling method of the data center of the present invention, the application is a best-effort application;

[0034] After the application is started, the steps of performing initial resource division include:

[0035] After the applications are started, resources are evenly allocated to the applications.

[0036] In a second aspect, an embodiment of the present invention provides a resource scheduling device for a data center constructed based on any one of the methods described above, the device comprising:

[0037] The initialization module is used to perform initial resource allocation after starting the application;

[0038] A cycle measurement module, used for periodically measuring the number of single-core cycle instructions of the application;

[0039] A real-time calculation module, used to calculate a real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores;

[0040] A Delta calculation module, used for calculating the incremental value of the number of cycle instructions after the application is allocated to the processor core according to the real-time parallelizable ratio value;

[0041] The resource adjustment module is used to preferentially allocate the processor core to the application having the largest increment value of the number of cycle instructions.

[0042] In a third aspect, an embodiment of the present invention provides a storage medium for storing a computer program for executing any one of the data center resource scheduling methods.

[0043] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements any one of the data center resource scheduling methods when executing the computer program.

[0044] By this, the resource scheduling technology of the data center of the present invention includes: performing initial resource division after starting the application; periodically measuring the number of single-core cycle instructions of the application; calculating the real-time parallelizable ratio value of the application according to the current number of single-core cycle instructions and the number of processor cores; calculating the incremental value of the cycle instruction number after the application is assigned a processor core according to the real-time parallelizable ratio value; and preferentially allocating the processor core to the application with the largest incremental value of the cycle instruction number. By this, the present invention can allocate processor core resources based on the parallelizable ratio value, thereby realizing resource management and throughput improvement of applications in the data center. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a flowchart of a resource scheduling method for a data center provided in Embodiment 1 of the present invention;

[0046] Figure 2 It is a flow chart of a resource scheduling strategy for a data center provided in Embodiment 2 of the present invention;

[0047] Figure 3 is a flow chart of real-time measurement of the parallelization ratio provided by the third embodiment of the present invention;

[0048] Figure 4 It is a structural diagram of a resource scheduling device for a data center provided in Embodiment 1 of the present invention;

[0049] Figure 5 It is a structural diagram of a resource scheduling device for a data center provided in Embodiment 2 of the present invention;

[0050] Figure 6 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] It should be noted that references to "one embodiment", "embodiment", "example embodiment", etc. in this specification refer to the embodiment described, which may include specific features, structures or characteristics, but not every embodiment must include these specific features, structures or characteristics. In addition, such expressions do not refer to the same embodiment. Furthermore, when describing specific features, structures or characteristics in conjunction with an embodiment, whether or not there is an explicit description, it has been shown that it is within the knowledge of those skilled in the art to combine such features, structures or characteristics into other embodiments.

[0053] In addition, certain words are used in the specification and subsequent claims to refer to specific components or parts. Those with ordinary knowledge in the relevant field should understand that manufacturers can use different nouns or terms to refer to the same component or part. This specification and subsequent claims do not use differences in names as a way to distinguish components or parts, but use differences in the functions of components or parts as the criteria for distinction. "Including" and "including" mentioned throughout the specification and subsequent claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the word "connected" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connection through other devices.

[0054] The resource scheduling method for a data center provided by the embodiment of the present invention is described in detail below through specific embodiments and application scenarios in conjunction with the accompanying drawings.

[0055] Figure 1 1 is a flow chart of a resource scheduling method for a data center provided in Embodiment 1 of the present invention, wherein the method comprises the following steps:

[0056] Step S101: After starting the application, initial resource division is performed.

[0057] Preferably, the application is a best effort application.

[0058] Better, after starting the application, allocate resources evenly to each application. Then run the scheduling strategy for a specified number of rounds at a fixed time interval, and terminate the application after the number of rounds is reached.

[0059] Step S102, periodically measuring the number of single-core cycle instructions of the application.

[0060] The single core refers to a unit processor core.

[0061] Preferably, this step includes: periodically measuring the number of single-core cycle instructions, limiting the number of available processor cores for the application to 1 during runtime, measuring the number of executed instructions and the number of cycles within a predetermined time period, and calculating the ratio to obtain the number of single-core cycle instructions.

[0062] Step S103, calculating the real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores.

[0063] Preferably, the real-time parallelizable ratio value of the application is calculated according to the following formula (1).

[0064] Formula (1)

[0065] Among them, S A, NA Indicates that it has N A The ratio of the number of instructions per cycle when there are 2 processor cores to the number of instructions per cycle when there are 1 processor core, that is, S is the speedup ratio, and F is the parallelization ratio value.

[0066] Step S104 , calculating the incremental value (Delta value) of the number of cycle instructions after the application is allocated to the processor core according to the real-time parallelizable ratio value.

[0067] Preferably, the cycle instruction count increment is calculated by the following formula (2): for application A, IPC A, n Indicates that application A is in N A The number of instructions per cycle that can be achieved by a processor core is A Under the premise of adding 1 core, the incremental value of the number of cycle instructions that can be obtained by adding 1 processor core to application A is:

[0068] Formula (2)

[0069] Formula (3)

[0070] Among them, S A, NA Indicates that application A is in N A The speedup ratio of the cores compared to the single core is F A is the parallelizable ratio of application A, which is determined by the multi-core speedup ratio and the corresponding number of cores.

[0071] Step S105, the processor core is preferentially allocated to the application with the largest increment value of the number of cycle instructions.

[0072] The present invention is a resource scheduling strategy, which starts a BE application and performs initial resource division, periodically measures the number of instructions per cycle of a single core, and calculates the real-time parallelizable ratio value of the BE application based on the number of current processor cores, and then calculates the number of instructions per cycle that can be increased after allocating processor core resources. By preferentially allocating processor cores to applications with larger increments of instruction values ​​per cycle, the throughput of the data center system can be improved. The present invention proposes a strategy for allocating processor core resources based on the parallelizable ratio value for BE applications, further improving the throughput of BE applications.

[0073] Figure 2 This is a flow chart of a resource scheduling strategy for a data center provided by Embodiment 2 of the present invention, including the following steps:

[0074] Step S201 , after calculating the incremental value of the number of cycle instructions of each application in the shared area, the incremental value of the number of cycle instructions of each application is sorted.

[0075] Step S202: Select the application with the smallest increment value of cycle instruction number among the applications with a value greater than the predetermined processor core allocation lower limit as the victim application.

[0076] Step S203 , selecting the application with the largest increment value of the number of cycle instructions among the applications that have not reached the preset upper limit of processor core allocation as the beneficiary application.

[0077] Step S204: If both the victim application and the beneficiary application are found, then execute step S205; otherwise, return to step S206. Figure 1 Step S101 in the embodiment is to recalculate the incremental value of the number of cycle instructions of each application.

[0078] Step S205: The processor core is preferentially allocated to the application with the largest increment value of the number of cycle instructions.

[0079] Preferably, the allocation unit is set to one twentieth of the average processor core resource amount of the application.

[0080] Preferably, the step S205 may further include:

[0081] (1) The number of scheduling rounds increases by one.

[0082] (2) Determine whether the current scheduling round number reaches the predetermined scheduling round number threshold.

[0083] (3) If yes, terminate the application.

[0084] (4) Otherwise, return Figure 1Step S101 in the embodiment is to recalculate the incremental value of the number of cycle instructions of each application.

[0085] Figure 3 This is a flow chart of real-time measurement of parallelization ratio provided by the third embodiment of the present invention. The scheduling strategy proposed by the present invention periodically performs resource adjustment in the data center. The adjustment interval is called the scheduling interval. During each adjustment, the incremental number of instructions per cycle that can be brought about by increasing the number of single cores is calculated using formula (1) and formula (2). A method for measuring the real-time parallelization ratio value.

[0086] A chart showing the real-time measurement of the parallelizable proportional workflow. The vertical axis Cores represents the number of cores, and the horizontal axis Time represents the time.

[0087] 1. Run stage: In the "Run" period in the chart, four cores are in operation, indicating that this is the parallel operation stage, and multiple cores are processing tasks simultaneously.

[0088] 2. Measure IPC stage (Measure IPC): Then enter the "Measure IPC (instructions per cycle)" stage, at this time only one core is working, which is used to measure IPC, which is a measure of system performance.

[0089] 3. Time Division (T r and T m ): "T r " represents the time spent in the operation phase, "T m " represents the time spent measuring the IPC stage. Through this phased workflow, multi-core parallel processing tasks are first used, and then the performance indicators are measured with a single core to obtain data related to the parallelizable ratio in real time.

[0090] Since measuring the real-time parallelization ratio of an application at runtime will introduce additional time overhead and interfere with the application to be tested, it needs to be done at regular intervals, that is, let the application run normally for a period of time T r , and then enter the time-consuming T m The measurement phase. If T m If the value is too large, the measurement will take time and may affect the normal execution of the application. If it is too small, the obtained F value will be unstable. m The number of instructions per cycle of a single core is measured during the period, and the speedup ratio is obtained based on the measured value of the number of instructions per cycle during the running phase. Combined with the current number of cores, the parallelization ratio value is calculated by the formula. Due to the long measurement interval, the number of instructions per cycle of multiple cores measured during the running phase is more stable. When measuring the number of instructions per cycle of a single core, there is no core change involved. The observed number of instructions per cycle is stable, so the calculated F value is also stable.

[0091] The pseudo code of the proposed scheduling strategy algorithm is shown in Table 1. In line 3, the CPU time slice adjustment unit allocationUnit of the strategy is defined. In lines 5-7 of the algorithm, ARQ-F first evenly distributes the CPU time slices it has to each application. Then, in lines 8-19 of the algorithm, the CPU time slice resources are continuously redistributed at a time interval of scheduleInterval. In each time interval, the number of instructions per cycle of the BE application is first periodically measured, and then in line 12, the maximum number of allocated cores maxCores is set for each application based on the number of threads running in real time for each application. Then, in line 13, the F value of each application is calculated, and in line 14, the incremental value Delta of the number of instructions per cycle brought about by the addition of allocationUnit CPU time slices to each application under the current core available time slice is calculated. In line 16 of the algorithm, the applications are sorted from small to large according to the Delta value. Finally, in line 17, the adjustResource function is called to adjust the CPU time slices of each application.

[0092] The definition of adjustResource function is shown in lines 22-32. First, call findVictimApp function to select the victim in line 24, and call findBeneficiaryApp function to select the resource victim in line 25. Perform CPU time slice adjustment operation in lines 26-31. If the application array subscript victimApp returned by findVictimApp function and the application array subscript beneficiaryApp returned by findBeneficiaryApp function are not equal to -1, and victimApp< beneficiaryApp, then increase or decrease the CPU time slice owned by the resource victim and beneficiary in allocationUnit.

[0093] The definition of the findVictimApp function is shown in lines 34-43. The input is the application array apps sorted in ascending order by Delta value. This function selects applications with remaining resources greater than allocationUnit as victim applications in descending order of Delta value and returns the array index. If not found, it returns -1. The definition of the findBeneficiaryApp function is shown in lines 45-55. The input is the application array apps sorted in ascending order by Delta value. This function selects beneficiary applications in descending order of Delta value. When the number of cores allocated to the application app.allocatedCores is less than the maximum number of cores that can be allocated to the application app.maxCores, the array index of the corresponding application is returned. If no application meets the condition, it returns -1.

[0094] The advantage of the parallelizable ratio value is that when multiple multithreaded applications compete for cores, processor cores are allocated to applications with higher scaling efficiency, that is, applications with higher parallelizable ratio values. It should be noted that the parallelizable ratio value loses its meaning when the number of processor cores is less than 1, so at least one core needs to be reserved for the application during scheduling.

[0095] Theoretically, the parallelizable ratio value can be used to predict the performance under any number of processor cores, but in actual applications, the number of application threads is fixed. When the number of processor cores exceeds the number of threads, increasing the number of cores will not bring additional performance benefits. The maxCores variable is added in the pseudo code to limit the maximum number of processor cores allocated to the application. This value can be set to the number of all child threads of the current process returned by the ps command, as shown in Table 1.

[0096]

[0097] Table 1 Scheduling strategy algorithm sequence table

[0098] The processor core allocation of BE applications uses the cgroup function in the Linux kernel to fine-grainedly control the CPU time slices available to each application. The Completely Fair Scheduler (CFS) is used in the operating system for inter-process scheduling to evenly distribute CPU time slices among processes. By using the cgroup function, cpu.cfs_period_us and cpu.cfs_quota_us can be used for fine-grained CPU time slice allocation. The former represents the period of reallocation of cgroup access to CPU resources in microseconds, and the latter represents the CPU time available to tasks in the cgroup within the period in microseconds. The actual number of equivalent CPU cores owned by the application is equal to the latter divided by the former. Note that this value is not necessarily an integer.

[0099] The present invention is based on a resource scheduling strategy for improving the throughput of a data center based on a parallelizable ratio value, proposes a method for real-time measurement of an application parallelizable ratio value, and develops a resource scheduling strategy based on the measured parallelizable ratio value to maximize the throughput of the data center system.

[0100] Preferably, the throughput optimization strategy of the data center based on the parallelizable ratio value of the present invention calculates the system throughput increment after allocating the processor cores according to the real-time parallelizable ratio values ​​of different BE applications, and allocates the processor core resources of the application with the smallest increment to the application with the largest increment to maximize the system throughput. The parallelizable ratio value is the proportion of the parallelizable part in the application.

[0101] Preferably, the feature of the real-time parallelizable ratio value is the ratio of the parallelizable parts in the current application. The system throughput increment is equal to the sum of the throughput increments of each application.

[0102] Preferably, the throughput increment is equal to the difference between the expected throughput of the single core and the current throughput.

[0103] Preferably, the real-time parallelizable ratio measurement method measures the current number of instructions per cycle during runtime and compares it with the regularly measured number of instructions per cycle of a single core to obtain the acceleration ratio of the program under a specific number of processor cores, and then calculates the real-time parallelizable ratio value according to the parallelizable ratio value calculation formula.

[0104] It should be noted that the resource scheduling method for a data center provided in an embodiment of the present invention can be executed by an electronic device, a device, or a control module in the device for executing the method. In the embodiment of the present invention, the resource scheduling device for a data center provided in an embodiment of the present invention is described by taking the device executing the method as an example.

[0105] Figure 4 1 is a schematic diagram of the structure of a resource scheduling device for a data center provided in Embodiment 1 of the present invention. The device 100 includes an initialization module 10, a cycle measurement module 20, a real-time calculation module 30, a Delta calculation module 40, and a resource adjustment module 50, wherein:

[0106] The initialization module 10 is used to perform initial resource allocation after starting the application. Preferably, the application is a best-effort application. Preferably, after starting the application, the initialization module 10 allocates resources evenly to each application.

[0107] The cycle measurement module 20 is used to periodically measure the number of single-core cycle instructions of an application.

[0108] The real-time calculation module 30 is used to calculate the real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores.

[0109] The Delta calculation module 40 is used to calculate the incremental value of the number of cycle instructions after the application is allocated to the processor core according to the real-time parallelizable ratio value.

[0110] The resource adjustment module 50 is used to preferentially allocate processor cores to applications with the largest increment value of cycle instruction count.

[0111] Figure 5 1 is a schematic diagram of the structure of a resource scheduling device for a data center provided in Embodiment 2 of the present invention. The device 100 includes an initialization module 10, a cycle measurement module 20, a real-time calculation module 30, a Delta calculation module 40, and a resource adjustment module 50, wherein:

[0112] The initialization module 10 is used to perform initial resource division after starting the application, measure the number of executed instructions and the number of cycles within a predetermined time period, and calculate the ratio to obtain the number of single-core cycle instructions.

[0113] The cycle measurement module 20 is used to periodically measure the number of single-core cycle instructions of an application.

[0114] Preferably, the cycle measurement module 20 is used to periodically measure the number of single-core cycle instructions, and limit the number of available processor cores for the application to 1 during runtime.

[0115] Preferably, the period measurement module 20 is used to calculate the real-time parallelizable ratio value of the application according to the following formula (1).

[0116] Formula (1)

[0117] Among them, S A, NA Indicates that it has N A The ratio of the number of instructions per cycle when there are 2 processor cores to the number of instructions per cycle when there are 1 processor core, S is the speedup ratio, and F is the parallelization ratio value.

[0118] The real-time calculation module 30 is used to calculate the real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores.

[0119] Preferably, the real-time calculation module 30 is used to calculate the incremental value of the number of cycle instructions by the following formula (2): for application A, IPC A, n Indicates that application A is in N A The number of instructions per cycle that can be achieved by a processor core is A Under the premise of adding 1 core, the incremental value of the number of cycle instructions that can be obtained by adding 1 processor core to application A is:

[0120] Formula (2)

[0121] Formula (3)

[0122] Among them, S A, NA Indicates that application A is in N A The speedup ratio of the cores compared to the single core is F A is the parallelizable ratio of application A, which is determined by the multi-core speedup ratio and the corresponding number of cores.

[0123] The Delta calculation module 40 is used to calculate the incremental value of the number of cycle instructions after the application is allocated to the processor core according to the real-time parallelizable ratio value.

[0124] The resource adjustment module 50 is used to preferentially allocate the processor core to the application with the largest increment value of the number of cycle instructions. The resource adjustment module 50 further includes:

[0125] The sorting submodule 51 is used to sort the incremental values ​​of the number of cycle instructions of each application in the shared area after calculating the incremental values ​​of the number of cycle instructions of each application.

[0126] The selection submodule 52 is used to select the application with the smallest cycle instruction number increment value among the applications that are greater than the predetermined processor core allocation lower limit as the victim application, and select the application with the largest cycle instruction number increment value among the applications that do not reach the predetermined processor core allocation upper limit as the beneficiary application.

[0127] The allocation submodule 53 is used to execute the step of allocating the processor core to the application with the largest cycle instruction number increment value preferentially if both the victim application and the beneficiary application are found, otherwise recalculate the cycle instruction number increment value of each application.

[0128] The resource adjustment module 50 further includes:

[0129] The counting submodule 54 is used to increase the scheduling round number by one after the allocating submodule 53 preferentially allocates the processor core to the application with the largest increment value of the number of cycle instructions.

[0130] The judging submodule 55 is used to judge whether the current scheduling round number reaches a predetermined scheduling round number threshold, and if so, terminate the application; otherwise, return to the cycle measurement module 20 to periodically measure the single-core cycle instruction number of the application again.

[0131] The resource scheduling device of the data center provided by the embodiment of the present invention can realize Figure 1~2 To avoid repetition, the various processes implemented in the embodiment of the resource scheduling method for the data center are not described again here.

[0132] The resource scheduling device of the data center provided by the embodiment of the present invention includes: performing initial resource division after starting the application; periodically measuring the number of single-core cycle instructions of the application; calculating the real-time parallelizable ratio value of the application according to the current number of single-core cycle instructions and the number of processor cores; calculating the incremental value of the cycle instruction number after the application is allocated the processor core according to the real-time parallelizable ratio value; and preferentially allocating the processor core to the application with the largest incremental value of the cycle instruction number. In this way, the present invention can allocate processor core resources based on the parallelizable ratio value, thereby realizing resource management and throughput improvement of applications in the data center.

[0133] The present invention also provides a storage medium for storing Figure 1~Figure 3A computer program of any of the resource scheduling methods of the data center. For example, a computer program instruction, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer, and can achieve the same technical effect. To avoid repetition, it will not be repeated here. The program instructions for calling the method of the present invention may be stored in a fixed or removable storage medium, and / or transmitted through a data stream in a broadcast or other signal-bearing medium and / or stored in a storage medium of a computer device that runs according to the program instructions.

[0134] According to one embodiment of the present invention, the present invention also provides a Figure 6 The electronic device 400 shown in the figure may optionally include a storage medium 200 for storing a computer program and a processor 300 for executing the computer program, wherein when the computer program is executed by the processor 300, any of the above-mentioned data center resource scheduling methods is implemented, triggering the electronic device 400 to execute the methods and / or technical solutions based on the aforementioned multiple embodiments, and the same technical effects can be achieved. To avoid repetition, it is not repeated here. It should be noted that the electronic devices in the embodiments of the present invention include mobile electronic devices and non-mobile electronic devices. Exemplarily, the mobile electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, a super mobile personal computer, a netbook or a personal digital assistant, etc., and the non-mobile electronic device may be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiments of the present invention.

[0135] It should be noted that the present invention can be implemented in software and / or a combination of software and hardware, for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer or any other similar hardware device. In one embodiment, the software program of the present invention can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present invention (including related data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and the like. In addition, some steps or functions of the present invention can be implemented using hardware, for example, as a circuit that cooperates with a processor to perform various steps or functions.

[0136] The present invention can be implemented on a computer as a computer-implemented method, or implemented in dedicated hardware, or implemented in a combination of the two. The executable code or part thereof for the method according to the present invention can be stored on a computer program product. Examples of computer program products include memory devices, optical storage devices, integrated circuits, servers, online software, etc. Optionally, the computer program product includes a non-temporary program code component stored on a computer-readable medium so as to perform the method according to the present invention when the program product is executed on a computer.

[0137] In an alternative embodiment, the computer program comprises computer program code means adapted to perform all the steps of the method according to the invention when the computer program is run on a computer. Optionally, the computer program is embodied on a computer readable medium.

[0138] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present invention is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0139] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A data center resource scheduling method, characterized in that: include: After starting the application, perform initial resource allocation; periodically measuring the number of single-core cycle instructions of the application; Calculating a real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores; Calculating, according to the real-time parallelizable ratio value, an incremental value of the number of cycle instructions after the application is allocated to a processor core; The processor core is preferentially allocated to the application having the largest increment value of cycle instruction number.

2. The resource scheduling method of a data center according to claim 1, characterized in that: The step of periodically measuring the number of single-core cycle instructions of the application comprises: The single-core cycle instruction number is measured periodically, the number of available processor cores for the application is limited to 1 during operation, the number of executed instructions and the number of cycles within a predetermined time period are measured, and the ratio is calculated to obtain the single-core cycle instruction number.

3. The resource scheduling method of a data center according to claim 1, characterized in that: The step of calculating the real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores includes: Calculating the real-time parallelizable ratio value of the application according to the following formula (1); Formula (1) Among them, S A, NA Indicates that you have N A The ratio of the number of instructions per cycle when there are 2 processor cores to the number of instructions per cycle when there are 1 processor core, that is, S is the speedup ratio, and F is the parallelization ratio value.

4. The resource scheduling method of a data center according to claim 3, characterized in that: The step of calculating the incremental value of the number of cycle instructions after the application is allocated to the processor core according to the real-time parallelizable ratio value comprises: The increment of the number of cycle instructions is calculated by the following formula (2). For application A, IPC A, n Indicates that application A is in N A The number of instructions per cycle that can be achieved by a processor core is A Under the premise of adding one processor core, the incremental value of the number of cycle instructions that can be obtained by adding one processor core to application A is: Formula (2) Formula (3) Among them, S A, NA Indicates that application A is in N A The speedup ratio of the cores compared to the single core is F A is the parallelizable ratio of application A, which is determined by the multi-core speedup ratio and the corresponding number of cores.

5. The data center resource scheduling method according to claim 1, characterized in that: The step of preferentially allocating the processor core to the application with the largest increment value of the number of cycle instructions comprises: After calculating the incremental value of the number of cycle instructions of each application in the shared area, sorting the incremental value of the number of cycle instructions of each application; Selecting an application with the smallest increment value of the number of cycle instructions among the applications whose number of cycle instructions is greater than a predetermined processor core allocation lower limit as a victim application; Selecting an application with the largest increment value of the number of cycle instructions among the applications that have not reached the predetermined upper limit of processor core allocation as a beneficiary application; If both the victim application and the beneficiary application are found, the processor core is preferentially allocated to the application with the largest cycle instruction count increment value, otherwise the cycle instruction count increment value of each application is recalculated.

6. The resource scheduling method of a data center according to claim 5, characterized in that: The step of preferentially allocating the processor core to the application with the largest increment value of the number of cycle instructions comprises: The scheduling round number increases by one; Determine whether the current scheduling round number reaches a predetermined scheduling round number threshold; If so, the application is terminated, otherwise the process returns to the step of periodically measuring the number of single-core cycle instructions of the application.

7. The data center resource scheduling method according to claim 1, characterized in that: The application is a best-effort application; After the application is started, the steps of performing initial resource division include: After the applications are started, resources are evenly allocated to the applications.

8. A data center resource scheduling device constructed based on the method described in any one of claims 1 to 7, characterized in that: The device comprises: The initialization module is used to perform initial resource allocation after starting the application; A cycle measurement module, used for periodically measuring the number of single-core cycle instructions of the application; A real-time calculation module, used to calculate a real-time parallelizable ratio value of the application according to the current single-core cycle instruction number and the number of processor cores; A Delta calculation module, used for calculating the incremental value of the number of cycle instructions after the application is allocated to the processor core according to the real-time parallelizable ratio value; The resource adjustment module is used to preferentially allocate the processor core to the application having the largest increment value of the number of cycle instructions.

9. A storage medium, characterized in that: Used to store a computer program for executing the resource scheduling method for a data center as described in any one of claims 1 to 7.

10. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that: When the processor executes the computer program, the resource scheduling method for a data center according to any one of claims 1 to 7 is implemented.

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