Computer system and data access method thereof

Abstract

The invention discloses a computer system and a data access method of the computer system, and belongs to the technical field of storage, and the computer system comprises an external request source which sends a read request and a write-back request; the write-back cache module is used for receiving a read request and a write-back request sent by the external request source; the Cache module is used for receiving a pre-reading request and the write-back request and writing data read by the pre-reading request into the write-back cache module; and the main memory is used for receiving the data updated by the Cache module and updating the data. According to the computer system, it is guaranteed that the data blocks in the write-back cache are always newest, the write-back waiting time during actual access of the Cache can be shortened, necessary data updating and synchronous operation are carried out in advance, and the data processing efficiency of the whole system is improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a computer system and a data access method of the computer system. Background Art

[0002] In modern computer systems, cache technology is used to increase data access speed and reduce overall system latency. The basic working principle of cache is to temporarily store frequently used data in a fast, small-capacity storage area so that the data can be retrieved faster during subsequent access. However, when the same data is accessed multiple times before the write-back is completed, in order to ensure data consistency, further access to the data must be blocked until the write-back is completed. Although this method ensures data consistency, it greatly affects the access efficiency of the external request source to the cache, resulting in a decrease in the overall system performance. Therefore, there is an urgent need for a computer system and a data access method for the computer system that can ensure that the data in the cache is consistent with the data in the main memory and significantly improve the cache access efficiency to meet the growing needs of modern computer systems. Summary of the invention

[0003] The purpose of this application is to overcome the defects of the prior art and provide a computer system and a data access method for the computer system.

[0004] In a first aspect, the present application provides a computer system, comprising: External request source, issues read request and write back request; A write-back cache module receives the read request and the write-back request sent by the external request source, and temporarily stores the write-back request; A cache module receives a pre-read request and the write-back request, and writes the data read by the pre-read request into the write-back cache module; The main memory receives the data updated by the cache module and performs data updates.

[0005] Optionally, the write-back cache module includes: A write-back cache unit stores data read from the cache module by a pre-read request and data written back by a write-back request; The write-back cache control logic unit coordinates the interaction between the write-back cache unit, the cache module, and the external request source.

[0006] Optionally, the Cache module includes: A cache unit, storing data read from the main memory and data updated in the write-back request; The cache control logic unit coordinates the interaction between the cache unit, the write-back cache module, and the external request source.

[0007] Optionally, the write-back cache control logic unit includes: A pre-reading request interface, receiving and transmitting the pre-reading request sent by the external request source; A write-back request interface, receiving and transmitting the write-back request sent by the external request source; A pre-reading request cache subunit, receiving and storing the pre-reading request transmitted by the pre-reading request interface; A write-back cache subunit, receiving and storing the write-back request transmitted by the write-back request interface; The arbitration subunit receives the pre-read request stored in the pre-read request cache subunit and the write-back request stored in the write-back cache subunit, performs arbitration operation, and outputs read enable signals to the pre-read request cache subunit and the write-back cache subunit.

[0008] Optionally, the cache control logic unit includes: A read request interface, receiving and transmitting a read request sent by the external request source; Read Cache ACK write interface, receiving data sent by the Cache control logic unit, and inputting the data into the write-back cache unit; A read Cache REQ write interface receives the read request transmitted by the pre-read request interface and inputs the read request into the write-back cache unit; A write-back interface, receiving the write-back request transmitted by the write-back request interface, and inputting the write-back request into the write-back cache unit; A read data interface receives the read request transmitted by the read request interface, reads data from the write-back cache unit, and returns the data to the external request source.

[0009] In a second aspect, the present application further provides a data access method for a computer system, the data access method for the computer system being executed based on the computer system, and the data access method for the computer system comprising the following steps: Writing frequently used data from the Cache module to the write-back cache module through a pre-read operation; The external request source sends a request; When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data to read in the write-back cache unit, and if so, returns the data read from the write-back cache unit; If not, reading data from the Cache module through the pre-read operation, and writing the data read from the Cache module into the write-back cache module; When the request is a write-back request, the write-back request is input into the Cache module, a write-back operation is performed on the Cache module, and the write-back request is input into the write-back cache module, and a write-back operation is performed on the write-back cache module.

[0010] Optionally, writing frequently used data from the Cache module to the write-back cache module through a pre-read operation includes: storing the pre-read request in the pre-read request cache subunit through the pre-read request interface; The arbitration subunit receives the pre-read request from the pre-read request cache subunit, performs arbitration operation, and outputs a read enable signal to the pre-read request cache subunit; Inputting the pre-read request to the Cache module to perform a pre-read operation based on the read enable signal of the pre-read request cache subunit; When the cache module completes processing the pre-read operation, it outputs a confirmation signal indicating completion of the pre-read operation, and writes the pre-read data into the write-back cache module.

[0011] Optionally, if not, reading data from the Cache module through the pre-read operation, and writing the data read from the Cache module into the write-back cache module, including: When the request is a read request, the write-back cache control logic unit receives the read request and checks whether the write-back cache unit has data to read, and if not, performs a pre-read operation on the cache module; storing the pre-read request in the pre-read request cache subunit through the pre-read request interface; The arbitration subunit receives data from the pre-read request cache subunit, performs arbitration operation, and outputs a read enable signal to the pre-read request cache subunit; Inputting the pre-read request in the pre-read request cache sub-unit into the Cache module for pre-reading operation based on the read enable signal to the pre-read request cache sub-unit; When the cache module completes the pre-read operation, it outputs the confirmation signal indicating that the pre-read operation is completed, and writes the pre-read data into the write-back cache module; The state of the write-back cache subunit changes to data being readable, the read request is input into the write-back cache module from the entry of the pre-read request cache subunit, a read operation is performed on the write-back cache module, and the read data is returned.

[0012] Optionally, when the request is a write-back request, inputting the write-back request into the Cache module, performing a write-back operation on the Cache module, and inputting the write-back request into the write-back cache module, performing a write-back operation on the write-back cache module, including: When the request is a write-back request, storing the write-back request in the write-back cache subunit through the write-back request interface; The arbitration subunit receives the write-back request from the write-back cache subunit, performs arbitration operation, and outputs a read enable signal to the write-back cache subunit; Based on the read enable signal of the write-back cache subunit, inputting the write-back request in the write-back cache subunit into the cache module for writing back, and updating the data in the main memory; The write-back request is input into the write-back cache unit through the write-back interface, and the write-back is performed on the write-back cache unit.

[0013] Optionally, the arbitration operation includes: setting absolute priority of the write-back request.

[0014] The present application provides a computer system and a data access method for the computer system. Through write-back request caching and a reasonable arbitration mechanism, it is possible to ensure absolute priority processing of write-back requests, thereby avoiding subsequent access blocking caused by failure to write back data in a timely manner; through pre-reading operations, relevant data is pre-fetched into a write-back cache module for temporary storage, thereby reducing the write-back waiting time during access; reading and writing operations are performed on the Cache module and synchronous reading and writing operations are performed on the write-back cache module at the same time, thereby ensuring timely updating and consistency of data, avoiding unnecessary data update operations, improving the utilization rate of system resources, and ensuring data consistency.

[0015] In order to make the above features and advantages of the invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of the structure of a computer system provided in one embodiment of the present application.

[0018] Figure 2A schematic diagram of the internal structure of a write-back cache control logic unit and a cache control logic unit in a computer system provided in one embodiment of the present application.

[0019] Figure 3 The present invention is a flowchart of a data access method of a computer system provided in one embodiment of the present application.

[0020] Figure 4 This is a flowchart of step S10 in the data access method of a computer system provided in one embodiment of the present application.

[0021] Figure 5 This is a flowchart of step S40 in the data access method of a computer system provided in one embodiment of the present application.

[0022] Figure 6 This is a flowchart of step S50 in the data access method of a computer system provided in one embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose and technical solution of the embodiment of the present application clearer, the technical solution of the embodiment of the present application will be clearly and completely described in conjunction with the drawings of the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, not all of the embodiments. Based on the described embodiment of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] like Figure 1As shown, the present application provides a computer system, including: an external request source 10, a write-back cache module 20, a cache module 30, and a main memory 40, wherein the external request source 10 issues a read request and a write-back request; the write-back cache module 20 receives the read request and the write-back request issued by the external request source 10; the cache module 30 receives the pre-read request and the write-back request, and writes the data read by the pre-read request into the write-back cache module 20; the main memory 40 is used to store all data, and receives the data updated by the cache module 30, and performs data update and replacement; the write-back cache module 20 includes: a write-back cache unit 21 and a write-back cache control logic unit 22. 2. The write-back cache unit 21 is used to store the data read from the cache module 30 by the pre-read request and the data written back by the write-back request; the write-back cache control logic unit 22 is used to coordinate the interaction between the write-back cache unit 21 and the cache module 30 and the external request source 10; the cache module 30 includes a cache cache unit 31 and a cache control logic unit 32, the cache cache unit 31 is used to store the data read from the main memory 40 and the data updated in the write-back request; the cache control logic unit 32 is used to coordinate the interaction between the cache cache unit 31 and the write-back cache module 20 and the external request source 10.

[0025] Specifically, the cache control logic unit 32 receives a pre-read request from an external request source and passes it to the cache unit 31. The cache unit 31 performs a pre-read operation. When the pre-read operation is completed, the cache control logic unit 32 sends a confirmation signal cache ack indicating the completion of the pre-read operation to the write-back cache module 20. The write-back cache control logic unit 22 receives the confirmation signal cache ack and writes the data read from the cache unit 31 into the write-back cache unit 21 for temporary storage. Repeat the above pre-read operation to write frequently used data from the cache unit 31 into the write-back cache unit 21 for temporary storage. By writing frequently used data from the cache unit 31 into the write-back cache unit 21 for temporary storage, subsequent read requests can directly obtain these data from the write-back cache unit 21 when they are needed, avoiding the delay caused by waiting for the write-back operation to be completed when reading from the cache unit 31, thereby reducing the access time of subsequent read requests.

[0026] Furthermore, when the external request source 10 issues a read request, the write-back cache control logic unit 22 receives the read request and checks whether there is readable data in the write-back cache unit 21. If so, a read operation is performed on the write-back cache unit 21, and the data read from the write-back cache unit 21 is returned to the external request source 10.

[0027] Further, when the external request source 10 issues a read request, the write-back cache control logic unit 22 receives the read request and checks whether there is data to be read in the write-back cache unit 21. If not, a pre-read operation is performed on the cache module 30. The cache control logic unit 32 receives the pre-read request and performs a pre-read operation on the cache unit 31 to read the data stored in the cache unit 31. When the pre-read operation is completed, the cache control logic unit 32 sends a confirmation signal cache ack indicating that the pre-read operation is completed to the write-back cache module 20. The write-back cache control logic unit 22 receives the confirmation signal cacheack and writes the data read from the cache unit 31 into the write-back cache unit 21. At this time, the state of the write-back cache unit 21 becomes that there is data to be read, that is, the bitmap of the write-back cache unit 21 becomes high. The write-back cache control logic unit 22 receives the read request issued by the external request source 10, performs a read operation on the write-back cache unit 21, reads data from the write-back cache unit 21, and returns it to the external request source 10.

[0028] Furthermore, when the external request source 10 issues a write-back request, the cache control logic unit 32 receives the write-back request and performs a write-back operation on the cache unit 31, writes the write-back data into the cache unit 31 to replace the originally stored data, and updates the data in the main memory 40. At the same time, the write-back cache control logic unit 22 also receives the write-back request and performs a write-back operation on the write-back cache unit 21 to achieve synchronous data update.

[0029] It should be noted that the pre-read request and the read request are the same request. Before the system is turned on, if there is no data in the write-back cache module 20, it is necessary to pre-read the data in the cache module 30 and write it into the write-back cache module 20. The read request at this time is the pre-read request. When there is data in the write-back cache module 20, the subsequent read request can directly hit the write-back cache module 20 and read the data directly. If it does not hit, it hits the cache module 30 through the pre-read request, reads the data, and writes the read data into the write-back cache module 20 for temporary storage.

[0030] As an example, see Figure 2, the cache control logic unit 32 includes: a pre-read request interface 324 receives and transmits a pre-read request from an external request source 10; a write-back request interface 325 receives and transmits a write-back request from an external request source 10; a pre-read request cache subunit 321 receives and stores the pre-read request transmitted by the pre-read request interface 324; a write-back cache subunit 322 receives and stores the write-back request transmitted by the write-back request interface 325; an arbitration subunit 323 receives and stores the pre-read request cache subunit 321 and the write-back cache subunit 322 data, and performs arbitration operation, the arbitration subunit 323 write-back request has absolute priority, the request sources of the arbitration subunit 323 are respectively the non-empty signal of the pre-read request cache subunit 321 and the non-empty signal of the write-back cache subunit 322, the arbitration subunit 323 generates signals as the read enable signal of the pre-read request cache subunit 321 and the read enable signal of the write-back cache subunit 322, and passes the pre-read request of the pre-read request cache subunit 321 and the write-back request of the write-back cache subunit 322 to the Cache cache unit 31.

[0031] As an example, the write-back cache control logic unit 22 includes: a read request interface 221 that receives a read request issued by an external request source 10 and transmits it; a read cache ACK write interface 222 that receives a confirmation signal cache ack issued by the cache control logic unit 32, and inputs the data pre-read from the cache cache unit 31 into the write-back cache unit 21; a read cache REQ write interface 223 that receives a read request transmitted by a pre-read request interface 324, and inputs the read request into the write-back cache unit 21; a write-back interface 224 that receives a write-back request transmitted by a write-back request interface 325, and inputs the write-back request into the write-back cache unit 21; a read data interface 225 that receives a read request transmitted by a read request interface 221, reads data from the write-back cache unit 21, and returns it to the external request source 10.

[0032] Specifically, the pre-read request interface 324 receives a pre-read request issued by an external request source, inputs the pre-read request into the pre-read request cache sub-unit 321 for temporary storage, and issues a pre-read request non-empty signal. The arbitration sub-unit 323 receives the non-empty signal and receives the pre-read request stored in the pre-read request cache sub-unit 321, performs an arbitration operation, sets the write-back request to have absolute priority during arbitration, arranges requests of the same type in chronological order, and outputs a read enable signal for the pre-read request cache sub-unit 321. The Cache cache unit 31 performs a pre-read operation. When the pre-read operation is completed, the Cache control logic unit 32 sends a confirmation signal cache ack indicating the completion of the pre-read operation to the write-back cache module 20. The read Cache ACK write interface 222 of the write-back cache module 20 receives the confirmation signal cache ack, and writes the data pre-read from the Cache cache unit 31 into the write-back cache unit 21 for temporary storage.

[0033] Furthermore, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether there is data to be read in the write-back cache unit 21. If so, the read request interface 221 transmits the read request to the read data interface 225. The read data interface 225 receives the read request and reads data from the write-back cache unit 21 and returns it to the external request source 10.

[0034] Further, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether there is data to be read in the write-back cache unit 21. If not, a pre-read operation is performed on the cache module 30. The pre-read request interface 324 receives the pre-read request and inputs the pre-read request into the pre-read request cache subunit 321. The pre-read request cache subunit 321 receives the pre-read request and outputs a pre-read request non-empty signal. The arbitration subunit 323 receives the non-empty signal and performs an arbitration operation. During arbitration, the write-back request is set to have absolute priority. Requests of the same type are arranged in chronological order, and a read enable signal for the pre-read request cache subunit 321 is output. The cache cache unit 31 performs a pre-read operation. When the pre-read operation is completed, the cache control logic unit 32 sends a confirmation signal cache ack indicating the completion of the pre-read operation to the write-back cache module 20. The read cache ACK write interface 222 of the write-back cache module 20 receives the confirmation signal cache ack and writes the data pre-read from the cache cache unit 31 into the write-back cache unit 21. At this time, the write-back cache unit 21 becomes readable, that is, the bitmap of the write-back cache unit 21 becomes high, the read request interface 221 transmits the read request to the read data interface 225, the read data interface 225 receives the read request and reads data from the write-back cache unit 21, and returns it to the external request source 10.

[0035] Further, when the external request source 10 issues a write-back request, the write-back request interface 325 receives the write-back request and inputs the write-back request into the write-back cache subunit 322. The write-back cache subunit 322 receives the write-back request and outputs a write-back request non-empty signal. The arbitration subunit 323 receives the non-empty signal and performs arbitration. During arbitration, the write-back request is given absolute priority. Requests of the same type are arranged in chronological order. The read enable signal for the write-back cache subunit 322 is output. The cache cache unit 31 writes the data in the write-back cache subunit 322 to replace the originally stored data and update the data in the main memory 40. At the same time, the write-back interface 224 also receives the write-back request and performs a write-back operation on the write-back cache unit 21 to achieve data update and replacement. Through the pre-read operation, the data that may be needed is pre-fetched into the write-back cache module 20 in advance, so that the data can be obtained faster during subsequent data access, reducing the delay caused by waiting for the data to be loaded from the main memory to the cache module 30, and improving the overall speed of data access; for read requests, when the write-back cache module 20 has data to read, the data can be read directly from the write-back cache module 20 and returned to the external request source 10, avoiding unnecessary access to the cache module 30 and further shortening the data acquisition time; even if the write-back cache module 20 has no data to read, the subsequent pre-read operation can quickly supplement the data to maintain an efficient reading process. In scenarios where multiple tasks are concurrent and data is frequently read and written, this mechanism can effectively reduce the waiting time between tasks and improve the overall throughput of the system; setting absolute priority for write-back requests in the arbitration sub-unit 323 ensures that the write-back operation is completed before any read operation, avoiding data inconsistency problems caused by incomplete write-back; the cache module 30 sends a confirmation signal cache ack indicating the completion of the pre-read operation to the write-back cache module 20, and the read cache ACK write interface 222 receives and writes the relevant data into the write-back cache unit 21, which enables the data in the write-back cache unit 21 to be updated in a timely manner and synchronized with the data in the cache unit 31, further ensuring the consistency of data between different storage levels.

[0036] As an example, the pre-read request may include: a pre-read request enable signal, a pre-read identifier KEY, a pre-read tag TAG, and the like.

[0037] As an example, the read request may include: a read request enable signal, a read identifier KEY, a read tag TAG, and the like.

[0038] As an example, the write-back request may include: a write-back request enable signal, a write-back identifier KEY, a write-back data Cacheline, a write-back control bit MASK and other data.

[0039] As an example, the cache ack signal indicating completion of the pre-read operation may include: a cache ack signal enabling signal, an ACK_TAG signal, an ACK data signal, and the like.

[0040] As an example, the write-back cache unit 21 includes multiple specific random access memories SPEC_RAM, all of which use parameterized design to meet the needs of caches of different specifications. For caches of different delay sizes, the expected depth can be configured to achieve read-write-back pipeline, thereby ensuring the consistency of data in the cache.

[0041] As an example, the write-back cache module 20 may include n specific random access memories SPEC_RAM.

[0042] As an example, the write-back cache module 20 can be built through internal registers, and can have 3 write interfaces and 1 read interface, supporting the storage of data cacheline, identification KEY, control bit MASK, read request, and write-back request flag to realize data storage, matching, and replacement.

[0043] As an example, the tag TAG of the read and write request ports of the write-back cache module 20 is the serial number of the specific random access memory SPEC_RAM.

[0044] As an example, the specific random access memory SPEC_RAM can store data, identification KEY, control bit MASK, read request, write back request, etc., supports identification KEY comparison and replacement of data, supports write back when the control bit MASK is high, supports Cache confirmation signal cache ack data return and writes it into the specific random access memory SPEC_RAM when the control bit MASK is low, and the read interface can return data at the same time.

[0045] As an example, the pre-read request cache subunit 321 is a first-in-first-out FIFO, and the depth of the pre-read request cache subunit 321 can be set to n, and the size of n can be set according to the access delay of the cache in different application scenarios to achieve read-write flow, thereby masking the cache access delay and ensuring that n read requests REQ can be cached at the same time. When there is data in the pre-read request cache subunit 321, that is, there is an unprocessed pre-read request, the arbitration subunit 323 receives the non-empty signal of the pre-read request cache subunit 321 and performs arbitration operations. During arbitration, the write-back request is set to have absolute priority, and requests of the same type are arranged in chronological order.

[0046] As an example, the write-back cache subunit 322 may be a special first-in-first-out FIFO constructed using registers, which stores data in a first-in-first-out manner, and all cached data are output to the port.

[0047] As an example, the depth of the write-back cache subunit 322 may be 4, and the write-back cache subunit 322 may use the first register REG0 , the second register REG1 , the third register REG2 , and the fourth register REG3 to store and process data.

[0048] As an example, all data cached by the write-back cache subunit 322 can be output to the port. Since the subsequent arbitration subunit 323 gives absolute priority to write-back, the depth of the write-back cache subunit 322 can be set to be relatively small.

[0049] As an example, the arbitration subunit 323 gives absolute priority to writing back, and always ensures that writing back is completed before reading out, so as to ensure data consistency within the cache.

[0050] As an example, the external request source 10 may include a CPU, a GPU, an I / O device, other hardware accelerators, etc. Among them, the I / O device may include a network interface card, a hard disk controller, etc., and other hardware accelerators may include an encryption and decryption accelerator, a video codec, etc. The specific type and function depend on the architecture and application scenario of the computer system.

[0051] In the above-mentioned computer system, the pre-read request interface 324 can be used to read the data that may be needed from the Cache unit 31 to the write-back cache unit 21 for temporary storage in advance, thereby reducing the access time of subsequent read requests and improving data access efficiency; the write-back absolute priority strategy of the arbitration sub-unit 323 can ensure that the write-back operation is completed first and then the read operation is performed, thereby preventing data conflicts; the write-back cache unit 21 performs data storage, matching and replacement, thereby improving the access efficiency of the Cache, ensuring the data consistency within the Cache, reducing the performance loss caused by data consistency maintenance, and improving the overall system operation efficiency.

[0052] In another embodiment, see Figure 3 The present application provides a data access method for a computer system. The data access method for the computer system is executed based on the above-mentioned computer system. The data access method for the computer system may include the following steps: S10~S50.

[0053] S10: Writing frequently used data from the cache module to the write-back cache module through a pre-read operation.

[0054] S20: The external request source sends a request.

[0055] S30: When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data to read in the write-back cache unit, and if so, returns the data read from the write-back cache unit.

[0056] S40: If not, read data from the cache module through a pre-read operation, and write the read data into the write-back cache module.

[0057] S50: When the request is a write-back request, the write-back request is input into the Cache module, a write-back operation is performed on the Cache module, and the write-back request is input into the write-back cache module, a write-back operation is performed on the write-back cache module.

[0058] In the data access method of the computer system of the present application, frequently used data is pre-fetched from the Cache module and stored in the write-back cache module through a pre-read operation, which can reduce the delay in subsequent reading of these data, improve the data reading speed and the overall system performance, and prepare for subsequent data access operations of the system; when a read request is received, data is read directly from the write-back cache module, and data is pre-read and supplemented from the Cache module when there is no data to read, thereby improving the data reading speed; when a write-back request is received, a write-back operation is performed on the Cache module and the write-back cache module at the same time to ensure the consistency of data updates, thereby optimizing the system's data access performance and data storage consistency, reducing data access delays, and improving the overall response speed and operating efficiency of the system.

[0059] In step S10, refer to Figure 3 In step S10, frequently used data is written from the cache module to the write-back cache module through a pre-read operation.

[0060] As an example, see Figure 4 , step S10 may include the following steps: S11~S14.

[0061] S11: storing the pre-read request in the pre-read request cache sub-unit through the pre-read request interface.

[0062] S12: the arbitration subunit receives the data from the pre-read request cache subunit, performs an arbitration operation, and outputs a read enable signal to the pre-read request cache subunit.

[0063] S13: inputting the pre-read request to the Cache module to perform a pre-read operation based on the read enable signal of the pre-read request cache sub-unit.

[0064] S14: When the cache module completes the pre-read operation, it outputs a confirmation signal indicating that the pre-read operation is completed, and writes the confirmation signal into the write-back cache module.

[0065] Specifically, in step S11 , the pre-read request interface 324 receives the pre-read request and inputs it into the pre-read request cache subunit 321 , and the pre-read request cache subunit 321 caches the data in the pre-read request.

[0066] As an example, the data cached in the pre-read request cache sub-unit 321 may include frequently accessed read requests, identifiers KEY, tags TAG, and the like.

[0067] Further, in step S12, the arbitration sub-unit 323 detects a non-empty signal of the pre-read request cache sub-unit 321, indicating that there is an unprocessed pre-read request in the pre-read request cache sub-unit 321, and the arbitration sub-unit 323 receives the pre-read request from the pre-read request cache sub-unit 321, makes a decision based on the set write-back absolute priority rule, and outputs a read enable signal to the pre-read request cache sub-unit 321.

[0068] Further, in step S13 , after receiving the read enable signal output by the arbitration subunit 323 , the pre-read request cache subunit 321 inputs the pre-read request cached in the pre-read request cache subunit 321 into the Cache cache unit 31 for pre-reading operation.

[0069] As an example, the pre-read request output by the pre-read request buffer sub-unit 321 may include a read request enable signal, a read tag TAG signal, a read identification KEY signal, and the like.

[0070] As an example, the read tag TAG may be read from the pre-read request cache subunit 321. This tag TAG is used to identify and locate the data block to be read in the Cache cache unit 31, ensuring that the data can be read accurately.

[0071] Further, in step S14, after the cache unit 31 of the cache module 30 completes processing the read operation, the cache control logic unit 32 transmits a confirmation signal cache ack indicating completion of the read operation to the read cache ACK interface 222, and writes the data read from the cache unit 31 into the write-back cache unit 21 in the write-back cache module 20 through the read cache ACK interface 222.

[0072] Specifically, when the cache control logic unit 32 returns a confirmation signal cache ack enable, and the returned tag TAG is consistent with the serial number NUM of the specific random access memory SPEC_RAM, if the WB flag in the specific random access memory SPEC_RAM is 0 at this time, the read RD flag is set to 1, the valid VLD flag is set to 1, the write WB flag is set to 0, and the data cacheline returned by the cache control logic unit 32 is all written to the data cacheline at the corresponding position of the write-back cache unit 21. And the bitmap at the corresponding position of the write-back cache unit 21 is set to valid, and the bitmap is set to high, indicating that the data cacheline already exists in the write-back cache unit 21.

[0073] As an example, the determination signal cache ack may include an ACK enable signal, an ACK_TAG signal, an ACK data signal, and the like.

[0074] As an example, the determination signal cache ack written into the write-back cache unit 21 may be one beat later than the determination signal cache ack returned by the cache control logic unit 32 .

[0075] In step S20, refer to Figure 3 In step S20, an external request source sends a request.

[0076] As an example, the external request source 10 may issue multiple requests, including n read requests and n write-back requests.

[0077] As an example, the external request source 10 may include a CPU, a GPU, an I / O device, other hardware accelerators, etc. Among them, the I / O device may include a network interface card, a hard disk controller, etc., and other hardware accelerators may include an encryption and decryption accelerator, a video codec, etc. The specific type and function depend on the architecture and application scenario of the computer system.

[0078] In step S30, refer to Figure 3 In step S30, when the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data to be read from the write-back cache unit. If so, the data read from the write-back cache unit is returned.

[0079] As an example, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether the corresponding bitmap in the write-back cache unit 21 in the write-back cache module 20 is high. If so, the read request interface 221 of the write-back cache module 20 receives the read request and passes it to the read data interface 225. The read data interface 225 locates the position of the read request in the write-back cache unit 21 according to the read tag TAG and identification KEY of the read request, performs a read operation on the write-back cache unit 21, and returns the read data.

[0080] As an example, the read-write cache unit 21 operation can only be initiated when the bitmap of the corresponding write-back cache unit 21 is high. The read-write cache unit 21 operation needs to be tagged with a tag TAG, and the tag TAG is used to match which write-back cache unit 21 data to read. The read-write cache unit 21 operation supports out-of-order reading, and the reading order is controlled by the tag TAG of the external request source 10.

[0081] Specifically, when the write-back cache unit 21 receives a read request REQ enable signal, and the read tag TAG is consistent with the serial number NUM of the specific random access memory SPEC_RAM, and the read identification KEY is consistent with the identification KEY in the specific random access memory SPEC_RAM, that is, the tag TAG and the identification KEY of the read request match, the read RD flag is set to 1, the valid VLD / write WB flag is set to 0, the identification KEY of the read request REQ is written, and the other fields remain unchanged.

[0082] As an example, when the write-back cache unit 21 receives a read request REQ enable signal, and the read tag TAG is consistent with the serial number NUM of the specific random access memory SPEC_RAM, and the read identification KEY is inconsistent with the identification KEY in the specific random access memory SPEC_RAM, that is, the tag TAG of the read request matches but the identification KEY does not match, the read RD flag is set to 1, the valid VLD / write WB flag is set to 0, the identification KEY of the read request REQ is written, and the other fields remain unchanged.

[0083] Among them, read RD is used to indicate whether the data has been read before. When the read RD flag is 1, it indicates that the data has been read before; when the read RD flag is 0, it indicates that the data has not been read before. Write WB is used to indicate whether the data has been written before. When the write WB flag is 1, it indicates that the data has been written before; when the write WB flag is 0, it indicates that the data has not been written before. Valid VLD is a valid flag, which is used to indicate the validity of the data. When the valid VLD flag is 1, it indicates that the relevant data is valid and can be used or processed; when the valid VLD flag is 0, it indicates that the data may be invalid or not ready yet. Identification KEY is used to uniquely identify data. Each data has a corresponding identification KEY. Different data can be quickly located and distinguished by identification KEY. The control bit MASK is used to control the writing and updating mode of data. It is input by bit. The lower 1 bit of every 8 bits is taken as the byte control bit MASK signal, which is combined with other data bits to determine which bytes of data need to be updated and which bytes of data remain unchanged.

[0084] In step S40, refer to Figure 3 In step S40, if not, read the data from the cache module through a pre-read operation, and write the read data into the write-back cache module.

[0085] As an example, see Figure 5 , step S40 may include the following steps: S41~S46.

[0086] S41: When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data to read in the write-back cache unit. If not, a pre-read operation is performed on the cache module.

[0087] S42: storing the pre-read request in the pre-read request cache sub-unit through the pre-read request interface.

[0088] S43: the arbitration sub-unit receives the data from the pre-read request cache sub-unit, performs an arbitration operation, and outputs a read enable signal to the pre-read request cache sub-unit.

[0089] S44: inputting the pre-read request to the cache module to perform a pre-read operation based on the read enable signal of the pre-read request cache sub-unit.

[0090] S45: When the cache module completes the pre-read operation, it outputs a confirmation signal indicating that the pre-read operation is completed, and writes the pre-read data into the write-back cache module.

[0091] S46: The state of the write-back cache module changes to data being readable, a read request is input into the write-back cache module from the entry of the pre-read request cache subunit, a read operation is performed on the write-back cache module, and the read data is returned.

[0092] Specifically, when the external request source 10 issues a read request, the read request interface 221 receives the read request and checks whether the corresponding bitmap in the write-back cache unit 21 in the write-back cache module 20 is high. If not, a pre-read operation is performed on the cache module 30. The pre-read request interface 324 receives the pre-read request and inputs it into the pre-read request cache sub-unit 321. The pre-read request cache sub-unit 321 caches the data in the pre-read request and issues a pre-read request non-empty signal. The arbitration sub-unit 323 detects the non-empty signal of the pre-read request cache sub-unit 321, indicating that there is an unprocessed pre-read request in the pre-read request cache sub-unit 321. The arbitration sub-unit 323 receives the pre-read request from the pre-read request cache sub-unit 321, makes a decision based on the set write-back absolute priority rule, and outputs a read enable signal for the pre-read request cache sub-unit 321. Since the write-back request of the arbitration subunit 323 has absolute priority, when the non-empty signals of the pre-read request cache subunit 321 and the write-back cache subunit 322 are detected at the same time, the arbitration subunit 323 will give priority to processing the write-back request in the write-back cache subunit 322 to ensure that the data can be written back to the Cache module 30 in time to maintain data consistency. Only when the write-back request processing of the Cache module 30 is completed and the write-back cache subunit 322 is empty, the arbitration subunit 323 will process the pre-read request in the pre-read request cache subunit 321, thereby achieving reasonable scheduling of read requests and write-back requests, avoiding problems caused by data competition and inconsistency, and also improving the efficiency of the entire cache system. After receiving the read enable signal output by the arbitration subunit 323, the pre-read request cached in the pre-read request cache subunit 321 is input into the Cache cache unit 31 for pre-read operation. When the Cache unit 31 of the Cache module 30 completes the pre-read operation, the Cache control logic unit 32 transmits the confirmation signal cache ack of the completion of the read operation to the read Cache ACK interface 222, and writes the data pre-read from the Cache unit 31 to the write-back cache unit 21 in the write-back cache module 20 through the read CacheACK interface 222. The bitmap of the write-back cache unit 21 becomes high, and the read Cache REQ write interface 223 obtains the read request from the entrance of the pre-read request cache subunit 321, transmits it to the write-back cache unit 21, performs a read operation on the write-back cache unit 21, and then returns the read data to the external request source 10 through the read data interface 225.

[0093] As an example, the write-back cache unit 21 can return the read data in the next beat of the read operation.

[0094] As an example, the obtaining of the read request from the entry of the pre-read request cache subunit 321 may directly send the read request from the entry of the pre-read request cache subunit 321 to the write-back replacement RAM.

[0095] As an example, the tag TAG of the read operation is read from the read request cache subunit 321, and each time a read operation is performed, the tag TAG+1 is increased, that is, the tag TAG changes from 0 to n-1, and then flips back to 0 and starts again.

[0096] As an example, when the cache control logic unit 32 returns a confirmation signal cache ack enable, and the returned tag TAG is consistent with the serial number NUM of the specific random access memory SPEC_RAM, if the WB flag in the specific random access memory SPEC_RAM is 0 at this time, the read RD flag is set to 1, the valid VLD flag is set to 1, the write WB flag is set to 0, and the data cacheline returned by the cache control logic unit 32 is all written to the data cacheline at the corresponding position of the write-back cache unit 21; if the write WB flag in the specific random access memory SPEC_RAM is 1 at this time, the read RD flag is set to 1, the valid VLD flag is set to 1, the data cacheline whose control bit MASK is 1 remains unchanged, and the field whose control bit MASK is 0 is modified to the data cacheline returned by the cache cache unit 31.

[0097] As an example, when the write-back cache unit 21 receives a read request REQ enable signal, and the read tag TAG is consistent with the serial number NUM of the specific random access memory SPEC_RAM, and the read identification KEY is consistent with the identification KEY in the specific random access memory SPEC_RAM, that is, the tag TAG and the identification KEY of the read request match, the read RD flag is set to 1, the valid VLD / write WB flag is set to 0, the identification KEY of the read request REQ is written, and the other fields remain unchanged.

[0098] As an example, when the write-back cache unit 21 receives a read request REQ enable signal, and the read tag TAG is consistent with the serial number NUM of the specific random access memory SPEC_RAM, and the read identification KEY is inconsistent with the identification KEY in the specific random access memory SPEC_RAM, that is, the tag TAG of the read request matches but the identification KEY does not match, the read RD flag is set to 1, the valid VLD / write WB flag is set to 0, the identification KEY of the read request REQ is written, and the other fields remain unchanged.

[0099] In step S50, refer to Figure 3In step S50, when the request is a write-back request, the write-back request is input into the Cache module, a write-back operation is performed on the Cache module, and the write-back request is input into the write-back cache module, a write-back operation is performed on the write-back cache module.

[0100] As an example, see Figure 6 , step S50 may include the following steps: S51~S56.

[0101] S51: When the request is a write-back request, storing the write-back request in a write-back cache subunit through a write-back request interface.

[0102] S52: The arbitration sub-unit receives the write-back request from the write-back cache sub-unit, performs an arbitration operation, and outputs a read enable signal to the write-back cache sub-unit.

[0103] S53: Based on the read enable signal of the write-back cache sub-unit, the write-back request in the write-back cache sub-unit is input to the cache module for writing back, and the data in the main memory is updated.

[0104] S54: Input the write-back request into the write-back cache unit through the write-back interface, and write back to the write-back cache unit.

[0105] As an example, when the external request source 10 issues a write-back request, the write-back request interface 325 receives the write-back request and inputs it into the write-back cache subunit 322. The write-back cache subunit 322 receives the write-back request and outputs a write-back request non-empty signal. The arbitration subunit 323 detects the non-empty signal of the write-back cache subunit 322, indicating that there is an unprocessed write-back request in the write-back cache subunit 322. The arbitration subunit 323 receives the write-back request from the write-back cache subunit 322, and makes a decision based on the set write-back absolute priority rule, and outputs a read enable signal for the write-back cache subunit. Since the arbitration subunit 323 has an absolute priority for the write-back request, when the non-empty signals of the pre-read request cache subunit 321 and the write-back cache subunit 322 are detected at the same time, the arbitration subunit 323 will give priority to the write-back request in the write-back cache subunit 322 to ensure that the data can be written back to the cache module 30 in time to maintain data consistency. Only when the write-back request processing of the Cache module 30 is completed and the write-back cache subunit 322 is empty, the arbitration subunit 323 will process the pre-read request in the pre-read request cache subunit 321, thereby realizing the reasonable scheduling of the read request and the write-back request, avoiding the problems caused by data competition and inconsistency, and also improving the efficiency of the entire cache system. After the write-back cache subunit 322 receives the read enable signal output by the arbitration subunit 323, the write-back data cached in the write-back cache subunit 322 is input into the Cache cache unit 31 for a write-back operation, and the data in the main memory 40 is updated. At the same time, the write-back request is directly input into the write-back cache unit 21 through the write-back interface 224 from the entrance of the write-back cache subunit 322, and the write-back operation is performed on the write-back cache unit 21.

[0106] Specifically, when the write-back cache unit 21 receives a write-back request, and the identification KEY of the write-back request is consistent with the identification KEY of the specific random access memory SPEC_RAM, and the read RD is 1, the write WB flag is set to 1; the control bit MASK signal of the write-back interface 224 is input bit by bit, and the lower 1 bit is taken for every 8 bits as the byte-by-byte control bit MASK signal, and the converted byte byte control bit MASK signal and the control bit MASK signal stored in the control bit MASK register are ORed and written into the control bit MASK signal field; the data field is written into the field where the control bit MASK signal is 1, and the other fields remain unchanged.

[0107] As an example, the tag TAG of the write operation is generated by internal logic, and the write-back request may include: a write-back enable signal, a write-back identification KEY signal, a write-back data Cacheline, a write-back control bit MASK signal, and the like.

[0108] Further, determine whether there are read requests and write-back requests at the same time. If not, return the data in the write-back cache unit 21. If so, determine whether the hardware has write-back penetration capability. When the hardware does not have write-back penetration capability, directly output the data returned by the write-back cache unit 21. When the hardware has write-back penetration capability, write-back processing is performed on the data in the write-back cache unit 21, and the written-back data is output.

[0109] Specifically, when the write-back request and read request data are returned in the same beat and the hardware does not have the write-back penetration function, the data returned by the write-back cache unit 21 is beat and output directly without being coupled with the write-back data; when the hardware has the write-back penetration function, and the write-back identifier KEY matches the identifier KEY in the write-back cache unit 21, the data returned by the write-back cache unit 21 is beat and returned together with the write-back data according to the write-back control bit MASK.

[0110] As an example, when the control bit MASK is 1, it indicates that the corresponding byte position needs to be updated with write-back data, which means that these bytes in the new write-back data contain new data that need to be retained, and these new data will overwrite the old data at the corresponding byte position in the write-back cache unit 21, thereby achieving the retention of new data. When the control bit MASK is 0, it indicates that the data at the corresponding byte position in the write-back cache unit 21 should be retained, that is, not updated, which is equivalent to eliminating the old data that may exist in the corresponding position in the write-back data, bitwise ORing the returned data, and directly outputting the operation result as the RSP data, which is the latest data. This ensures that during the data processing process, only the parts that are confirmed to need to be updated will be changed, while the other parts remain unchanged, thereby maintaining the stability and consistency of the data.

[0111] In one embodiment, when the write-back request and the cache control logic unit 32 return a confirmation signal cache ack at the same time and the read RD is 1, it means that in the same clock cycle, the existing data write-back operation is in progress, and the cache unit 31 also completes the read operation and the cache control logic unit 32 returns a confirmation signal cache ack. The valid VLD / write WB flag is set to 1, and the control bit MASK field is the control bit MASK of the write-back and the control bit MASK in the specific random access memory SPEC_RAM. The data cacheline is written to the specific random access memory SPEC_RAM according to the write-back data cacheline, and the data cacheline returned by the cache unit 31 is written back according to the write-back control bit MASK.

[0112] In another embodiment, when the write-back request and the read request REQ are valid at the same time, and the identification KEY of the write-back request is consistent with the identification KEY of the read request REQ, that is, in the same clock cycle, both a write-back request and a read request are generated, and the identification KEY of the data involved in these two requests is the same. The read RD and write WB flags are set to 1, the identification KEY of the read request REQ is input into the specific random access memory SPEC_RAM, the control bit MASK field is the control bit MASK of the write-back request and the control bit MASK in the specific random access memory SPEC_RAM are ORed, and the data cacheline is the write-back data and the specific random access memory SPEC_RAM data cacheline is written back according to the write-back request control bit MASK.

[0113] In another embodiment, when the write-back request and the read request REQ are valid at the same time, and the identification KEY of the write-back request is inconsistent with the identification KEY of the read request REQ, that is, in the same clock cycle, there are both the write-back request and the read request, but the identification KEY of the data cacheline targeted by these two operations is not the same, the read RD flag is set to 1, the valid VLD / write WB flag is set to 0, the identification KEY of the read request REQ is input into the specific random access memory SPEC_RAM, and other fields remain unchanged.

[0114] As an example, the present application has made special designs and arrangements so that there is no situation where the read request REQ and the cache control logic unit 32 return confirmation signal cache ack are valid at the same time, that is, the occurrence of the read request and the cache cache unit 31 returns the confirmation signal cache ack after completing the read operation. These two events will not occur at the same time.

[0115] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0116] In the data access method of the computer system of the present application, by pre-reading operations and using the arbitration subunit 323 to ensure write-back priority, data errors caused by untimely write-back are effectively avoided, and the accuracy and integrity of the data are maintained; by finely processing the read and write data, the read data and the write-back data are respectively sent to the write-back cache unit 21, and the cache control logic unit 32 returns the confirmation signal cache ack and properly processes it, thereby achieving precise control of data flow and improving the orderliness of data processing; the control bit MASK parameterized design of the write-back cache unit 21 can meet the needs of caches of different specifications, realize read-write-back pipelining, maintain data consistency, further improve cache access efficiency, and meet the diverse needs of the system.

[0117] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] Although the present application has been disclosed as above with the embodiments, it is not intended to limit the present application. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope of the attached patent application.

Claims

1. A computer system, characterized in that: The computer system comprises: External request source, issues read request and write back request; A write-back cache module receives the read request and the write-back request sent by the external request source; A cache module receives a pre-read request and the write-back request, and writes the data read by the pre-read request into the write-back cache module; The main memory receives the data updated by the cache module and updates the data.

2. The computer system according to claim 1, characterized in that: The write-back cache module includes: A write-back cache unit stores data read from the cache module by a pre-read request and data written back by a write-back request; The write-back cache control logic unit coordinates the interaction between the write-back cache unit, the Cache module, and the external request source.

3. The computer system according to claim 1, characterized in that: The Cache module includes: A cache unit, storing data read from the main memory and data updated in the write-back request; The cache control logic unit coordinates the interaction between the cache unit, the write-back cache module, and the external request source.

4. The computer system according to claim 2, characterized in that: The write-back cache control logic unit includes: A pre-reading request interface, receiving and transmitting the pre-reading request sent by the external request source; A write-back request interface, receiving and transmitting the write-back request sent by the external request source; A pre-reading request cache subunit, receiving and storing the pre-reading request transmitted by the pre-reading request interface; A write-back cache subunit, receiving and storing the write-back request transmitted by the write-back request interface; The arbitration subunit receives the pre-read request stored by the pre-read request cache subunit and the write-back request stored by the write-back cache subunit, performs arbitration operation, and outputs read enable signals to the pre-read request cache subunit and the write-back cache subunit.

5. The computer system according to claim 3, characterized in that: The cache control logic unit includes: A read request interface, receiving and transmitting a read request sent by the external request source; Read Cache ACK write interface, receiving data sent by the Cache control logic unit, and inputting the data into the write-back cache unit; A read Cache REQ write interface receives the read request transmitted by the pre-read request interface and inputs the read request into the write-back cache unit; A write-back interface, receiving the write-back request transmitted by the write-back request interface, and inputting the write-back request into the write-back cache unit; A read data interface receives the read request transmitted by the read request interface, reads data from the write-back cache unit, and returns the data to the external request source.

6. A data access method for a computer system, characterized in that: The data access method of the computer system is executed based on the computer system according to claim 1 or 5, comprising the following steps: Writing frequently used data from the Cache module to the write-back cache module through a pre-read operation; The external request source sends a request; When the request is a read request, the write-back cache control logic unit receives the read request and checks whether there is data to read in the write-back cache unit, and if so, returns the data read from the write-back cache unit; If not, reading data from the cache module through the pre-read operation, and writing the read data into the write-back cache module; When the request is a write-back request, the write-back request is input into the Cache module, a write-back operation is performed on the Cache module, and the write-back request is input into the write-back cache module, and a write-back operation is performed on the write-back cache module.

7. The data access method of a computer system according to claim 6, characterized in that: Writing frequently used data from the cache module to the write-back cache module through a pre-read operation includes: storing the pre-read request in the pre-read request cache subunit through the pre-read request interface; The arbitration subunit receives the pre-read request from the pre-read request cache subunit, performs arbitration operation, and outputs a read enable signal to the pre-read request cache subunit; Inputting the pre-read request to the Cache module to perform a pre-read operation based on the read enable signal of the pre-read request cache subunit; When the cache module completes processing the pre-read operation, it outputs a confirmation signal indicating completion of the pre-read operation, and writes the pre-read data into the write-back cache module.

8. The data access method of a computer system according to claim 6, characterized in that: If not, reading data from the cache module through the pre-read operation and writing the read data into the write-back cache module, including: When the request is a read request, the write-back cache control logic unit receives the read request and checks whether the write-back cache unit has data to read, and if not, performs a pre-read operation on the cache module; storing the pre-read request in the pre-read request cache subunit through the pre-read request interface; The arbitration subunit receives data from the pre-read request cache subunit, performs arbitration operation, and outputs a read enable signal to the pre-read request cache subunit; Inputting the pre-read request to the Cache module to perform a pre-read operation based on the read enable signal of the pre-read request cache subunit; When the cache module completes the pre-read operation, it outputs a confirmation signal indicating that the pre-read operation is completed, and writes the pre-read data into the write-back cache module; The state of the write-back cache subunit changes to data being readable, the read request is input into the write-back cache module from the entry of the pre-read request cache subunit, a read operation is performed on the write-back cache module, and the read data is returned.

9. The data access method of a computer system according to claim 6, characterized in that: When the request is a write-back request, inputting the write-back request into the Cache module, performing a write-back operation on the Cache module, and inputting the write-back request into the write-back cache module, performing a write-back operation on the write-back cache module, including: When the request is a write-back request, storing the write-back request in the write-back cache subunit through a write-back request interface; The arbitration subunit receives the write-back request from the write-back cache subunit, performs arbitration operation, and outputs a read enable signal to the write-back cache subunit; Based on the read enable signal of the write-back cache subunit, the write-back request in the write-back cache subunit is input into the cache module for writing back, and the data in the main memory is updated; The write-back request is input into the write-back cache unit through the write-back interface, and the write-back is performed on the write-back cache unit.

10. The data access method of a computer system according to any one of claims 7 to 9, characterized in that: The arbitration operation includes: setting an absolute priority for the write-back request.

Images