A method for analyzing high-temperature gate bias performance change of a p-type gate GaN HEMT device

Abstract

This invention discloses a method for analyzing the high-temperature gate bias performance variation of p-gate GaN HEMT devices, comprising the following steps: First, parameters are acquired and two-dimensional modeling is performed on the p-gate GaN HEMT device, and a fine mesh is generated. Next, an electrical model is constructed and optimized. After verifying the consistency between the model and the device datasheet, the operating conditions of the device are set, including temperature and bias voltage. Simultaneously, models such as lattice heating, traps and interface states, and mobility are introduced to accurately simulate the device's performance under actual operating conditions. Subsequently, the influence of different HTGB stress times on the internal defect density, charge concentration, and carrier concentration of the device is analyzed by introducing a time model. Finally, the electrical characteristics of the device after different HTGB stress times are simulated and analyzed to evaluate the device's reliability. This invention intuitively demonstrates the impact mechanism of HTGB on device performance degradation and can assess the trend of device performance changes over time.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a method for analyzing the high-temperature gate bias performance variation of a p-type gate GaN HEMT device. Background Technology

[0002] As a representative of third-generation semiconductor materials, gallium nitride (GaN) has attracted increasing attention due to its superior properties such as high electron mobility and high critical electric field. High electron mobility transistors with p-type gate caps (p-GaN HEMTs) are among the most common GaN devices and are widely used in high-temperature, high-voltage, and high-current applications. However, the reliability issues brought about by high-power operating environments are becoming increasingly prominent, making it necessary to analyze their failure mechanisms and assess their lifetime.

[0003] According to existing experimental studies, the failure mechanisms of GaN HEMT devices differ under different operating conditions. Under HTGB (High-temperature gate bias), the device threshold voltage (Vth)... TH The most obvious phenomenon is the drift. First, the gate bias stress causes the p-GaN region to form a negative charge center, which causes the threshold voltage to drift positively. Second, the high temperature changes the defect density inside the device and significantly reduces the electron concentration in the channel region below the gate, which exacerbates the positive drift of the threshold voltage.

[0004] In the development and application of modern power semiconductor devices, high-temperature gate bias (HTGB) testing is an important method for evaluating the reliability of devices under high-temperature environments. HTGB testing is mainly used to analyze the electrical performance and long-term stability of devices under high-temperature gate bias conditions, especially for new wide-bandgap semiconductor devices such as GaN HEMTs and SiC MOSFETs. These devices may exhibit threshold voltage drift and increased leakage current under high temperature and high electric field environments, affecting their normal operation and lifespan. Currently, traditional HTGB testing methods mainly rely on device reliability experiments, which are time-consuming and costly. Moreover, in practice, these methods are difficult to intuitively demonstrate the physical processes of device performance changes, and also difficult to explain and analyze the specific causes of the phenomena. Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to provide a method for analyzing the high-temperature gate bias performance changes of p-type gate GaN HEMT devices, so as to accurately simulate the internal physical processes of the device and reveal the performance changes of the device.

[0006] Technical solution: A method for analyzing the high-temperature gate bias performance variation of p-type gate GaN HEMT devices, including the following steps:

[0007] S1. Based on the process structure parameters of a typical p-gate GaN HEMT device, the device is modeled in two dimensions using software, and the two-dimensional model is meshed to form a meshed device structure that matches the device structure.

[0008] S2, TCAD software is used to simulate the electrical model of the gridded device structure and construct the device electrical simulation model;

[0009] S3, set the operating temperature of the device, and use the device electrical simulation model to simulate the effect of different operating temperatures on the electrical characteristics of the device;

[0010] S4. Select an appropriate simulation operating temperature and set the electrode bias voltage according to the device's operating conditions.

[0011] S5, Select the physical model required for TCAD software simulation;

[0012] S6, add a time model and set different HTGB stress times;

[0013] S7 simulates the electrical characteristics of devices after different HTGB stress times;

[0014] S8, obtain the changes in defect density, charge concentration and carrier concentration inside the device over time at each time point;

[0015] S9 compares the electrical characteristics and internal microphysical quantities of the device under different HTGB stress times, analyzes the device performance degradation mechanism, and evaluates its reliability.

[0016] Furthermore, when meshing the two-dimensional model, the step size near the 2DEG region is 0.01μm, and the step size for other regions is 0.1μm to 0.5μm.

[0017] Furthermore, in step S5, the required physical models include polarization charge model, lattice heating model, trap and interface state model, carrier generation and recombination model, collision ionization model, mobility model and defect dynamic model; after introducing the lattice heating model, it is necessary to define the location of thermal contact and thermal conductivity.

[0018] Furthermore, in step S6, different HTGB stress times are set, and a physical quantity distribution file of the device is output after each HTGB stress time; wherein, the time calculation step size is adjusted with the change of HTGB stress time, and must be less than the HTGB stress time.

[0019] Compared with the prior art, the significant advantages of this invention are as follows:

[0020] 1. This invention utilizes TCAD simulation to construct a device HTGB degradation model, which can accurately simulate the internal physical processes of the device, such as current transport, carrier movement, and defect evolution. This helps researchers reveal the intrinsic mechanisms of device performance changes (such as threshold voltage drift and leakage current changes), improve device structural parameters with high model accuracy, and optimize device electrical characteristics. On the other hand, TCAD simulation does not rely on physical samples or require a large number of experiments and tests, which can significantly reduce testing costs and time, meeting its urgent needs in the semiconductor industry.

[0021] 2. By introducing a time model, this invention can dynamically observe the evolution of physical quantities such as internal trap charge concentration, carrier concentration, and defect density of the device over time after HTGB. This process more intuitively demonstrates the impact mechanism of HTGB on device performance degradation. Finally, by combining the changes of various microscopic physical quantities inside the device with the changes of the device's electrical curves over time, the trend of device performance changes over time can be evaluated. Attached Figure Description

[0022] Figure 1 This is a flowchart of the present invention;

[0023] Figure 2 (a) is a schematic diagram of the HEMT device unit structure, and (b) is the cell structure diagram used in the simulation.

[0024] Figure 3 In the diagram, (a) shows the transfer characteristics of the HEMT device, and (b) shows the output and breakdown characteristics of the HEMT device.

[0025] Figure 4 (a) in the diagram shows the effect of operating temperature on transfer characteristics, and (b) shows the effect of operating temperature on output characteristics.

[0026] Figure 5 (a) shows the effect of different HTGB stress times on the device transfer characteristics; (b) is a magnified view of A; and (c) shows the effect of different HTGB stress times on the device threshold voltage.

[0027] Figure 6 This diagram illustrates the effect of different HTGB stress times on the ionization density of the main defects inside the device, where (a) represents t = 1 × 10⁻⁶. 0 At time s, (b) is t = 1 × 10 2 At time s, (c) is t = 1 × 10 5 At time s, (d) is a comparison of the ionization density of the host defect in the channel region at different HTGB stress times;

[0028] Figure 7This is a schematic diagram illustrating the effect of different HTGB stress times on the internal electron concentration of the device, where (a) represents t = 1 × 10⁻⁶. 0 At time s, (b) is t = 1 × 10 2 At time s, (c) is t = 1 × 10 5 At time s, (d) is a comparison of electron concentration in the channel region at different HTGB stress times;

[0029] Figure 8 The effect of different HTGB stress times on the internal charge concentration of the device is shown, where (a) is t = 1 × 10 0 At time s, (b) is t = 1 × 10 2 At time s, (c) is t = 1 × 10 5 At time s, (d) is a comparison of the charge concentration in the channel region at different HTGB stress times. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0031] like Figure 1 As shown, this invention proposes a simulation analysis method for the performance variation of p-gate GaN HEMT devices (HTGB), comprising the following steps:

[0032] Step 1: Based on the process structure parameters of a typical p-gate GaN HEMT device, use software to perform two-dimensional modeling of the device and mesh the two-dimensional model to form a meshed device structure that matches the device structure.

[0033] Figure 2 The diagram shows the structure of an enhancement-mode p-gate GaN HEMT device. Figure 2 Figure (a) shows a schematic diagram of the cell structure of a p-type gate GaNHEMT device, which includes a 2 μm thick GaN buffer layer, a 200 nm thick GaN channel layer, a 15 nm thick AlGaN barrier layer (Al composition 20%), and a 200 nm thick Si3N4 passivation layer. A 70 nm thick p-type GaN layer is placed between the gate and the AlGaN barrier layer to achieve enhancement-mode functionality. The hole doping concentration in the p-type GaN layer is 2 × 10⁻⁶. 17 cm -3 The gate length is 2μm, the distance between the gate and the source is 2μm, and the spacing between the gate and the drain is 6μm. Figure 2(b) in the figure shows a schematic diagram of the cell structure used in the simulation of the p-gate GaN HEMT device. Based on the design and process parameters of the p-gate GaN HEMT device, a two-dimensional model of the GaN HEMT device is created using semiconductor device modeling tools. Then, the model is meshed (specifically, the area near the 2DEG (two-dimensional electron gas) region, which has a significant impact on electrical parameters, is meshed with a step size of 0.01 μm or even lower, while the remaining areas are meshed with a step size of 0.1 μm-0.5 μm), generating a meshed device structure to ensure that the mesh structure matches the device structure.

[0034] Step 2: Use TCAD software to perform electrical model simulation of the meshed device structure and construct the device electrical simulation model;

[0035] Electrical simulations of the gridded structure of a p-gate GaN HEMT device were performed using TCAD (Technology Computer Aided Design) software. The SRH (Shockley-Read-Hall) recombination model, Auger recombination model, and Fermi-Dirac carrier statistical model were introduced to obtain the drain voltage V. DS Transfer characteristic curve and gate voltage V at 0.5V GS Output characteristic curves at 1V, 3V, and 5V are generated. The electrical simulation results of the device are then compared with the electrical parameters or curves measured in experiments. Key process parameters such as the size and concentration of each region of the device are optimized and calibrated to ensure that the electrical simulation results match the experimental results. The specific steps of optimization and calibration are as follows: the size and doping concentration of each region of the device are changed as variables. The magnitude of the change in the simulation curve is used to determine whether the parameter has a significant impact on the device characteristics. These parameters with significant impact are identified as the primary variables for optimization. Then, by adjusting these variables, a simple and efficient optimization and calibration of the simulation results can be achieved.

[0036] Figure 3 The figure shows the electrical characteristic curves obtained after electrical optimization of the device structure. Figure 3 (a) in the figure is the transfer characteristic curve obtained from the electrical characteristic simulation of the p-gate GaN HEMT device, and the threshold voltage V of the device is... TH At approximately 1.8V; Figure 3 Figure (b) shows the output and breakdown characteristics of the p-gate GaN HEMT device. The highest withstand voltage of the simulated device structure model is 650V, which is consistent with the withstand voltage value provided in the product manual.

[0037] Step 3: Set the operating temperature of the device and use the device electrical simulation model to simulate the effect of different operating temperatures on the electrical characteristics of the device;

[0038] Since the device may operate at different ambient temperatures during application, this embodiment first needs to study the impact of high-temperature environment on the device's electrical performance when the device gate is not energized. Therefore, based on the device electrical simulation model optimized in step 2, different operating temperatures are set to simulate the impact of various ambient temperatures on the device's electrical characteristics. Figure 4 The transfer and output characteristics of the device are shown at 300K, 350K, and 400K. From... Figure 4 As can be seen, the saturation leakage current of the device decreases significantly with increasing temperature, and the simulation results are basically consistent with theoretical expectations. Specifically, as... Figure 4 As shown in (a), the transfer characteristic curve of the device shifts downward with increasing temperature, and the threshold voltage V TH It decreases slightly as the temperature rises; such as Figure 4 As shown in (b) above, when V GS At 3V, the saturation I of a p-gate GaN HEMT device at 300K D The saturation leakage current is 7.83 A at 300 K and drops to about 3.70 A at 400 K, less than half of that at 300 K. This phenomenon is due to the increased atomic vibration in the crystal lattice caused by the increased operating temperature of the device, resulting in more phonons. These phonons scatter with the charge carriers, increasing the scattering probability and causing the charge carriers to be scattered more frequently during movement, thus reducing their mean free path and ultimately leading to a decrease in mobility. The saturation leakage current is caused by the flow of charge carriers from the source to the drain. When the mobility of charge carriers decreases, under the same bias voltage, the overall mobility of charge carriers decreases, reducing the charge carrier injection at the drain, thereby leading to a decrease in the saturation leakage current.

[0039] Step 4: Select an appropriate simulation operating temperature and set the electrode bias voltage according to the device's operating conditions;

[0040] After determining the impact of operating temperature on the electrical performance of the device, it is necessary to select an appropriate simulation operating temperature and device bias voltage for HTGB simulation modeling. In this embodiment, the selected ambient temperature is 400K and the drain voltage V0 is... D With source voltage V S Set to 0V. According to the product datasheet, the device's gate voltage rating is 5V. In the simulation, the gate voltage V... G Set to 5V.

[0041] Step 5: Select the physical model required for the TCAD software simulation;

[0042] Building upon step 4, when performing HTGB simulation calculations using TCAD software, it is necessary to select an appropriate physical model to ensure the accuracy and reliability of the simulation results. The physical models required for HTGB simulation include: a polarization charge model to simulate the polarization effect between the GaN and AlGaN layers; a lattice heating model to simulate the thermal behavior of the device under high-temperature conditions; a trap and interface state model to consider the influence of defects and interface states on current conduction in semiconductor devices; a carrier generation and recombination model to describe the generation and recombination processes of carriers, thus affecting the electrical performance of the device; a collisional ionization model to describe the collisional ionization phenomenon of carriers under high electric fields; a mobility model to describe the mobility of carriers in the material; and a defect dynamics model to simulate the impact of the dynamic behavior of defects under different conditions on device performance. (During the simulation, after introducing the lattice heating model, it is necessary to define the location of thermal contacts and set the thermal conductivity to 2500 W / K).

[0043] Step 6: Add the time model and set different HTGB stress times;

[0044] In step 5, the physical model required for HTGB simulation was first defined. This step then introduces a time model to simulate the dynamic evolution of various physical quantities within the device over time. This process will more intuitively reflect the impact of HTGB on the device performance degradation mechanism. During the simulation, this implementation selected multiple HTGB stress time points, including 1×10⁻⁶. 0 s, 1×10 2 s, 1×10 3 s, 1×10 4 s and 1×10 5 The time calculation step size should be adjusted according to the HTGB stress time (after defining the end time of the high-temperature bias stress, the time calculation step size is generally 2-3 orders of magnitude smaller than that time point; for example, if the stress time is 100s, then the time calculation iteration step size is generally 1s or less), and must be less than the HTGB stress time.

[0045] Step 7: Perform electrical characteristic simulations on the devices after different HTGB stress times, and compare and analyze the influence of different stress times on the electrical characteristics of the devices.

[0046] Next, the change in the device threshold voltage was measured at different HTGB times, such as... Figure 5 As shown in (a), the results indicate that as the HTGB time increases, the device's threshold voltage gradually increases, while the saturation leakage current (Ig) decreases. D The value gradually decreases. Figure 5As can be seen from (b), the change in threshold voltage is 1 mV at 1 s, and reaches 1 × 10⁻⁶ mV at 1 s. 5 The voltage increases to 103 mV over time; this result indicates that HTGB causes significant changes in the threshold voltage and saturation leakage current of p-gate GaN HEMT devices, and that increasing the HTGB time may exacerbate this effect.

[0047] Step 8: Obtain the changes in defect density, charge concentration, and carrier concentration inside the device over time at each time point;

[0048] To explain the variations in the electrical characteristics of p-gate GaN HEMT devices, this embodiment compares different gate bias stress times (1s, 10s, ...). 0 s, 1×10 5 s) The influence of the ionization density, electron concentration, and charge concentration of the main defect inside the device, such as Figure 6 , Figure 7 and Figure 8 As shown. Specifically, as Figure 6 As shown, under prolonged exposure to high temperature and high electric field, the thermal energy in the material increases, leading to the excitation of more defect or impurity atoms. Over time, the thermal ionization degree of the acceptor defects gradually increases, resulting in an increase in ionization density. Figure 6 As shown in (d) in the diagram. Figure 7 As shown, an increase in the number of acceptor defects means that more ionized acceptors can bind free electrons, resulting in a gradual decrease in the free electron concentration over time. Figure 7 As shown in (d), this is because the acceptor defect consumes these electrons by combining with free electrons.

[0049] In addition, such as Figure 8 As shown, due to the application of a positive voltage to the gate of the device, more electrons drift to the p-GaN region under the influence of the electric field and are trapped in the traps of this region, forming a negatively charged electron. With increasing stress time, the charge concentration in this region gradually increases. Figure 8 As shown in (d) above. These results further validate the mechanism by which the HTGB process affects the performance of power semiconductor devices.

[0050] Step 9: Under different HTGB stress times, compare the electrical characteristics and internal microphysical quantities of the device, analyze the device performance degradation mechanism, and evaluate its reliability.

[0051] The threshold voltage changes after different HTGB stress times in step 7 are consistent with the trends observed in the changes of internal micro-parameters of the device in step 8. Specifically, the decrease in electron concentration in the channel region of the p-gate GaN HEMT device directly affects the device's conductivity and current flow capability, leading to an increase in the threshold voltage. On the other hand, the accumulation of negative charges in the p-GaN region reduces the potential of the channel region below the gate, meaning that a higher gate voltage needs to be applied to achieve the conduction state, thereby increasing the threshold voltage.

Claims

1. A method for analyzing high-temperature gate bias performance variation of a p-gate GaN HEMT device, characterized in that, The steps include the following: S1, according to the process structure parameters of a typical p-gate GaN HEMT device, a two-dimensional model of the device is established by using software, and the two-dimensional model is meshed to form a meshed device structure matching the device structure; S2, an electrical model of the meshed device structure is simulated by using TCAD software to construct a device electrical simulation model; S3, the working temperature of the device is set, and the device electrical simulation model is used to simulate the influence of different working temperatures on the electrical characteristics of the device; S4, according to the working conditions of the device, an appropriate simulation working temperature is selected, and an electrode bias voltage is set; S5, the physical model required for simulation is selected; S6, a time model is added, and different HTGB stress times are set; S7, the electrical characteristics of the device after different HTGB stress times are simulated; S8, the changes of the defect density, charge concentration and carrier concentration in the device at each time point with time are obtained; S9, the electrical characteristics and internal microscopic physical quantities of the device under different HTGB stress times are compared, the performance degradation mechanism of the device is analyzed, and the reliability of the device is evaluated.

2. The method of claim 1, wherein the p-gate GaN HEMT device is a p-gate GaN HEMT device of claim 1. When the two-dimensional model is meshed, the step size near the 2DEG region is 0.01 μm, and the step size of the remaining regions is 0.1 μm-0.5 μm.

3. The method of claim 1, wherein the p-gate GaN HEMT device is a p-gate GaN HEMT device of claim 2. In step S5, the required physical models include polarization charge model, lattice heating model, trap and interface state model, carrier generation and recombination model, collision ionization model, mobility model and defect dynamic model; after introducing the lattice heating model, the position of thermal contact and thermal conductivity need to be defined.

4. The method of claim 1, wherein the p-gate GaN HEMT device is a high-temperature gate bias performance variation analysis method. In step S6, different HTGB stress times are set, and the internal physical quantity distribution file of the device is output after each HTGB stress time ends; wherein the time calculation step size is adjusted according to the change of the HTGB stress time, and must be less than the HTGB stress time.

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