An automatic timing processing method and device, electronic equipment and storage medium

Abstract

The application relates to an automatic timing processing method and device, electronic equipment and a storage medium, the method comprising: acquiring a to-be-processed PCB design file, the to-be-processed PCB design file comprising a group of signal lines needing timing processing, the group of signal lines comprising at least two signal lines; determining a winding area in the to-be-processed PCB design file according to a preset spacing rule, the winding area being an area needing winding with the same length; and automatically winding each signal line in the group of signal lines in the winding area according to a preset winding length requirement, the spacing rule and a preset winding rule. Through the method, the winding length requirement, the spacing rule and the winding rule are considered, each signal line in the group of signal lines is automatically wound, the winding quality can be guaranteed, and the winding efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB design, and in particular to an automatic timing processing method, device, electronic device and storage medium. Background Art

[0002] Timing processing is a crucial step in the PCB design process. This involves aligning the lengths of a group of signal lines with specific timing requirements. The current process involves establishing a timing group, designing equal-length rules, routing lines to equal lengths, and then reviewing these rules. This process is the most time-consuming step in timing processing. Conventional methods often rely on manual routing, reducing PCB design efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an automatic time sequence processing method, device, electronic device and storage medium, aiming to solve at least one of the above technical problems.

[0004] In a first aspect, the present invention provides a technical solution to the above-mentioned technical problem as follows: an automatic time sequence processing method, the method comprising:

[0005] Obtaining a PCB design file to be processed, wherein the PCB design file to be processed includes a group of signal lines that require timing processing, and the group of signal lines includes at least two signal lines;

[0006] Determine the winding area in the PCB design file to be processed according to a preset spacing rule, where the winding area is an area where winding of equal length is required;

[0007] Each signal line in the group of signal lines is automatically wound in the winding area according to a preset winding length requirement, the spacing rule and a preset winding rule.

[0008] The beneficial effects of the present invention are as follows: taking into account the winding length requirements, spacing rules and winding rules, each signal line in a group of signal lines is automatically wound, thereby ensuring the winding quality and improving the winding efficiency.

[0009] On the basis of the above technical solution, the present invention can also be improved as follows.

[0010] Furthermore, the automatically winding each signal line in the group of signal lines in the winding area according to the preset winding length requirement, the spacing rule and the preset winding rule includes:

[0011] determining a first target area in the winding area according to a preset winding length requirement, the spacing rule, and a preset winding rule;

[0012] Automatically routing a first signal line in the group of signal lines in the first target area, and determining a first remaining area after the first signal line is automatically routed, the first remaining area being an area in the first target area excluding an area occupied by the first signal line;

[0013] determining whether the first remaining area is a winding area of ​​the second signal line;

[0014] If the first remaining area is a winding area for a second signal line, automatically winding the second signal line in the first remaining area until the automatic winding of the last signal line in the group of signal lines is completed;

[0015] If the first remaining area is not the winding area of ​​the second signal line, the position of the first remaining area is adjusted so that the adjusted first remaining area becomes the winding area of ​​the second signal line, and the second signal line is automatically wound in the adjusted first remaining area until the automatic winding of the last signal line in the group of signal lines is completed.

[0016] Furthermore, the method further comprises:

[0017] Determine, according to the preset spacing rule, a prohibited area in the PCB design file to be processed, wherein the prohibited area is an area where winding of equal length is not required;

[0018] The determining whether the first remaining area is a winding area of ​​the second signal line includes:

[0019] It is determined whether the first remaining area is a routing area of ​​the second signal line according to the position of the prohibited area.

[0020] Furthermore, if the first remaining area is not a wiring area for the second signal line, the method further includes:

[0021] determining a second target area corresponding to each signal line except the first signal line in the wiring area;

[0022] According to the winding method of the first signal line in the first target area, each signal line except the first signal line is automatically wound in each second target area until the automatic winding of the last signal line in the group of signal lines is completed.

[0023] Furthermore, if the first remaining area is not the winding area of ​​the second signal line, adjusting the position of the first remaining area so that the adjusted first remaining area becomes the winding area of ​​the second signal line includes:

[0024] If the first residual region is not a winding region of the second signal line, the position of the straight signal line in the first residual region is adjusted to obtain an adjusted first residual region, the adjusted first residual region is a winding region of the second signal line, and the adjusted first residual region is located between the first signal line and the second signal line.

[0025] In a second aspect, the present application provides an automatic timing processing device to solve the above technical problems, which comprises:

[0026] An acquisition module is configured to acquire a to-be-processed PCB design file, the to-be-processed PCB design file comprising a group of signal lines requiring timing processing, and the group of signal lines comprising at least two signal lines;

[0027] A winding region determination module is configured to determine a winding region in the to-be-processed PCB design file according to a preset spacing rule, the winding region being a region requiring winding to the same length;

[0028] A first automatic winding module is configured to automatically wind each signal line in the group of signal lines in the winding region according to a preset winding length requirement, the spacing rule and a preset winding rule.

[0029] In a third aspect, the present application provides an electronic device to solve the above technical problems, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the automatic timing processing method of the present application when executing the computer program.

[0030] In a fourth aspect, the present application provides a computer readable storage medium to solve the above technical problems, the computer readable storage medium storing a computer program, and the computer program is executed by a processor to implement the automatic timing processing method of the present application.

[0031] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the description of the embodiments of the present application will be briefly introduced.

[0033] Figure 1 A flowchart of an automatic timing processing method provided by an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a group of signal lines provided by an embodiment of the present application;

[0035] Figure 3 A schematic diagram of a prohibited area provided by an embodiment of the present invention;

[0036] Figure 4 A schematic diagram of a winding result of a winding rule provided by one embodiment of the present invention;

[0037] Figure 5 A schematic diagram of a first target area provided by an embodiment of the present invention;

[0038] Figure 6 A schematic diagram of a first signal line winding completion effect provided by an embodiment of the present invention;

[0039] Figure 7 A schematic diagram of the position of a first target area after adjustment provided by an embodiment of the present invention;

[0040] Figure 8 A schematic diagram of a second signal line winding completion effect in an adjusted first target area provided by one embodiment of the present invention;

[0041] Figure 9 A schematic diagram of the effect of winding a second signal line according to the winding method of a first signal line provided by one embodiment of the present invention;

[0042] Figure 10 A schematic diagram showing the effect of a group of signal lines being wound according to an embodiment of the present invention;

[0043] Figure 11 A schematic structural diagram of an automatic time sequence processing device provided by one embodiment of the present invention;

[0044] Figure 12 The present invention provides a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The principles and features of the present invention are described below. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0046] The following describes in detail the technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems using specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The following embodiments of the present invention are described in conjunction with the accompanying drawings.

[0047] The solution provided by the embodiments of the present invention can be applied to any application scenario requiring automatic wire winding in PCB design files. The solution provided by the embodiments of the present invention can be executed by any electronic device, for example, a user's terminal device. The terminal device can be any terminal device that can install applications and access web pages through applications, including at least one of the following: a smartphone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, a smart TV, and a smart car device.

[0048] The embodiment of the present invention provides a possible implementation method, such as Figure 1 As shown in FIG, a flowchart of an automatic time sequence processing method is provided. The solution can be executed by any electronic device, for example, a terminal device, or a terminal device and a server. For the convenience of description, the method provided by the embodiment of the present invention will be described below using the terminal device as the execution subject. Figure 1 As shown in the flowchart, the method may include the following steps:

[0049] S10, obtaining a PCB design file to be processed, wherein the PCB design file to be processed includes a group of signal lines that require timing processing, and the group of signal lines includes at least two signal lines;

[0050] S20, determining a winding area in the PCB design file to be processed according to a preset spacing rule, wherein the winding area is an area where winding of equal length is required;

[0051] S30 , automatically winding each signal line in the group of signal lines in the winding area according to a preset winding length requirement, the spacing rule, and a preset winding rule.

[0052] By adopting the method of the present invention, each signal line in a group of signal lines is automatically wound in consideration of the winding length requirement, spacing rule and winding rule, thereby ensuring the winding quality and improving the winding efficiency.

[0053] The present invention is further described below with reference to the following specific embodiments. In this embodiment, automatic wire routing is configured by a computer to meet set constraint rules. The purpose of the wire routing (equal length winding) is to allow the computer to adjust the length of each signal line in a group according to the rules, ultimately making all signal lines of the same length. Based on this, this embodiment provides an automatic timing processing method. Before executing the method, spacing rules, winding length requirements, and winding rules must be set. Spacing rules refer to the spacing between wires and vias, the spacing between wires and copper foil, and the spacing between wires. The winding length requirement refers to the length error rule, for example, setting a length tolerance of ±10 mil for 11 signal lines. The winding rules refer to the wire width w, the winding height h, the wire-to-wire distance d, and the wire bend angle. When the value w is fixed, the values ​​of h and d can be set. According to common design rules and specifications, d is set to ≥ 3w. The value of h is not restricted. Based on the spacing rules, winding length requirements, and winding rules, the PCB design file can be rationally planned, and the winding position and winding method of each signal line can be clearly determined. The details are described below.

[0054] Based on the above content, this embodiment provides an automatic time sequence processing method, which may include the following steps:

[0055] S10, obtaining a PCB design file to be processed, wherein the PCB design file to be processed includes a group of signal lines that require timing processing, and the group of signal lines includes at least two signal lines;

[0056] The PCB design file to be processed can be a PCB file generated by PCB design software. In this PCB file, automatic signal line routing can be performed. Figure 2 A group of signal lines is shown, and each signal line in the group of signal lines is a signal line with timing requirements.

[0057] S20, determining a winding area in the PCB design file to be processed according to a preset spacing rule, wherein the winding area is an area where winding of equal length is required;

[0058] Among them, based on the spacing rules and the number of signal lines in a group of signal lines, the size of the area required for each signal line in this group of signal lines when winding can be determined, thereby determining which area in the PCB design file to be processed can be used as an area of ​​equal length for winding.

[0059] S30 , automatically winding each signal line in the group of signal lines in the winding area according to a preset winding length requirement, the spacing rule, and a preset winding rule.

[0060] Among them, based on the winding length requirements, we can know the length of each signal line and the length error rules between each signal line. Based on the spacing rules, we can know the spacing from the line to the via, the spacing from the line to the copper foil, and the spacing between the lines when winding. Based on the winding rules, we can know the specific winding method, including the width of the line, the height of the winding, the distance between two adjacent lines, and the bending angle of the line. In this solution, the bending angle of the line can be 45 degrees. As an example, see Figure 4 The winding effect diagram shown in Figure 4 In the middle, the line bending angle is 45 degrees.

[0061] Optionally, one implementation of the above S30 is:

[0062] S301, according to the preset winding length requirement, the spacing rule and the preset winding rule, determine a first target area in the winding area; wherein the first target area refers to the area where the first signal line is wound. As an example, see Figure 5 The schematic diagram of the location of the first target area shown in FIG. Figure 5 The enclosed area formed by the thick white line is the first target area.

[0063] S302 , automatically winding a first signal line in the group of signal lines in the first target area. After the first signal line is wound, it includes a curved signal line portion and a straight signal line portion.

[0064] After the first signal line is automatically routed, a first remaining area is determined, where the first remaining area is an area in the first target area excluding an area occupied by the first signal line; see Figure 6 The schematic diagram shown, Figure 6 The enclosed area formed by the medium grey thick line is the first remaining area. It should be noted that Figure 6 The area marked with a medium gray thick line only roughly illustrates the position of the first remaining area and does not represent the actual position of the first remaining area. In different situations, the position of the first remaining area will be adjusted based on actual conditions.

[0065] S303 , determining whether the first remaining area is a routing area for the second signal line; that is, determining whether the first remaining area can be used to route the second signal line.

[0066] S304: If the first remaining area is the routing area for the second signal line, automatically routing the second signal line in the first remaining area. After the second signal line is automatically routed, a target area corresponding to the third signal line is determined in the same manner as in S301 to S303 above. The third signal line is routed in the same manner as in the first target area, until the automatic routing of the last signal line in the group of signal lines is completed.

[0067] S305: If the first remaining area is not the winding area of ​​the second signal line, please refer to Figure 6 The position of the first remaining area shown in Figure 6 , then the first remaining area is not the winding area of ​​the second signal line, then the position of the first remaining area is adjusted so that the adjusted first remaining area becomes the winding area of ​​the second signal line, see Figure 7 The position of the adjusted first remaining area is shown as Figure 7 The closed area is formed by the medium gray thick line, and the second signal line is automatically routed in the adjusted first remaining area. Figure 8 Schematic diagram of the winding effect of the second signal line in the first remaining area. In this way, the winding area can be used to the maximum extent, and the success rate of automated winding can be improved.

[0068] After the second signal line is automatically wound, the target area corresponding to the third signal line can be determined in the same processing method as S301 to S303 above, and the third signal line can be wound in the same way as the winding processing method for the first signal line in the first target area above until the automatic winding of the last signal line in the group of signal lines is completed.

[0069] Optionally, the above method further includes:

[0070] According to the preset spacing rule, the prohibited area in the PCB design file to be processed is determined, and the prohibited area is an area where no winding of equal length is required; see Figure 3 The schematic diagram shown, Figure 3 The area corresponding to the grid is the prohibited area.

[0071] In the above S303, determining whether the first remaining area is a wiring area of ​​the second signal line includes:

[0072] It is determined whether the first remaining area is a routing area of ​​the second signal line according to the position of the prohibited area.

[0073] Specifically, if the first remaining area is located between the prohibited area and the first signal line, it is judged that the first remaining area is not the winding area of ​​the second signal line; if the first remaining area is located between the first signal line and the second signal line, it is judged that the first remaining area is the winding area of ​​the second signal line.

[0074] Based on the above principle of determining whether the first remaining area is the winding area of ​​the second signal line, optionally, if the first remaining area is not the winding area of ​​the second signal line, adjusting the position of the first remaining area so that the adjusted first remaining area becomes the winding area of ​​the second signal line includes:

[0075] If the first remaining area is not the winding area of ​​the second signal line, the position of the straight signal line in the first remaining area is adjusted to obtain an adjusted first remaining area. The adjusted first remaining area is the winding area of ​​the second signal line, and the adjusted first remaining area is located between the first signal line and the second signal line.

[0076] As an example, the adjusted first remaining area may be Figure 7 The enclosed area is formed by the thick medium gray line.

[0077] Optionally, if the first remaining area is not a routing area for the second signal line, and the utilization rate of the signal line is not considered, the method further includes:

[0078] determining a second target area corresponding to each signal line except the first signal line in the wiring area;

[0079] According to the winding method of the first signal line in the first target area, each signal line except the first signal line is automatically wound in each second target area until the automatic winding of the last signal line in the group of signal lines is completed.

[0080] That is, according to the winding method of the first signal line in the first target area, each signal line in a group of signal lines is processed in the same way to complete the automatic winding of each signal line in a group of signal lines. Figure 9 The second signal line is shown in the diagram of the winding effect in the corresponding second target area. In this way, the winding speed is faster, but the winding success rate may be reduced.

[0081] Based on the automatic timing processing method provided by this solution, after automatically winding a group of signal lines, the resulting effect diagram can be seen in Figure 10 The effect diagram shown.

[0082] Compared with the prior art, the solution of the present invention has the following beneficial effects:

[0083] The computer automatically winds the wires according to the set rules to meet the requirements of the constraint rules, reducing the time of manual processing.

[0084] Based on Figure 1 The same principle as the method shown in , the embodiment of the present invention also provides an automatic time sequence processing device 20, such as Figure 11 As shown in , the automatic timing processing device 20 may include an acquisition module 210, a winding area determination module 220 and a first automatic winding module 230, wherein:

[0085] An acquisition module 210 is configured to acquire a PCB design file to be processed, wherein the PCB design file to be processed includes a group of signal lines that require timing processing, wherein the group of signal lines includes at least two signal lines;

[0086] The winding area determination module 220 is used to determine the winding area in the PCB design file to be processed according to a preset spacing rule, where the winding area is an area where winding of equal length is required;

[0087] The first automatic winding module 230 is configured to automatically wind each signal wire in the group of signal wires in the winding area according to a preset winding length requirement, the spacing rule, and a preset winding rule.

[0088] Optionally, when the first automatic winding module 230 automatically winds each signal line in the group of signal lines in the winding area according to the preset winding length requirement, the spacing rule and the preset winding rule, it is specifically used to:

[0089] determining a first target area in the winding area according to a preset winding length requirement, the spacing rule, and a preset winding rule;

[0090] Automatically routing a first signal line in the group of signal lines in the first target area, and determining a first remaining area after the first signal line is automatically routed, the first remaining area being an area in the first target area excluding an area occupied by the first signal line;

[0091] determining whether the first remaining area is a winding area of ​​the second signal line;

[0092] If the first remaining area is a winding area for a second signal line, automatically winding the second signal line in the first remaining area until the automatic winding of the last signal line in the group of signal lines is completed;

[0093] If the first remaining area is not a winding area of the second signal line, the position of the first remaining area is adjusted so that the adjusted first remaining area is a winding area of the second signal line, and the second signal line is automatically wound in the adjusted first remaining area until the last signal line in the group of signal lines is automatically wound.

[0094] Optionally, the device further comprises:

[0095] The forbidden area determination module is configured to determine a forbidden area in the to-be-processed PCB design file according to the preset spacing rule, the forbidden area being an area that is not to be lengthened by winding.

[0096] The first automatic winding module 230, when judging whether the first remaining area is a winding area of the second signal line, is specifically configured to:

[0097] The first automatic winding module 230, when judging whether the first remaining area is a winding area of the second signal line, is specifically configured to:

[0098] Optionally, if the first remaining area is not a winding area of the second signal line, the device further comprises:

[0099] The second automatic winding module is configured to determine, in the winding area, a second target area corresponding to each signal line except the first signal line; and perform automatic winding on each signal line except the first signal line in each second target area according to the winding mode of the first signal line in the first target area until the last signal line in the group of signal lines is automatically wound.

[0100] Optionally, when the first automatic winding module 230 adjusts the position of the first remaining area so that the adjusted first remaining area is a winding area of the second signal line, the first automatic winding module 230 is specifically configured to:

[0101] If the first remaining area is not a winding area of the second signal line, the position of a straight signal line in the first remaining area is adjusted to obtain an adjusted first remaining area, the adjusted first remaining area being a winding area of the second signal line, and the adjusted first remaining area being located between the first signal line and the second signal line.

[0102] The automatic timing processing device of the embodiment of the present invention can execute the automatic timing processing method provided by the embodiment of the present invention. The implementation principle is similar. The actions performed by each module and unit in the automatic timing processing device in each embodiment of the present invention correspond to the steps in the automatic timing processing method in each embodiment of the present invention. For the detailed functional description of each module of the automatic timing processing device, please refer to the description of the corresponding automatic timing processing method shown in the previous text, and will not be repeated here.

[0103] The automatic timing processing device may be a computer program (including program code) running in a computer device, for example, the automatic timing processing device is an application software; the device may be used to execute the corresponding steps in the method provided in the embodiment of the present invention.

[0104] In some embodiments, the automatic timing processing device provided by the embodiments of the present invention can be implemented in a combination of software and hardware. As an example, the automatic timing processing device provided by the embodiments of the present invention can be a processor in the form of a hardware decoding processor, which is programmed to execute the automatic timing processing method provided by the embodiments of the present invention. For example, the processor in the form of a hardware decoding processor can adopt one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components.

[0105] In other embodiments, the automatic timing processing device provided by the embodiment of the present invention can be implemented in software. Figure 11 An automatic timing processing device stored in a memory is shown, which can be software in the form of a program and a plug-in, and includes a series of modules, including an acquisition module 210, a winding area determination module 220 and a first automatic winding module 230, for implementing the automatic timing processing method provided by an embodiment of the present invention.

[0106] The modules involved in the embodiments of the present invention may be implemented in software or hardware, wherein the name of a module does not necessarily limit the module itself.

[0107] Based on the same principle as the method shown in the embodiments of the present invention, an electronic device is also provided in the embodiments of the present invention, which may include but is not limited to: a processor and a memory; the memory is used to store computer programs; the processor is used to execute the method shown in any embodiment of the present invention by calling the computer program.

[0108] In an alternative embodiment, an electronic device is provided, such as Figure 12 As shown, Figure 12 The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data exchange between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the number of transceivers 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0109] Processor 4001 can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. Processor 4001 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0110] Bus 4002 may include a path for transmitting information between the above components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. Bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 12 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0111] The memory 4003 can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0112] The memory 4003 is configured to store application code (computer program) for implementing the scheme of the present application, and the processor 4001 is configured to control the execution. The processor 4001 is configured to execute the application code stored in the memory 4003 to implement the content shown in the foregoing method embodiments.

[0113] The electronic device can also be a terminal device, Figure 12 The electronic device shown is only an example, and should not limit the functions and use range of the embodiments of the present application.

[0114] The embodiments of the present application provide a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program runs on a computer, the computer can execute the corresponding content in the foregoing method embodiments.

[0115] According to another aspect of the present application, a computer program product or computer program is also provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform the method provided in the various implementation manners of the above embodiments.

[0116] Computer program code for performing the operations of the present invention may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0117] It should be understood that the flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions.

[0118] The computer-readable storage medium provided by the embodiments of the present invention may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or device.

[0119] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method shown in the above embodiment.

[0120] The above description is merely an illustration of preferred embodiments of the present invention and the underlying technical principles. Those skilled in the art should understand that the scope of the present invention is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned concepts. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this invention.

Claims

1. An automatic time sequence processing method, characterized in that: The following steps are involved: Obtaining a PCB design file to be processed, wherein the PCB design file to be processed includes a group of signal lines that require timing processing, and the group of signal lines includes at least two signal lines; Determine the winding area in the PCB design file to be processed according to a preset spacing rule, where the winding area is an area where winding of equal length is required; Automatically winding each signal line in the group of signal lines in the winding area according to a preset winding length requirement, the spacing rule, and a preset winding rule; The automatically winding each signal line in the group of signal lines in the winding area according to the preset winding length requirement, the spacing rule and the preset winding rule includes: S301, determining a first target area in the winding area according to a preset winding length requirement, the spacing rule, and a preset winding rule; S302, automatically routing a first signal line in the group of signal lines in the first target area, and determining a first remaining area after the first signal line is automatically routed, where the first remaining area is an area in the first target area excluding an area occupied by the first signal line; S303, determining whether the first remaining area is a winding area of ​​the second signal line; S304: If the first remaining area is a routing area for a second signal line, automatically routing the second signal line in the first remaining area. After the second signal line is automatically routed, determining a second remaining area, where the second remaining area is an area of ​​the first remaining area excluding an area occupied by the second signal line. S305: Use the second remaining area as a new first remaining area, and repeat S303 to S304 for each signal line after the second signal line, until the last signal line in the group of signal lines is automatically wound; S306: If the first remaining area is not the routing area for the second signal line, adjusting the position of the first remaining area so that the adjusted first remaining area becomes the routing area for the second signal line, automatically routing the second signal line in the adjusted first remaining area, and after the second signal line is automatically routed, determining a third remaining area, the third remaining area being the area of ​​the adjusted first remaining area excluding the area occupied by the second signal line. S307 , using the third remaining area as a new first remaining area, and repeating S303 to S306 for each signal line after the second signal line, until the last signal line in the group of signal lines is automatically wound.

2. The method according to claim 1, characterized in that The method further comprises: Determine, according to the preset spacing rule, a prohibited area in the PCB design file to be processed, wherein the prohibited area is an area where winding of equal length is not required; The determining whether the first remaining area is a winding area of ​​the second signal line includes: It is determined whether the first remaining area is a routing area of ​​the second signal line according to the position of the prohibited area.

3. The method according to claim 1, characterized in that If the first remaining area is not a routing area for the second signal line, the method further includes: determining a second target area corresponding to each signal line except the first signal line in the wiring area; According to the winding method of the first signal line in the first target area, each signal line except the first signal line is automatically wound in each second target area until the automatic winding of the last signal line in the group of signal lines is completed.

4. The method according to claim 1, wherein If the first remaining area is not the winding area of ​​the second signal line, adjusting the position of the first remaining area so that the adjusted first remaining area becomes the winding area of ​​the second signal line includes: If the first remaining area is not the winding area of ​​the second signal line, the position of the straight signal line in the first remaining area is adjusted to obtain an adjusted first remaining area. The adjusted first remaining area is the winding area of ​​the second signal line, and the adjusted first remaining area is located between the first signal line and the second signal line.

5. An automatic time sequence processing device, characterized in that: The automatic time sequence processing method according to claim 1 is adopted, wherein the device comprises: An acquisition module is used to acquire a PCB design file to be processed, wherein the PCB design file to be processed includes a group of signal lines that need timing processing, and the group of signal lines includes at least two signal lines; A winding area determination module is used to determine the winding area in the PCB design file to be processed according to a preset spacing rule, where the winding area is an area where winding of equal length is required; The first automatic winding module is used to automatically wind each signal wire in the group of signal wires in the winding area according to a preset winding length requirement, the spacing rule and a preset winding rule.

6. The device according to claim 5, characterized in that The device further comprises: A prohibited area determination module is used to determine the prohibited area in the PCB design file to be processed according to the preset spacing rule, wherein the prohibited area is an area of ​​equal length that does not require winding; When the first automatic winding module determines whether the first remaining area is the winding area of ​​the second signal line, the first automatic winding module is specifically configured to: It is determined whether the first remaining area is a routing area of ​​the second signal line according to the position of the prohibited area.

7. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 4 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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