Secondary Mapping scheduling method and system of wafer processing system

Abstract

The invention discloses a secondary Mapping scheduling method and system for a wafer processing system, and the method comprises the steps: carrying out the virtual matching of a wafer processing technology formula for each wafer sub-layer of a wafer box, obtaining a virtual matching sequence table, and then loading the wafer box to a box opener machine table for wafer processing; then, data information of a wafer box which is loaded into the machine and provided with a wafer to be processed is obtained, and a wafer processing matching sequence is obtained according to output of a wafer detection module and the virtual matching sequence table in combination with the constructed wafer correction strategy; the problem that at present, formula selection needs to be carried out after the wafer is scanned, and extra time waste is caused is solved, and the wafer processing efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of wafer processing technology, and in particular to a secondary mapping scheduling method and system for a wafer processing system. Background Art

[0002] Mapping scheduling is an important step in the wafer processing process. It generally refers to the process of planning and adjusting the wafer processing path in order to optimize processing efficiency, improve product yield, and reduce production cycle time (CycleTime) during the semiconductor manufacturing process. However, the Mapping scheduling process set up in the current traditional wafer processing machine generally requires waiting for the wafer box to be loaded into the machine, and scanning the number of wafers in the wafer box when it is opened, and then feeding back to the user interface, and selecting the processing process recipe for the loaded wafer to create a wafer processing workflow, and finally processing through the machine according to the created workflow.

[0003] However, this type of mapping scheduling method still cannot meet the situation of delayed wafer scanning, that is, if you still have to wait until the wafer is scanned before selecting the recipe, it will cause extra time waste, making the wafer processing efficiency lower. Summary of the invention

[0004] The present invention provides a secondary Mapping scheduling method and system for a wafer processing process to overcome the above technical problems.

[0005] In order to achieve the above object, the technical solution of the present invention is:

[0006] A secondary mapping scheduling method for a wafer processing system specifically comprises the following steps:

[0007] S1: obtaining one or more wafer processing process recipes for wafer processing;

[0008] S2: Obtaining process parameters of each wafer processing process recipe according to the wafer processing process recipe, storing them in a preset host computer, and obtaining a process recipe sequence table;

[0009] S3: Encode the location of the wafer box slot layer on the wafer box rack to obtain a wafer slot sequence table of each wafer sub-layer;

[0010] According to wafer processing requirements, a virtual matching sequence table is obtained;

[0011] The virtual matching sequence table is used to characterize the virtual matching relationship between each wafer sub-layer in the wafer slot sequence table and the wafer processing process recipe in the process recipe sequence table;

[0012] S4: After obtaining the virtual matching sequence table, the wafer box is loaded onto the box opener through the robot to realize a mapping scheduling for wafer processing;

[0013] S5: Detect each wafer sub-layer of the wafer box loaded onto the box opener to obtain a coded wafer layer sequence;

[0014] The coded wafer layer sequence is used to characterize a wafer sub-layer sequence having a wafer to be processed;

[0015] Based on the constructed wafer correction strategy, the matching sequence of the wafer to be processed is obtained according to the coded wafer layer sequence and the virtual matching sequence table;

[0016] S6: Call the process parameters of the wafer processing process recipe saved in the preset host computer, configure the transfer mapping relationship between the existing wafer box and the wafer processing process support mechanism according to the matching sequence of the wafer to be processed, and execute the processing of the wafer in the wafer sub-layer based on the transfer mapping relationship to realize the secondary mapping scheduling of the wafer processing.

[0017] Furthermore, in S3, the method for virtually matching the wafer processing process recipes for each wafer sub-layer of the wafer box according to the wafer processing requirements is as follows:

[0018] S31: According to the bottom-up coding rule, position coding is performed on each wafer sub-layer in the wafer box of the wafer to be processed to obtain a wafer slot sequence table;

[0019] S32: Before loading the wafer box onto the box opener by the robot, a random or directional relationship mapping is performed with each wafer sub-layer in the wafer Slot sequence table according to one or more wafer processing process recipes in the process recipe sequence table to obtain a mapping relationship table between wafer sub-layers and wafer processing process recipes, i.e., a virtual matching sequence table.

[0020] Furthermore, the wafer correction strategy constructed in S5 is specifically:

[0021] Confirm whether the coded wafer layer sequence in the wafer box loaded on the box opener is exactly the same as the wafer slot of each wafer sub-layer in the virtual matching sequence table;

[0022] If it is confirmed that they are exactly the same, the encoded wafer layer sequence is used as the wafer processing layer, and the processing process recipe of the wafer sub-layer virtual matching corresponding to the virtual matching sequence table is called as the execution process recipe to obtain the matching sequence to be processed by the wafer;

[0023] Otherwise, according to the encoded wafer layer sequence, the processing recipe of the wafer sub-layer corresponding to the virtual matching sequence table is called as the execution process recipe;

[0024] The wafer sub-layer in the encoded wafer layer sequence that is different from the virtual matching sequence table is taken as the mismatched wafer processing layer, and the process recipe sequence table is called to manually edit and re-match the wafer processing process recipe of the mismatched wafer processing layer to obtain the matching sequence for the wafer to be processed.

[0025] A secondary mapping scheduling system for a wafer processing system, comprising a recipe editing module, a configuration management module, a position encoding module, a virtual matching module, a wafer box loading module, a wafer detection module, a wafer transfer mapping module and a wafer matching correction module;

[0026] The recipe editing module is used to set one or more wafer processing process recipes for wafer processing;

[0027] The configuration management module is used to call the process parameters of the wafer processing process recipe according to the wafer processing process recipe to obtain the process recipe sequence table, and store it in a preset host computer for storage;

[0028] The position encoding module is used to encode the position of the Slot layer of the wafer box on the wafer box rack to obtain the wafer Slot sequence table of each wafer sub-layer;

[0029] The virtual matching module is used to obtain a virtual matching sequence table for characterizing the virtual matching relationship between each wafer sub-layer in the wafer slot sequence table and the wafer processing process recipe in the process recipe sequence table according to the wafer processing requirements;

[0030] The wafer box loading module is used to load the wafer box onto the box opener by calling the robot after obtaining the virtual matching sequence table;

[0031] The wafer detection module is used to detect each wafer sub-layer of the wafer box loaded on the box opener machine, and obtain a coded wafer layer sequence corresponding to the wafer to be processed;

[0032] The wafer matching correction module is used to construct a wafer correction strategy, and obtain a matching sequence for wafer processing according to the coded wafer layer sequence and the virtual matching sequence table, and transmit it to the wafer transfer mapping module;

[0033] The wafer transfer mapping module is used to call the process parameters of the wafer processing process recipe saved in the preset host computer, configure the transfer mapping relationship between the existing wafer box and the wafer processing process support mechanism according to the matching sequence of the wafer to be processed, and perform processing on the wafer in the wafer sub-layer based on the transfer mapping relationship.

[0034] Furthermore, it also includes a manual editing module.

[0035] Used to confirm that the coded wafer layer sequence in the wafer box loaded on the box opener is not exactly the same as the wafer slots of each wafer sub-layer in the virtual matching sequence table;

[0036] The wafer sub-layer of the wafer to be processed that does not correspond to the same wafer in the virtual matching sequence table is used as an incorrectly matched wafer processing layer, and the process recipe sequence table is called to manually edit and re-match the wafer processing process recipe of the incorrectly matched wafer processing layer to obtain a matching sequence for the wafer to be processed;

[0037] It is also used to manually edit the correspondence between the positions of the wafer box and the wafer processing process support mechanism.

[0038] Beneficial effect: The present invention provides a secondary Mapping scheduling method and system for a wafer processing process, which performs virtual matching of wafer processing process recipes on each wafer sub-layer of a wafer box, and loads the wafer box onto a box opener after obtaining a virtual matching sequence table, and then obtains data information of the wafer box loaded into the machine and provided with wafers to be processed, and obtains a matching sequence for wafer processing according to the output of a wafer detection module and a virtual matching sequence table in combination with a constructed wafer correction strategy; solves the problem of having to wait for the wafer to be scanned before selecting a recipe, which causes extra time waste, and greatly improves wafer processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1 It is a flow chart of the secondary Mapping scheduling method of the wafer processing process of the present invention;

[0041] Figure 2 Schematic diagram of the secondary mapping scheduling system for the wafer processing process in this embodiment. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] This embodiment provides a secondary mapping scheduling method for a wafer processing system, wherein the scheduling method involves a wafer box rack, a robot, a box opener, a wafer box, and a wafer processing process support mechanism in the wafer processing system, such as Figure 1 As shown, the specific steps include:

[0044] S1: obtaining one or more wafer processing process recipes for wafer processing;

[0045] S2: Obtaining process parameters of each wafer processing process recipe according to the wafer processing process recipe, storing them in a preset host computer, and obtaining a process recipe sequence table;

[0046] S3: Encode the location of the wafer box slot layer on the wafer box rack to obtain a wafer slot sequence table of each wafer sub-layer;

[0047] According to wafer processing requirements, a virtual matching sequence table is obtained;

[0048] The virtual matching sequence table is used to characterize the virtual matching relationship between each wafer sub-layer in the wafer slot sequence table and the wafer processing process recipe in the process recipe sequence table.

[0049] Specifically, the method for virtually matching the wafer processing process recipes for each wafer sub-layer of the wafer box according to the wafer processing requirements in S3 is as follows:

[0050] S31: According to the bottom-up coding rule, position coding is performed on each wafer sub-layer in the wafer box of the wafer to be processed to obtain a wafer slot sequence table;

[0051] S32: before loading the wafer box onto the box opener through the robot, a random or directional relationship mapping is performed with each wafer sub-layer in the wafer slot sequence table according to one or more wafer processing process recipes in the process recipe sequence table, to obtain a mapping relationship table between the wafer sub-layer and the wafer processing process recipe, i.e., a virtual matching sequence table;

[0052] For example, if there are seven wafer processing recipes in the process recipe sequence table: recipe 1, recipe 2, recipe 3, ..., recipe 7; the wafer sub-layers in the wafer slot sequence table are coded from bottom to top as Slot1, Slot2, Slot3, Slot4, Slot5, ..., Slot25; and based on the wafer slot sequence table, the manual editing module is called to perform random or directional relationship mapping on each wafer sub-layer in the wafer slot sequence table to obtain a virtual matching sequence table, as shown in Table 1:

[0053] Table 1. Virtual matching sequence list

[0054] Wafer Select Recipe Recipe List Slot.25 Recipe 1 Recipe 1 S1ot.24 Recipe 1 Recipe 2 S1ot.23 Recipe 1 Recipe 3 S1ot.22 Recipe 1 Recipe 4 Slot.21 Recipe 2 Recipe 5 Slot.20 Recipe 2 Recipe 6 Slot.19 Recipe 4 Recipe 7 Slot.18 S1ot.17 Recipe 4 S1ot.16 S1ot.15 Recipe 4 Slot.14 Slot.13 Slot.12 Slot.11 Recipe 4 S1ot.10 S1ot.9 Recipe 7 Slot.8 Slot.7 Slot.6 Recipe 7 Slot.5 Slot.4 S1ot.3 Recipe 7 S1ot.2 Slot.1

[0055] S4: After obtaining the virtual matching sequence table, the wafer box is loaded onto the box opener by calling the robot to realize a mapping scheduling for wafer processing;

[0056] S5: Detect each wafer sub-layer of the wafer box loaded onto the box opener to obtain a coded wafer layer sequence; the coded wafer layer sequence is used to characterize a wafer sub-layer sequence with wafers to be processed;

[0057] Based on the constructed wafer correction strategy, the matching sequence of the wafer to be processed is obtained according to the coded wafer layer sequence and the virtual matching sequence table;

[0058] The wafer correction strategy constructed is specifically as follows:

[0059] The wafer correction strategy constructed in S5 is specifically:

[0060] Confirm whether the coded wafer layer sequence in the wafer box loaded on the box opener is exactly the same as the wafer slot of each wafer sub-layer in the virtual matching sequence table;

[0061] If it is confirmed that they are exactly the same, the encoded wafer layer sequence is used as the wafer processing layer, and the processing process recipe of the wafer sub-layer virtual matching corresponding to the virtual matching sequence table is called as the execution process recipe to obtain the matching sequence to be processed by the wafer;

[0062] Otherwise, according to the encoded wafer layer sequence, the processing recipe of the wafer sub-layer corresponding to the virtual matching sequence table is called as the execution process recipe;

[0063] The wafer sub-layer in the encoded wafer layer sequence that is different from the virtual matching sequence table is taken as the wrong matching wafer processing layer, and the process recipe sequence table is called to manually edit and re-match the wafer processing process recipe of the wrong matching wafer processing layer to obtain the matching sequence for the wafer to be processed;

[0064] For example, if it is confirmed that the coded wafer layer sequence of the wafer to be processed loaded into the wafer box on the box opener is not exactly the same as the wafer Slot of each wafer sub-layer in the virtual matching sequence table, the two results will be taken as the union. For example, the recipe wafer sub-layers issued by manually editing the virtual matching sequence table are Slot1, Slot2, Slot3 and Slot4, and the wafer sub-layer of the wafer to be processed is the scanning result of the coded wafer layer sequence: Slot2, Slot4, Slot5 and Slot6, then the obtained matching sequence result of the wafer to be processed is [Slot2, Slot4]; and the process recipe sequence table is called to manually edit and re-match the matching wafer processing layer with the matching wafer processing process recipe, that is, Slot5 and Slot6 are corrected to obtain the final matching sequence of the wafer to be processed;

[0065] S6: Call the process parameters of the wafer processing process recipe saved in the preset host computer, configure the transfer mapping relationship between the existing wafer box and the wafer processing process support mechanism according to the matching sequence of the wafer to be processed, and execute the processing of the wafer in the wafer sub-layer based on the transfer mapping relationship to realize the secondary mapping scheduling of the wafer processing.

[0066] In this embodiment, a set of wafer metadata with a recipe is obtained based on the final matching result, i.e., the matching sequence of the wafers to be processed. This data is sent to the factory side using the SEMI protocol, and the start method of the scheduling program is called at the same time. The scheduling program calls the wafer fetching method according to the matching result, and the equipment starts running and starts working from the bottom-level wafer Slot in the matching sequence results of the wafers to be processed to perform wafer processing. The start method of the scheduling program and the calling of the wafer fetching method are both existing publicly known technical means, which will not be elaborated here.

[0067] A secondary mapping scheduling system for wafer processing system, such as Figure 2 As shown, it includes a recipe editing module, a configuration management module, a position encoding module, a virtual matching module, a wafer box loading module, a wafer detection module, a wafer transfer mapping module and a wafer matching correction module;

[0068] The recipe editing module is used to set one or more wafer processing process recipes for wafer processing;

[0069] The configuration management module is used to call the process parameters of the wafer processing process recipe according to the wafer processing process recipe to obtain the process recipe sequence table, and store it in a preset host computer for storage;

[0070] The position encoding module is used to encode the position of the Slot layer of the wafer box on the wafer box rack to obtain the wafer Slot sequence table of each wafer sub-layer;

[0071] The virtual matching module is used to obtain a virtual matching sequence table for characterizing the virtual matching relationship between each wafer sub-layer in the wafer slot sequence table and the wafer processing process recipe in the process recipe sequence table according to the wafer processing requirements;

[0072] The wafer box loading module is used to load the wafer box onto the box opener by calling the robot after obtaining the virtual matching sequence table;

[0073] The wafer detection module is used to detect each wafer sub-layer of the wafer box loaded on the box opener machine, and obtain a coded wafer layer sequence corresponding to the wafer to be processed;

[0074] The wafer matching correction module is used to construct a wafer correction strategy, and obtain a matching sequence for wafer processing according to the coded wafer layer sequence and the virtual matching sequence table, and transmit it to the wafer transfer mapping module;

[0075] The wafer transfer mapping module is used to call the process parameters of the wafer processing process recipe saved in the preset host computer, configure the transfer mapping relationship between the existing wafer box and the wafer processing process support mechanism according to the matching sequence of the wafer to be processed, and perform processing on the wafer in the wafer sub-layer based on the transfer mapping relationship.

[0076] In a specific embodiment, a manual editing module is also included.

[0077] Used to confirm that the coded wafer layer sequence in the wafer box loaded on the box opener is not exactly the same as the wafer slots of each wafer sub-layer in the virtual matching sequence table;

[0078] The wafer sub-layer of the wafer to be processed that does not correspond to the same wafer in the virtual matching sequence table is used as an incorrectly matched wafer processing layer, and the process recipe sequence table is called to manually edit and re-match the wafer processing process recipe of the incorrectly matched wafer processing layer to obtain a matching sequence for the wafer to be processed;

[0079] It is also used to manually edit the correspondence between the positions of the wafer box and the wafer processing process support mechanism.

[0080] This embodiment performs virtual matching of wafer processing process recipes for each wafer sub-layer of the wafer box, and loads the wafer box into a machine for wafer processing after obtaining the virtual matching sequence table, and then obtains data information of the wafer box loaded into the machine and provided with wafers to be processed, and obtains the matching sequence for wafer processing according to the output of the wafer detection module and the virtual matching sequence table in combination with the constructed wafer correction strategy; this solves the current problem of having to wait for the wafer to be scanned before selecting a recipe, which causes extra time waste, and greatly improves the wafer processing efficiency.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A secondary mapping scheduling method for a wafer processing system, characterized in that: The specific steps include: S1: obtaining one or more wafer processing process recipes for wafer processing; S2: Obtaining process parameters of each wafer processing process recipe according to the wafer processing process recipe, storing them in a preset host computer, and obtaining a process recipe sequence table; S3: Encode the location of the slot layer of the wafer box on the wafer box rack to obtain a wafer slot sequence table of each wafer sub-layer; According to wafer processing requirements, a virtual matching sequence table is obtained; The virtual matching sequence table is used to characterize the virtual matching relationship between each wafer sub-layer in the wafer slot sequence table and the wafer processing process recipe in the process recipe sequence table; S4: After obtaining the virtual matching sequence table, the wafer box is loaded onto the box opener through the robot to realize a mapping scheduling for wafer processing; S5: Detect each wafer sub-layer of the wafer box loaded onto the box opener to obtain a coded wafer layer sequence; The coded wafer layer sequence is used to characterize a wafer sub-layer sequence having a wafer to be processed; Based on the constructed wafer correction strategy, the matching sequence of the wafer to be processed is obtained according to the coded wafer layer sequence and the virtual matching sequence table; S6: Call the process parameters of the wafer processing process recipe saved in the preset host computer, configure the transfer mapping relationship between the existing wafer box and the wafer processing process support mechanism according to the matching sequence of the wafer to be processed, and execute the processing of the wafer in the wafer sub-layer based on the transfer mapping relationship to realize the secondary mapping scheduling of the wafer processing.

2. The secondary mapping scheduling method for a wafer processing system according to claim 1, characterized in that: In S3, the method for virtually matching the wafer processing process recipes for each wafer sub-layer of the wafer box according to the wafer processing requirements is as follows: S31: According to the bottom-up coding rule, position coding is performed on each wafer sub-layer in the wafer box of the wafer to be processed to obtain a wafer slot sequence table; S32: Before loading the wafer box onto the box opener by the robot, a random or directional relationship mapping is performed with each wafer sub-layer in the wafer Slot sequence table according to one or more wafer processing process recipes in the process recipe sequence table to obtain a mapping relationship table between wafer sub-layers and wafer processing process recipes, i.e., a virtual matching sequence table.

3. The secondary mapping scheduling method for a wafer processing system according to claim 2, characterized in that: The wafer correction strategy constructed in S5 is specifically: Confirm whether the coded wafer layer sequence in the wafer box loaded on the box opener is exactly the same as the wafer slot of each wafer sub-layer in the virtual matching sequence table; If it is confirmed that they are exactly the same, the encoded wafer layer sequence is used as the wafer processing layer, and the processing process recipe of the wafer sub-layer virtual matching corresponding to the virtual matching sequence table is called as the execution process recipe to obtain the matching sequence to be processed by the wafer; Otherwise, according to the encoded wafer layer sequence, the processing recipe of the wafer sub-layer corresponding to the virtual matching sequence table is called as the execution process recipe; The wafer sub-layer in the encoded wafer layer sequence that is different from the virtual matching sequence table is taken as the mismatched wafer processing layer, and the process recipe sequence table is called to manually edit and re-match the wafer processing process recipe of the mismatched wafer processing layer to obtain the matching sequence for the wafer to be processed.

4. A scheduling system based on the secondary mapping scheduling method of the wafer processing system according to any one of claims 1 to 3, characterized in that: It includes a recipe editing module, a configuration management module, a position encoding module, a virtual matching module, a wafer box loading module, a wafer detection module, a wafer transfer mapping module and a wafer matching correction module; The recipe editing module is used to set one or more wafer processing process recipes for wafer processing; The configuration management module is used to call the process parameters of the wafer processing process recipe according to the wafer processing process recipe to obtain the process recipe sequence table, and store it in a preset host computer for storage; The position encoding module is used to encode the position of the Slot layer of the wafer box on the wafer box rack to obtain the wafer Slot sequence table of each wafer sub-layer; The virtual matching module is used to obtain a virtual matching sequence table for characterizing the virtual matching relationship between each wafer sub-layer in the wafer slot sequence table and the wafer processing process recipe in the process recipe sequence table according to the wafer processing requirements; The wafer box loading module is used to load the wafer box onto the box opener by calling the robot after obtaining the virtual matching sequence table; The wafer detection module is used to detect each wafer sub-layer of the wafer box loaded on the box opener machine, and obtain a coded wafer layer sequence corresponding to the wafer to be processed; The wafer matching correction module is used to construct a wafer correction strategy, and obtain a matching sequence for wafer processing according to the coded wafer layer sequence and the virtual matching sequence table, and transmit it to the wafer transfer mapping module; The wafer transfer mapping module is used to call the process parameters of the wafer processing process recipe saved in the preset host computer, configure the transfer mapping relationship between the existing wafer box and the wafer processing process support mechanism according to the matching sequence of the wafer to be processed, and perform processing on the wafer in the wafer sub-layer based on the transfer mapping relationship.

5. The secondary mapping scheduling system for a wafer processing system according to claim 4, characterized in that: Also includes manual editing modules, Used to confirm that the coded wafer layer sequence in the wafer box loaded on the box opener is not exactly the same as the wafer slots of each wafer sub-layer in the virtual matching sequence table; The wafer sub-layer of the wafer to be processed that does not correspond to the same wafer in the virtual matching sequence table is used as an incorrectly matched wafer processing layer, and the process recipe sequence table is called to manually edit and re-match the wafer processing process recipe of the incorrectly matched wafer processing layer to obtain a matching sequence for the wafer to be processed; It is also used to manually edit the correspondence between the positions of the wafer box and the wafer processing process support mechanism.

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