Shift register circuit and control method thereof, gate drive circuit and display device

Abstract

The invention provides a shift register circuit and a control method thereof, a gate drive circuit and a display device, and the shift register circuit comprises an input sub-circuit which inputs an input signal of an effective level to a pull-up node based on a signal of an input end; the pull-up sub-circuit is used for electrically connecting a first clock signal end with the output end based on the potential of a pull-up node; the first pull-down control sub-circuit is electrically connected to a second clock signal end and a first pull-down node and inputs a signal of an effective level into the first pull-down node based on a signal of the second clock signal end; and the first pull-down sub-circuit is used for electrically connecting a first power supply signal end with a first pull-down node based on the potential of the pull-up node, and the signal of the second clock signal end is a signal of which the effective level is delayed by at least one H compared with the effective level of the signal of the first clock signal end. According to the embodiment of the invention, the first pull-down control sub-circuit and the first pull-down sub-circuit can be prevented from being switched on at the same time, and the transistor on the branch circuit is protected from being burnt.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register circuit and a control method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the advancement of display technology, high-resolution and narrow-frame display panels have become a development trend. For this reason, a gate driver on array (GOA) technology has emerged to scan pixel units during display. GOA technology replaces external driver chips and has the advantages of low cost, fewer processes, and high production capacity. Summary of the invention

[0003] In order to solve at least one of the above problems, the present disclosure provides a shift register circuit according to a first aspect, comprising:

[0004] an input subcircuit, electrically connected to the input terminal and the pull-up node, configured to input an input signal of a valid level to the pull-up node based on a signal at the input terminal;

[0005] a pull-up sub-circuit electrically connected to the pull-up node, the first clock signal terminal and the output terminal, and configured to electrically connect the first clock signal terminal to the output terminal based on the potential of the pull-up node;

[0006] A first pull-down control subcircuit, electrically connected to the second clock signal terminal and the first pull-down node, configured to input a signal of a valid level into the first pull-down node based on a signal at the second clock signal terminal; and

[0007] a first pull-down subcircuit electrically connected to the first pull-down node, the first power signal terminal and the pull-up node, and configured to electrically connect the first power signal terminal to the first pull-down node based on the potential of the pull-up node,

[0008] The signal at the second clock signal end is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the first clock signal end, and H represents the time for the signal at the output end to scan a row of pixels.

[0009] Optionally, the shift register circuit further includes:

[0010] a second pull-down control subcircuit electrically connected to the third clock signal terminal and the second pull-down node, configured to input a signal of a valid level into the second pull-down node based on a signal at the third clock signal terminal; and

[0011] The second pull-down sub-circuit is electrically connected to the second pull-down node, the first power signal terminal and the pull-up node, and is configured to electrically connect the first power signal terminal to the second pull-down node based on the potential of the pull-up node.

[0012] The signal at the third clock signal end is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the second clock signal end.

[0013] Optionally, the first pull-down control subcircuit comprises: a 1A transistor, a first electrode and a control electrode of the 1A transistor being electrically connected to the second clock signal terminal, and a second electrode being electrically connected to the first pull-down node; and

[0014] The first pull-down sub-circuit includes: a 2A transistor, a first electrode of the 2A transistor is electrically connected to the first pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

[0015] and / or

[0016] The second pull-down control subcircuit comprises: a 1B transistor, a first electrode and a control electrode of the 1B transistor being electrically connected to the third clock signal terminal, and a second electrode being electrically connected to the second pull-down node; and

[0017] The second pull-down sub-circuit includes: a 2B transistor, a first electrode of the 2B transistor is electrically connected to the second pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

[0018] Optionally, the first pull-down control subcircuit comprises: a 1A transistor, a first electrode of the 1A transistor being electrically connected to the second power signal terminal, a second electrode being electrically connected to the first pull-down node, and a control electrode being electrically connected to the second clock signal terminal; and

[0019] The first pull-down sub-circuit includes: a 2A transistor, a first electrode of the 2A transistor is electrically connected to the first pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

[0020] and / or

[0021] The second pull-down control subcircuit comprises: a 1B transistor, a first electrode of the 1B transistor being electrically connected to the second power signal terminal, a second electrode being electrically connected to the second pull-down node, and a control electrode being electrically connected to the third clock signal terminal; and

[0022] The second pull-down sub-circuit includes: a 2B transistor, a first electrode of the 2B transistor is electrically connected to the second pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

[0023] Optionally, the shift register circuit further includes:

[0024] a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the second power signal terminal, and a second electrode of the first capacitor is electrically connected to the first pull-down node, and / or

[0025] A second capacitor, wherein a first electrode of the second capacitor is electrically connected to the second power signal terminal, and a second electrode of the second capacitor is electrically connected to the second pull-down node.

[0026] Optionally, the shift register circuit further includes:

[0027] A 3A transistor, wherein a first electrode of the 3A transistor is electrically connected to the second power signal terminal, a second electrode is electrically connected to the first pull-down node, and a control electrode is electrically connected to the first control terminal; and

[0028] A 3B transistor, wherein a first electrode of the 3B transistor is electrically connected to the second power signal terminal, a second electrode is electrically connected to the second pull-down node, and a control electrode is electrically connected to the first control terminal.

[0029] Optionally, the first pull-down control subcircuit is electrically connected to the second clock signal terminal, the third clock signal terminal and the first pull-down node, and is configured to input a signal of a valid level into the first pull-down node based on a signal of the second clock signal terminal, and to input a signal of a valid level into the first pull-down node based on a signal of the third clock signal terminal,

[0030] The signal at the third clock signal end is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the second clock signal end, and H represents the time for the signal at the output end to scan a row of pixels.

[0031] Optionally, the first lower control subcircuit comprises: a 1A transistor and a 1B transistor, wherein the first electrode of the 1A transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the first pull-down node, and the control electrode is electrically connected to the second clock signal terminal; the first electrode of the 1B transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the first pull-down node, and the control electrode is electrically connected to the third clock signal terminal;

[0032] The first pull-down sub-circuit includes: a second transistor, a first electrode of the second transistor is electrically connected to the first pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

[0033] Optionally, the shift register circuit further includes:

[0034] a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the second power signal terminal, and a second electrode of the first capacitor is electrically connected to the first pull-down node;

[0035] A third transistor, wherein a first electrode of the third transistor is electrically connected to the second power signal terminal, a second electrode of the third transistor is electrically connected to the first pull-down node, and a control electrode of the third transistor is electrically connected to the first control terminal.

[0036] Optionally, the input sub-circuit comprises a fifth transistor, wherein a first electrode and a control electrode of the fifth transistor are electrically connected to the input terminal, and a second electrode is electrically connected to the pull-up node;

[0037] The pull-up sub-circuit includes a sixth transistor and a third capacitor, wherein the first electrode of the sixth transistor is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the output terminal, the control electrode is electrically connected to the pull-up node, the first electrode of the third capacitor is electrically connected to the pull-up node, and the second electrode is electrically connected to the output terminal.

[0038] Optionally, the shift register circuit further includes: a carry output subcircuit,

[0039] The carry output subcircuit includes a seventh transistor, a first electrode of the seventh transistor is electrically connected to the first clock signal terminal, a second electrode is electrically connected to the carry output terminal, and a control electrode is electrically connected to the pull-up node.

[0040] Optionally, the shift register circuit further includes:

[0041] a first noise reduction subcircuit, electrically connected to the pull-up node, the first pull-down node, and the first power signal terminal, configured to electrically connect the pull-up node to the first power signal terminal based on a signal of the first pull-down node;

[0042] The second noise reduction sub-circuit is electrically connected to the pull-up node, the second pull-down node and the first power signal terminal, and is configured to electrically connect the pull-up node to the first power signal terminal based on a signal of the second pull-down node.

[0043] The second aspect of the present disclosure provides a gate driving circuit, comprising: N cascaded shift register circuits as described above, wherein

[0044] The input end of the n-th stage shift register circuit is electrically connected to the output end or the carry output end of another stage shift register circuit;

[0045] The input end of the first-stage shift register circuit is electrically connected to the start signal end of the gate drive circuit.

[0046] N is a positive integer greater than or equal to 2, and n is a positive integer greater than 1 and less than or equal to N.

[0047] Optionally, the shift register circuit includes a second pull-down control subcircuit, the second pull-down control subcircuit is electrically connected to the third clock signal terminal and the second pull-down node, and is configured to input a signal of an effective level into the second pull-down node based on a signal of the third clock signal terminal, wherein the signal of the third clock signal terminal is a signal whose effective level is delayed by at least 1 H than the effective level of the signal of the second clock signal terminal.

[0048] The first clock signal terminal of the 4m-3 stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line.

[0049] The first clock signal terminal of the 4m-2 stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line.

[0050] The first clock signal terminal of the 4m-1th stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line.

[0051] The first clock signal terminal of the 4m-stage shift register circuit is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line.

[0052] Wherein, m is a positive integer greater than or equal to 1.

[0053] A third aspect of the present disclosure provides a display device, comprising the gate driving circuit as described above.

[0054] A fourth aspect of the present disclosure provides a control method using the shift register circuit as described above, comprising:

[0055] In the first stage, a signal of a valid level is provided to the input terminal, and the input subcircuit transmits the input signal of the valid level to the pull-up node to pull up the potential of the pull-up node;

[0056] In the second phase, the pull-up sub-circuit transmits the signal of the first clock signal terminal to the output terminal under the control of the potential of the pull-up node.

[0057] The beneficial effects of the present disclosure are as follows:

[0058] In response to the existing problems, the present disclosure develops a shift register circuit and a control method thereof, a gate drive circuit, and a display device. By providing a first pull-down control subcircuit electrically connected to a second clock signal terminal, and the effective level of the signal at the second clock signal terminal is delayed compared to the effective level of the first clock signal of the pull-up subcircuit, the first pull-down control subcircuit and the first pull-down subcircuit can be prevented from being turned on at the same time, thereby protecting the transistors on the branch from burning out, improving the high-voltage stability of the product, and having broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0060] Figure 1 A schematic circuit diagram of a shift register circuit according to the related art is shown;

[0061] Figure 2 Show according to Figure 1 Timing diagrams of key ports or signal lines in the circuit shown;

[0062] Figure 3 A schematic structural block diagram of a shift register circuit according to an embodiment of the present disclosure is shown;

[0063] Figure 4 A circuit schematic diagram of a shift register circuit according to an embodiment of the present disclosure is shown;

[0064] Figure 5 Show Figure 4 The timing diagram of the key ports of the shift register circuit shown;

[0065] Figure 6 Show according to Figure 4 The timing simulation diagram of the key ports of the shift register circuit shown;

[0066] Figure 7 Show Figure 4 A simulation diagram of potential change after the first pull-down node continues to work in the embodiment of the present invention;

[0067] Figure 8 A circuit schematic diagram of a shift register circuit according to another embodiment of the present disclosure is shown;

[0068] Fig. 9 Show Figure 8 The timing diagram of the key ports of the shift register circuit shown;

[0069] Figures 10 to 12 A circuit schematic diagram showing a shift register circuit according to some other embodiments of the present disclosure;

[0070] Fig.13 A schematic diagram showing a gate driving circuit according to an embodiment of the present disclosure;

[0071] Fig.14 Show Fig.13 The signal lines and port timing diagram in the gate drive circuit shown;

[0072] Fig.15 A schematic diagram showing a display device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0073] In order to more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present disclosure.

[0074] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantitative restrictions, but indicate that there is at least one. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0075] The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices of the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of this article, because all transistors are N-type transistors, in order to distinguish the source and drain of the transistor, the drain is called the first pole, the source is called the second pole, and the gate is called the control pole. When the gate inputs a high level, the source and drain are turned on, that is, the effective level represents a high level. In addition, when the gate and the source are both high levels with equal potentials, the source and drain are not turned on. It should be noted that the present disclosure is not intended to be limited to this, and the type of transistor may also be a P-type transistor. In this case, the first pole represents the source, the second pole represents the drain, and the effective level of the gate as the control pole is a low level, which will not be repeated below.

[0076] In the current shift register unit structure, transistors in the branch for controlling the pull-down nodes PD_1 and PD_2 are prone to heat up or even burn out.

[0077] Reference Figure 1 As shown in the figure, a circuit schematic diagram of a shift register unit in the related art is shown. It can be seen that the current shift register unit mainly includes an input circuit formed by a transistor T1, an output circuit formed by a capacitor C1 and a transistor T3, a transistor T5A and a transistor T6A form a branch for controlling the potential of a pull-down node PD_1, and a transistor T6B and a transistor T6B form another branch for controlling the potential of a pull-down node PD_2. Of course, the shift register unit also includes transistors T2, T4 and T15 for resetting, and other transistors are used to reduce noise at each node.

[0078] Combination Figure 1 and Figure 2 As can be seen from the timing diagram, STV1 represents the signal of the input terminal Input of the first-stage shift register circuit, CLK1 to CLK4 represent the clock signals provided by the clock terminals CLK of each stage after the shift register circuit is cascaded, when the input terminal Input is connected to a high-level signal, the transistor T1 is turned on and charges the capacitor C1, increasing the potential of the pull-up node PU, and when the clock terminal CLK is connected to a high-level signal, the output terminal OUT1 outputs the high-level signal. The pull-down nodes PD1_1 and PD_2 are sequentially associated with transistors for noise reduction of each node, and when the pull-down nodes PD1_1 and PD_2 are at a high level, at least the transistors T8A and T8B are turned on and the potential of the node PU is pulled down. Therefore, during the period of charging the pull-up node PU, the pull-down nodes PD1_1 and PD_2 are controlled to be low levels by transistors T5A and transistor T6A, and transistors T6B and transistor T6B.

[0079] However, in the current circuit structure, transistor T5A and transistor T5B are transistors that work alternately, and the signal terminals VDDO and VDDE are always at a constant high level in the image frame in which they work. Taking the nth frame as an example, when the pull-up node PU is at a high level, transistor T6A is turned on, and at the same time, transistor T5A is turned on by being controlled by the high level VDDO, that is, transistor T5A and transistor T6A are turned on at the same time, and the signal terminal VDDO and the signal terminal LVGL are short-circuited. Because the signal terminal VDDO is connected to a high-level power signal and the signal terminal LVGL is connected to a low-level power signal, the current flowing through transistor T5A can reach several hundred microamperes and lasts for the refresh time of 4-8 rows of pixels. During this period, transistor T5A continues to heat up and is easily burned after running for a period of time. In particular, some display products, especially GOA circuits in electronic paper (EPO) or handwriting products require higher driving voltages. For example, the color mixing process of the color paper film in color electronic paper products requires a higher driving voltage to shorten the display refresh time, and handwriting products require high voltage to reduce the writing delay time. This makes the high voltage usually reach 35V to 40V or even higher. During the display driving process, the transistor T5A is at a greater risk of burning due to excessive current, reducing the stability and yield of the display product.

[0080] In order to solve at least one of the above problems, refer to Figure 3 As shown, an embodiment of the present disclosure provides a shift register circuit, comprising:

[0081] An input subcircuit 10, electrically connected to the input terminal and the pull-up node, configured to input an input signal of a valid level to the pull-up node based on a signal at the input terminal;

[0082] The pull-up sub-circuit 20 is electrically connected to the pull-up node PU, the first clock signal terminal CLK and the output terminal OUT1, and is configured to electrically connect the first clock signal terminal CLK to the output terminal OUT1 based on the potential of the pull-up node PU;

[0083] A first pull-down control sub-circuit 31, electrically connected to the second clock signal terminal CLKB and the first pull-down node PD_A, configured to input a valid level signal to the first pull-down node PU based on the signal of the second clock signal terminal CLKB; and

[0084] The first pull-down sub-circuit 41 is electrically connected to the first pull-down node PD_A, the first power signal terminal CLK and the pull-up node PU, and is configured to electrically connect the first power signal terminal CLK to the first pull-down node PD_A based on the potential of the pull-up node PU.

[0085] The signal at the second clock signal terminal CLKB is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the first clock signal terminal CLK, where H represents the time for the signal at the output terminal to scan a row of pixels.

[0086] In this embodiment, a first pull-down control sub-circuit electrically connected to the second clock signal terminal is provided, and the effective level of the signal at the second clock signal terminal is delayed compared to the effective level of the first clock signal of the pull-up sub-circuit, thereby preventing the first pull-down control sub-circuit and the first pull-down sub-circuit from being turned on at the same time, thereby protecting the transistors on the branch from burning out and improving the high-voltage stability of the product.

[0087] In order to explain in detail the structure and functional advantages of the shift register circuit in the embodiment of the present disclosure, a specific circuit structure is described in detail below in combination with specific examples.

[0088] In a specific embodiment, in combination Figure 4 As shown, it shows that Figure 3 The circuit diagram of a specific circuit of the structural block diagram shown may be any shift register circuit among N cascaded shift register circuits, where N is an integer greater than or equal to 2.

[0089] Reference Figure 3 and Figure 4 As shown, the shift register circuit includes an input sub-circuit 10 , a pull-up sub-circuit 20 , a first pull-down control sub-circuit 31 and a first pull-down sub-circuit 41 .

[0090] The input sub-circuit 10 is electrically connected to the input terminal Input and the pull-up node PU, and is configured to input an input signal of a valid level to the pull-up node PU based on a signal at the input terminal Input.

[0091] Specifically in this example, the input subcircuit 10 is only electrically connected to the input terminal Input and the pull-up node PU, and the input signal is the signal connected to the input terminal Input. However, those skilled in the art should understand that the present disclosure is not limited to this, and the input subcircuit 10 can also be further electrically connected to another signal terminal that is separately connected to the input signal, so that the signal connected to the input terminal Input is only used as a control signal, which is not described in detail here.

[0092] The pull-up sub-circuit 20 is electrically connected to the pull-up node PU, the first clock signal terminal CLK and the output terminal OUT, and is configured to electrically connect the first clock signal terminal CLK to the output terminal OUT based on the potential of the pull-up node PU.

[0093] The first pull-down control sub-circuit 31 is electrically connected to the second clock signal terminal CLKB and the first pull-down node PD_A, and is configured to input a signal of a valid level into the first pull-down node PD_A based on the signal of the second clock signal terminal CLKB.

[0094] The first pull-down sub-circuit 41 is electrically connected to the first pull-down node PD_A, the first power signal terminal LVGL and the pull-up node PU, and is configured to electrically connect the first power signal terminal LVGL to the first pull-down node PD_A based on the potential of the pull-up node PU.

[0095] In particular, the signal at the second clock signal terminal CLKB is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the first clock signal terminal CLK, where H represents the time for the signal at the output terminal to scan a row of pixels.

[0096] Specifically, refer to Figure 4 As shown, the first pull-down control subcircuit 31 includes a 1A transistor M1A, a first electrode and a control electrode of the 1A transistor M1A are electrically connected to the second clock signal terminal CLKB, and a second electrode is electrically connected to the first pull-down node PD_A. In this example, when the signal of the second clock signal terminal CLKB is at a high level, the 1A transistor M1A is turned on, the second clock signal terminal CLKB is electrically connected to the first pull-down node PD_A, and the high-level signal connected to the second clock signal terminal CLKB is input to the first pull-down node PD_A.

[0097] Specifically, the first pull-down sub-circuit 41 includes a 2A transistor M2A, a first electrode of the 2A transistor M2A is electrically connected to the first pull-down node PD_A, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the pull-up node PU. In this example, when the potential of the pull-up node PU is at a high level, the 2A transistor M2A is turned on, the first power signal terminal LVGL is electrically connected to the first pull-down node PD_A, and the low-level power signal connected to the first power signal terminal LVGL is input to the first pull-down node PD_A.

[0098] In particular, in the embodiment of the present disclosure, by electrically connecting the first pull-down control subcircuit 31 to the second clock signal terminal CLKB, and setting the effective level of the signal connected to the second clock signal terminal CLKB to be delayed by at least 1 H than the effective level of the signal connected to the first clock signal terminal CLK of the pull-up subcircuit 20, the time period when the signal connected to the first clock signal terminal CLK is at an effective level and the time period when the input terminal Input is at a high level before that, through the above settings, when the pull-up node PU is at a high level, the 2A transistor M2A in the first pull-down subcircuit 41 is turned on, and the 1A transistor M1A in the first pull-down control subcircuit 31 will not be turned on, thereby avoiding the large current caused by the high voltage difference between the first electrode and the second electrode of the 1A transistor M1A when the first pull-down control subcircuit and the first pull-down subcircuit are in the on state at the same time, and reducing the current of the transistor to a minimum, preventing the transistor from heating and burning, and improving the stability and yield of the shift register circuit.

[0099] It should be noted that the present application does not intend to limit the effective level delay time, and the specific number of H delays can be determined according to the application scenario of the shift register circuit. For example, when the shift register circuit scans pixel rows row by row, the delay is 1 H. If the shift register circuit drives spaced pixel rows, the delay time is increased according to the number of spaced rows.

[0100] Considering that when the first pull-down control subcircuit 31 is electrically connected to a clock signal that is not always at a high level within an image frame, if the second clock signal terminal continues to become an invalid level after becoming a valid level, the first pull-down node PD_A will float due to the 1A transistor M1A being turned off, and the potential of the first pull-down node PD_A may decrease due to the floating. However, in the period after the current shift register circuit outputs a valid level within an image frame, a high-level pull-down node is desired to reduce circuit noise.

[0101] In view of this, in the embodiment of the present disclosure, the shift register circuit further includes: a second pull-down control sub-circuit 32 and a second pull-down sub-circuit 42 .

[0102] The second pull-down control subcircuit 32 is electrically connected to the third clock signal terminal CLKC and the second pull-down node PD_B, and is configured to input a valid level signal to the second pull-down node PD_B based on the signal of the third clock signal terminal CLKC. The second pull-down subcircuit 42 is electrically connected to the second pull-down node PD_B, the first power signal terminal LVGL and the pull-up node PU, and is configured to electrically connect the first power signal terminal LVGL to the second pull-down node PD_B based on the potential of the pull-up node PU.

[0103] In particular, the signal at the third clock signal terminal is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the second clock signal terminal.

[0104] Specifically, the second pull-down control subcircuit 32 includes: a 1B transistor M1B, a first electrode and a control electrode of the 1B transistor M1B are electrically connected to the third clock signal terminal CLKC, and a second electrode is electrically connected to the second pull-down node PD_B. In this example, when the signal of the third clock signal terminal CLKC is at a high level, the 2A transistor M2A is turned on, the third clock signal terminal CLKC is electrically connected to the second pull-down node PD_B, and the high-level signal connected to the third clock signal terminal CLKC is input into the second pull-down node PD_B.

[0105] The second pull-down sub-circuit 42 includes: a 2B transistor M2B, a first electrode of the 2B transistor M2B is electrically connected to the second pull-down node PD_B, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the pull-up node PU. In this example, when the potential of the pull-up node PU is at a high level, the 2B transistor M2B is turned on, the first power signal terminal LVGL is electrically connected to the second pull-down node PD_B, the first power signal terminal LVGL is electrically connected to the second pull-down node PD_B, and the low-level power signal connected to the first power signal terminal LVGL is input to the second pull-down node PD_B.

[0106] Through the above improved structure, the second pull-down control subcircuit 32 becomes effective after the first pull-down control subcircuit 31 becomes effective, thereby avoiding the second pull-down control subcircuit 32 and the second pull-down subcircuit 42 from being turned on at the same time, and making the first pull-down control subcircuit 31 and the first pull-down subcircuit 41, as well as the second pull-down control subcircuit 32 and the second pull-down subcircuit 42 function in different time periods in an image frame, so that after the first pull-down node PD_A floats, the second pull-down node PD_B continues to provide a stable high level, ensuring that the shift register circuit has a high-level pull-down node of sufficient duration to achieve a good noise reduction effect.

[0107] Continuing with the previous example, refer to Figure 4 As shown, the input subcircuit 10 may include a fifth transistor M5, a first electrode and a control electrode of the fifth transistor M5 are electrically connected to the input terminal Input, and a second electrode is electrically connected to the pull-up node PU. When the input signal connected to the input terminal Input is at a high level, the fifth transistor M5 is turned on, and the input terminal Input is electrically connected to the pull-up node PU, so that the input signal connected to the Input is transmitted to the pull-up node PU.

[0108] Of course, the present disclosure is not limited to this. It is also possible to set the first electrode of the transistor to be electrically connected to a high-level signal terminal and use the signal of the signal terminal as an input signal. When the input terminal Input is at a high level, the input signal is transmitted to the pull-up node PU. This will not be elaborated here.

[0109] The pull-up sub-circuit 20 may include a sixth transistor M6 and a third capacitor C3, the first electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CLK, the second electrode is electrically connected to the output terminal OUT, and the control electrode is electrically connected to the pull-up node PU, the first electrode of the third capacitor C3 is electrically connected to the pull-up node PU, and the second electrode is electrically connected to the output terminal OUT.

[0110] Alternatively, refer to Figure 3 and Figure 4 As shown, the shift register circuit further includes: a carry output subcircuit 50.

[0111] The carry output subcircuit 50 includes a seventh transistor M7, a first electrode of the seventh transistor M7 is electrically connected to the first clock signal terminal CLK, a second electrode is electrically connected to the carry output terminal OUT_C, and a control electrode is electrically connected to the pull-up node PU. The output timing of the carry output terminal OUT_C ​​of the output subcircuit 50 is the same as the output timing of the output terminal OUT, and can be used for cascading with other stages of shift register circuits.

[0112] Optionally, continue to refer to Figure 3 As shown, the shift register circuit further includes: a first noise reduction sub-circuit 61. The first noise reduction sub-circuit 61 is electrically connected to the pull-up node PU, the first pull-down node PD_A and the first power signal terminal LVGL, and is configured to electrically connect the pull-up node PU to the first power signal terminal LVGL based on the signal of the first pull-down node PD_A.

[0113] Specifically, refer to Figure 4 As shown, the first noise reduction sub-circuit 61 includes an 8A transistor M8A, a first electrode of the 8A transistor M8A is electrically connected to the pull-up node PU, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the first pull-down node PD_A. When the first pull-down node PD_A is at a high level, the 8A transistor M8A is turned on, and the first power signal terminal LVGL is electrically connected to the pull-up node PU, thereby reducing the noise of the pull-up node PU.

[0114] Additionally, optionally, when the shift register circuit includes a second pull-down control sub-circuit 32 and a second pull-down sub-circuit 42, the shift register circuit may further include a second noise reduction sub-circuit 62, the second noise reduction sub-circuit 62 being electrically connected to the pull-up node PU, the second pull-down node PD_B and the first power signal terminal LVGL, and being configured to electrically connect the pull-up node PU to the first power signal terminal LVGL based on a signal of the second pull-down node PD_B.

[0115] Specifically, refer to Figure 4As shown, the second noise reduction sub-circuit 62 includes an 8B transistor M8B, a first electrode of the 8B transistor M8B is electrically connected to the pull-up node PU, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the second pull-down node PD_B. When the second pull-down node PD_B is at a high level, the 8B transistor M8B is turned on, and the first power signal terminal LVGL is electrically connected to the pull-up node PU, thereby reducing the noise of the pull-up node PU.

[0116] Optionally, refer to Figure 3 As shown, the shift register circuit further includes: a third noise reduction sub-circuit 63. The third noise reduction sub-circuit 63 is electrically connected to the first pull-down node PD_A, the first power signal terminal LVGL and the output terminal OUT, and is configured to electrically connect the output terminal OUT to the first power signal terminal LVGL based on the signal of the first pull-down node PD_A.

[0117] Specifically, refer to Figure 4 As shown, the third noise reduction sub-circuit 63 includes a 9A transistor M9A, a first electrode of the 9A transistor M9A is electrically connected to the output terminal OUT, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the first pull-down node PD_A. When the first pull-down node PD_A is at a high level, the 9A transistor M9A is turned on, and the first power signal terminal LVGL is electrically connected to the output terminal OUT, thereby reducing the noise of the output terminal OUT.

[0118] Additionally, optionally, when the shift register circuit includes a second pull-down control sub-circuit 32 and a second pull-down sub-circuit 42, the shift register circuit may further include a fourth noise reduction sub-circuit 64, the fourth noise reduction sub-circuit 54 being electrically connected to the output terminal OUT, the second pull-down node PD_B and the first power signal terminal LVGL, and being configured to electrically connect the output terminal OUT to the first power signal terminal LVGL based on a signal of the second pull-down node PD_B.

[0119] Specifically, refer to Figure 4 As shown, the fourth noise reduction sub-circuit 64 includes a 9B transistor M9B, a first electrode of the 9B transistor M9B is electrically connected to the output terminal OUT, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the second pull-down node PD_B. When the second pull-down node PD_B is at a high level, the 9B transistor M9B is turned on, and the first power signal terminal LVGL is electrically connected to the output terminal OUT, thereby reducing the noise of the output terminal OUT.

[0120] Continue to refer to Figure 4 As shown, although Figure 3 Not shown, the shift register circuit may further include a fifth noise reduction sub-circuit and a sixth noise reduction sub-circuit.

[0121] Specifically, the fifth noise reduction sub-circuit may include a 10A transistor M10A, a first electrode of the 10A transistor M10A is electrically connected to the first pull-down node PD_A, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the input terminal Input, so that when the input terminal Input is at a high level, the 10A transistor M10A is turned on, and the first power signal terminal LVGL is used to reduce the noise of the first pull-down node PD_A.

[0122] The sixth noise reduction sub-circuit may include a 10B transistor M10B, a first electrode of the 10B transistor M10B is electrically connected to the second pull-down node PD_B, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the input terminal Input, so that when the input terminal Input is at a high level, the 10B transistor M10B is turned on, and the first power signal terminal LVGL is used to reduce the noise of the second pull-down node PD_B.

[0123] Continue to refer to Figure 4 As shown, although Figure 3 Not shown, the shift register circuit may further include a seventh noise reduction sub-circuit and an eighth noise reduction sub-circuit.

[0124] Specifically, the seventh noise reduction sub-circuit may include an 11A transistor M11A, a first electrode of the 11A transistor M11A is electrically connected to, a second electrode is electrically connected to the carry output terminal OUT_C, a first power signal terminal LVGL, and a control electrode is electrically connected to the first pull-down node PD_A, so that when the first pull-down node PD_A is at a high level, the 11A transistor M11A is turned on, and the first power signal terminal LVGL is used to reduce the noise of the carry output terminal OUT_C.

[0125] The eighth noise reduction sub-circuit may include an 11B transistor M11B, a first electrode of the 11B transistor M11B is electrically connected to, a second electrode is electrically connected to the carry output terminal OUT_C, a first power signal terminal LVGL, and a control electrode is electrically connected to the second pull-down node PD_B, so that when the second pull-down node PD_B is at a high level, the 11B transistor M11B is turned on, and the first power signal terminal LVGL is used to reduce the noise of the carry output terminal OUT_C.

[0126] Optionally, the shift register circuit further includes: a first reset subcircuit 71. Figure 3 As shown, the first reset sub-circuit 71 is electrically connected to the output terminal OUT, the second power signal terminal VGL and the first reset signal terminal Reset.

[0127] Specifically, refer to Figure 4As shown, the first reset sub-circuit 71 includes a twelfth transistor M12, a first electrode of the twelfth transistor M12 is electrically connected to the output terminal OUT, a second electrode is electrically connected to the second power signal terminal VGL, and a control electrode is electrically connected to the first reset signal terminal Reset. When the first reset signal terminal Reset is connected to a signal of an effective level, the twelfth transistor M12 is turned on, and the output terminal OUT is pulled low by the signal connected to the second power signal terminal VGL. The second power signal terminal VGL can be a low-level power signal of a different level than the first power signal terminal LVGL, or can be connected to the same low-level power signal.

[0128] Optionally, the shift register circuit further includes: a second reset subcircuit 72. Figure 3 As shown, the second reset sub-circuit 72 is electrically connected to the pull-up node PU, the first power signal terminal LVGL and the second reset signal terminal T_RST1.

[0129] Reference Figure 4 As shown, the second reset sub-circuit 72 includes a thirteenth transistor M13, a first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node PU, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the second reset signal terminal T_RST1. When the second reset signal terminal T_RST1 is connected to a signal of an effective level, the thirteenth transistor M13 is turned on, and the pull-up node PU is pulled down by the signal connected to the first power signal terminal LVGL.

[0130] When the shift register circuit is used in cascade connection, the second reset signal terminal T_RST1 can be used as a global reset signal terminal to receive a global reset signal, so that all shift register circuits are reset when the signal terminal receives a signal of a valid level.

[0131] Alternatively, refer to Figure 3 As shown, if necessary, the shift register circuit may further include a third reset subcircuit 73. Figure 3 As shown, the third reset sub-circuit 73 is electrically connected to the pull-up node PU, the first power signal terminal LVGL and the third reset signal terminal PU Reset.

[0132] Reference Figure 4As shown, the third reset sub-circuit 73 includes a fourteenth transistor M14, a first electrode of the fourteenth transistor M14 is electrically connected to the pull-up node PU, a second electrode is electrically connected to the first power signal terminal LVGL, and a control electrode is electrically connected to the third reset signal terminal PU Reset. When the third reset signal terminal PU Reset is connected to a signal of an effective level, the fourteenth transistor M14 is turned on, and the pull-up node PU is pulled down using the signal connected to the first power signal terminal LVGL. Exemplarily, the signal connected to the third reset signal terminal PU Reset can be the same as the signal connected to the first reset signal terminal Reset.

[0133] In order to further understand the structure and function of the shift register circuit of the embodiment of the present disclosure, Figure 5 and Figure 6 The timing diagram shown, describes Figure 4 The circuit structure shown works in different time periods.

[0134] Figure 5 In the nth frame and the n+1th frame, n can be any positive integer greater than or equal to 1, and is intended to represent two adjacent image frames. Figure 5 As can be seen, the signals connected to the first power signal terminal LVGL and the second power signal terminal VGL are always at a low level. The input terminal Input, the first clock signal terminal CLK, the second clock signal terminal CLKB and the third clock signal terminal CLKC are sequentially changed to a valid level (a high level in this example).

[0135] At t1, refer to Figure 5 and Figure 6 As shown, the input terminal Input is connected to a high-level input signal, the fifth transistor M5 is turned on, and the potential of the pull-up node PU is pulled up by the input signal and the third capacitor C3 is charged. At the same time, because the potential of the pull-up node PU is pulled up to a high level, the 2A transistor M2A of the first pull-down sub-circuit 41 and the 2B transistor M2B of the second pull-down sub-circuit 42 are turned on, and the first power signal terminal LVGL is electrically connected to the first pull-down node PD_A and the second pull-down node PD_B, respectively, so that the potentials of the first pull-down node PD_A and the second pull-down node PD_B are pulled down.

[0136] In particular, because the second clock signal terminal CLKB and the third clock signal terminal CLKC are still at a low level, that is, at an invalid level, the 1A transistor M1A of the first pull-down control subcircuit 31 and the 2A transistor M2A of the second pull-up control subcircuit 32 are turned off, no current flows through the 1A transistor M1A and the 2A transistor M2A, and there is no risk of overcurrent burning.

[0137] Of course, the control terminals of the 10A transistor M10A as the fifth noise reduction sub-circuit and the 10B transistor M10B as the sixth noise reduction sub-circuit receive high-level input signals and are turned on, which also play a role in noise reduction for the first pull-down node PD_A and the second pull-down node PD_B.

[0138] At t2, refer to Figure 5 and Figure 6 As shown, the presence of the third capacitor C3 in the pull-up sub-circuit 20 allows it to continue charging and raise the potential of the pull-up node PU. At the same time, during this period, the first clock signal terminal CLK becomes a high level, and the turned-on sixth transistor M6 makes the first clock signal CLK electrically connected to the output terminal OUT, and the output terminal OUT outputs a high-level signal.

[0139] During this period, because the potential of the pull-up node PU is still at a high level, the 2A transistor M2A of the first pull-down sub-circuit 41 and the 2B transistor M2B of the second pull-down sub-circuit 42 are still turned on, and the first power signal terminal LVGL is electrically connected to the first pull-down node PD_A and the second pull-down node PD_B, respectively, so that the potential of the first pull-down node PD_A and the second pull-down node PD_B remains at a low level.

[0140] In particular, because the second clock signal terminal CLKB and the third clock signal terminal CLKC are still at a low level, that is, at an invalid level, the 1A transistor M1A of the first pull-down control subcircuit 31 and the 2A transistor M2A of the second pull-up control subcircuit 32 are still in the off state, no current passes through the 1A transistor M1A and the 2A transistor M2A, and there is no risk of overcurrent burning.

[0141] At the same time, in this stage, the first pull-down node PD_A and the second pull-down node PD_B are at a low level, the 9A transistor M9A and the 9B transistor M9B are turned off to reduce the noise of the output terminal OUT, and the 11A transistor M11A and the 11B transistor M11B are turned off to reduce the noise of the carry output terminal OUT_C. Of course, because the input terminal Input becomes a low level, the 10A transistor M10A and the 10B transistor M10B are turned off, and the potential of the pull-up node PU will not be pulled down.

[0142] At t3, refer to Figure 5 and Figure 6 As shown, at this time, the second clock signal terminal CLKB becomes a high level, and the 1A transistor M1A of the first pull-down control sub-circuit 31 is turned on, electrically connecting the second clock signal terminal CLKB to the first pull-down node PD_A, and transmitting the high level to the first pull-down node PD_A.

[0143] In particular, at this time, the high level of the second clock signal terminal CLKB occurs after the effective level of the first clock signal terminal CLK, the pull-up node PU has been pulled down by the signal of the first power signal terminal LVGL due to the 8A transistor M8A of the turned-on first noise reduction sub-circuit 61, and the 2A transistor M2A of the first pull-down sub-circuit 41 is turned off.

[0144] That is to say, even if the second clock signal terminal CLKB becomes a high level during the period t3 based on the need for noise reduction, because the 2A transistor M2A in the first pull-down sub-circuit 41 is in the off state, there is no situation where the 1A transistor M1A and the 2A transistor M2A are turned on at the same time, so there is no risk of overcurrent burning.

[0145] It should also be noted that, because the high level period of the third clock signal terminal CLKC has not yet arrived, Figure 4 It can be seen that the third clock signal terminal CLKC is the only source of the high level of the second pull-down node PD_B, and thus the rising edge of the second pull-down node PD_B has not arrived yet.

[0146] At t4, refer to Figure 5 and Figure 6 As shown, at this time, the third clock signal terminal CLKC becomes a high level, and the 1B transistor M1B of the second pull-down control sub-circuit 32 is turned on, electrically connecting the third clock signal terminal CLKC to the second pull-down node PD_B, and transmitting the high level to the second pull-down node PD_B.

[0147] It is worth mentioning that from Figure 6 As can be seen from the simulation diagram, the second clock signal terminal CLKB is used as a clock signal. If the cascade factor is taken into account, the high level period is only one t3 period. In the t4 period, the second clock signal terminal CLKB becomes low level, and the first pull-down node PD_A floats, and the level begins to decrease. Under the control of the third clock signal terminal CLKC, the second pull-down control subcircuit 32 continues to provide a high potential pull-down node, so that the noise reduction control potential can be provided for a long enough time within an image frame.

[0148] It should be noted that reference Figure 5 As shown, in each image frame, the second clock signal terminal CLB and the third clock signal terminal CLKC are successively changed to high level, that is, in the embodiment of the present disclosure, the first pull-down control subcircuit 31 and the second pull-down control subcircuit 32 need to function in each image frame to achieve the effect of avoiding the transistor from being burned and prolonging the high potential time of the pull-down node.

[0149] Of course, the third clock signal terminal CLKC can be used as a successor clock of the second clock signal terminal CLKB. Figure 6It can be seen that the 1B transistor M1B and the 2B transistor M2B will not be turned on at the same time, so there is no risk of overcurrent burning.

[0150] Continue to refer to Figure 5 As shown, the second reset signal terminal T_RST1 serves as a global reset signal terminal and becomes a valid level before the t1 period in a frame, thereby providing a global reset when cascading. Of course, the high level period after the t4 period is also used for global reset.

[0151] During the research, the inventor simulated the shift register circuit and found that the shift register circuit was running continuously for a long time. Figure 7 The simulation diagram shown in the figure simulates the potential comparison diagram of the first pull-down node PD_A before and after the shift register circuit continues to run for 8 hours. It can be seen from the simulation diagram that after 8 hours of continuous operation, the potential of the first pull-down node PD_A is significantly reduced. After further research, the inventor found that this change is due to the offset of the threshold voltage Vth of the 1A transistor M1A after a long period of operation, resulting in an increase in leakage current, thereby lowering the potential of the first pull-down node PD_A. Of course, those skilled in the art can understand that the change pattern of the second pull-down node PD_B is similar.

[0152] Preferably, refer to Figure 8 As shown, Figure 8 An exemplary structure of a shift register circuit according to another embodiment is shown.

[0153] contrast Figure 8 and Figure 4 It can be seen that the difference lies in the structures of the first pull-down control sub-circuit 31 and the second pull-down control sub-circuit 32 .

[0154] Specifically, the first pull-down control subcircuit 31 includes: a 1A transistor M1A. In particular, in this embodiment, the first electrode of the 1A transistor M1A is electrically connected to the second power signal terminal VDD, the second electrode is electrically connected to the first pull-down node PD_A, and the control electrode is electrically connected to the second clock signal terminal CLKB.

[0155] Reference Fig. 9 As shown, the timing of the second clock signal terminal CLKB is the same as the timing of the second clock signal terminal CLKB in the above embodiment, and the second power signal terminal VDD is a high-level power signal.

[0156] Reference Figure 8 As shown, when the shift register circuit includes the second pull-down control subcircuit 32, the second pull-down control subcircuit 32 includes: a 1B transistor M1B. In this embodiment, the first electrode of the 1B transistor M1B is electrically connected to the second power signal terminal VDD, the second electrode is electrically connected to the second pull-down node PD_B, and the control electrode is electrically connected to the third clock signal terminal CLKC. Fig. 9 As shown, the timing of the third clock signal terminal CLKC is the same as the timing of the third clock signal terminal CLKC in the above embodiment.

[0157] The difference between this circuit structure and the shift register circuit in the above embodiment during operation is that the high level potential of the first electrode of the 1A transistor M1A in the first pull-down control subcircuit 31 comes from the second power signal terminal VDD, and the conduction of the transistor still comes from the control of the second clock signal terminal CLKB, but its first electrode is continuously connected to the DC high voltage signal, so that after the second clock signal terminal CLKB changes from a high level to a low level, the first electrode and the second electrode of the first pull-down node PD_A are both high voltages, thereby preventing the first pull-down node PD_A from decreasing. The effect of the second power signal terminal VDD on the second pull-down node PD_B is similar to this, and will not be described in detail here.

[0158] It should be noted that the other structures and working states of the circuit in this embodiment are similar to those described in the above embodiment and will not be described in detail here. Figure 8 The circuit schematic diagram is only an example. The optional structure in the circuit structure described in the above embodiment is also optional in this embodiment and will not be described in detail herein.

[0159] In some other optional embodiments, the charge retention effect of the capacitor may be used to stabilize the potential of the first pull-down node PD_A and / or the second pull-down node PD_B.

[0160] Optionally, refer to Fig.10 As shown, the shift register circuit includes: a first capacitor C1, a first electrode of the first capacitor C1 is electrically connected to the second power signal terminal VDD, and a second electrode of the first capacitor C1 is electrically connected to the first pull-down node PD_A.

[0161] Optionally, the shift register circuit includes: a second capacitor C2. A first electrode of the second capacitor C2 is electrically connected to the second power signal terminal VDD, and a second electrode of the second capacitor C2 is electrically connected to the second pull-down node PD_B.

[0162] Through the above configuration, compared with the second clock signal terminal CLKB and the third clock signal terminal CLKC providing the noise reduction high voltage only 50% of the time, the first capacitor C1 and the second capacitor C2 that are always electrically connected can be used to maintain the potential of the corresponding pull-down node, thereby ensuring a good noise reduction effect.

[0163] It is worth mentioning that although Fig.10 is Figure 8 The first capacitor C1 and the second capacitor C2 are added to the circuit structure of FIG. 1 , but the present disclosure is not limited thereto. Figure 3 When the first capacitor C1 and the second capacitor C2 are arranged on the basis of the circuit structure of Figure 3 The potential holding effect of the first pull-down node PD_A and / or the second pull-down node PD_B is improved on the basis of the structure shown, which is also within the scope of protection of the present disclosure.

[0164] Considering that in the embodiments of the present disclosure, the first pull-down node PD_A and / or the second pull-down node PD_B are not high voltages before the start of each frame, and the second clock signal terminal CLKB and the third clock signal terminal CLKC also have a timing sequence, when the first clock signal terminal CLK drives the output terminal OUT to output, the first pull-down node PD_A and the second pull-down node PD_B are not sufficient to achieve the noise reduction effect, and 3A transistor M3A and 3B transistor M3B are additionally provided to charge the first pull-down node PD_A and the second pull-down node PD_B before and after the frame.

[0165] Reference Fig.11 As shown, the shift register circuit further includes: a 3A transistor M3A and a 3B transistor M3B. The first electrode of the 3A transistor M3B is electrically connected to the second power signal terminal VDD, the second electrode is electrically connected to the first pull-down node PD_A, and the control electrode is electrically connected to the first control terminal STV0; a 3B transistor, the first electrode of the 3B transistor is electrically connected to the second power signal terminal VDD, the second electrode is electrically connected to the second pull-down node PD_B, and the control electrode is electrically connected to the first control terminal STV0.

[0166] In order to simplify the number of signal lines, the signal connected to the first control terminal STV0 may be the same as the signal connected to the second reset signal terminal T_RST1.

[0167] Through the above configuration, the first control terminal STV0 can be used to charge the first pull-down node PD_A and the second pull-down node PD_B using the high potential of the second power signal terminal VDD before and after each frame, thereby maintaining a good noise reduction effect.

[0168] It should be noted that other structures and operating modes in this embodiment are the same as those of the circuit structure parts in the above embodiment, and will not be described in detail here.

[0169] Considering that in the embodiment of the present disclosure, when two pull-down control sub-circuits and a pull-down sub-circuit are included, both pull-down control sub-circuits are operative in each image frame, and the functions of the pull-down sub-circuits are substantially identical, it is further preferred that the embodiment of the present disclosure proposes a simplified circuit structure.

[0170] Reference Fig.12 As shown, the same reference numerals are used to indicate Figure 4 Circuit structures and subcircuits similar to the examples in .

[0171] Reference Fig.12As shown, the structures of the input subcircuit 10, the pull-up subcircuit 20, the carry output subcircuit 50, the first reset subcircuit 71, the second reset subcircuit 72 and the third reset subcircuit 73 of the shift register circuit in this embodiment are the same as those of the above embodiment.

[0172] The difference is that the shift register circuit only includes the first pull-down control sub-circuit 31 and the first pull-down sub-circuit 41, and the one branch structure realizes the completely identical functions of the two branches in the above embodiment.

[0173] Specific reference Fig.12 As shown, the first pull-down control subcircuit 31 is electrically connected to the second clock signal terminal CLKB, the third clock signal terminal CLKC and the first pull-down node PD_A, and is configured to input a signal of a valid level into the first pull-down node PD_A based on the signal of the second clock signal terminal CLKB, and to input a signal of a valid level into the first pull-down node PD_A based on the signal of the third clock signal terminal CLKC. The timing of the second clock signal terminal CLKB and the third clock signal terminal CLKC are the same as those in the above embodiments, that is, the signal of the second clock signal terminal CLKB is a signal whose valid level is delayed by at least 1 H than the valid level of the signal of the first clock signal terminal CLK, and the signal of the third clock signal terminal is a signal whose valid level is delayed by at least 1 H than the valid level of the signal of the second clock signal terminal, and H represents the time for the signal at the output terminal to scan a row of pixels.

[0174] Optionally, refer to Fig.12 As shown, the first lower control subcircuit 31 includes: a 1A transistor M1A and a 1B transistor M1B. The first electrode of the 1A transistor M1A is electrically connected to the second power signal terminal VDD, the second electrode is electrically connected to the first pull-down node PD_A, and the control electrode is electrically connected to the second clock signal terminal CLKB; the first electrode of the 1B transistor M1B is electrically connected to the second power signal terminal VDD, the second electrode is electrically connected to the first pull-down node PD_B, and the control electrode is electrically connected to the third clock signal terminal CLKC.

[0175] The first pull-down sub-circuit 41 includes: a second transistor M2 , a first electrode of the second transistor M2 being electrically connected to the first pull-down node PD_A, a second electrode of the second transistor M2 being electrically connected to the first power signal terminal LVGL, and a control electrode of the second transistor M2 being electrically connected to the pull-up node PU.

[0176] Through this structure, it is equivalent to merging the first pull-down node PD_A and the second pull-down node PD_B in the above embodiment into a first pull-down node PD_A in this embodiment. When the second clock signal terminal CLKB becomes a high level, the 1A transistor M1A is turned on to pull up the potential of the first pull-down node PD_A, and when the third clock signal terminal CLKC becomes a high level, the 1B transistor M1B is turned on to maintain the potential of the first pull-down node PD_A.

[0177] Through this configuration, a first pull-down control sub-circuit and a first pull-down sub-circuit are used to enable a pull-down node PD_A to obtain the same function as the two pull-down nodes PD_A and PD_B described above.

[0178] certainly, Fig.12 It is shown that the first electrodes of the transistors in the first pull-down control subcircuit 31 and the second pull-down control subcircuit 32 are electrically connected to the second power signal terminal VDD, thereby avoiding the problem of pull-down node lowering caused by increased leakage current due to threshold voltage shift during long-term operation.

[0179] However, the present disclosure is not limited thereto, and when the number of signal lines needs to be simplified, the first electrode of the 1A transistor M1A and the first electrode of the 1B transistor M1B may also be electrically connected to the second clock signal terminal CLKB and the third clock signal terminal CLKC, respectively, which will not be elaborated herein.

[0180] Continue to refer to Fig.12 As shown, a more significant advantage is that, through the structure of this embodiment, the transistors of the noise reduction sub-circuit related to the second pull-down node PD_B above are no longer needed, but the functions are the same, thereby greatly simplifying the circuit structure and facilitating narrow frame design.

[0181] Reference Fig.12 As shown, preferably, the shift register circuit may further include: a first capacitor C1, a first electrode of the first capacitor C1 is electrically connected to the second power signal terminal, and a second electrode is electrically connected to the first pull-down node PD_A; and a third transistor M3, a first electrode of the third transistor M3 is electrically connected to the second power signal terminal, a second electrode is electrically connected to the first pull-down node, and a control electrode is electrically connected to the first control terminal. The signal connected to the first control terminal STV0 may be the same as the second reset signal terminal T_RST1.

[0182] Through the above configuration, the potential of the first pull-down node PD_A can be stabilized by utilizing the storage effect of the capacitor on charges, and the first pull-down node PD_A can be charged by turning on the third transistor M3 before and after the frame to maintain a good noise reduction effect.

[0183] Based on the same inventive concept, the second aspect of the present disclosure provides a gate driving circuit, comprising N cascaded shift register circuits as described above, wherein

[0184] The input end of the n-th stage shift register circuit is electrically connected to the output end or the carry output end of another stage shift register circuit;

[0185] The input end of the first-stage shift register circuit is electrically connected to the start signal end of the gate drive circuit, N is a positive integer greater than or equal to 2, and n is a positive integer greater than 1 and less than or equal to N.

[0186] Optionally, another level of shift register circuit serving as the carry circuit of the n-th level shift register circuit can be the next level shift register circuit adjacent thereto or can be a certain level of shift register circuit in between. For example, the n-th level shift register circuit can be cascaded with the shift register circuit located two levels before it, for example, the n-1-th level shift register circuit, or can be cascaded with the shift register circuit located three levels before it, for example, the n-2-th level shift register circuit. Of course, this is merely exemplary, and the present disclosure is not limited to a specific cascading method, so that a flexible cascading method can be implemented as needed.

[0187] Alternatively, the reset mode is not limited to two adjacent shift register circuits. For example, the reset control terminal of the a-th shift register circuit can be electrically connected to the output terminal of the a+1-th shift register circuit, or can be electrically connected to the output terminal of the a+2-th shift register circuit, so as to achieve more flexible reset control. Of course, the specific number of stages used for reset is not limited.

[0188] The structure and function of the shift register circuit for cascading have been described in detail in the above embodiments in conjunction with the circuit structure and timing diagram, and will not be described in detail here.

[0189] Through the above arrangement, by providing a first pull-down control sub-circuit electrically connected to the second clock signal terminal, and the effective level of the signal at the second clock signal terminal is delayed compared to the effective level of the first clock signal of the pull-up sub-circuit, it is possible to avoid the first pull-down control sub-circuit and the first pull-down sub-circuit being turned on at the same time, thereby protecting the transistors on the branch from burning out and improving the high-voltage stability of the display product.

[0190] Optionally, because three clock signals are required in each stage of the shift register circuit, in order to simplify the circuit structure, the number of clock signal lines is simplified by using the relationship between the various signals during cascading.

[0191] Preferably, the number of the clock signal lines of the gate driving circuit may be four.

[0192] Optionally, in the gate drive circuit, the first clock signal terminal of the 4m-3-level shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line; the first clock signal terminal of the 4m-2-level shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line; the first clock signal terminal of the 4m-1-level shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line; the first clock signal terminal of the 4m-level shift register circuit is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line, wherein m is a positive integer greater than or equal to 1.

[0193] Fig.13 Taking 6 cascaded shift registers as an example, the above example of implementing multiple cascades through four clock signal lines, where for simplicity, the output terminal OUT is used for carry, but the embodiments of the present disclosure are not limited thereto. Fig.14 The timing relationship between each clock signal line is given. In this example, if each stage of the cascaded shift register provides a scan signal to a row of pixels and the cascaded shift register scans each row of pixels line by line in turn, the effective level of each clock signal line is delayed by one row of scanning time H in turn. If each stage of the cascaded shift register provides a scan signal to a row of pixels and the cascaded shift register is only responsible for scanning odd rows of pixels or only responsible for scanning even rows of pixels, the effective level of each clock signal line is delayed by two rows of scanning time, that is, 2 H. Of course, the delay time is longer when the number of interval rows is more, which will not be elaborated here.

[0194] It should also be noted that the number of clock signal lines in the gate driving circuit of the embodiment of the present disclosure is not limited to 4, as long as the above-mentioned delay relationship can be achieved, which will not be elaborated here.

[0195] A third aspect of the present disclosure provides a display device, comprising the gate driving circuit of an embodiment of the present disclosure.

[0196] In this embodiment, a gate drive circuit is formed by cascading a shift register circuit including a first pull-down control sub-circuit electrically connected to a second clock signal terminal, and the effective level of the signal at the second clock signal terminal is delayed compared to the effective level of the first clock signal of the pull-up sub-circuit, thereby preventing the first pull-down control sub-circuit and the first pull-down sub-circuit from being turned on at the same time, thereby protecting the transistors on the branch from burning out and improving the high-voltage stability of the display product.

[0197] It is worth noting that the gate driving circuit of the embodiment of the present disclosure can be applied to various forms of display devices. Those skilled in the art should understand that all display devices based on the working mode of the gate driving circuit of the present disclosure are within the protection scope of the present disclosure.

[0198] Indicatively, Fig.15 FIG. 1 shows an application example of the gate drive circuit GOA. It can be seen that the display panel of the display device includes a display area and a non-display area. The gate drive circuit GOA is located in the non-display area, and provides a scan signal to the transistors in the drive circuit of the array-arranged pixels in the non-display area through the output end of the sequentially cascaded shift register circuit. The scan signal is electrically connected to each gate signal line Gate1, Gate2, Gate3, Gate4, ..., Gate N-1, GateN through the output end and provided to the gate of the corresponding transistor. Fig.14 As shown, the gate drive circuit in the display device is not limited to one group. Each group of gate drive circuits GOA can provide scanning signals to each row of gate signal lines at the same time, or one group of gate drive circuits can provide scanning signals to the gate signal lines of odd rows, and one group of gate drive circuits can provide scanning signals to the gate signal lines of even rows; in addition, the transistors in the drive circuit of each pixel also need multiple groups of gate drive circuits, which will not be described in detail here.

[0199] In addition, the display device provides data signals to each data signal line Data1, Data2, Data3, Data4, ..., DataN, Data Last in the display panel through the display driver chip IC1, and provides a power signal to the shift register circuit in the gate drive circuit through the level conversion chip IC2. Of course, the number of data signal lines and gate signal lines is not limited.

[0200] A fourth aspect of the present disclosure provides a control method using a shift register circuit according to an embodiment of the present disclosure, comprising:

[0201] In the first stage, a signal of a valid level is provided to the input terminal, and the input subcircuit transmits the input signal of the valid level to the pull-up node to pull up the potential of the pull-up node;

[0202] In the second stage, the pull-up sub-circuit transmits the signal of the first clock signal terminal to the output terminal under the control of the potential of the pull-up node.

[0203] In the above manner, by providing a signal whose effective level is delayed than the effective level of the first clock signal of the pull-up sub-circuit to the first pull-down control sub-circuit electrically connected to the second clock signal terminal, it is possible to avoid the first pull-down control sub-circuit and the first pull-down sub-circuit being turned on at the same time, thereby protecting the transistors on the branch from burning and improving the high-voltage stability of the display product.

[0204] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A shift register circuit, characterized in that: include: an input subcircuit, electrically connected to the input terminal and the pull-up node, configured to input an input signal of a valid level to the pull-up node based on a signal at the input terminal; a pull-up subcircuit, electrically connected to the pull-up node, the first clock signal terminal and the output terminal, configured to electrically connect the first clock signal terminal to the output terminal based on the potential of the pull-up node; A first pull-down control subcircuit, electrically connected to the second clock signal terminal and the first pull-down node, configured to input a signal of an effective level into the first pull-down node based on a signal at the second clock signal terminal; as well as a first pull-down subcircuit electrically connected to the first pull-down node, the first power signal terminal and the pull-up node, and configured to electrically connect the first power signal terminal to the first pull-down node based on the potential of the pull-up node, The signal at the second clock signal end is a signal whose effective level is delayed by at least 1 H than the effective level of the signal at the first clock signal end, and H represents the time for the signal at the output end to scan a row of pixels.

2. The shift register circuit according to claim 1, characterized in that: Also includes: A second pull-down control subcircuit, electrically connected to the third clock signal terminal and the second pull-down node, configured to input a signal of a valid level into the second pull-down node based on a signal of the third clock signal terminal; as well as a second pull-down sub-circuit, electrically connected to the second pull-down node, the first power signal terminal and the pull-up node, and configured to electrically connect the first power signal terminal to the second pull-down node based on the potential of the pull-up node, The signal at the third clock signal end is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the second clock signal end.

3. The shift register circuit according to claim 2, characterized in that: The first pull-down control subcircuit comprises: a 1A transistor, a first electrode and a control electrode of the 1A transistor being electrically connected to the second clock signal terminal, and a second electrode being electrically connected to the first pull-down node; and The first pull-down sub-circuit comprises: a 2A transistor, a first electrode of the 2A transistor is electrically connected to the first pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node. and / or The second pull-down control subcircuit comprises: a 1B transistor, a first electrode and a control electrode of the 1B transistor being electrically connected to the third clock signal terminal, and a second electrode being electrically connected to the second pull-down node; and The second pull-down sub-circuit includes: a 2B transistor, a first electrode of the 2B transistor is electrically connected to the second pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

4. The shift register circuit according to claim 2, characterized in that: The first pull-down control subcircuit comprises: a 1A transistor, a first electrode of the 1A transistor being electrically connected to the second power signal terminal, a second electrode being electrically connected to the first pull-down node, and a control electrode being electrically connected to the second clock signal terminal; and The first pull-down sub-circuit comprises: a 2A transistor, a first electrode of the 2A transistor is electrically connected to the first pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node. and / or The second pull-down control subcircuit comprises: a 1B transistor, a first electrode of the 1B transistor being electrically connected to the second power signal terminal, a second electrode being electrically connected to the second pull-down node, and a control electrode being electrically connected to the third clock signal terminal; and The second pull-down sub-circuit includes: a 2B transistor, a first electrode of the 2B transistor is electrically connected to the second pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

5. The shift register circuit according to claim 2, characterized in that: Also includes: a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the second power signal terminal, and a second electrode of the first capacitor is electrically connected to the first pull-down node, and / or A second capacitor, wherein a first electrode of the second capacitor is electrically connected to the second power signal terminal, and a second electrode of the second capacitor is electrically connected to the second pull-down node.

6. The shift register circuit according to claim 3 or 4, characterized in that: Also includes: A 3A transistor, wherein a first electrode of the 3A transistor is electrically connected to the second power signal terminal, a second electrode is electrically connected to the first pull-down node, and a control electrode is electrically connected to the first control terminal; as well as A 3B transistor, wherein a first electrode of the 3B transistor is electrically connected to the second power signal terminal, a second electrode is electrically connected to the second pull-down node, and a control electrode is electrically connected to the first control terminal.

7. The shift register circuit according to claim 1, characterized in that: The first pull-down control subcircuit is electrically connected to the second clock signal terminal, the third clock signal terminal and the first pull-down node, and is configured to input a signal of an effective level into the first pull-down node based on a signal of the second clock signal terminal, and to input a signal of an effective level into the first pull-down node based on a signal of the third clock signal terminal, The signal at the third clock signal end is a signal whose effective level is delayed by at least 1 H compared to the effective level of the signal at the second clock signal end, and H represents the time for the signal at the output end to scan a row of pixels.

8. The shift register circuit according to claim 7, characterized in that: The first lower control subcircuit comprises: a 1A transistor and a 1B transistor, wherein the first electrode of the 1A transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the first pull-down node, and the control electrode is electrically connected to the second clock signal terminal; the first electrode of the 1B transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the first pull-down node, and the control electrode is electrically connected to the third clock signal terminal; The first pull-down sub-circuit includes: a second transistor, a first electrode of the second transistor is electrically connected to the first pull-down node, a second electrode is electrically connected to the first power signal terminal, and a control electrode is electrically connected to the pull-up node.

9. The shift register circuit according to claim 8, characterized in that: Also includes: a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the second power signal terminal, and a second electrode of the first capacitor is electrically connected to the first pull-down node; A third transistor, wherein a first electrode of the third transistor is electrically connected to the second power signal terminal, a second electrode is electrically connected to the first pull-down node, and a control electrode is electrically connected to the first control terminal.

10. The shift register circuit according to claim 1, characterized in that: An input subcircuit, comprising a fifth transistor, a first electrode and a control electrode of the fifth transistor being electrically connected to the input terminal, and a second electrode being electrically connected to the pull-up node; The pull-up sub-circuit comprises a sixth transistor and a third capacitor, wherein the first electrode of the sixth transistor is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the output terminal, the control electrode is electrically connected to the pull-up node, the first electrode of the third capacitor is electrically connected to the pull-up node, and the second electrode is electrically connected to the output terminal.

11. The shift register circuit according to claim 1, characterized in that: Also includes: Carry output subcircuit, The carry output subcircuit includes a seventh transistor, a first electrode of the seventh transistor is electrically connected to the first clock signal terminal, a second electrode is electrically connected to the carry output terminal, and a control electrode is electrically connected to the pull-up node.

12. The shift register circuit according to claim 2, characterized in that: Also includes: a first noise reduction subcircuit, electrically connected to the pull-up node, the first pull-down node and the first power signal terminal, configured to electrically connect the pull-up node with the first power signal terminal based on a signal of the first pull-down node; The second noise reduction sub-circuit is electrically connected to the pull-up node, the second pull-down node and the first power signal terminal, and is configured to electrically connect the pull-up node with the first power signal terminal based on a signal of the second pull-down node.

13. A gate drive circuit, characterized in that: include: N cascaded shift register circuits according to any one of claims 1 to 12, wherein The input end of the n-th stage shift register circuit is electrically connected to the output end or the carry output end of another stage shift register circuit; The input end of the first-stage shift register circuit is electrically connected to the start signal end of the gate drive circuit, N is a positive integer greater than or equal to 2, and n is a positive integer greater than 1 and less than or equal to N.

14. The gate driving circuit according to claim 13, characterized in that: The shift register circuit includes a second pull-down control subcircuit, the second pull-down control subcircuit is electrically connected to a third clock signal terminal and a second pull-down node, and is configured to input a signal of an effective level into the second pull-down node based on a signal of the third clock signal terminal, wherein the signal of the third clock signal terminal is a signal whose effective level is delayed by at least 1 H compared with the effective level of the signal of the second clock signal terminal. The first clock signal terminal of the 4m-3 stage shift register circuit is electrically connected to the first clock signal line, the second clock signal terminal is electrically connected to the second clock signal line, and the third clock signal terminal is electrically connected to the third clock signal line. The first clock signal terminal of the 4m-2-stage shift register circuit is electrically connected to the second clock signal line, the second clock signal terminal is electrically connected to the third clock signal line, and the third clock signal terminal is electrically connected to the fourth clock signal line. The first clock signal terminal of the 4m-1th stage shift register circuit is electrically connected to the third clock signal line, the second clock signal terminal is electrically connected to the fourth clock signal line, and the third clock signal terminal is electrically connected to the first clock signal line. The first clock signal terminal of the 4m-stage shift register circuit is electrically connected to the fourth clock signal line, the second clock signal terminal is electrically connected to the first clock signal line, and the third clock signal terminal is electrically connected to the second clock signal line. Wherein, m is a positive integer greater than or equal to 1.

15. A display device, characterized in that: Comprising the gate drive circuit as claimed in claim 13 or 14.

16. A control method using the shift register circuit according to any one of claims 1 to 12, characterized in that: include: In the first stage, a signal of a valid level is provided to the input terminal, and the input subcircuit transmits the input signal of the valid level to the pull-up node to pull up the potential of the pull-up node; In the second stage, the pull-up sub-circuit transmits the signal of the first clock signal terminal to the output terminal under the control of the potential of the pull-up node.

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