Display device, time schedule controller and control method thereof

Abstract

The invention discloses a display device, a time schedule controller and a control method thereof, and the time schedule controller comprises a detection unit which obtains a voltage detection signal of an IIC clock line; the control unit obtains the first time when the voltage of the IIC clock line reaches the set voltage for the first time and judges whether the voltage of the IIC clock line reaches the set voltage or not after the first time is delayed by the set time; the voltage switching unit adjusts the voltage provided for the IIC data line and the IIC clock line when the voltage of the IIC clock line does not reach the set voltage after the first time is delayed for the set time; the register stores the corresponding IIC setting parameters when the voltage of the IIC clock line reaches the set voltage after the first time is delayed for the set time, and the control unit further continues to receive the voltage detection signals after adjusting the voltage provided for the IIC data line and the IIC clock line. According to the application, the voltage on the IIC clock line and the IIC data line can meet the IIC protocol requirement when different time schedule controllers and different memories are matched to work, and the requirement of saving power consumption can be met.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device, a timing controller and a control method thereof. Background Art

[0002] In the era of rapid development of electronic technology, consumers have higher and higher requirements for the stability and low power consumption of electronic devices. In the driving circuit of some display devices, at least a timing controller (Timer Control Register, TCON) and a memory are included. The memory stores the code required by the timing controller, and the timing controller establishes communication with the memory to obtain the required code.

[0003] However, there are inter-chip differences between different timing controllers and different memories. For example, when the timing controller and the memory communicate via IIC, and different timing controllers and memories or different timing controllers and different memories work together to obtain codes, the inter-chip difference between the two may cause the IIC signal to fail to meet the requirements of the IIC protocol, resulting in a code reading error, causing an abnormal display screen. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a display device, a timing controller and a control method thereof, which can ensure that the voltages on the IIC clock line and the IIC data line meet the IIC protocol requirements when different timing controllers and different memories work together, and can also achieve the requirements of saving power consumption.

[0005] According to one aspect of the present application, a timing controller is provided, which obtains a code from a memory through an IIC clock line and an IIC data line, including:

[0006] A detection unit, obtaining voltage detection signals of the IIC clock line at different times;

[0007] a control unit, obtaining, according to the voltage detection signal, a first time when the voltage of the IIC clock line first reaches a set voltage, and judging, according to the voltage detection signal, whether the voltage of the IIC clock line reaches the set voltage after the first time delay set time;

[0008] a voltage switching unit, which adjusts the voltage provided to the IIC data line and the IIC clock line when the voltage of the IIC clock line does not reach the set voltage after the first time delay set time; and

[0009] a register, storing a corresponding IIC setting parameter when the voltage of the IIC clock line reaches the set voltage after the first time delay setting time,

[0010] The control unit also continues to receive the voltage detection signal after adjusting the voltages provided to the IIC data line and the IIC clock line.

[0011] Optionally, the control unit also calls the IIC setting parameters in the register during the power-on phase of the timing controller, and provides corresponding voltages to the IIC data line and the IIC clock line through the voltage switching unit.

[0012] Optionally, the control unit generates n groups of first control signals and second control signals according to the IIC setting parameters or according to the IIC setting parameters and the step value, where n is an integer greater than 1.

[0013] The voltage switching unit includes n first pull-up voltage loops and n second pull-up circuit loops,

[0014] Each first pull-up resistor loop includes: a first pull-up resistor, a first switch tube, and a second switch tube, wherein the control end of the first switch tube receives a corresponding first control signal, the first end of the first switch tube is grounded, the second end of the first switch tube is connected to the control end of the second switch tube, the second end of the second switch tube is connected to the power supply line via the first pull-up resistor, and the first end of the second switch tube is connected to the IIC clock line to provide a corresponding voltage;

[0015] Each second pull-up resistor loop includes: a second pull-up resistor, a third switch tube, and a fourth switch tube. The control end of the third switch tube receives a corresponding second control signal. The first end of the third switch tube is grounded. The second end of the third switch tube is connected to the control end of the fourth switch tube. The second end of the fourth switch tube is connected to the power supply line via the second pull-up resistor. The first end of the fourth switch tube is connected to the IIC data line to provide a corresponding voltage.

[0016] Optionally, the IIC setting parameters include a resistance value of a first pull-up resistor in a first pull-up resistor loop that is turned on and a resistance value of a second pull-up resistor in a second pull-up resistor loop that is turned on.

[0017] Alternatively, the IIC setting parameter includes two n-bit binary numbers, one n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal.

[0018] Optionally, the detection unit includes:

[0019] A voltage divider network connected between the power supply line and the ground;

[0020] an operational amplifier, wherein a first input terminal of the operational amplifier is connected to a voltage dividing node of the voltage dividing network, a second input terminal of the operational amplifier is connected to its own output terminal, and an output terminal of the operational amplifier outputs a set voltage; and

[0021] A comparator, wherein a first input end of the comparator is connected to the IIC clock line to receive the voltage of the IIC clock line, a second input end of the comparator is connected to the output end of the operational amplifier to receive the set voltage, and an output end of the comparator outputs the voltage detection signal.

[0022] According to another aspect of the present application, a control method of a timing controller is provided, wherein the timing controller obtains a code from a memory through an IIC clock line and an IIC data line, comprising:

[0023] The detection unit obtains the voltage detection signal of the IIC clock line at different times;

[0024] The control unit obtains, according to the voltage detection signal, a first time when the voltage of the IIC clock line reaches a set voltage for the first time;

[0025] and judging, according to the voltage detection signal, whether the voltage of the IIC clock line reaches the set voltage after the first time delay set time;

[0026] The register stores the corresponding IIC setting parameter when the voltage of the IIC clock line reaches the set voltage after the first time delay setting time; and

[0027] The voltage switching unit adjusts the voltage provided to the IIC data line and the IIC clock line when the voltage of the IIC clock line does not reach the set voltage after the first time delay setting time, and the control unit continues to obtain the voltage detection signal.

[0028] Optionally, before obtaining the voltage detection signal of the IIC clock line at different times, the method further includes:

[0029] The stored IIC setting parameters are called to provide corresponding voltages to the IIC data line and the IIC clock line.

[0030] Optionally, adjusting the voltage provided to the IIC data line and the IIC clock line includes:

[0031] Generate n groups of first control signals and second control signals according to the IIC setting parameters and the step value, where n is an integer greater than 1;

[0032] Based on n groups of first control signals and second control signals, the corresponding first pull-up resistor loop is turned on to output the corresponding voltage to the IIC clock line, and the corresponding second pull-up resistor loop is turned on to output the corresponding voltage to the IIC data line.

[0033] Optionally, the IIC setting parameter includes the resistance value of the first pull-up resistor in the first pull-up resistor loop that is turned on and the resistance value of the second pull-up resistor in the second pull-up resistor loop that is turned on, or the IIC setting parameter includes two n-bit binary numbers, one n-bit binary number consists of the level of each first control signal, and the other n-bit binary number consists of the level of each second control signal.

[0034] According to another aspect of the present application, a display device is provided, including an IIC clock line and an IIC data line; a memory storing a code; a timing controller as described above, providing corresponding voltages to the IIC clock line and the IIC data line, and obtaining the code from the memory through the IIC clock line and the IIC data line to configure the timing controller.

[0035] The display device, timing controller and control method provided by the present application obtain the voltage detection signal of the IIC clock line at different times, and after the voltage of the IIC clock line reaches the set voltage for the first time, the voltage provided to the IIC data line and the IIC clock line is recorded when the voltage of the IIC clock line reaches the set voltage, and the voltage provided to the IIC data line and the IIC clock line is adjusted when the voltage of the IIC clock line does not reach the set voltage, and the voltage detection signal of the IIC clock line at different times is continued to be obtained. So that the timing controller of the present application can provide a suitable voltage to the IIC clock line and the IIC data line, which not only ensures that the voltage on the IIC clock line and the IIC data line meets the IIC protocol requirements when different timing controllers and different memories work together, thereby avoiding the situation where the display screen is abnormal due to encoding reading errors, but also can achieve the requirement of saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0037] Figure 1 A schematic structural diagram of a display device according to an embodiment of the present application is shown;

[0038] Figure 2 A circuit diagram of a detection unit in a timing controller according to an embodiment of the present application is shown;

[0039] Figure 3 A waveform diagram of voltage detection performed by a timing controller according to an embodiment of the present application is shown;

[0040] Figure 4 A circuit diagram of a voltage switching unit in a timing controller according to an embodiment of the present application is shown;

[0041] Figure 5 A schematic flow chart of a control method of a timing controller according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0043] At present, a pull-up resistor with a small resistance is generally configured on the IIC data line and the IIC clock line so that the voltage on the IIC clock line and the IIC data line can meet the IIC protocol requirements when different timing controllers and different memories work together. However, the above solution will also increase power consumption.

[0044] The specific implementation of the present application is further described in detail below in conjunction with the drawings and examples.

[0045] Figure 1 A schematic structural diagram of a display device according to an embodiment of the present application is shown.

[0046] The display device at least includes a display panel and a driving circuit. The display panel, for example, includes a plurality of pixel units. The driving circuit is used to drive the plurality of pixel units in the display panel to realize image display.

[0047] like Figure 1 As shown, the driving circuit at least includes a serial bidirectional bus, a timing controller 100 , and a memory 200 .

[0048] The memory 200 is, for example, an erasable and programmable memory (EEPROM), and is used to store codes required by the timing controller 100. The codes include, for example, initialization codes.

[0049] The timing controller 100 communicates with the memory 200 via a serial bidirectional bus to read the code and at least perform initialization configuration. The serial bidirectional bus includes, for example, an IIC data line SDA and an IIC clock line SCL. Exemplarily, the timing controller 100 includes a control unit 110, which reads the code stored in the memory via the IIC data line SDA and the IIC clock line SCL, and at least completes the initialization configuration of the timing controller 100.

[0050] Furthermore, the timing controller 100 can also provide a suitable voltage to the IIC clock line and the IIC data line to ensure that the voltage on the IIC clock line and the IIC data line meets the IIC protocol requirements when different timing controllers and different memories work together. Exemplarily, the timing controller 100 also includes a detection unit 120, a voltage switching unit 130, and a register 140. The detection unit 120 is connected to the IIC clock line SCL, and is used to obtain the voltage detection signal of the IIC clock line SCL at different times. The control unit 110 is connected to the detection unit 120, and obtains the first time T1 when the voltage of the IIC clock line SCL first reaches the set voltage according to the voltage detection signal, and determines whether the voltage of the IIC clock line SCL reaches the set voltage after the delay setting time t at the first time T1 according to the voltage detection signal. The voltage switching unit 130 is connected to the control unit 110 and the IIC data line SDA and the IIC clock line SCL, and is used to adjust the voltage provided to the IIC data line SDA and the IIC clock line SCL when the voltage of the IIC clock line SCL does not reach the set voltage after the first time T1 delay setting time t. The register 140 is connected to the control unit 110, and is used to store the corresponding IIC setting parameter when the voltage of the IIC clock line SCL reaches the set voltage after the first time T1 delay setting time t. The control unit 110 also continues to receive the voltage detection signal from the detection unit 120 after adjusting the voltage provided to the IIC data line SDA and the IIC clock line SCL.

[0051] In other embodiments, during the power-on phase of the timing controller, the control unit 110 first calls the IIC setting parameters in the register 140, and then provides corresponding voltages to the IIC data line SDA and the IIC clock line SCL by controlling the voltage switching unit 130. The above-mentioned IIC setting parameters are values ​​stored in the register 140 after previous adjustment or pre-set initial values.

[0052] Furthermore, the timing controller 100 also receives data signals from at least the main control system, and provides corresponding data signals. Exemplarily, the timing controller 100 also includes a data receiving unit 150, a data processing unit 160, and a data output unit 170. The data receiving unit 150 receives data signals from the main control system, and transmits them to the data processing unit 160 through the register 140 or directly, and then transmits the corresponding data to the data output unit 170 via the data processing unit 160, and then the data output unit 170 outputs the data signal. Among them, the data processing unit 160 can, for example, at least reorder the data signal data. Taking the transmission of display data from the timing controller 100 to the data driving circuit in the driving circuit as an example, the data output unit 170 of the timing controller 100 transmits display data to the P2P interface of the data driving circuit through the P2P (Point-to-Point, point-to-point) interface. The display data output by the timing controller 100 is transmitted to the data driving circuit in the form of a Package. A Package, for example, includes multiple UIs (Unit Intervals).

[0053] Furthermore, the IIC data line SDA and the IIC clock line SCL are connected to the power supply line VDD via resistors, respectively.

[0054] Figure 2 A circuit diagram of a detection unit in a timing controller according to an embodiment of the present application is shown. Figure 3 A waveform diagram of voltage detection performed by a timing controller according to an embodiment of the present application is shown.

[0055] like Figure 2As shown, the detection unit 120 includes a comparator U1, an operational amplifier U2, and a voltage divider network. The voltage divider network is connected between the power supply line VDD and the ground, the first input terminal of the operational amplifier U2 is connected to the voltage divider node of the voltage divider network, the second input terminal of the operational amplifier U2 is connected to its output terminal, and the output terminal of the operational amplifier U2 outputs the set voltage Vref. The first power supply terminal of the operational amplifier U2 receives the voltage VLED, and the second power supply terminal of the operational amplifier U2 is grounded. The voltage divider network, for example, includes a resistor R3 and a resistor R4, and the resistor R3 and the resistor R4 are sequentially connected in series between the power supply line VDD and the ground, and the connection node of the resistor R3 and the resistor R4 serves as a voltage divider node. The first input terminal of the comparator U1 is connected to the IIC clock line SCL to receive the voltage VSCL of the IIC clock line SCL, the second input terminal of the comparator U1 is connected to the output terminal of the operational amplifier U2 to receive the set voltage Vref, and the output terminal of the comparator U1 outputs a voltage detection signal SCLC. The first power supply terminal of the comparator U1 receives the power supply voltage Vdd, and the second power supply terminal of the comparator U1 is grounded. Exemplarily, the first input terminal of the operational amplifier U2 and the comparator U1 is, for example, a non-inverting input terminal, and the second input terminal of the operational amplifier U2 and the comparator U1 is, for example, an inverting input terminal. When the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref, the voltage detection signal SCLC is at a high level, otherwise it is at a low level.

[0056] like Figure 3 As shown, when the power-on voltage VOK becomes a valid state (e.g., a high level), the timing controller 100 is powered on. When the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time, it is the rising edge detection point A of the voltage detection signal SCLC. When the voltage VSCL of the IIC clock line SCL decreases to the set voltage Vref, it is the falling edge detection point B of the voltage detection signal SCLC. The set voltage Vref that meets the requirements of the IIC protocol is, for example, 1.98V-3.3V, the set time t>600ns, and the time between the rising edge detection point A and the falling edge detection point B of the voltage detection signal SCLC needs to be greater than or equal to the set time t.

[0057] During the power-on phase of the timing controller, the control unit 110 first calls the IIC setting parameters in the register 140, and then provides the corresponding n groups of first control signals and second control signals to the control voltage switching unit 130 to provide corresponding voltages to the IIC data line SDA and the IIC clock line SCL. The above-mentioned IIC setting parameters are the values ​​stored in the register 140 after adjustment at power-on or the preset initial values. Afterwards, the control unit 110 receives the voltage detection signal, and for example, counts when the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time through an internal counter, and determines whether the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements according to the voltage detection signal after the set time is continuously counted.

[0058] Further, when the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time and delays for the set time, if the voltage VSCL of the IIC clock line SCL does not reach the set voltage Vref, the control unit 110 provides the voltage switching unit 130 with the corresponding n groups of first control signals and second control signals to increase the voltage provided to the IIC data line SDA and the IIC clock line SCL in a step-by-step manner until the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements. When the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time and delays for the set time and still reaches the set voltage Vref, the control unit 110 stores the corresponding IIC parameter in the register 140.

[0059] Figure 4 A circuit diagram of a voltage switching unit in a timing controller according to an embodiment of the present application is shown.

[0060] like Figure 4 As shown, the voltage switching unit 130 includes, for example, n first pull-up voltage loops and n second pull-up circuit loops, where n is an integer greater than 1.

[0061] Each first pull-up resistor loop includes a first pull-up resistor R1n, a first switch tube SCNn, and a second switch tube SCPn. The control end of the first switch tube SCNn is connected to the control unit 110 to receive the corresponding first control signal SCn. The first end of the first switch tube SCNn is grounded, the second end of the first switch tube SCNn is connected to the control end of the second switch tube SCPn, the second end of the second switch tube SCPn is connected to the power supply line VDD via the corresponding first pull-up resistor R1n, and the first end of the second switch tube SCPn is connected to the IIC clock line SCL to provide the corresponding voltage VSCL. Exemplarily, a resistor is connected between the control end of the second switch tube SCPn and its first end.

[0062] Each second pull-up resistor loop includes a second pull-up resistor R2n, a third switch tube SDNn, and a fourth switch tube SDPn. The control end of the third switch tube SDNn is connected to the control unit 110 to receive the corresponding second control signal SDn. The first end of the third switch tube SDNi is grounded. The second end of the third switch tube SDNn is connected to the control end of the fourth switch tube SDPn. The second end of the fourth switch tube SDPn is connected to the power supply line VDD via the corresponding second pull-up resistor R2i. The first end of the fourth switch tube SDPn is connected to the IIC data line SDA to provide the corresponding voltage VSDA. Exemplarily, a resistor is connected between the control end of the fourth switch tube SDPn and its first end.

[0063] The first switch tube is one of an NMOS tube and a PMOS tube, and the second switch tube is the other of the NMOS tube and the PMOS tube. The third switch tube is one of an NMOS tube and a PMOS tube, and the fourth switch tube is the other of the NMOS tube and the PMOS tube. The control end of the switch tube is, for example, a gate of a MOS tube, the first end of the switch tube is, for example, a source of a MOS tube, and the second end of the switch tube is, for example, a drain of a MOS tube. In other embodiments, the first end of the switch tube may also be the drain of a MOS tube, and the second end of the switch tube may be the source of a MOS tube.

[0064] Further, the IIC setting parameter is the resistance value of the first pull-up resistor and the second pull-up resistor stored in the register 140 after adjustment at power-on or the preset initial value of the first pull-up resistor and the second pull-up resistor. The step value is the resistance difference between two adjacent resistors. Preferably, the resistance difference between every two adjacent resistors is equal.

[0065] In other embodiments, the IIC setting parameter may also be two n-bit binary numbers, one n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal. The step value is 1, for example.

[0066] Exemplarily, the resistance values ​​of the first pull-up resistors R11, R12, ..., R1n decrease in sequence, and the resistance values ​​of the second pull-up resistors R21, R22, ..., R2n decrease in sequence. Further, the difference between each two adjacent resistors in the first pull-up resistors R11, R12, ..., R1n is, for example, equal, and the difference between each two adjacent resistors in the second pull-up resistors R21, R22, ..., R1n is, for example, equal.

[0067] In the power-on phase of the timing controller 100, the IIC setting parameters stored in the register 140 are called, for example, the first pull-up resistor R11 and the second pull-up resistor R21. Among the multiple groups of first control signals and second control signals generated by the corresponding control unit 110, only the first control signal SC1 and the second control signal SD1 are in a valid state, and the remaining groups of first control signals and second control signals are in an invalid state. Correspondingly, only the first pull-up resistor loop where the first pull-up resistor R11 is located and the second pull-up loop where the second pull-up resistor R21 is located are turned on to provide corresponding voltages to the IIC clock line SCL and the IIC data line SDA. In the voltage detection phase of the timing controller 100, when it is detected that the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements (when the voltage VSCL of the IIC clock line SCL reaches the set voltage Vref for the first time and still reaches the set voltage Vref after the delay setting time), the control unit 110 continues to store the first pull-up resistor R11 and the second pull-up resistor R21 as IIC setting parameters to the corresponding positions of the register 140. When it is detected that the voltage VSCL of the IIC clock line SCL does not meet the IIC protocol requirements (when the voltage VSCL of the IIC clock line SCL first reaches the set voltage Vref and after the set delay time, the voltage VSCL of the IIC clock line SCL does not reach the set voltage Vref), the control unit 110 provides the voltage switching unit 130 with the corresponding n groups of first control signals and second control signals to step-by-step increase the voltage provided to the IIC data line SDA and the IIC clock line SCL until the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements. Exemplarily, among the n groups of first control signals and second control signals provided during the first adjustment, only the first control signal SC2 and the second control signal SD2 are in a valid state, and the remaining groups of first control signals and second control signals are in an invalid state, and correspondingly only the first pull-up resistor loop where the first pull-up resistor R12 is located and the second pull-up loop where the second pull-up resistor R22 is located are turned on to provide the corresponding voltage to the IIC clock line SCL and the IIC data line SDA. If the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements after the first adjustment, the control unit 110 stores the first pull-up resistor R12 and the second pull-up resistor R22 as IIC setting parameters in the corresponding positions of the register 140. If the voltage VSCL of the IIC clock line SCL does not meet the IIC protocol requirements after the first adjustment, the next adjustment is continued until the voltage VSCL of the IIC clock line SCL meets the IIC protocol requirements. Each time the adjustment is continued, for example, the loop where the next first pull-up resistor is located and the loop where the second pull-up resistor is located are turned on in sequence.

[0068] Figure 5 A schematic flow chart of a control method of a timing controller according to an embodiment of the present application is shown.

[0069] like Figure 5 As shown, the present application provides a control method for a timing controller of a display device, comprising the following steps:

[0070] Step S310: obtaining voltage detection signals of the IIC clock line at different times.

[0071] Step S320: obtaining the first time when the voltage of the IIC clock line reaches the set voltage for the first time according to the voltage detection signal.

[0072] Step S330: determining whether the voltage of the IIC clock line reaches a set voltage after the first time delay setting time according to the voltage detection signal.

[0073] When the voltage of the IIC clock line reaches the set voltage after the first time delay setting time, step S340 is executed: the corresponding IIC setting parameter is stored.

[0074] If the voltage of the IIC clock line does not reach the set voltage after the first time delay setting time, step S350 is executed: the voltage provided to the IIC data line and the IIC clock line is adjusted. Then, step S310 is continued.

[0075] Further, step S350 includes: generating n groups of first control signals and second control signals according to the IIC setting parameters and step values, where n is an integer greater than 1; and based on the n groups of first control signals and second control signals, turning on the corresponding first pull-up resistor loop to output the corresponding voltage to the IIC clock line, and turning on the corresponding second pull-up resistor loop to output the corresponding voltage to the IIC data line.

[0076] In other embodiments, before obtaining the voltage detection signal of the IIC clock line at different times, the method further includes: calling the stored IIC setting parameters to provide corresponding voltages to the IIC data line and the IIC clock line.

[0077] Further, the IIC setting parameter includes a resistance value of a first pull-up resistor in a first pull-up resistor loop that is turned on and a resistance value of a second pull-up resistor in a second pull-up resistor loop that is turned on, or the IIC setting parameter includes two n-bit binary numbers, one n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal.

[0078] In other embodiments, the timing controller 100 may also execute the above control method, for example.

[0079] The display device, timing controller and control method provided by the present application obtain the voltage detection signal of the IIC clock line at different times, and after the voltage of the IIC clock line reaches the set voltage for the first time, the voltage provided to the IIC data line and the IIC clock line is recorded when the voltage of the IIC clock line reaches the set voltage, and the voltage provided to the IIC data line and the IIC clock line is adjusted when the voltage of the IIC clock line does not reach the set voltage, and the voltage detection signal of the IIC clock line at different times is continued to be obtained. So that the timing controller of the present application can provide a suitable voltage to the IIC clock line and the IIC data line, which not only ensures that the voltage on the IIC clock line and the IIC data line meets the IIC protocol requirements when different timing controllers and different memories work together, thereby avoiding the situation where the display screen is abnormal due to encoding reading errors, but also can achieve the requirement of saving power consumption.

[0080] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A timing controller, which obtains codes from a memory through an IIC clock line and an IIC data line, characterized in that: include: A detection unit, obtaining voltage detection signals of the IIC clock line at different times; a control unit, obtaining, according to the voltage detection signal, a first time when the voltage of the IIC clock line first reaches a set voltage, and judging, according to the voltage detection signal, whether the voltage of the IIC clock line reaches the set voltage after the first time delay set time; a voltage switching unit, which adjusts the voltage provided to the IIC data line and the IIC clock line when the voltage of the IIC clock line does not reach the set voltage after the first time delay setting time; as well as a register, storing a corresponding IIC setting parameter when the voltage of the IIC clock line reaches the set voltage after the first time delay setting time, The control unit also continues to receive the voltage detection signal after adjusting the voltages provided to the IIC data line and the IIC clock line.

2. The timing controller according to claim 1, characterized in that: The control unit also calls the IIC setting parameters in the register during the power-on phase of the timing controller, and provides corresponding voltages to the IIC data line and the IIC clock line through the voltage switching unit.

3. The timing controller according to claim 1 or 2, characterized in that: The control unit generates n groups of first control signals and second control signals according to the IIC setting parameters or according to the IIC setting parameters and the step value, where n is an integer greater than 1. The voltage switching unit includes n first pull-up voltage loops and n second pull-up circuit loops, Each first pull-up resistor loop includes: a first pull-up resistor, a first switch tube, and a second switch tube, wherein the control end of the first switch tube receives a corresponding first control signal, the first end of the first switch tube is grounded, the second end of the first switch tube is connected to the control end of the second switch tube, the second end of the second switch tube is connected to the power supply line via the first pull-up resistor, and the first end of the second switch tube is connected to the IIC clock line to provide a corresponding voltage; Each second pull-up resistor loop includes: a second pull-up resistor, a third switch tube, and a fourth switch tube. The control end of the third switch tube receives a corresponding second control signal. The first end of the third switch tube is grounded. The second end of the third switch tube is connected to the control end of the fourth switch tube. The second end of the fourth switch tube is connected to the power supply line via the second pull-up resistor. The first end of the fourth switch tube is connected to the IIC data line to provide a corresponding voltage.

4. The timing controller according to claim 3, characterized in that: The IIC setting parameters include the resistance value of the first pull-up resistor in the first pull-up resistor loop that is turned on and the resistance value of the second pull-up resistor in the second pull-up resistor loop that is turned on, Alternatively, the IIC setting parameter includes two n-bit binary numbers, one n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal.

5. The timing controller according to claim 1, characterized in that: The detection unit comprises: A voltage divider network connected between the power supply line and the ground; an operational amplifier, wherein a first input terminal of the operational amplifier is connected to a voltage dividing node of the voltage dividing network, a second input terminal of the operational amplifier is connected to its own output terminal, and an output terminal of the operational amplifier outputs a set voltage; and A comparator, wherein a first input end of the comparator is connected to the IIC clock line to receive the voltage of the IIC clock line, a second input end of the comparator is connected to the output end of the operational amplifier to receive the set voltage, and an output end of the comparator outputs the voltage detection signal.

6. A control method for a timing controller, wherein the timing controller obtains a code from a memory through an IIC clock line and an IIC data line, characterized in that: include: The detection unit obtains the voltage detection signal of the IIC clock line at different times; The control unit obtains, according to the voltage detection signal, a first time when the voltage of the IIC clock line reaches a set voltage for the first time; and judging, according to the voltage detection signal, whether the voltage of the IIC clock line reaches the set voltage after the first time delay set time; The register stores the corresponding IIC setting parameter when the voltage of the IIC clock line reaches the set voltage after the first time delay setting time; as well as The voltage switching unit adjusts the voltage provided to the IIC data line and the IIC clock line when the voltage of the IIC clock line does not reach the set voltage after the first time delay setting time, and the control unit continues to obtain the voltage detection signal.

7. The control method of the timing controller according to claim 6, characterized in that: Before obtaining the voltage detection signal of the IIC clock line at different times, the following steps are also included: The stored IIC setting parameters are called to provide corresponding voltages to the IIC data line and the IIC clock line.

8. The control method of the timing controller according to claim 6 or 7, characterized in that: Regulating the voltage provided to the IIC data line and the IIC clock line includes: Generate n groups of first control signals and second control signals according to the IIC setting parameters and the step value, where n is an integer greater than 1; Based on n groups of first control signals and second control signals, the corresponding first pull-up resistor loop is turned on to output the corresponding voltage to the IIC clock line, and the corresponding second pull-up resistor loop is turned on to output the corresponding voltage to the IIC data line.

9. The control method of the timing controller according to claim 8, characterized in that: The IIC setting parameter includes a resistance value of a first pull-up resistor in a first pull-up resistor loop that is turned on and a resistance value of a second pull-up resistor in a second pull-up resistor loop that is turned on, or the IIC setting parameter includes two n-bit binary numbers, one n-bit binary number is composed of the level of each first control signal, and the other n-bit binary number is composed of the level of each second control signal.

10. A display device, characterized in that: include: IIC clock line and IIC data line; A memory, storing the code; And the timing controller as described in any one of claims 1-5, provides corresponding voltages to the IIC clock line and the IIC data line, and obtains the code from the memory through the IIC clock line and the IIC data line to configure the timing controller.

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