Shift register, gate drive circuit and display panel

Abstract

The invention discloses a shift register, a gate drive circuit and a display panel. The shift register comprises an input module, a first control module, a second control module, a first output module and a second output module, the input module is used for transmitting an input signal to the input end of the first control module and the first end of the second control module according to a first clock signal; the first control module is used for transmitting a signal opposite to the control end logic to the first node; a signal which is logically opposite to the first node is transmitted to the second node; the second control module is used for transmitting the signal of the first end to the second node according to the first clock signal; the second control module and the input module are opposite in conduction level logic. The first output module is used for outputting a first power supply voltage according to a signal of a first node and outputting a second clock signal according to a signal of a second node; the second output module is used for outputting a first power supply voltage according to the signal of the first node and outputting a third clock signal according to the signal of the second node. The use performance of the shift register can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a gate drive circuit and a display panel. Background Art

[0002] With the development of display technology, display panels using technologies such as OLED (Organic Light Emitting Diode) are being used more and more widely, and correspondingly, the requirements for display panels are becoming higher and higher.

[0003] A shift register is required in a display panel to provide a scanning signal. However, the performance of the shift register in the related art is poor, which limits the further application of the display panel. Summary of the invention

[0004] The invention provides a shift register, a gate driving circuit and a display panel to improve the use performance of the shift register.

[0005] According to one aspect of the present invention, there is provided a shift register, the shift register comprising:

[0006] An input module, a first control module, a second control module, a first output module, and a second output module;

[0007] The input module is used to transmit the input signal to the input end of the first control module and the first end of the second control module according to the first clock signal; the first control module is used to transmit the signal which is logically opposite to its control end to the first node; and transmit the signal which is logically opposite to the first node to the second node;

[0008] The second control module is used to transmit the signal at its first end to the second node according to the first clock signal; wherein the conduction level logic of the second control module is opposite to that of the input module;

[0009] The first output module is used to output a first power supply voltage according to the signal of the first node, and to output a second clock signal according to the signal of the second node;

[0010] The second output module is used to output the first power supply voltage according to the signal of the first node, and to output a third clock signal according to the signal of the second node.

[0011] Optionally, the first control module includes a first inverting unit and a second inverting unit, the input end of the first inverting unit is electrically connected to the input end of the first control module, and the output end of the first inverting unit is electrically connected to the first node; the input end of the second inverting unit is electrically connected to the first node, and the output end of the second inverting unit is electrically connected to the second node;

[0012] Preferably, the first inverting unit comprises a first sub-switch and a second sub-switch, a control end of the first sub-switch is electrically connected to a control end of the second sub-switch and serves as an input end of the first inverting unit, a first end of the first sub-switch is electrically connected to a second end of the second sub-switch and serves as an output end of the first inverting unit, a second end of the first sub-switch is connected to a first power supply voltage, and a second end of the second sub-switch is connected to a second power supply voltage; the transistor channel types of the first sub-switch and the second sub-switch are different, and the transistor channel type of the first sub-switch and the input module is the same;

[0013] Preferably, the second inverting unit comprises a third sub-switch and a fourth sub-switch, the control end of the third sub-switch is electrically connected to the control end of the fourth sub-switch and serves as the input end of the second inverting unit, the first end of the third sub-switch is electrically connected to the second end of the fourth sub-switch and serves as the output end of the second inverting unit, the second end of the third sub-switch is connected to the first power supply voltage, and the second end of the fourth sub-switch is connected to the second power supply voltage; the transistor channel type of the third sub-switch is different from that of the fourth sub-switch, and the transistor channel type of the third sub-switch is the same as that of the input module;

[0014] Preferably, the first end of the input module is connected to the input signal, the second end of the input module is electrically connected to the input end of the first inverting unit and the first end of the second control module, and the control end of the input module is connected to the first clock signal; the second end of the second control module is electrically connected to the second node, and the control end of the second control module is connected to the first clock signal.

[0015] Optionally, the first output module includes a first pull-up unit, a first pull-down unit and a first coupling unit, the first end of the first pull-up unit is connected to the first power supply voltage, the control end of the first pull-up unit is electrically connected to the first node, and the second end of the first pull-up unit is electrically connected to the output end of the first output module; the first end of the first pull-down unit is connected to the second clock signal, the control end of the first pull-down unit is electrically connected to the second node, and the second end of the first pull-down unit is electrically connected to the output end of the first output module; the first end of the first coupling unit is electrically connected to the second end of the first pull-down unit, and the second end of the first coupling unit is electrically connected to the control end of the first pull-down unit.

[0016] Optionally, the second output module includes a second pull-up unit, a second pull-down unit and a second coupling unit; the first end of the second pull-up unit is connected to the first power supply voltage, the control end of the second pull-up unit is electrically connected to the first node, and the second end of the second pull-up unit is electrically connected to the output end of the second output module; the first end of the second pull-down unit is connected to the second clock signal, the control end of the second pull-down unit is electrically connected to the second node, and the second end of the second pull-down unit is electrically connected to the output end of the second output module; the first end of the second coupling unit is electrically connected to the second end of the second pull-down unit, and the second end of the second coupling unit is electrically connected to the control end of the second pull-down unit.

[0017] According to another aspect of the present invention, a gate driving circuit is provided, wherein the gate driving circuit comprises n-stage cascaded shift registers as described above; n is an integer greater than 1.

[0018] According to another aspect of the present invention, there is provided a display panel, the display panel comprising the gate driving circuit as described above and 2n rows of pixel circuits;

[0019] The first output module of the k-th shift register is used to drive the (2*k-1)-th row of pixel circuits, and the second output module of the k-th shift register is used to drive the (2*k)-th row of pixel circuits.

[0020] Optionally, the display panel further includes three clock lines;

[0021] In the shift register of the same level, the first clock signal is provided by the ath clock line, the second clock signal is provided by the bth clock line, and the third clock signal is provided by the cth clock line; wherein, if a is less than or equal to 2, b is equal to a plus 1; if a is equal to 3, b is equal to 1; if b is less than or equal to 2, c is equal to b plus 1; if b is equal to 3, c is equal to 1;

[0022] In two adjacent stages of the shift register, the first clock signal of the shift register of the latter stage and the third clock signal of the shift register of the former stage are provided by the same clock line.

[0023] Optionally, in two adjacent stages of the shift register, the input signal of the shift register of the latter stage is provided by the second output module of the shift register of the former stage.

[0024] Optionally, the display panel further includes 4 clock lines;

[0025] In the shift register of the same level, the first clock signal is provided by the ath clock line, the second clock signal is provided by the bth clock line, and the third clock signal is provided by the cth clock line; wherein, if a is less than or equal to 2, b is equal to a plus 2; if a is greater than or equal to 3, b is equal to a plus 2 minus 4; if b is less than or equal to 3, c is equal to b plus 1; if b is equal to 4, c is equal to 1;

[0026] In two adjacent stages of the shift register, the first clock signal of the shift register of the latter stage and the second clock signal of the shift register of the former stage are provided by the same clock line.

[0027] Optionally, in two adjacent stages of the shift register, the input signal of the shift register of the latter stage is provided by the first output module of the shift register of the former stage.

[0028] Optionally, the display panel includes six clock lines;

[0029] In the three adjacent shift registers, the first clock signal of the first shift register is provided by the j1th clock line, where j1 is an odd number less than or equal to 5; the first clock signal of the second shift register is provided by the j2th clock line; the first clock signal of the third shift register is provided by the j3th clock line; wherein, if j1 is less than or equal to 3, j2 is equal to j1 plus 2, and if j1 is equal to 5, j2 is equal to 1; if j2 is less than or equal to 3, j3 is equal to j2 plus 2, and if j2 is equal to 5, j3 is equal to 1; in the two adjacent shift registers, the first clock signal of the shift register of the latter stage and the second clock signal of the shift register of the previous stage are provided by the same clock line; in the shift register of the same stage, the second clock signal is provided by the ath clock line, and the third clock signal is provided by the bth clock line, and b is equal to a plus 1;

[0030] Preferably, in two adjacent stages of the shift registers, the input signal of the shift register of the latter stage is provided by the first output module of the shift register of the former stage.

[0031] The technical solution of the embodiment of the present invention adopts a shift register including: an input module, a first control module, a second control module, a first output module and a second output module; the input module is used to transmit the input signal to the input end of the first control module and the first end of the second control module according to the control of the first clock signal; the first control module is used to transmit the signal with the opposite logic to its control end to the first node; and transmit the signal with the opposite logic to the first node to the second node; the second control module is used to transmit the signal of its first end to the second node according to the first clock signal; wherein the conduction level of the second control module is logically opposite to that of the input module; the first output module is used to output the first power supply voltage according to the signal of the first node, and output the second clock signal according to the signal of the second node; the second output module is used to output the first power supply voltage according to the signal of the first node, and output the third clock signal according to the signal of the second node. By setting two output modules and providing different clock signals for the two output modules, the first output module and the second output module can output scanning signals with different timings, and the shift register can realize the above functions with a small number of components, thereby greatly reducing the area occupied by the shift register, which is conducive to reducing the frame of the display panel and improving the performance of the shift register.

[0032] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention;

[0036] Figure 3 A timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention;

[0038] Figure 5A timing diagram of a shift register provided by an embodiment of the present invention;

[0039] Figure 6 A schematic diagram of a circuit structure of a gate drive circuit provided by an embodiment of the present invention;

[0040] Figure 7 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0041] Figure 8 for Figure 7 Timing diagram of the gate drive circuit in the figure;

[0042] Fig. 9 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0043] Fig.10 for Fig. 9 Timing diagram of the gate drive circuit in the figure;

[0044] Fig.11 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0045] Fig.12 for Fig.11 Timing diagram of the gate drive circuit in the figure;

[0046] Fig.13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] The shift register in the related art has the problem of poor performance. After extensive research, the inventor found that the reason for this technical problem is that the display panel needs to have a narrow frame, and the shift register in the related art requires more components, so it occupies a large space. In addition, a shift register can only provide one scanning signal, and the number of rows of pixel circuits that can be driven is small. In other words, when the number of rows of pixel circuits is large, more shift registers are required, which is more unfavorable to the narrow frame of the display panel.

[0050] In view of the above technical problems, the present invention proposes the following solutions: Figure 1 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention, referring to Figure 1 The shift register includes an input module 11, a first control module 12, a second control module 13, a first output module 14 and a second output module 15; the input module 11 is used to transmit an input signal IN to an input end of the first control module 12 and a first end of the second control module 13 according to a first clock signal CK1; the first control module 12 is used to transmit a signal that is logically opposite to its control end to a first node QB, and transmit a signal that is logically opposite to the first node QB to a second node Q; the second control module 13 is used to transmit a signal at its first end to a second node Q according to the first clock signal CK1; wherein the conduction level of the second control module 13 is logically opposite to that of the input module 11; the first output module 14 is used to output a first power supply voltage VGH according to a signal at the first node QB, and output a second clock signal CK2 according to a signal at the second node Q; the second output module 15 is used to output a first power supply voltage VGH according to a signal at the first node QB, and output a third clock signal CK3 according to a signal at the second node Q.

[0051] Specifically, the shift register can shift the input signal and then output it. The first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 can be clock signals with the same cycle, and the duty cycle of the same level of each clock signal is the same. And in the same cycle, the conduction level of the second clock signal CK2 is later than the conduction level of the first clock signal CK1, and the conduction level of the third clock signal CK3 is later than the conduction level of the second clock signal CK2. Among them, the conduction level of the clock signal refers to the level at which the shift register can turn on the module driven in the pixel circuit.

[0052] In this embodiment, only a small number of components are needed to realize the function of outputting two different scanning signals at the same time. More specifically, the first output module 14 can output a scanning signal with a certain shift function relative to the input signal IN, hereinafter referred to as the first output signal Pout1. The second output module 15 can output a scanning signal that is shifted backward relative to the input signal IN and also shifted backward relative to the first output signal Pout1, hereinafter referred to as the second output signal Pout2. The first output signal Pout1 and the second output signal Pout2 have the same conduction level, such as both are low levels, which can be used to drive the P-type transistor in the pixel circuit. And because the second output signal Pout2 has a certain shift compared with the first output signal Pout1, it can drive the same module in different rows of pixel circuits. That is to say, a shift register in this embodiment can drive the same module in two rows of pixel circuits, and the number of shift registers required to drive all rows of pixel circuits on the display panel is small, which is conducive to the narrow frame of the display panel.

[0053] In this embodiment, the logic of the conduction level of the input module 11 and the second control module 13 is opposite, that is, if the conduction level of the input module 11 is low, then the conduction level of the second control module 13 is high; conversely, if the conduction level of the input module 11 is high, then the conduction level of the second control module 13 is low. And because the control ends of the input module 11 and the second control module 13 are both connected to the first clock signal CK1, that is, the control ends of both are connected to the same periodically changing signal, then the input module 11 and the second control module 13 are both periodically turned on and off, and the conduction states of the two are opposite. The first clock signal CK1 and the second clock signal CK2 have the same period, and in the same clock period, the pulse of the second clock signal CK2 is later than the pulse of the first clock signal CK1, and the pulse time of the first clock signal CK1 and the pulse of the second clock signal CK2 do not overlap. That is to say, the second clock signal CK2 can be understood as a signal that is shifted backward in timing of the first clock signal CK1. The pulse described in this article is a level with a relatively small duty cycle, such as a low level.

[0054] By configuring the conduction level (eg, low level) of the input signal IN to be within the conduction level (ie, low level) of the first clock signal CK1 corresponding to the input module 11 , the first output signal Pout1 can be shifted to a certain extent relative to the input signal IN.

[0055] When the first clock signal CK1 is at a low level and the input signal IN is at a low level, the input module 11 is turned on, so that the low-level input signal IN is transmitted to the input end of the first control module 12 and the first end of the second control module 13; at this time, the first control module 12 transmits a high level to the first node QB, and the first node QB is at a cut-off level; and at this time, the second output module 13 is turned off, so the second node Q is controlled by the first node QB and the first control module 12 and becomes a low level. In summary, at this time, the output of the first output module 14 follows the second clock signal CK2.

[0056] In the next stage, the first clock signal CK1 is at a high level, and the second clock signal CK2 is at a low level. At this time, the input module 11 is turned off, and the second control module 13 is turned on, and then the second control module 13 transmits the low level of its first end at the previous moment to the second node Q, and the first output module 14 responds to the low level on the second node Q, so that the first output signal Pout1 follows the second clock signal CK2, that is, outputs a low level.

[0057] In the next clock cycle, when the first clock signal CK1 becomes low again, the input signal IN is high at this time, so the first control module 12 will output a low level to the first node QB, and the first output signal Pout1 output by the first output module 14 becomes the first power supply voltage VGH. The second node Q is high, and in the next stage, when the second control module 13 is turned on, the high level of its first end is transmitted to the second node Q. In summary, in the shift register of this embodiment, the pulse timing of the first output signal Pout1 is the same as the pulse timing of the second clock signal CK2 in the clock cycle where the input signal IN pulse is located, and the first output signal Pout1 has only one pulse in one frame time. Therefore, it can be used as a scanning signal in a pixel circuit, such as a scanning signal for driving a P-type transistor.

[0058] Similarly, for the second output module 15, when the first clock signal CK1 is at a low level and the input signal IN is at a low level, the input module 11 is turned on, so that the low-level input signal IN is transmitted to the input end of the first control module 12 and the first end of the second control module 13; at this time, the first control module 12 transmits a high level to the first node QB, and the first node QB is at a turn-off level; and at this time, the second output module 13 is turned off, so the second node Q is controlled by the first node QB and the first control module 12 and becomes a low level. In summary, at this time, the output of the second output module 15 follows the third clock signal CK3.

[0059] In the next stage, the first clock signal CK1 is at a high level, and the third clock signal CK3 is at a low level. At this time, the input module 11 is turned off, and the second control module 13 is turned on, and then the second control module 13 transmits the low level of its first end at the previous moment to the second node Q, and the first output module Pout1 responds to the low level on the second node Q, so that the second output signal Pout2 follows the second clock signal CK2, that is, outputs a low level.

[0060] In the next clock cycle, when the first clock signal CK1 becomes low again, the input signal IN is high at this time, so the first control module 12 will output a low level to the first node QB, and the first output signal Pout1 output by the second output module 15 becomes the first power supply voltage VGH. The second node Q is high, and in the next stage, when the second control module 13 is turned on, the high level of its first end is transmitted to the second node Q. In summary, in the shift register of this embodiment, the pulse timing of the second output signal Pout2 is the same as the pulse timing of the third clock signal CK3 in the clock cycle where the input signal IN pulse is located, and the second output signal Pout2 has only one pulse in one frame time. Therefore, it can be used as a scanning signal in a pixel circuit, such as a scanning signal for driving a P-type transistor.

[0061] In addition, since the third clock signal CK3 is shifted relative to the second clock signal CK2, the second output signal Pout2 is shifted relative to the first output signal Pout1, and can be used to drive the same module in pixel circuits of different rows.

[0062] The technical solution of this embodiment adopts a shift register including: an input module, a first control module, a second control module, a first output module and a second output module; the input module is used to transmit the input signal to the input end of the first control module and the first end of the second control module according to the control of the first clock signal; the first control module is used to transmit the signal with the opposite logic to its control end to the first node; and transmit the signal with the opposite logic to the first node to the second node; the second control module is used to transmit the signal of its first end to the second node according to the first clock signal; wherein the conduction level of the second control module is logically opposite to that of the input module; the first output module is used to output the first power supply voltage according to the signal of the first node, and output the second clock signal according to the signal of the second node; the second output module is used to output the first power supply voltage according to the signal of the first node, and output the third clock signal according to the signal of the second node. By setting two output modules and providing different clock signals for the two output modules, the first output module and the second output module can output scanning signals with different timings, and the shift register can realize the above functions with a small number of components, thereby greatly reducing the area occupied by the shift register, which is conducive to reducing the frame of the display panel and improving the performance of the shift register.

[0063] For the convenience of description, the pixel circuit that can be driven by the shift register described in this embodiment is briefly introduced below.

[0064] Figure 2 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention is provided. Figure 3 A timing diagram of a pixel circuit provided by an embodiment of the present invention, Figure 3 and Figure 2 Corresponding. Reference Figure 2The pixel circuit includes: a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a first initialization transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a second initialization transistor M7, a third initialization transistor M8, a storage capacitor Cst and a light emitting element 9. The first end of the data writing transistor M2 is connected to the data voltage Data, the second end of the data writing transistor M2 is electrically connected to the first end of the driving transistor M1, and the control end of the data writing transistor M2 is connected to the second scanning signal S2. The first end of the threshold compensation transistor M3 is electrically connected to the second end of the driving transistor M1, the second end of the threshold compensation transistor M3 is electrically connected to the control end of the driving transistor M1, and the control end of the threshold compensation transistor M3 is connected to the third scanning signal S3; the first end of the first initialization transistor M4 is connected to the first initialization signal Vref1, the second end of the first initialization transistor M4 is electrically connected to the first end of the threshold compensation transistor M3, and the control end of the first initialization transistor M4 is connected to the first scanning signal S1; the first end of the first light-emitting control transistor M5 is connected to the first power supply signal ELVDD, the second end of the first light-emitting control transistor M5 is electrically connected to the first end of the driving transistor M1, and the control end of the first light-emitting control transistor M5 is connected to the light-emitting control signal EM; the first end of the second light-emitting control transistor M6 is electrically connected to the second end of the driving transistor M1, and the second light-emitting control The second end of the control transistor M6 is electrically connected to the first end of the light emitting element 9, and the control end of the second light emitting control transistor M6 is connected to the light emitting control signal EM; the first end of the second initialization transistor M7 is connected to the second initialization signal Vref2, the second end of the second initialization transistor M7 is electrically connected to the first end of the light emitting element 9, and the control end of the second initialization transistor M7 is connected to the fourth scanning signal S4; the first end of the third initialization transistor M8 is connected to the third initialization signal Vref3, the second end of the third initialization transistor M8 is electrically connected to the second end of the driving transistor M1, and the control end of the third initialization transistor M8 is connected to the fourth scanning signal S4; the second end of the light emitting element 9 is connected to the second power supply signal ELVSS; the first end of the storage capacitor Cst is connected to the first power supply signal ELVDD, and the second end of the storage capacitor Cst is electrically connected to the control end of the driving transistor M1. Among them, the threshold compensation transistor M3 and the first initialization transistor M4 can be N-type oxide transistors to reduce leakage current, which is more suitable for low-frequency display. The remaining transistors can be P-type low-temperature polysilicon transistors.

[0065] like Figure 3 As shown, the working process of the pixel circuit includes a first initialization stage t11, a charging stage t12, a second initialization stage t13 and a light emitting stage t14.

[0066] In the first initialization stage t11 , the first scan signal S1 controls the first initialization transistor M4 to be turned on, the third scan signal S3 controls the threshold compensation transistor M3 to be turned on, and the gate of the driving transistor M1 is initialized by the first initialization signal Vref1 .

[0067] In the charging stage t12, the second scan signal S2 controls the data writing transistor M2 to turn on, and the third scan signal S3 controls the threshold compensation transistor M3 to turn on. In this stage, the data voltage Data is written to the control end of the driving transistor M1, and the threshold compensation of the driving transistor M1 is completed in this stage.

[0068] In the second initialization stage t13, the fourth scan signal S4 controls the second initialization transistor M7 and the third initialization transistor M8 to be turned on, and the second initialization signal Vref2 and the third initialization signal Vref3 respectively complete the initialization of the first end of the light emitting element 9 and the second end of the driving transistor M1.

[0069] In the light emitting stage t14, the light emitting control signal EM controls the first light emitting control transistor M5 and the second light emitting control transistor M6 to be turned on, the driving transistor M1 generates a driving current, and the light emitting element 9 emits light in response to the driving current.

[0070] From the above analysis and Figure 3 It can be seen that the pixel circuit requires at least one low-level conduction scanning signal, namely the second scanning signal S2. The shift register of this embodiment can output two output signals, and can provide the second scanning signal for two adjacent rows of pixel circuits respectively. Therefore, the shift register structure required on the display panel is simpler, which is more conducive to achieving a narrow frame.

[0071] Optionally, Figure 4 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 4 The first control module 12 includes a first inverting unit 121 and a second inverting unit 122; the input end of the first inverting unit 121 is electrically connected to the input end of the first control module 12, and the output end of the first inverting unit 121 is electrically connected to the first node QB; the input end of the second inverting unit 122 is electrically connected to the first node QB, and the output end of the second inverting unit 122 is electrically connected to the second node Q.

[0072] Specifically, in this embodiment, the first inverting unit 121 and the second inverting unit 122 are used to implement all functions of the first control module 12, and the circuit structure is simple. When the second control module 12 is turned on and the input module 11 is turned off, the output end of the second inverting unit 122 is electrically connected to the input end of the first inverting unit 121, and the first inverting unit 121 and the second inverting unit 122 form a latch, so that the stability of the first node QB and the second node Q can be maintained without external input, that is, the power consumption of the shift register is low, which can reduce the power consumption of the display panel.

[0073] Optionally, continue to refer to Figure 4 The first inverting unit 121 includes a first sub-switch and a second sub-switch. The control end of the first sub-switch is electrically connected to the control end of the second sub-switch and serves as the input end of the first inverting unit 121. The first end of the first sub-switch is electrically connected to the second end of the second sub-switch unit and serves as the output end of the first inverting unit 121. The second end of the first sub-switch is connected to the first power supply voltage VGH, and the second end of the second sub-switch is connected to the second power supply voltage VGL; the transistor channel type of the first sub-switch is different from that of the second sub-switch, and the transistor channel type of the first sub-switch is the same as that of the input module; the second inverting unit 122 includes a third sub-switch and a fourth sub-switch. The control end of the third sub-switch is electrically connected to the control end of the fourth sub-switch and serves as the input end of the second inverting unit. The first end of the third sub-switch is electrically connected to the second end of the fourth sub-switch unit and serves as the output end of the second inverting unit. The second end of the third sub-switch is connected to the first power supply voltage, and the second end of the fourth sub-switch is connected to the second power supply voltage; the transistor channel type of the third sub-switch is different from that of the fourth sub-switch, and the transistor channel type of the third sub-switch is the same as that of the input module. In this embodiment, the first sub-switch and the second sub-switch form a complementary metal oxide inverter, and the third sub-switch and the fourth sub-switch form a complementary metal oxide inverter. The complementary metal oxide inverter has lower power consumption. Therefore, the shift register of this embodiment can also have lower power consumption.

[0074] Optionally, in the above embodiment, the first end of the input module 11 is connected to the input signal IN, the second end of the input module 11 is electrically connected to the input end of the first inverting unit 121 and the first end of the second control module 13, and the control end of the input module 11 is connected to the first clock signal CK1; the second end of the second control module 13 is electrically connected to the second node Q, and the control end of the second control module 13 is connected to the first clock signal CK1.

[0075] Optionally, continue to refer to Figure 4The first output module 14 includes a first pull-up unit 141, a first pull-down unit 142 and a first coupling unit 143; a first end of the first pull-up unit 141 is connected to the first power supply voltage VGH, a control end of the first pull-up unit 141 is electrically connected to the first node QB, and a second end of the first pull-up unit 141 is electrically connected to the output end of the first output module 14; a first end of the first pull-down unit 142 is connected to the second clock signal CK2, a control end of the first pull-down unit 142 is electrically connected to the second node Q, and a second end of the first pull-down unit 142 is electrically connected to the output end of the first output module 14; a first end of the first coupling unit 143 is electrically connected to the second end of the first pull-down unit 142, and a second end of the first coupling unit 143 is electrically connected to the control end of the first pull-down unit 142.

[0076] Specifically, when the first node QB is at a conduction level (low level), the first pull-up unit 141 is turned on, thereby controlling the output end of the first output module 14 to output the first power supply voltage VGH, that is, the first output signal Pout1 follows the first power supply voltage VGH. When the second node Q is at a conduction level (low level), the first pull-down unit 142 is turned on, thereby controlling the output end of the first output module 14 to output the second clock signal CK2, that is, the first output signal Pout1 follows the second clock signal CK2. The first coupling unit 143 can couple the first output signal Pout1 to the control end of the first pull-down unit 142, so that the conduction degree of the first pull-down unit 142 is deeper. This embodiment uses three simple units to realize the function of the first output module 14, and the circuit structure is simpler.

[0077] Optionally, the second output module 15 includes a second pull-up unit 151, a second pull-down unit 152 and a second coupling unit 153; the second pull-up unit 151 is connected to the first power supply voltage VGH, the control end of the second pull-up unit 151 is electrically connected to the first node QB, and the second end of the second pull-up unit 151 is electrically connected to the output end of the second output module 15; the first end of the second pull-down unit 152 is connected to the third clock signal CK3, the control end of the second pull-down unit 152 is electrically connected to the second node Q, and the second end of the second pull-down unit 152 is electrically connected to the output end of the second output module 15; the first end of the second coupling unit 153 is electrically connected to the second end of the second pull-down unit 152, and the second end of the second coupling unit 153 is electrically connected to the control end of the second pull-down unit 152.

[0078] Specifically, when the first node QB is at a conduction level (low level), the second pull-up unit 151 is turned on, thereby controlling the output end of the second output module 15 to output the first power supply voltage VGH, that is, the second output signal Pout2 follows the first power supply voltage VGH. When the second node Q is at a conduction level (low level), the second pull-down unit 152 is turned on, thereby controlling the output end of the second output module 15 to output the third clock signal CK3, that is, the second output signal Pout2 follows the third clock signal CK3. The second coupling unit 153 can couple the second output signal Pout2 to the control end of the second pull-down unit 152, so that the conduction degree of the second pull-down unit 152 is deeper. This embodiment uses three simple units to realize the function of the second output module 15, and the circuit structure is simpler.

[0079] Optionally, continue to refer to Figure 4 The input module 11 includes a first transistor T1, which may be a P-channel transistor. The first end of the first transistor T1 serves as the first end of the input module 11, the second end of the first transistor T1 serves as the second end of the input module 11, and the control end of the first transistor T1 serves as the control end of the input module 11.

[0080] The first sub-switch includes a second transistor T2, and the second sub-switch includes a third transistor T3, the second transistor T2 is a P-channel transistor, and the third transistor T3 is an N-channel transistor; the control end of the second transistor T2 is electrically connected to the control end of the third transistor T3 and serves as the input end of the first inverting unit 121; the first end of the second transistor T2 is electrically connected to the first end of the third transistor T3 and serves as the output end of the first inverting unit 121; the second end of the second transistor T2 is connected to the first power supply voltage VGH, and the second end of the third transistor T3 is connected to the second power supply voltage VGL.

[0081] The third sub-switch includes a fourth transistor T4, and the fourth sub-switch includes a fifth transistor T5, the fourth transistor T4 is a P-channel transistor, and the fifth transistor T5 is an N-channel transistor; the control end of the fourth transistor T4 is electrically connected to the control end of the fifth transistor T5 and serves as the input end of the second inverting unit 122; the first end of the fourth transistor T4 is electrically connected to the first end of the fifth transistor T5 and serves as the output end of the second inverting unit 122; the second end of the fourth transistor T4 is connected to the first power supply voltage VGH, and the second end of the fifth transistor T5 is connected to the second power supply voltage VGL.

[0082] The first pull-up unit 141 includes a sixth transistor T6, which may be a P-channel transistor. The first end of the sixth transistor T6 serves as the first end of the first pull-up unit 141, the second end of the sixth transistor T6 serves as the second end of the first pull-up unit 141, and the control end of the sixth transistor T6 serves as the control end of the first pull-up unit 141.

[0083] The first pull-down unit 142 includes a seventh transistor T7, which can be a P-channel transistor. The first end of the seventh transistor T7 serves as the first end of the first pull-down unit 142, the second end of the seventh transistor T7 serves as the second end of the first pull-down unit 142, and the control end of the seventh transistor T7 serves as the control end of the first pull-down unit 142.

[0084] The shift register further includes an eighth transistor T8, which is a normally-on transistor having a control terminal connected to the second power supply voltage VGL. The second node Q is electrically connected to the control terminal of the seventh transistor T7 via the eighth transistor T8. Setting the eighth transistor T8 can reduce leakage current.

[0085] The first coupling unit 143 includes a first capacitor C1 , a first end of the first capacitor C1 serves as a first end of the first coupling unit 143 , and a second end of the first capacitor C1 serves as a second end of the first coupling unit 143 .

[0086] The third pull-up unit 151 includes a ninth transistor T9, which may be a P-channel transistor. The first end of the ninth transistor T9 serves as the first end of the third pull-up unit 151, the second end of the ninth transistor T9 serves as the second end of the third pull-up unit 151, and the control end of the ninth transistor T9 serves as the control end of the third pull-up unit 151.

[0087] The second pull-up unit 151 includes a ninth transistor T9, which may be a P-channel transistor. The first end of the ninth transistor T9 serves as the first end of the second pull-up unit 151, the second end of the ninth transistor T9 serves as the second end of the second pull-up unit 151, and the control end of the ninth transistor T9 serves as the control end of the second pull-up unit 151.

[0088] The second pull-down unit 152 includes a tenth transistor T10, which may be a P-channel transistor. The first end of the tenth transistor T10 serves as the first end of the second pull-down unit 152, the second end of the tenth transistor T10 serves as the second end of the second pull-down unit 152, and the control end of the tenth transistor T10 serves as the control end of the second pull-down unit 152.

[0089] The second coupling unit 153 includes a second capacitor C2 , a first end of the second capacitor C2 serves as a first end of the second coupling unit 153 , and a second end of the second capacitor C2 serves as a second end of the second coupling unit 153 .

[0090] The shift register also includes an eleventh transistor T11, which is a normally-on transistor. Its control terminal is connected to the second power supply voltage VGL. The second node Q is electrically connected to the control terminal of the tenth transistor T10 through the eleventh transistor T11. Setting the eleventh transistor T11 can reduce leakage current.

[0091] The second control module 13 includes a twelfth transistor T12, which can be a P-channel transistor. The first end of the twelfth transistor T12 serves as the first end of the second control module 13, the second end of the twelfth transistor T12 serves as the second end of the second control module 13, and the control end of the twelfth transistor T12 serves as the control end of the second control module 13.

[0092] Further, Figure 5 A timing diagram of a shift register provided by an embodiment of the present invention, Figure 5 and Figure 4 Correspondingly, the period of each clock signal is TT.

[0093] In the first stage t1, the input signal IN is at a low level, the first clock signal CK1 is at a low level, and the twentieth clock signal CK2 and the third clock signal CK3 are both at a high level. At this time, the first transistor T1 is turned on, and the twelfth transistor T12 is turned off. The input end of the first inverting unit 121 is connected to a low level, so the second transistor T2 is turned on, the third transistor T4 is turned off, and the first node QB is at a high level. In turn, the second node Q is at a low level, the seventh transistor T7 is turned on, the tenth transistor T10 is turned on, and the first output signal Pout1 and the second output signal Pout2 are both at a high level.

[0094] In the second stage t2, the input signal IN is at a high level, the second clock signal CK2 is at a low level, and the first clock signal CK1 is at a high level. At this time, the twelfth transistor T12 is turned on, and the first inverting unit 121 and the second inverting unit 122 form a latch, and the outputs of both remain unchanged. That is, the first node QB remains at a high level, and the second node Q remains at a low level. Then, since the seventh transistor T7 is turned on, the first output signal Pout1 follows the second clock signal CK2 to be at a low level.

[0095] Similarly, in the third stage t3, the input signal IN is at a high level, and the third clock signal CK3 is at a low level. In this stage, the second output signal Pout2 follows the third clock signal CK3 and is at a low level.

[0096] In the next cycle of the clock, that is, when the low level of the first clock signal CK1 comes again, since the input signal IN is at a high level, the input end of the first inverting unit 121 is at a high level, and then the first node QB is at a low level, and the second node Q is at a high level. Then the sixth transistor T6 and the tenth transistor T10 are both turned on, and the first output signal Pout1 and the second output signal Pout2 are both kept at a high level.

[0097] Based on the same inventive concept, the present invention also provides a gate drive circuit, such as Figure 6 As shown, Figure 6 A schematic diagram of the circuit structure of a gate driving circuit provided by an embodiment of the present invention. The gate driving circuit comprises n-stage cascaded shift registers 2 provided by any embodiment of the present invention, where n is an integer greater than 1.

[0098] Specifically, the gate drive circuit can be used to drive multiple rows of pixel circuits in a display panel. In a cascaded two-stage shift register, the output of the previous stage shift register is used as the input of the next stage shift register, wherein the output of the previous stage shift register can be the first output signal Pout1 or the second output signal Pout2, which is not limited in this embodiment. Since the gate drive circuit provided by the embodiment of the present invention includes the shift register provided by the embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0099] Based on the same inventive concept, the present invention also provides a display panel. Figure 7 As shown, Figure 7 A schematic diagram of the structure of a display panel provided in an embodiment of the present invention, the display panel includes a gate drive circuit and 2n rows of pixel circuits provided in any embodiment of the present invention. The first output module of the k-th shift register is used to drive the (2*k-1)-th row of pixel circuits, and the second output module of the k-th shift register is used to drive the (2*k)-th row of pixel circuits.

[0100] Specifically, in this embodiment, the first output signal Pout1 of the shift register can be used as the second scanning signal S2 of the corresponding pixel circuit. The second output signal Pout2 of the shift register can be used as the second scanning signal S2 of the corresponding pixel circuit. That is to say, the first output signal Pout1 of the k-th shift register is used as the second scanning signal S2 corresponding to the (2*k-1)-th row of pixel circuits; the second output signal Pout2 of the k-th shift register is used as the second scanning signal S2 corresponding to the (2*k-1)-th row of pixel circuits. A first-level shift register can provide scanning signals for the same module of two rows of pixel circuits, so the number of shift registers required in the display panel is relatively small, and the border of the display panel can be reduced.

[0101] Optionally, in some embodiments, the display panel may include two gate drive circuits. The two gate drive circuits are located in different frames of the display panel, such as one located in the left frame and the other located in the right frame. By setting two gate drive circuits to jointly drive the pixel circuit, the voltage drop on the scanning signal line corresponding to the pixel circuit in the same row can be reduced, that is, the second scanning signal S2 received by the pixel circuit in the same row is more consistent.

[0102] Optionally, continue to refer to Figure 7 , the display panel includes three clock lines, namely, the first clock line SCK1, the second clock line SCK2 and the third clock line SCK3; the clock signal cycles output by the first clock line SCK1, the second clock line SCK2 and the third clock line SCK3 are the same, and within the same clock cycle, the clock pulse of the second clock line SCK2 is later than the clock pulse of the first clock line SCK1, and the clock pulse of the third clock line SCK3 is later than the clock pulse of the second clock line SCK2;

[0103] In the same level shift register, the first clock signal is provided by the ath clock line, the second clock signal is provided by the bth clock line, and the third clock signal is provided by the cth clock line; wherein, if a is less than or equal to 2, then b is equal to a plus 1; if a is equal to 3, then b is equal to 1; if b is less than or equal to 2, then c is equal to b plus 1; if b is equal to 3, then c is equal to 1;

[0104] In two adjacent shift registers, the first clock signal of the next shift register and the third clock signal of the previous shift register are provided by the same clock line.

[0105] Specifically, in this embodiment, in two adjacent stages of shift registers, the input signal of the shift register of the latter stage is provided by the second output module of the shift register of the previous stage. Figure 8 As shown, Figure 8 for Figure 7Timing diagram of the gate drive circuit in. Exemplarily, for example, the first clock signal CK1 of the first-stage shift register is provided by the first clock line SCK1, the corresponding second clock signal CK2 of the first-stage shift register is provided by the second clock line SCK2, and the third clock signal CK3 of the first-stage shift register is provided by the third clock line SCK3. The first clock signal CK1 of the second-stage shift register is provided by the third clock line SCK3, the second clock signal CK2 of the second-stage shift register is provided by the first clock line SCK1, and the third clock signal CK3 of the second-stage shift register is provided by the second clock line SCK2. Then, the pulse of the first output signal Pout1 of the first-stage shift register is the pulse of the second clock signal in the first clock cycle, the pulse of the second output signal Pout2 of the first-stage shift register is the pulse of the third clock signal in the first clock cycle, the first output signal Pout1 of the second-stage shift register is the pulse of the first clock signal in the second clock cycle, and the second output signal Pout2 of the second-stage shift register is the pulse of the second clock signal in the second clock cycle. That is to say, the output signals output by the gate driving circuit do not overlap in timing, and are shifted signals in sequence, which can meet the driving requirements of multiple rows of pixel circuits.

[0106] Optionally, Fig. 9 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig.10 for Fig. 9 For the timing diagram of the gate drive circuit in Fig. 9 and Fig.10 The display panel further includes four clock lines, namely, the first clock line SCK1, the second clock line SCK2, the third clock line SCK3 and the fourth clock line SCK4; the clock signal cycles output by the first clock line SCK1, the second clock line SCK2, the third clock line SCK3 and the fourth clock line SCK4 are the same, and within the same clock cycle, the clock pulse of the second clock line SCK2 is later than the clock pulse of the first clock line SCK1, and the clock pulse of the third clock line SCK3 is later than the clock pulse of the fourth clock line SCK4. The clock pulse of the 2nd clock line SCK2 and the clock pulse of the 4th clock line SCK4 are later than the clock pulse of the 3rd clock line SCK3; in the same level shift register, the first clock signal is provided by the ath clock line, the second clock signal is provided by the bth clock line, and the third clock signal is provided by the cth clock line; wherein, if a is less than or equal to 2, then b is equal to a plus 2; if a is greater than or equal to 3, then b is equal to a plus 2 minus 4; if b is less than or equal to 3, then c is equal to b plus 1; if b is equal to 4, then c is equal to 1;

[0107] In two adjacent shift registers, the first clock signal of the subsequent shift register and the second clock signal of the previous shift register are provided by the same clock line.

[0108] Specifically, in the present embodiment, in the two adjacent shift registers, the input signal of the shift register of the next stage is provided by the first output module of the shift register of the previous stage. That is, the first output signal Pout1 of the previous stage is used as the input signal IN of the next stage. Exemplarily, for example, the first clock signal CK1 of the first stage shift register is provided by the first clock line SCK1, the corresponding second clock signal CK2 of the first stage shift register is provided by the third clock line SCK3, and the third clock signal CK3 of the first stage shift register is provided by the fourth clock line SCK3. The first clock signal CK1 of the second stage shift register is provided by the third clock line SCK3, the second clock signal CK2 of the second stage shift register is provided by the first clock line SCK1, and the third clock signal CK3 of the second stage shift register is provided by the second clock line SCK2. Then, the pulse of the first output signal Pout1 of the first-stage shift register is the pulse of the third clock line in the first clock cycle, the pulse of the second output signal Pout2 of the first-stage shift register is the pulse of the fourth clock line in the first clock cycle, the first output signal Pout1 of the second-stage shift register is the pulse of the first clock line in the second clock cycle, and the second output signal Pout2 of the second-stage shift register is the pulse of the second clock line in the second clock cycle. In other words, the output signals output by the gate drive circuit do not overlap in timing, and are shifted signals in sequence, which can meet the driving requirements of multiple rows of pixel circuits.

[0109] Optionally, Fig.11 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig.12 for Fig.11 For the timing diagram of the gate drive circuit in Fig.11 and Fig.12The display panel also includes 6 clock lines, namely, the 1st clock line SCK1, the 2nd clock line SCK2, the 3rd clock line SCK3, the 4th clock line SCK4, the 5th clock line SCK5 and the 6th clock line SCK6; the clock signal cycles output by the 1st clock line SCK1, the 2nd clock line SCK2, the 3rd clock line SCK3, the 4th clock line SCK4, the 5th clock line SCK5 and the 6th clock line SCK6 are the same, and in the same clock cycle, the clock pulse of the 2nd clock line SCK2 is later than the clock pulse of the 1st clock line SCK1, the clock pulse of the 3rd clock line SCK3 is later than the clock pulse of the 2nd clock line SCK2, the clock pulse of the 4th clock line SCK4 is later than the clock pulse of the 3rd clock line SCK3, the clock pulse of the 5th clock line SCK5 is later than the clock pulse of the 4th clock line SCK4, and the clock pulse of the 6th clock line SCK6 is later than the clock pulse of the 5th clock line SCK5. The clock pulse of SCK6 is later than the clock pulse of the fifth clock line SCK5; in the adjacent three-stage shift register, the first clock signal of the first-stage shift register is provided by the j1-th clock line, where j1 is an odd number less than or equal to 5; the first clock signal of the second-stage shift register is provided by the j2-th clock line; the first clock signal of the third-stage shift register is provided by the j3-th clock line; wherein, if j1 is less than or equal to 3, then j2 is equal to j1 plus 2, and if j1 is equal to 5, then j2 is equal to 1; if j2 is less than or equal to 3, then j3 is equal to j2 plus 2, and if j2 is equal to 5, then j3 is equal to 1; in the adjacent two-stage shift register, the first clock signal of the shift register of the latter stage and the second clock signal of the shift register of the previous stage are provided by the same clock line; in the shift register of the same stage, the second clock signal is provided by the a-th clock line, and the third clock signal is provided by the b-th clock line, and b is equal to a plus 1;

[0110] Preferably, in two adjacent stages of shift registers, the input signal of the shift register of the latter stage is provided by the first output module of the shift register of the former stage.

[0111] Specifically, in the present embodiment, in the two adjacent shift registers, the input signal of the shift register of the next stage is provided by the first output module of the shift register of the previous stage. That is, the first output signal Pout1 of the previous stage is used as the input signal IN of the next stage. Exemplarily, for example, the first clock signal CK1 of the first stage shift register is provided by the first clock line SCK1, the corresponding second clock signal CK2 of the first stage shift register is provided by the third clock line SCK3, and the third clock signal CK3 of the first stage shift register is provided by the fourth clock line SCK3. The first clock signal CK1 of the second stage shift register is provided by the third clock line SCK3, the second clock signal CK2 of the second stage shift register is provided by the fifth clock line SCK5, and the third clock signal CK3 of the second stage shift register is provided by the sixth clock line SCK6. The first clock signal of the third-stage shift register is provided by the fifth clock line SCK3, the second clock signal of the third-stage shift register is provided by the first clock line SCK1, and the third clock signal of the third-stage shift register is provided by the second clock line SCK2. Then, the pulse of the first output signal Pout1 of the first-stage shift register is the pulse of the third clock line in the first clock cycle, and the pulse of the second output signal Pout2 of the first-stage shift register is the pulse of the fourth clock line in the first clock cycle; the first output signal Pout1 of the second-stage shift register is the pulse of the fifth clock line in the first clock cycle, and the second output signal Pout2 of the second-stage shift register is the pulse of the sixth clock line in the first clock cycle; the first output signal Pout1 of the third-stage shift register is the pulse of the first clock line in the second clock cycle, and the second output signal Pout2 of the third-stage shift register is the pulse of the second clock line in the second clock cycle. That is to say, the output signals output by the gate drive circuit do not overlap in timing, and are shifted signals in sequence, which can meet the driving requirements of multiple rows of pixel circuits.

[0112] The present invention also provides a display device, such as Fig.13 As shown, Fig.13 A schematic diagram of the structure of a display device provided in an embodiment of the present invention. The display device includes a display panel provided in any embodiment of the present invention. The display device may be a mobile phone, a tablet computer, an MP3, an MP4, a smart watch, a smart helmet, a videophone, a personal digital assistant or other wearable device. Since the display device provided in an embodiment of the present invention includes the display panel provided in an embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0113] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0114] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A shift register, characterized in that: The shift register comprises: An input module, a first control module, a second control module, a first output module, and a second output module; The input module is used to transmit the input signal to the input end of the first control module and the first end of the second control module according to the first clock signal; the first control module is used to transmit the signal which is logically opposite to its control end to the first node; and transmit the signal which is logically opposite to the first node to the second node; The second control module is used to transmit the signal at its first end to the second node according to the first clock signal; wherein the conduction level logic of the second control module is opposite to that of the input module; The first output module is used to output a first power supply voltage according to the signal of the first node, and to output a second clock signal according to the signal of the second node; The second output module is used to output the first power supply voltage according to the signal of the first node, and to output a third clock signal according to the signal of the second node.

2. The shift register according to claim 1, characterized in that: The first control module includes a first inverting unit and a second inverting unit, the input end of the first inverting unit is electrically connected to the input end of the first control module, and the output end of the first inverting unit is electrically connected to the first node; the input end of the second inverting unit is electrically connected to the first node, and the output end of the second inverting unit is electrically connected to the second node; Preferably, the first inverting unit comprises a first sub-switch and a second sub-switch, a control end of the first sub-switch is electrically connected to a control end of the second sub-switch and serves as an input end of the first inverting unit, a first end of the first sub-switch is electrically connected to a second end of the second sub-switch and serves as an output end of the first inverting unit, a second end of the first sub-switch is connected to a first power supply voltage, and a second end of the second sub-switch is connected to a second power supply voltage; the transistor channel types of the first sub-switch and the second sub-switch are different, and the transistor channel type of the first sub-switch and the input module is the same; Preferably, the second inverting unit comprises a third sub-switch and a fourth sub-switch, the control end of the third sub-switch is electrically connected to the control end of the fourth sub-switch and serves as the input end of the second inverting unit, the first end of the third sub-switch is electrically connected to the second end of the fourth sub-switch and serves as the output end of the second inverting unit, the second end of the third sub-switch is connected to the first power supply voltage, and the second end of the fourth sub-switch is connected to the second power supply voltage; the transistor channel type of the third sub-switch is different from that of the fourth sub-switch, and the transistor channel type of the third sub-switch is the same as that of the input module; Preferably, the first end of the input module is connected to the input signal, the second end of the input module is electrically connected to the input end of the first inverting unit and the first end of the second control module, and the control end of the input module is connected to the first clock signal; the second end of the second control module is electrically connected to the second node, and the control end of the second control module is connected to the first clock signal.

3. The shift register according to claim 1, wherein: The first output module includes a first pull-up unit, a first pull-down unit and a first coupling unit, wherein a first end of the first pull-up unit is connected to the first power supply voltage, a control end of the first pull-up unit is electrically connected to the first node, and a second end of the first pull-up unit is electrically connected to an output end of the first output module; a first end of the first pull-down unit is connected to the second clock signal, a control end of the first pull-down unit is electrically connected to the second node, and a second end of the first pull-down unit is electrically connected to an output end of the first output module; a first end of the first coupling unit is electrically connected to a second end of the first pull-down unit, and a second end of the first coupling unit is electrically connected to a control end of the first pull-down unit.

4. The shift register according to claim 1, wherein: The second output module includes a second pull-up unit, a second pull-down unit and a second coupling unit; the first end of the second pull-up unit is connected to the first power supply voltage, the control end of the second pull-up unit is electrically connected to the first node, and the second end of the second pull-up unit is electrically connected to the output end of the second output module; the first end of the second pull-down unit is connected to the second clock signal, the control end of the second pull-down unit is electrically connected to the second node, and the second end of the second pull-down unit is electrically connected to the output end of the second output module; the first end of the second coupling unit is electrically connected to the second end of the second pull-down unit, and the second end of the second coupling unit is electrically connected to the control end of the second pull-down unit; Preferably, the periods of the first clock signal, the second clock signal and the third clock signal are the same; the duty cycles of the same level in each of the clock signals are the same; within the same period, the on-level of the second clock signal is later than the on-level of the first clock signal, and the on-level of the third clock signal is later than the on-level of the second clock signal.

5. A gate drive circuit, characterized in that: The gate drive circuit comprises n-stage cascaded shift registers as described in any one of claims 1 to 4; n is an integer greater than 1.

6. A display panel, characterized in that: The display panel comprises the gate driving circuit according to claim 5 and 2n rows of pixel circuits; The first output module of the k-th shift register is used to drive the (2*k-1)-th row of pixel circuits, and the second output module of the k-th shift register is used to drive the (2*k)-th row of pixel circuits.

7. The display panel according to claim 6, characterized in that: The display panel also includes three clock lines; In the shift register of the same level, the first clock signal is provided by the ath clock line, the second clock signal is provided by the bth clock line, and the third clock signal is provided by the cth clock line; wherein, if a is less than or equal to 2, b is equal to a plus 1; if a is equal to 3, b is equal to 1; if b is less than or equal to 2, c is equal to b plus 1; if b is equal to 3, c is equal to 1; In two adjacent stages of the shift register, the first clock signal of the shift register of the latter stage and the third clock signal of the shift register of the former stage are provided by the same clock line.

8. The display panel according to claim 7, characterized in that: In two adjacent stages of the shift register, the input signal of the shift register of the latter stage is provided by the second output module of the shift register of the former stage.

9. The display panel according to claim 6, characterized in that: The display panel also includes 4 clock lines; In the shift register of the same level, the first clock signal is provided by the ath clock line, the second clock signal is provided by the bth clock line, and the third clock signal is provided by the cth clock line; wherein, if a is less than or equal to 2, b is equal to a plus 2; if a is greater than or equal to 3, b is equal to a plus 2 minus 4; if b is less than or equal to 3, c is equal to b plus 1; if b is equal to 4, c is equal to 1; In two adjacent stages of the shift register, the first clock signal of the shift register of the latter stage and the second clock signal of the shift register of the former stage are provided by the same clock line; Preferably, in two adjacent stages of the shift register, the input signal of the shift register of the latter stage is provided by the first output module of the shift register of the former stage.

10. The display panel according to claim 6, characterized in that: The display panel also includes six clock lines; In the three adjacent shift registers, the first clock signal of the first shift register is provided by the j1th clock line, where j1 is an odd number less than or equal to 5; the first clock signal of the second shift register is provided by the j2th clock line; the first clock signal of the third shift register is provided by the j3th clock line; wherein, if j1 is less than or equal to 3, j2 is equal to j1 plus 2, and if j1 is equal to 5, j2 is equal to 1; if j2 is less than or equal to 3, j3 is equal to j2 plus 2, and if j2 is equal to 5, j3 is equal to 1; in the two adjacent shift registers, the first clock signal of the shift register of the latter stage and the second clock signal of the shift register of the previous stage are provided by the same clock line; in the shift register of the same stage, the second clock signal is provided by the ath clock line, and the third clock signal is provided by the bth clock line, and b is equal to a plus 1; Preferably, in two adjacent stages of the shift register, the input signal of the shift register of the latter stage is provided by the first output module of the shift register of the former stage.

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