Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises at least one electronic circuit, a scanning line and a scanning signal conversion circuit. The scanning line transmits a first scanning signal. The scanning signal conversion circuit is electrically connected to the at least one electronic circuit and the scanning line. The scanning signal conversion circuit receives a first scanning signal, converts the first scanning signal into a second scanning signal, and provides the second scanning signal to the at least one electronic circuit.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device capable of adjusting a scan signal located on a scan line. Background Art

[0002] The current electronic device may include a plurality of electronic circuits. The electronic device may sequentially provide scan signals to the electronic circuits via scan lines to drive the electronic circuits. The electronic circuits may be selected according to the scan signals on the scan lines. The selected electronic circuits may operate according to the received data signals.

[0003] As the resolution of an electronic device increases, the width of the scan line becomes shorter and the length of the scan line becomes shorter. This makes it easy for the scan signal to be delayed or distorted due to the resistance and / or capacitance associated with the scan line. Once the scan signal is significantly delayed or distorted, the operation of the electronic circuit may become abnormal. Summary of the invention

[0004] The present disclosure is directed to an electronic device capable of adjusting a scan signal located on a scan line.

[0005] According to an embodiment of the present disclosure, an electronic device includes at least one electronic circuit, a scan line, and a scan signal conversion circuit. The scan line transmits a first scan signal. The scan signal conversion circuit is electrically connected to the at least one electronic circuit and the scan line. The scan signal conversion circuit receives the first scan signal, converts the first scan signal into a second scan signal, and provides the second scan signal to the at least one electronic circuit.

[0006] Based on the above, the scanning signal conversion circuit converts the first scanning signal into the second scanning signal. The scanning signal conversion circuit can adjust the first scanning signal located on the scanning line to the second scanning signal. The electronic circuit receives the second scanning signal. In this way, the operation of the electronic circuit will not be abnormal due to the delay or distortion of the first scanning signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0009] Figure 3 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0010] Figure 4is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0011] Figure 5 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0012] Figure 6 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0013] Figure 7 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0014] Figure 8 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0015] Fig. 9 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0016] Fig.10 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0017] Fig.11 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0018] Fig.12 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0019] Fig.13 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0020] Fig.14 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure;

[0021] Fig.15 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0022] Fig.16 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0023] Description of Reference Numerals

[0024] 100, 200, 300: Electronic devices

[0025] 110_1 to 110_n, 210, 310, 410, 510, 610, 710, 810, 910, 1010, 1110, 1210, 1310, 1410: scanning signal conversion circuit

[0026] 220: Scanning drive circuit

[0027] EE: Electronic Components

[0028] GU1~GUn:Electronic circuit group

[0029] IB: Current Source

[0030] IVT1: First inverter

[0031] IVT2: Second inverter

[0032] LS: Scan Line

[0033] N1, N2, N3, N4, NB: N-type transistors

[0034] P1, P2, P3, P4: P-type transistors

[0035] OPA1: Operational Amplifier

[0036] R1, R2, RB: Resistors

[0037] SC: Select Circuit

[0038] SD, SD1, SDn: data signal

[0039] SS: First scanning signal

[0040] SS', SS1'~SSn': second scanning signal

[0041] SW: Switch

[0042] td1, tdn: scanning delay

[0043] TS: Select transistor

[0044] U, U1~Un: electronic circuit

[0045] VGH, VGH1, VGH2: Reference high voltage

[0046] VGL: Reference low voltage DETAILED DESCRIPTION

[0047] The present disclosure may be understood by reference to the following detailed description in conjunction with the accompanying drawings as described below. It should be noted that for the purpose of clarity and ease of understanding by the reader, the various drawings of the present disclosure illustrate a portion of an electronic device, and certain elements in the various drawings may not be drawn to scale. In addition, the number and size of each device shown in the drawings are merely illustrative and are not intended to limit the scope of the present disclosure.

[0048] Certain terms are used to refer to specific elements throughout the description and in the following scope of rights. As will be understood by those skilled in the art, electronic equipment manufacturers may refer to elements by different names. This document is not intended to distinguish between elements that are different in name but not in function. In the following description and in the scope of rights, the terms "comprise", "include" and "have" are used in an open manner, and therefore should be interpreted as meaning "including but not limited to..." Therefore, when the terms "comprise", "include" and / or "have" are used in the description of this disclosure, it will indicate that there are corresponding features, regions, steps, operations and / or elements, but not limited to the presence of one or more corresponding features, regions, steps, operations and / or elements.

[0049] It should be understood that when an element is referred to as being "coupled to", "connected to" or "conducted to" another element, the element may be directly connected to the other element and an electrical connection may be directly established, or an intermediate element may exist between these elements for relaying the electrical connection (indirect electrical connection). In contrast, when an element is referred to as being "directly coupled to", "directly conductive to" or "directly connected to" another element, there are no intermediate elements.

[0050] Although terms such as first, second, third, etc. can be used to describe different components, such components are not limited by these terms. The terms are only used to distinguish components in the specification from other components. The scope of rights protection may not use the same terms, but may use the terms first, second, third, etc. relative to the order required for the elements. Therefore, in the following description, the first component may be the second component in the scope of rights protection.

[0051] The electronic device disclosed herein may include a display device, an antenna device, a sensing device, a light-emitting device, a touch display, a curved display, or a free shape display, but is not limited thereto. The electronic device may include a bendable or flexible electronic device. The electronic device may, for example, include a liquid crystal, a light-emitting diode, a quantum dot (QD), fluorescence, phosphorescence, other suitable display media, or a combination of the above materials, but is not limited thereto. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (miniLED), a micro-light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED, which may include QLED, QDLED), or other suitable materials, or a combination of the above materials, but is not limited thereto. The display device may, for example, include a spliced ​​display device, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, or a splicing device, but the present disclosure is not limited thereto. The sensing device may include a camera or an infrared sensor (infrared sensor) or a fingerprint sensor, etc., and the present disclosure is not limited thereto. In some embodiments, the sensing device may also include a flash, an infrared (IR) light source, other sensors, an electronic circuit, or a combination thereof, but is not limited thereto.

[0052] In the present disclosure, embodiments use "electronic circuit", "pixel" or "pixel unit" as a unit for describing a specific area including at least one functional circuit for at least one specific function. The area of ​​a "pixel" depends on the unit used to provide a specific function, and adjacent pixels may share the same part or wire, but may also include their own specific part therein. For example, adjacent pixels may share the same scan line or the same data line, but the pixel may also have its own transistor or capacitor.

[0053] It should be noted that the technical features in the different embodiments described below may be replaced, reorganized or mixed with each other to constitute another embodiment without departing from the spirit of the present disclosure.

[0054] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 100 at least includes electronic circuits U1 to Un, scan lines LS, and scan signal conversion circuits 110_1 to 110_n. The scan lines LS transmit a first scan signal SS. In this embodiment, the scan signal conversion circuit 110_1 is electrically connected to the scan lines LS and the electronic circuit U1. The scan signal conversion circuit 110_2 is electrically connected to the scan lines LS1 and the electronic circuit U2, and so on.

[0055] In the present embodiment, the scan signal conversion circuit 110_1 receives the first scan signal SS located at the scan line LS, and converts the first scan signal SS into a second scan signal SS1'. The scan signal conversion circuit 110_1 provides the second scan signal SS1' to the electronic circuit U11. The scan signal conversion circuit 110_2 receives the first scan signal SS located at the scan line LS, and converts the first scan signal SS into a second scan signal SS2'. The scan signal conversion circuit 110_2 provides the second scan signal SS2' to the electronic circuit U2. Similarly, the scan signal conversion circuit 110_n receives the first scan signal SS located at the scan line LS, and converts the first scan signal SS into a second scan signal SSn'. The scan signal conversion circuit 110_n provides the second scan signal SSn' to the electronic circuit Un.

[0056] It is worth mentioning that the scan signal conversion circuits 110_1-110_n can adjust the received first scan signal SS into the second scan signal SS1'-SSn'. The electronic circuits U1-Un receive the corresponding one of the second scan signals SS1'-SSn'. In this way, the operation of the electronic circuits U1-Un will not be abnormal due to the delay or distortion of the first scan signal SS.

[0057] In this embodiment, the electronic device 100 is a display device, an antenna device, a sensing device, a light emitting device or a touch electronic device, but the disclosure is not limited thereto. The electronic circuits U1 to Un can be pixel circuits, touch units or light emitting circuits, respectively, but the disclosure is not limited thereto.

[0058] The number of scan lines disclosed herein may be one or more. The number of scan lines disclosed herein may be one or more. The number of scan signal conversion circuits disclosed herein and the number of scan signal conversion circuits disclosed herein may be changed accordingly according to the number of scan lines. The disclosure is not limited to the number of electronic circuits, the number of scan lines, and the number of scan signal conversion circuits.

[0059] The following is an example of an implementation of the scan signal conversion circuit disclosed herein.

[0060] Please refer to Figure 2 , Figure 2 It is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In the present embodiment, the scan signal conversion circuit 210 includes a first inverter IVT1 and a second inverter IVT2. The first inverter IVT1 and the second inverter IVT2 are electrically connected in a cascade manner. Specifically, the input end of the first inverter IVT1 receives the first scan signal SS. The input end of the second inverter IVT2 is electrically connected to the output end of the first inverter IVT1. The output end of the second inverter IVT2 is electrically connected to the electronic circuit U and outputs the second scan signal SS'. In the present embodiment, the first inverter IVT1 is implemented by a first complementary metal oxide semiconductor (CMOS) circuit. The second inverter IVT2 is implemented by a second CMOS circuit.

[0061] In the present embodiment, the first inverter IVT1 includes a P-type transistor P1 and an N-type transistor N1. The first end of the P-type transistor P1 is electrically connected to the reference high voltage VGH. The control end of the P-type transistor P1 receives the first scan signal SS. The first end of the N-type transistor N1 is electrically connected to the second end of the P-type transistor P1. The second end of the N-type transistor N1 is electrically connected to the reference low voltage VGL. The control end of the N-type transistor N1 receives the first scan signal SS.

[0062] The second inverter IVT2 includes a P-type transistor P2 and an N-type transistor N2. The first end of the P-type transistor P2 is electrically connected to the reference high voltage VGH. The second end of the P-type transistor P2 is electrically connected to the electronic circuit U. The control end of the P-type transistor P2 is electrically connected to the second end of the P-type transistor P1. The first end of the N-type transistor N2 is electrically connected to the second end of the P-type transistor P2. The second end of the N-type transistor N2 is electrically connected to the reference low voltage VGL. The control end of the N-type transistor N2 is electrically connected to the second end of the P-type transistor P1.

[0063] In this embodiment, the first inverter IVT1 can provide an inverted signal according to the first scan signal SS, and the second inverter IVT2 can provide a second scan signal SS′ according to the inverted signal.

[0064] Generally speaking, during the transmission of the first scan signal SS, the waveform of the first scan signal SS changes according to the resistance value and / or capacitance value of the scan line LS. Therefore, the rising edge and the falling edge of the first scan signal SS are delayed. After the conversion of the first inverter IVT1 and the second inverter IVT2, the delay of the rising edge and the delay of the falling edge of the second scan signal SS' are eliminated. In other words, the rising edge and the falling edge of the second scan signal SS' are reconstructed.

[0065] In this embodiment, the electronic circuit U includes an electronic element EE and a selection circuit SC. The selection circuit SC is electrically connected to the scan signal conversion circuit 210 and the electronic element EE. The selection circuit SC receives the second scan signal SS' and the data signal SD, and provides the data signal SD to the electronic element EE according to the second scan signal SS'. The electronic element EE operates according to the data signal SD.

[0066] In the present embodiment, the selection circuit SC includes a selection transistor TS. The first end of the selection transistor TS receives the data signal SD. The second end of the selection transistor TS is electrically connected to the electronic element EE. The control end of the selection transistor TS receives the second scan signal SS'. For example, the selection transistor TS can be implemented by an N-type transistor. Therefore, when the voltage value of the second scan signal SS' is a high voltage level, the selection transistor TS is turned on to transmit the data signal SD. The electronic element EE can receive the data signal SD through the selection transistor TS. When the voltage value of the second scan signal SS' is a low voltage level, the selection transistor TS is disconnected. In some embodiments, the selection transistor TS can be implemented by a P-type transistor.

[0067] In this embodiment, the data signal SD may be a voltage signal, a current signal or a pulse width modulation (PWM) signal. The electronic element EE may include a liquid crystal element, a light emitting element or a modulation element. The modulation element may be a variable capacitor or a variable resistor.

[0068] In this embodiment, based on actual needs, the layout area of ​​the P-type transistor P2 and the N-type transistor N2 or the width-to-length ratio of the transistor channel can be adjusted. For example, in order to adjust the impedance of the scan signal conversion circuit 210, the layout area of ​​the P-type transistor P2 or the width-to-length ratio of the transistor channel can be greater than or equal to the layout area of ​​the P-type transistor P1 or the width-to-length ratio of the transistor channel. The layout area of ​​the N-type transistor N2 or the width-to-length ratio of the transistor channel can be greater than or equal to the layout area of ​​the N-type transistor N1 or the width-to-length ratio of the transistor channel.

[0069] Please refer to Figure 3 , Figure 3 It is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 310 includes a first inverter IVT1 and a second inverter IVT2. The first inverter IVT1 and the second inverter IVT2 are electrically connected in a cascade manner. The first inverter IVT1 includes a resistor R1 and an N-type transistor N1. The first end of the resistor R1 is electrically connected to a reference high voltage VGH. The first end of the N-type transistor N1 is electrically connected to the second end of the resistor R1. The second end of the N-type transistor N1 is electrically connected to a reference low voltage VGL. The control end of the N-type transistor N1 receives a first scan signal SS.

[0070] The second inverter IVT2 includes a resistor R2 and an N-type transistor N2. The first end of the resistor R2 is electrically connected to the reference high voltage VGH. The first end of the N-type transistor N2 is electrically connected to the second end of the resistor R2 and the output end of the second inverter IVT2. The second end of the N-type transistor N2 is electrically connected to the reference low voltage VGL. The control end of the N-type transistor N2 is electrically connected to the first end of the N-type transistor N1.

[0071] In this embodiment, the operations of the first inverter IVT1 and the second inverter IVT2 are similar to Figure 2 The operation of the embodiment of the present invention is not repeated here.

[0072] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0073] Please refer to Figure 4 , Figure 4Schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In the present embodiment, the scan signal conversion circuit 410 includes a first inverter IVT1 and a second inverter IVT2. The first inverter IVT1 and the second inverter IVT2 are electrically connected in a cascade manner. The first inverter IVT1 includes a P-type transistor P1 and a resistor R1. The first end of the P-type transistor P1 is electrically connected to a reference high voltage VGH. The control end of the P-type transistor P1 receives a first scan signal SS. The resistor R1 is electrically connected between the second end of the P-type transistor P1 and the reference low voltage VGL. The second inverter IVT2 includes a P-type transistor P2 and a resistor R2. The first end of the P-type transistor P2 is electrically connected to the reference high voltage VGH. The second end of the P-type transistor P2 is electrically connected to the output end of the second inverter IVT2. The control end of the P-type transistor P2 is electrically connected to the second end of the P-type transistor P1. The resistor R2 is electrically connected between the second end of the P-type transistor P2 and the reference low voltage VGL.

[0074] In this embodiment, the operations of the first inverter IVT1 and the second inverter IVT2 are similar to Figure 2 The operation of the embodiment of the present invention is not repeated here.

[0075] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0076] Please refer to Figure 5 , Figure 5 It is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 510 includes a first inverter IVT1 and a second inverter IVT2. The first inverter IVT1 and the second inverter IVT2 are electrically connected in a cascade manner. The first inverter IVT1 includes a resistor R1 and an N-type transistor N1. The first end of the resistor R1 is electrically connected to a reference high voltage VGH. The first end of the N-type transistor N1 is electrically connected to the second end of the resistor R1. The second end of the N-type transistor N1 is electrically connected to a reference low voltage VGL, and the control end of the N-type transistor N1 receives a first scan signal SS.

[0077] In the present embodiment, the resistor R1 includes an N-type transistor N3. A first end of the N-type transistor N3 is electrically connected to a control end of the N-type transistor N3 and a reference high voltage VGH. A second end of the N-type transistor N3 is electrically connected to a first end of the N-type transistor N1. In other words, the N-type transistor N3 is electrically connected between the reference high voltage VGH and the first end of the N-type transistor N1 in a diode connection manner.

[0078] The second inverter IVT2 includes a resistor R2 and an N-type transistor N2. The first end of the resistor R2 is electrically connected to the reference high voltage VGH. The first end of the N-type transistor N2 is electrically connected to the second end of the resistor R2. The second end of the N-type transistor N2 is electrically connected to the reference low voltage VGL, and the control end of the N-type transistor N2 receives the first scan signal SS.

[0079] In the present embodiment, the resistor R2 includes an N-type transistor N4. A first end of the N-type transistor N4 is electrically connected to a control end of the N-type transistor N4 and a reference high voltage VGH. A second end of the N-type transistor N4 is electrically connected to a first end of the N-type transistor N2. In other words, the N-type transistor N4 is electrically connected between the reference high voltage VGH and the first end of the N-type transistor N2 in a diode connection manner.

[0080] In this embodiment, the operations of the first inverter IVT1 and the second inverter IVT2 are similar to Figure 2 The operation of the embodiment of the present invention is not repeated here.

[0081] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0082] Please refer to Figure 6 , Figure 6 It is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 610 includes a first inverter IVT1 and a second inverter IVT2. The first inverter IVT1 and the second inverter IVT2 are electrically connected in a cascade manner. The first inverter IVT1 includes a P-type transistor P1 and a resistor R1. The first end of the P-type transistor P1 is electrically connected to a reference high voltage VGH. The control end of the P-type transistor P1 receives a first scan signal SS. The resistor R1 is electrically connected between the second end of the P-type transistor P1 and the reference low voltage VGL.

[0083] In the present embodiment, the resistor R1 includes a P-type transistor P3. The first end of the P-type transistor P3 is electrically connected to the second end of the P-type transistor P1. The second end of the P-type transistor P3 is electrically connected to the control end of the P-type transistor P3 and the reference low voltage VGL. In other words, the P-type transistor P3 is electrically connected between the second end of the P-type transistor P1 and the reference low voltage VGL in a diode connection manner.

[0084] The second inverter IVT2 includes a P-type transistor P2 and a resistor R2. The first end of the P-type transistor P2 is electrically connected to the reference high voltage VGH. The second end of the P-type transistor P2 is electrically connected to the output end of the second inverter IVT2. The control end of the P-type transistor P2 is electrically connected to the second end of the P-type transistor P1. The resistor R2 is electrically connected between the second end of the P-type transistor P2 and the reference low voltage VGL.

[0085] In the present embodiment, the resistor R2 includes a P-type transistor P4. The first end of the P-type transistor P4 is electrically connected to the second end of the P-type transistor P2. The second end of the P-type transistor P4 is electrically connected to the control end of the P-type transistor P4 and the reference low voltage VGL. In other words, the P-type transistor P4 is electrically connected between the second end of the P-type transistor P2 and the reference low voltage VGL in a diode connection manner.

[0086] In this embodiment, the operations of the first inverter IVT1 and the second inverter IVT2 are similar to Figure 2 The operation of the embodiment of the present invention is not repeated here.

[0087] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0088] Please refer to Figure 7 , Figure 7 Schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 710 can be implemented by a level shifter. The scan signal conversion circuit 710 includes a first inverter IVT1, a second inverter IVT2, a resistor R1, and a P-type transistor P3.

[0089] In the present embodiment, the input end of the first inverter IVT1 receives the first scan signal SS. The input end of the second inverter IVT2 is electrically connected to the output end of the first inverter IVT1. The output end of the second inverter IVT2 is electrically connected to the electronic circuit U and outputs the second scan signal SS'. The first inverter IVT1 is implemented by a first complementary metal oxide semiconductor (CMOS) circuit. The second inverter IVT2 is implemented by a second CMOS circuit. The resistor R1 is electrically connected between the reference high voltage VGH2 and the high voltage end of the first inverter IVT1. The first end of the P-type transistor P3 is electrically connected to the reference high voltage VGH2. The second end of the P-type transistor P3 is electrically connected to the high voltage end of the first inverter IVT1. The control end of the P-type transistor P3 is electrically connected to the output end of the second inverter IVT2.

[0090] In the present embodiment, the resistor R1 includes an N-type transistor N3. A first end of the N-type transistor N3 is electrically connected to a control end of the N-type transistor N3 and a reference high voltage VGH2. A second end of the N-type transistor N3 is electrically connected to a high voltage end of the first inverter IVT1. In other words, the N-type transistor N3 is electrically connected between the reference high voltage VGH2 and the high voltage end of the first inverter IVT1 in a diode connection manner.

[0091] In the present embodiment, the first inverter IVT1 includes a P-type transistor P1 and an N-type transistor N1. The first end of the P-type transistor P1 serves as a high voltage end of the first inverter IVT1 and is electrically connected to the second end of the N-type transistor N3. The control end of the P-type transistor P1 receives a first scan signal SS. The first end of the N-type transistor N1 is electrically connected to the second end of the P-type transistor P1. The second end of the N-type transistor N1 is electrically connected to a reference low voltage VGL. The control end of the N-type transistor N1 receives the first scan signal SS.

[0092] The second inverter IVT2 includes a P-type transistor P2 and an N-type transistor N2. The first end of the P-type transistor P2 is electrically connected to the reference high voltage VGH2. The second end of the P-type transistor P2 is electrically connected to the electronic circuit U and the control end of the P-type transistor P3. The control end of the P-type transistor P2 is electrically connected to the second end of the P-type transistor P1. The first end of the N-type transistor N2 is electrically connected to the second end of the P-type transistor P2. The second end of the N-type transistor N2 is electrically connected to the reference low voltage VGL. The control end of the N-type transistor N2 is electrically connected to the second end of the P-type transistor P1.

[0093] In the present embodiment, the resistor R1 provides a reference high voltage VGH1 to the high voltage end of the first inverter IVT1 (i.e., the first end of the P-type transistor P1). The voltage value of the reference high voltage VGH1 is lower than the voltage value of the reference high voltage VGH2. When the voltage value of the first scan signal SS is a low voltage level, the voltage value of the second scan signal SS' is a low voltage level. The P-type transistor P3 is turned on. At this time, the voltage value at the first end of the P-type transistor P1 is substantially equal to the reference high voltage VGH2.

[0094] On the other hand, when the voltage value of the first scan signal SS is a high voltage level, the voltage value of the second scan signal SS' is a high voltage level. The P-type transistor P3 is disconnected. At this time, the voltage value at the first end of the P-type transistor P1 drops from the reference high voltage VGH2 to the reference high voltage VGH1. Therefore, when the voltage value of the first scan signal SS is a high voltage level, the voltage value at the first end of the P-type transistor P1 is reduced. In this way, the scan signal conversion circuit 710 can effectively disconnect the P-type transistor P1.

[0095] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0096] Please refer to Figure 8 , Figure 8 8 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 810 can be implemented by an analog buffer. The scan signal conversion circuit 810 includes a switch SW and a current source IB. The first end of the switch SW is electrically connected to the reference high voltage VGH. The second end of the switch SW is electrically connected to the electronic circuit U. The control end of the switch SW receives the first scan signal SS. The current source IB is electrically connected between the second end of the switch SW and the reference low voltage VGL.

[0097] In the present embodiment, when the voltage value of the first scan signal SS is a high voltage value, the switch SW is turned on. The second end of the switch SW outputs a second scan signal SS' having a high voltage value. When the voltage value of the first scan signal SS is a low voltage value, the switch SW is turned off. The second end of the switch SW outputs a second scan signal SS' having a low voltage value. In the present embodiment, the switch SW may be implemented by an N-type transistor.

[0098] In this embodiment, the current source IB includes a resistor RB. The resistor RB is electrically connected between the second terminal of the switch SW and the reference low voltage VGL.

[0099] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0100] Please refer to Fig. 9 , Fig. 9 Schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 910 can be implemented by an analog buffer. The scan signal conversion circuit 910 includes a switch SW and a current source IB. The first end of the switch SW is electrically connected to the reference high voltage VGH. The second end of the switch SW is electrically connected to the electronic circuit U. The control end of the switch SW receives the first scan signal SS. The current source IB is electrically connected between the second end of the switch SW and the reference low voltage VGL.

[0101] In the present embodiment, when the voltage value of the first scan signal SS is a high voltage value, the switch SW is turned on. The second end of the switch SW outputs a second scan signal SS' having a high voltage value. When the voltage value of the first scan signal SS is a low voltage value, the switch SW is turned off. The second end of the switch SW outputs a second scan signal SS' having a low voltage value. In the present embodiment, the switch SW may be implemented by an N-type transistor.

[0102] In this embodiment, the current source IB includes an N-type transistor NB. A first terminal of the N-type transistor NB is electrically connected to a control terminal of the N-type transistor NB and a second terminal of the switch SW. A second terminal of the N-type transistor NB is electrically connected to a reference low voltage VGL.

[0103] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0104] Please refer to Fig.10 , Fig.10 1 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 1010 can be implemented by an analog buffer. The scan signal conversion circuit 1010 includes an operational amplifier OPA1. The first input terminal of the operational amplifier OPA1 receives a first scan signal SS. The second input terminal of the operational amplifier OPA1 is electrically connected to the output terminal of the operational amplifier OPA1 and the electronic circuit U. In this embodiment, the scan signal conversion circuit 1010 can be a unity gain buffer or a follower. The first input terminal of the operational amplifier OPA1 is a non-inverting input terminal (+). The second input terminal of the operational amplifier OPA1 is an inverting input terminal (-).

[0105] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0106] Please refer to Fig.11 , Fig.11 1 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 1110 can be implemented by an analog amplifier. The scan signal conversion circuit 1110 includes a switch SW and a current source IB. The first end of the switch SW is electrically connected to the electronic circuit U. The second end of the switch SW is electrically connected to the reference low voltage VGL. The control end of the switch SW receives the first scan signal SS. The current source IB is electrically connected between the reference high voltage VGH2 and the first end of the switch SW.

[0107] In the present embodiment, when the voltage value of the first scan signal SS is a high voltage value, the switch SW is turned on. The first end of the switch SW outputs a second scan signal SS' having a low voltage value. When the voltage value of the first scan signal SS is a low voltage value, the switch SW is turned off. The second end of the switch SW outputs a second scan signal SS' having a high voltage value. At this time, the high voltage value of the second scan signal SS' is substantially equal to the voltage value of the reference high voltage VGH2. Therefore, the high voltage value of the second scan signal SS' can be amplified to the voltage value of the reference high voltage VGH2. In the present embodiment, the switch SW can be implemented by an N-type transistor. The voltage value of the reference high voltage VGH2 can be adjusted according to actual needs.

[0108] It should be noted that Figures 2 to 10 The phase of the second scan signal SS' is similar to the phase of the first scan signal SS. In this embodiment, the phase of the second scan signal SS' is opposite to the phase of the first scan signal SS.

[0109] In this embodiment, the current source IB includes a resistor RB. The resistor RB is electrically connected between the reference low voltage VGH and the first end of the switch SW.

[0110] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0111] Please refer to Fig.12 , Fig.12 1 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 1210 can be implemented by an analog amplifier. The scan signal conversion circuit 1210 includes a switch SW and a current source IB. The first end of the switch SW is electrically connected to the electronic circuit U. The second end of the switch SW is electrically connected to the reference low voltage VGL. The control end of the switch SW receives the first scan signal SS. The current source IB is electrically connected between the reference high voltage VGH2 and the first end of the switch SW.

[0112] In the present embodiment, when the voltage value of the first scan signal SS is a high voltage value, the switch SW is turned on. The first end of the switch SW outputs the second scan signal SS' having a low voltage value. When the voltage value of the first scan signal SS is a low voltage value, the switch SW is turned off. The second end of the switch SW outputs the second scan signal SS' having a high voltage value. At this time, the high voltage value of the second scan signal SS' is substantially equal to the voltage value of the reference high voltage VGH2. Therefore, the high voltage value of the second scan signal SS' can be amplified to the voltage value of the reference high voltage VGH2. In the present embodiment, the switch SW can be implemented by an N-type transistor.

[0113] In this embodiment, the phase of the second scan signal SS′ is opposite to the phase of the first scan signal SS.

[0114] In this embodiment, the current source IB includes an N-type transistor NB. A first terminal of the N-type transistor NB is electrically connected to a control terminal of the N-type transistor NB and a reference high voltage VGH. A second terminal of the N-type transistor NB is electrically connected to a second terminal of the switch SW.

[0115] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0116] Please refer to Fig.13 , Fig.13 1 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 1310 can be implemented by an analog amplifier. The scan signal conversion circuit 1310 includes an operational amplifier OPA1 and resistors R1 and R2. The first end of the resistor R1 receives a first scan signal SS. The first input end of the operational amplifier OPA1 is electrically connected to the second end of the resistor R1. The second input end of the operational amplifier OPA1 is electrically connected to a reference low voltage (for example, ground). The output end of the operational amplifier OPA1 is electrically connected to the electronic circuit U. The resistor R2 is electrically connected between the first input end of the operational amplifier OPA1 and the output end of the operational amplifier OPA1.

[0117] In the present embodiment, the first input terminal of the operational amplifier OPA1 is the inverting input terminal (-). The second input terminal of the operational amplifier OPA1 is the non-inverting input terminal (+). The scan signal conversion circuit 1310 can gain the voltage value of the first scan signal SS to generate the second scan signal SS' according to the resistance value of the resistor R1 and the resistance value of the resistor R2. In the present embodiment, the voltage value of the second scan signal SS' can be (-r2 / r1) times that of the first scan signal SS. "r1" is the resistance value of the resistor R1. "r2" is the resistance value of the resistor R2. Therefore, the phase of the second scan signal SS' of the present embodiment is opposite to the phase of the first scan signal SS.

[0118] The resistance value of the resistor R1 and the resistance value of the resistor R2 can be adjusted according to actual needs.

[0119] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0120] Please refer to Fig.14 , Fig.141 is a schematic diagram of a scan signal conversion circuit and an electronic circuit according to an embodiment of the present disclosure. In this embodiment, the scan signal conversion circuit 1410 can be implemented by an analog amplifier. The scan signal conversion circuit 1410 includes an operational amplifier OPA1 and resistors R1 and R2. The first input terminal of the operational amplifier OPA1 receives the first scan signal SS. The output terminal of the operational amplifier OPA1 is electrically connected to the electronic circuit U. The resistor R1 is electrically connected between the second input terminal of the operational amplifier OPA1 and the reference low voltage VGL. The resistor R2 is electrically connected between the second input terminal of the operational amplifier OPA1 and the output terminal of the operational amplifier OPA1.

[0121] In the present embodiment, the first input terminal of the operational amplifier OPA1 is a non-inverting input terminal (+). The second input terminal of the operational amplifier OPA1 is an inverting input terminal (-). The scan signal conversion circuit 1410 can gain the voltage value of the first scan signal SS to generate a second scan signal SS' according to the resistance value of the resistor R1 and the resistance value of the resistor R2. In the present embodiment, the voltage value of the second scan signal SS' can be (1+(r2 / r1)) times that of the first scan signal SS. "r1" is the resistance value of the resistor R1. "r2" is the resistance value of the resistor R2. Therefore, the phase of the second scan signal SS' of the present embodiment is similar to the phase of the first scan signal SS.

[0122] The resistance value of the resistor R1 and the resistance value of the resistor R2 can be adjusted according to actual needs.

[0123] In this embodiment, the implementation details of the electronic circuit U are already in Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0124] Please refer to Fig.15 , Fig.15 2 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 200 at least includes electronic circuit groups GU1 -GUn, scan lines LS, scan signal conversion circuits 110_1 - 110 — n and a scan driving circuit 220 .

[0125] In this embodiment, each of the electronic circuit groups GU1-GUn includes one or more electronic circuits. The implementation details of the electronic circuits have been Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0126] The scan driving circuit 220 is electrically connected to the scan line LS. The scan driving circuit 220 generates a first scan signal SS and provides the first scan signal SS to the scan line LS.

[0127] The scan signal conversion circuit 110_1 is electrically connected to the scan line LS and the electronic circuit group GU1. The scan signal conversion circuit 110_1 receives the first scan signal SS on the scan line LS and converts the first scan signal SS into a second scan signal SS1'. The scan signal conversion circuit 110_1 provides the second scan signal SS1' to the electronic circuit in the electronic circuit group GU1.

[0128] The scan signal conversion circuit 110_2 is electrically connected to the scan line LS1 and the electronic circuit group GU2. The scan signal conversion circuit 110_2 receives the first scan signal SS on the scan line LS1 and converts the first scan signal SS into a second scan signal SS2'. The scan signal conversion circuit 110_2 provides the second scan signal SS2' to the electronic circuit in the electronic circuit group GU2.

[0129] Similarly, the scan signal conversion circuit 110_n is electrically connected to the scan line LS1 and the electronic circuit group GUn. The scan signal conversion circuit 110_n receives the first scan signal SS located at the scan line LS1 and converts the first scan signal SS into a second scan signal SSn'. The scan signal conversion circuit 110_n provides the second scan signal SSn' to the electronic circuit in the electronic circuit group GUn.

[0130] Please refer to Fig.16 , Fig.16 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 300 at least includes electronic circuits U1 to Un, scan lines LS1, scan signal conversion circuits 110_1 to 110_n, and a scan driving circuit 220. The implementation details of the electronic circuits U1 to Un have been Figure 2 This is clearly described in the embodiments, so it will not be repeated here.

[0131] The scan driving circuit 220 is electrically connected to the scan line LS1 . The scan driving circuit 220 generates a first scan signal SS and provides the first scan signal SS to the scan line LS1 .

[0132] The scan signal conversion circuit 110_1 is electrically connected to the scan line LS1 and the electronic circuit U1. The scan signal conversion circuit 110_1 receives the first scan signal SS on the scan line LS1 and converts the first scan signal SS into a second scan signal SS'. The scan signal conversion circuit 110_1 provides the second scan signal SS' to the electronic circuit U1.

[0133] Similarly, the scan signal conversion circuit 110_n is electrically connected to the scan line LS1 and the electronic circuit Un. The scan signal conversion circuit 110_n receives the first scan signal SS on the scan line LS1 and converts the first scan signal SS into a second scan signal SS'. The scan signal conversion circuit 110_n provides the second scan signal SS' to the electronic circuit Un.

[0134] In the present embodiment, the second scan signal SS' is delayed compared to the first scan signal SS generated by the scan driving circuit 220. Taking the electronic circuit U1 as an example, the second scan signal SS' received by the electronic circuit U1 has a scan delay td1 compared to the first scan signal SS generated by the scan driving circuit 220. Taking the electronic circuit Un as an example, the second scan signal SS' received by the electronic circuit Un has a scan delay tdn compared to the first scan signal SS generated by the scan driving circuit 220. The scan delay tdn is greater than the scan delay td1. It can be seen that the second scan signal SS' received by the electronic circuit Un lags behind the second scan signal SS' received by the electronic circuit U1.

[0135] Scan delay td1 depends on the transmission delay of scan line LS1 (i.e., RC delay of scan line LS1) and the conversion delay of scan signal conversion circuit 110_1. Scan delay tdn depends on the transmission delay of scan line LS1 (i.e., RC delay of scan line LS1) and the conversion delay of scan signal conversion circuit 110_n.

[0136] Therefore, the data signal SD1 provided to the electronic circuit U1 is delayed based on the scanning delay td1. The data signal SDn provided to the electronic circuit Un is delayed based on the scanning delay tdn. The data signal SD1 has the scanning delay td1. The data signal SDn has the scanning delay tdn. In this way, the electronic circuit U1 can surely receive the data signal SD1 during the period when the electronic circuit U1 is selected. The electronic circuit Un can surely receive the data signal SDn during the period when the electronic circuit Un is selected.

[0137] In summary, the scan signal conversion circuit can adjust the first scan signal located on the scan line to the second scan signal. The electronic circuit receives the second scan signal. In this way, the operation of the electronic circuit will not be abnormal due to the delay or distortion of the first scan signal. In addition, in some embodiments, the second scan signal has a scan delay compared to the first scan signal generated by the scan driving circuit. The data signal is delayed based on the scan delay. In this way, the electronic circuit can indeed receive the data signal during the period when the electronic circuit is selected.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that: The electronic device comprises: at least one electronic circuit; A scan line configured to transmit a first scan signal; and The scan signal conversion circuit is electrically connected to the at least one electronic circuit and the scan line, and is configured to receive the first scan signal, convert the first scan signal into a second scan signal, and provide the second scan signal to the at least one electronic circuit.

2. The electronic device according to claim 1, characterized in that: The scanning signal conversion circuit comprises: a first inverter, an input terminal of which receives the first scanning signal; and A second inverter, wherein an input terminal of the second inverter is electrically connected to an output terminal of the first inverter, and an output terminal of the second inverter outputs the second scanning signal.

3. The electronic device according to claim 1, characterized in that: The scanning signal conversion circuit comprises: A first inverter, wherein an input terminal of the first inverter receives the first scanning signal; A second inverter, wherein an input end of the second inverter is electrically connected to an output end of the first inverter, and an output end of the second inverter outputs the second scanning signal; a resistor electrically connected between a reference high voltage and a high voltage terminal of the first inverter; and A P-type transistor, a first end of the P-type transistor is electrically connected to the reference high voltage, a second end of the P-type transistor is electrically connected to the high voltage end of the first inverter, and a control end of the P-type transistor is electrically connected to the output end of the second inverter.

4. The electronic device according to claim 1, characterized in that: The scan signal conversion circuit is implemented by one of an analog buffer and an analog amplifier.

5. The electronic device according to claim 4, characterized in that: The scanning signal conversion circuit comprises: a switch, wherein a first end of the switch is electrically connected to a reference high voltage, a second end of the switch is electrically connected to the at least one electronic circuit, and a control end of the switch receives the first scan signal; and a current source electrically connected between the second end of the switch and a reference low voltage, When the voltage value of the first scanning signal is a high voltage value, the switch is turned on, and When the voltage value of the first scan signal is a low voltage value, the switch is turned off.

6. The electronic device according to claim 5, characterized in that: The current source comprises: The resistor is electrically connected between the second end of the switch and the reference low voltage.

7. The electronic device according to claim 5, characterized in that: The current source comprises: An N-type transistor, wherein a first end of the N-type transistor is electrically connected to a control end of the N-type transistor and a second end of the switch, and a second end of the N-type transistor is electrically connected to the reference low voltage.

8. The electronic device according to claim 4, characterized in that: The scanning signal conversion circuit comprises: An operational amplifier, wherein a first input terminal of the operational amplifier receives the first scanning signal, and a second input terminal of the operational amplifier is electrically connected to an output terminal of the operational amplifier and the at least one electronic circuit.

9. The electronic device according to claim 4, characterized in that: The scanning signal conversion circuit comprises: a switch, wherein a first end of the switch is electrically connected to the at least one electronic circuit, a second end of the switch is electrically connected to a reference low voltage, and a control end of the switch receives the first scan signal; and a current source electrically connected between a reference high voltage and the first end of the switch, When the voltage value of the first scanning signal is a high voltage value, the switch is turned on, and When the voltage value of the first scan signal is a low voltage value, the switch is turned off.

10. The electronic device according to claim 1, characterized in that: Each at least one electronic circuit comprises: Electronic components; and The selection circuit is electrically connected to the scan signal conversion circuit and the electronic component, and is configured to receive the second scan signal and the data signal, and provide the data signal to the electronic component according to the second scan signal, so that the electronic component operates according to the data signal.

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