Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, and relate to the technical field of display, and are used for reducing the area occupied by a driving circuit. The display panel comprises a substrate, a driving circuit and an output line located at one side of the substrate, at least part of the output line extends along a first direction, the driving circuit comprises a plurality of driving units arranged in cascade, the plurality of driving units are arranged along a second direction, the second direction intersects the first direction, each driving unit comprises an input end and an output end, the output line is connected to the output end of a current stage driving unit, each driving unit comprises an output module, the output module comprises a first capacitor, the first capacitor is electrically connected to the output end, and at least one pole plate of the first capacitor at least partially overlaps the output line in a direction perpendicular to the plane where the substrate is located.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] To control the pixel driving circuit in the display panel, a driving circuit that provides control signals to the pixel driving circuit, as well as multiple traces connected to the driving circuit, need to be installed in the display panel. Currently, the driving circuit and traces occupy a large amount of space in the display panel, limiting the improvement of the display panel's visual effect. Summary of the Invention

[0003] This invention provides a display panel and display device for reducing the total area occupied by the driving circuit and the first output line in the display panel.

[0004] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0005] Substrate;

[0006] A driving circuit and a first output line located on one side of the substrate; at least a portion of the first output line extends along a first direction;

[0007] The driving circuit includes multiple cascaded driving units arranged along a second direction; the second direction intersects with the first direction.

[0008] The driving unit includes a first input terminal and a first output terminal; the first output line is connected to the first output terminal of the current driving unit;

[0009] The drive unit includes an output module, and the output module includes a first capacitor, which is electrically connected to a first output terminal.

[0010] and,

[0011] Along a direction perpendicular to the plane of the substrate, the first output line at least partially overlaps with at least one plate of the first capacitor.

[0012] Secondly, embodiments of the present invention provide a display device, including the display panel described above.

[0013] The solution provided by the embodiments of the present invention can reduce the area occupied by the first output line and the driving unit in the display panel, which is beneficial to improving the visual effect of the display panel. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A top view schematic diagram of a display panel provided in an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram illustrating the connection relationship between a driving circuit and a pixel circuit, provided in an embodiment of the present invention.

[0017] Figure 3 A circuit diagram of a driving unit provided in an embodiment of the present invention;

[0018] Figure 4 A wiring diagram of a first output line and a driving unit provided for an embodiment of the present invention;

[0019] Figure 5 A wiring diagram of another first output line and driving unit provided in an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0021] Figure 7 A timing diagram of a driving unit provided in an embodiment of the present invention;

[0022] Figure 8 This is a timing diagram of another driving unit provided in an embodiment of the present invention;

[0023] Figure 9 for Figure 4 An enlarged schematic diagram of the central region E1;

[0024] Figure 10 for Figure 9 A schematic diagram of a cross-section along B1-B1';

[0025] Figure 11 A wiring diagram of another driving unit and a first output line provided in an embodiment of the present invention;

[0026] Figure 12 for Figure 11 An enlarged schematic diagram of the central region E2;

[0027] Figure 13 for Figure 12 A schematic diagram of a cross-section along B2-B2';

[0028] Figure 14 An enlarged schematic diagram of a first connecting part and a first capacitor provided for an embodiment of the present invention;

[0029] Figure 15 for Figure 14 A schematic diagram of a cross-section along B00-B00';

[0030] Figure 16 for Figure 14 A simplified schematic diagram of the distribution of three vias in the middle;

[0031] Figure 17 An enlarged schematic diagram of another first connecting part and a first capacitor provided in an embodiment of the present invention;

[0032] Figure 18 for Figure 17 A schematic diagram of a cross-section along B0-B0';

[0033] Figure 19 for Figure 9 A schematic diagram of the first output line in the circuit;

[0034] Figure 20 An enlarged schematic diagram of another first connecting part and first capacitor provided in an embodiment of the present invention;

[0035] Figure 21 for Figure 20 A schematic diagram of the first output line in the circuit;

[0036] Figure 22 for Figure 9 A schematic diagram of a cross-section along B3-B3';

[0037] Figure 23 for Figure 9 A schematic diagram of a cross-section along B4-B4';

[0038] Figure 24 for Figure 4 An enlarged schematic diagram of the central region E3;

[0039] Figure 25 for Figure 24 A schematic diagram of a cross-section along B5-B5';

[0040] Figure 26 for Figure 24 An enlarged schematic diagram of the central region E4;

[0041] Figure 27 for Figure 26 A schematic diagram of a cross-section along B6-B6';

[0042] Figure 28 for Figure 26A schematic diagram of a cross-section along B7-B7';

[0043] Figure 29 A partial wiring diagram of another driving unit provided in an embodiment of the present invention;

[0044] Figure 30 for Figure 29 A schematic diagram of a cross-section along B8-B8'.

[0045] Figure 31 for Figure 29 An enlarged schematic diagram of the central region E5;

[0046] Figure 32 for Figure 4 An enlarged schematic diagram of the central region E6;

[0047] Figure 33 for Figure 32 A schematic diagram of a cross-section along B10-B10';

[0048] Figure 34 for Figure 32 A schematic diagram of a cross-section along B11-B11';

[0049] Figure 35 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0050] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0051] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0052] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0053] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0054] This invention provides a display panel, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes a substrate 1 and a driving circuit 2 located on one side of the substrate 1, and a light-emitting element (…). Figure 1 (not shown) and pixel circuit 3.

[0055] The pixel circuit 3 is electrically connected to the light-emitting element. The pixel circuit 3 is used to provide driving current to the light-emitting element to drive the light-emitting element to emit light. For example, the light-emitting element includes any one of a micro-LED, a mini-LED, or an organic light-emitting diode (OLED).

[0056] In this embodiment of the invention, the driving circuit 2 is used to provide a first control signal to the pixel circuit 3 to control the on and off of the corresponding transistors in the pixel circuit 3. For example... Figure 1 As shown, the display panel also includes a scan control line 31, through which the driving circuit 2 provides a first control signal to the pixel circuit 3.

[0057] For example, such as Figure 1 and Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the connection relationship between a driving circuit and a pixel circuit according to an embodiment of the present invention. The driving circuit 2 includes N driving units 20, where N ≥ 2 and N is an integer. The multiple driving units 20 are used to output first control signals to the corresponding pixel circuits 3 in a step-by-step manner.

[0058] Combination Figure 2 and Figure 3 As shown, Figure 3 This is a circuit diagram of a driving unit provided in an embodiment of the present invention. The driving unit 20 includes a first input terminal IN1 and a first output terminal OUT1. Optionally, the first input terminal IN1 is used to receive a first input signal, and the first output terminal OUT1 is used to output a first output signal. In the driving circuit 2, multiple driving units 20 are cascaded, that is, the first output terminal OUT1 of the i-th stage driving unit 20_i and the first input terminal IN1 of the (i+1)-th stage driving unit 20_i+1 are electrically connected. In other words, for two adjacent stages of driving units 20, the first output terminal OUT1 of the previous stage driving unit 20 is electrically connected to the first input terminal IN1 of the next stage driving unit 20.

[0059] It should be noted that, as Figure 2As shown, for the first-stage driving unit 20 in the driving circuit 2, its first input terminal IN1 can be electrically connected to the start signal line STV to receive the start signal. For the last-stage driving unit 20_N in the driving circuit 2, its first output terminal OUT1 can be connected to the corresponding pixel circuit 3, but not electrically connected to other driving units 20.

[0060] For example, such as Figure 4 As shown, Figure 4 This is a wiring diagram of a driving unit provided in an embodiment of the present invention. The display panel also includes multiple first output lines OUT1 (to more clearly illustrate the connection relationship between each trace and the corresponding signal terminal in the driving unit, the same reference numerals are used in this embodiment to label the corresponding signal lines and corresponding signal terminals, such as OUT1 for both the first output line and the first output terminal). The first output lines OUT1 are electrically connected to the first output terminal OUT1 of the current driving unit 20. Taking the driving circuit 2 as an example, which includes N cascaded driving units 20, the display panel may include N first output lines OUT1, wherein the N first output lines OUT1 are electrically connected to the first output terminals OUT1 of the N driving units 20 in a one-to-one correspondence. The current driving unit 20 corresponding to the first output line OUT1 is the driving unit 20 among the multiple driving units 20 whose first output terminal OUT1 is connected to the first output line OUT1.

[0061] For example, such as Figure 1 and Figure 4 As shown, at least a portion of the first output line OUT1 extends along a first direction h11; a plurality of drive units 20 are arranged along a second direction h12. The second direction h12 intersects the first direction h11.

[0062] For example, such as Figure 1 and Figure 4 As shown, the first output line OUT1 includes a main body OUT10, and the main body OUT10 and the drive unit 20 are arranged along the second direction h12. Along the second direction h12, the main body OUT10 is located on the side of the current-level drive unit 20 closest to the next-level drive unit 20. Optionally, as... Figure 4 As shown, at least a portion of the main body OUT10 can extend along the first direction h11. Figure 1 and Figure 4 The first direction h11 and the second direction h12 are shown as perpendicular. Alternatively, the first direction h11 can also be any other portion of the first output line OUT11 that does not extend along the second direction h12. This embodiment of the invention does not limit the angle between the first direction h11 and the second direction h12.

[0063] Combination Figure 2 , Figure 3 and Figure 4 As shown, the drive unit 20 also includes an output module 4.

[0064] like Figure 3 and Figure 4 As shown, output module 4 includes a first capacitor C1, which is electrically connected to the first output terminal OUT1. The first capacitor C1 can improve the potential stability of the first output signal output from the first output terminal OUT1. Specifically, as... Figure 3 As shown, the first capacitor C1 includes a first plate C11 and a second plate C12. The first plate C11 of the first capacitor C1 is electrically connected to the first output terminal OUT1, and the second plate C12 is electrically connected to the second level signal terminal VGL.

[0065] When setting the first output line OUT1 and the first capacitor C1, for example, as follows: Figure 4 As shown, along the direction h2 perpendicular to the plane of substrate 1, in this embodiment of the invention, the first output line OUT1 can at least partially overlap with at least one electrode of the first capacitor C1. Based on this arrangement, compared to a method where both electrodes of the first output line OUT1 and the first capacitor C1 are staggered in the direction h2 perpendicular to the plane of substrate 1, the total area occupied by the first output line OUT1 and the first capacitor C1 in the display panel can be reduced. Combined with... Figure 5 As shown, Figure 5 This is a wiring diagram of another driving unit provided in an embodiment of the present invention, wherein the first output line OUT1 and the first capacitor C1 do not overlap in the direction h2 perpendicular to the plane where the substrate 1 is located. Figure 5 As shown, the first output line OUT1 includes a first portion 101 extending along a second direction h12, and at least a portion of the first portion 101 and a first capacitor C1 are arranged along a first direction h11. Figure 5 compared to, Figure 4 The method shown can compress the length d1 of the drive unit 20 in the first direction h11.

[0066] like Figure 2 and Figure 3 As shown, the driving unit 20 also includes a first control signal output terminal OUT2, which is used to output the aforementioned first control signal under the control of the first output terminal OUT1. The pixel circuit 3 is used to receive the first control signal and generate a driving current under the control of the first control signal to drive the light-emitting element to emit light.

[0067] Optional, combined Figure 2 , Figure 3 , Figure 4 and Figure 5As shown, output module 4 includes a first output module 41 and a second output module 42; wherein, the first output module 41 is electrically connected to the first output terminal OUT1, and the second output module 42 is electrically connected to the first control signal output terminal OUT2. Figure 3 As shown, the first output module 41, in response to the signal from the first node N1, is electrically connected to the first output terminal OUT1 and the first level signal terminal VGH; and in response to the signal from the second node N2, it is electrically connected to the first output terminal OUT1 and the second level signal terminal VGL. The second output module 42, in response to the signal from the first node N1, is electrically connected to the first control signal output terminal OUT2 and the first control signal input terminal IN21; and in response to the signal from the first output terminal OUT1, it is electrically connected to the first control signal output terminal OUT2 and the second control signal input terminal IN22.

[0068] Optional, such as Figure 3 As shown, the first output module 41 includes a first output transistor T21 and a third output transistor T22. The gate of the first output transistor T21 is electrically connected to the first node N1, and its first and second terminals are electrically connected to the first level signal terminal VGH and the first output terminal OUT1, respectively. The gate of the third output transistor T22 is electrically connected to the second node N2, and its first and second terminals are electrically connected to the second level signal terminal VGL and the first output terminal OUT1, respectively.

[0069] For example, such as Figure 3 As shown, the second output module 42 includes a second output transistor T31 and a fourth output transistor T32. The gate of the second output transistor T31 is electrically connected to the first node N1, the first terminal is electrically connected to the first control signal input terminal IN21, and the second terminal is electrically connected to the first control signal output terminal OUT2. The gate of the fourth output transistor T32 is electrically connected to the first output terminal OUT1, and the first and second terminals are electrically connected to the second control signal input terminal IN22 and the first control signal output terminal OUT2, respectively.

[0070] Optional, such as Figure 3As shown, the driving unit 20 also includes a first processing module 21 electrically connected to the first node N1 and a second processing module 22 electrically connected to the second node N2. When the driving unit 20 is operating, the first processing module 21 and the second processing module 22 write signals to the first node N1 and the second node N2, respectively. When the first node N1 is written with an enable level, the third output transistor T22 is turned on, and the second level signal provided by the second level signal terminal VGL can be written to the first output terminal OUT1. Under the control of the first output terminal OUT1, the fourth output transistor T32 is turned on, and the signal provided by the second control signal input terminal IN22 can be written to the first control signal output terminal OUT2 through the turned-on fourth output transistor T32, causing the first control signal output terminal OUT2 to output a first control signal, which is then provided to the corresponding pixel circuit 3.

[0071] Optional, such as Figure 6 As shown, Figure 6 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. The pixel circuit 3 includes a pulse width modulation module 10 and a pulse amplitude modulation module 20. The pulse width modulation module 10 receives a sweep frequency signal SWEEP and controls the duration of the light-emitting driving current supplied to the light-emitting element 12, thereby controlling the light-emitting duration of the light-emitting element 12 and adjusting the brightness of the light emitted by the light-emitting element 12. The pulse amplitude modulation module 20 provides the light-emitting driving current to the light-emitting element 12 and controls the luminous efficiency of the light-emitting element 12 by adjusting the amplitude of the light-emitting driving current. Based on this configuration, the light-emitting element 12 can operate under a suitable driving current, which is beneficial for achieving higher luminous efficiency and better display effects.

[0072] Optional, such as Figure 6 As shown, the pulse amplitude modulation module 20 may include a first light-emitting control transistor T021, a first driving transistor Td1, a second light-emitting control transistor T022, a pulse amplitude data writing transistor T023, a pulse amplitude compensation transistor T024, a pulse amplitude gate reset transistor T025, a pulse amplitude anode reset transistor T026, and a first storage capacitor Cst1.

[0073] Among them, the first terminal of the first light-emitting control transistor T021 is electrically connected to the first power line PAM_VDD, and the second terminal is electrically connected to the first terminal of the first driving transistor Td1.

[0074] The first terminal of the second light-emitting control transistor T022 is electrically connected to the second terminal of the first driving transistor Td1, and the second terminal is electrically connected to the first terminal of the light-emitting element 12.

[0075] The gates of the first light-emitting control transistor T021 and the second light-emitting control transistor T022 receive the pulse amplitude light-emitting control signal provided by the pulse amplitude light-emitting control signal terminal PAM_EM.

[0076] The first terminal of the pulse amplitude data writing transistor T023 is electrically connected to the first data signal line PAM_DATA, and the second terminal is electrically connected to the first terminal of the first driving transistor Td1.

[0077] The first terminal of the pulse amplitude compensation transistor T024 is electrically connected to the second terminal of the first driving transistor Td1, and the second terminal is electrically connected to the gate of the first driving transistor Td1.

[0078] The first terminal of the pulse amplitude gate reset transistor T025 is electrically connected to the first reset signal line PAM_REF, and the second terminal is electrically connected to the gate of the first drive transistor Td1.

[0079] The first terminal of the pulse amplitude anode reset transistor T026 is electrically connected to the third power supply line PVEE, and the second terminal is electrically connected to the first terminal of the light-emitting element 12.

[0080] The gate of the pulse amplitude gate reset transistor T025 receives the first scan signal provided by the first scan signal line PAM_S1, and the gates of the pulse amplitude data writing transistor T023, the pulse amplitude compensation transistor T024, and the pulse amplitude anode reset transistor T026 receive the second scan signal provided by the second scan signal line PAM_S2.

[0081] Continue to refer to Figure 6 The pulse width modulation module 10 may include a third light-emitting control transistor T031, a pulse width data writing transistor T032, a second driving transistor Td2, a pulse width compensation transistor T033, a pulse width gate reset transistor T034, a fourth light-emitting control transistor T035, and a second storage capacitor Cst2.

[0082] Among them, the first terminal of the third light-emitting control transistor T031 is electrically connected to the second power line PWM_VDD, and the second terminal is electrically connected to the first terminal of the second driving transistor Td2.

[0083] The first terminal of the fourth light-emitting control transistor T035 is electrically connected to the second terminal of the second driving transistor Td2, and the second terminal is electrically connected to the gate of the first driving transistor Td1 in the pulse amplitude modulation module 20.

[0084] The first terminal of the pulse width data writing transistor T032 is electrically connected to the second data signal line PWM_DATA, and the second terminal is electrically connected to the first terminal of the second driving transistor Td2.

[0085] The first terminal of the pulse width compensation transistor T033 is electrically connected to the second terminal of the second driving transistor Td2, and the second terminal is electrically connected to the gate of the second driving transistor Td2.

[0086] The first terminal of the pulse width gate reset transistor T034 is electrically connected to the second reset signal line PWM_REF, and the second terminal is electrically connected to the gate of the second drive transistor Td2.

[0087] One plate of the second storage capacitor Cst2 is electrically connected to the gate of the second driving transistor Td2, and the other plate is electrically connected to the sweep frequency signal terminal SWEEP.

[0088] The gates of the third light-emitting control transistor T031 and the fourth light-emitting control transistor T035 are electrically connected to the pulse width light-emitting control signal line PWM_EM to receive the pulse width light-emitting control signal provided by the pulse width light-emitting control signal line PWM_EM.

[0089] The gate of the pulse width gate reset transistor T034 is electrically connected to the third scan signal line PWM_S1 to receive the third scan signal provided by the third scan signal line PWM_S1.

[0090] The gates of the pulse width data writing transistor T032 and the pulse width compensation transistor T033 are electrically connected to the fourth scan signal line PWM_S2 to receive the fourth scan signal provided by the fourth scan signal line PWM_S2.

[0091] When the pixel circuit 3 is operating, a reference voltage (such as the voltage on the second power line PWM_VDD) is set at the first terminal of the second driving transistor Td2 of the pulse width modulation module 10. A changing potential is formed at the gate of the second driving transistor Td2 by the data voltage on the second data signal line PWM_DATA and the sweep signal on the sweep signal terminal SWEEP. When the voltage difference between the gate and the first terminal of the second driving transistor Td2 is greater than the threshold voltage of the second driving transistor Td2, the second driving transistor Td2 is in a cutoff state, causing the pulse width modulation module 10 to not provide a control signal to the pulse amplitude modulation module 20. The first driving transistor Td1 in the pulse amplitude modulation module 20 provides a light-emitting driving current to the light-emitting element 12 according to the voltage on the first data signal line PAM_DATA.

[0092] As the voltage of the signal transmitted by the SWEEP sweep signal terminal changes, the potential of the gate of the second driving transistor Td2 changes synchronously until the voltage difference between the gate and the first terminal of the second driving transistor Td2 is equal to (or less than) the threshold voltage of the second driving transistor Td2. Then, the second driving transistor Td2 turns on and transmits the voltage on the second power line PWM_VDD as the cutoff voltage to the pulse amplitude modulation module 20, causing the first driving transistor Td1 in the pulse amplitude modulation module 20 to turn off, thereby stopping the supply of driving current to the light-emitting element 12. It can be seen that the pulse width modulation module 10 can control the duration of the light-emitting driving current output by the pulse amplitude modulation module 20, thereby adjusting the effective light-emitting duration of the light-emitting element 12 within a frame, and thus adjusting the brightness of the light-emitting element 12.

[0093] For example, the first control signal output by the aforementioned drive unit 20 includes a sweep frequency signal SWEEP; that is, the first control signal output terminal OUT2 of the drive circuit can be connected to... Figure 6 The sweep frequency signal terminal SWEEP of the pixel circuit 3 shown is electrically connected. The first control signal input terminal IN21 includes a constant signal terminal; for example, this constant signal terminal can be used to transmit a constant high level or a constant low level. The second control signal input terminal IN22 includes a sweep frequency input signal terminal SWEEP_IN. For example, as shown... Figure 7 As shown, Figure 7 This invention provides a timing diagram for a driving unit, wherein the sweep frequency input signal terminal SWEEP_IN is used to transmit a triangular ramp signal. Optionally, the triangular ramp signal can be a signal whose level gradually increases over time, or it can be a signal whose level gradually decreases over time; this invention does not limit the specific type of signal.

[0094] Alternatively, the first control signal output by the aforementioned driving unit 20 may also include a pulse amplitude emission control signal PAM_EM; that is, the first control signal output terminal OUT2 of the driving circuit may be connected to... Figure 4 The pixel circuit 3 shown has its pulse amplitude emission control signal terminal PAM_EM electrically connected. The first control signal input terminal IN21 includes a constant signal terminal; exemplarily, this constant signal terminal can be used to transmit a constant high level or a constant low level. The second control signal input terminal IN22 includes the pulse amplitude emission control signal input terminal PAM_EM_IN. For example, as... Figure 8 As shown, Figure 8 The present invention provides a timing diagram of a driving unit, wherein the pulse amplitude emission control signal input terminal PAM_EM_IN is used to transmit a square wave signal.

[0095] It should be noted that, Figure 6The circuit structure of pixel circuit 3 shown is only an illustration. The structure of pixel circuit 3 provided in this embodiment of the invention is not limited thereto, and this embodiment of the invention does not specifically limit the structure of pixel circuit 3.

[0096] For example, such as Figure 4 As shown, the display panel also includes a second-level signal connection line VGL (marked with the same symbol as the second-level signal terminal) and a first-level signal connection line VGH (marked with the same symbol as the first-level signal terminal). At least a portion of the second-level signal connection line VGL and at least a portion of the first-level signal connection line VGH extend along a first direction h11. Furthermore, along a second direction h12, at least a portion of the second-level signal connection line VGL is located between the first-level signal connection line VGH and the main body OUT10 of the aforementioned first output line OUT1.

[0097] When configuring the first output transistor T21 and the third output transistor T22, for example, as follows: Figure 4 As shown, along the second direction h12, the first output transistor T21 can be located on the side of the first capacitor C1 close to the first level signal connection line VGH. Based on this arrangement, the distance between the first output transistor T21 and the first level signal connection line VGH can be shortened, which facilitates the connection between the first electrode of the first output transistor T21 and the first level signal connection line VGH.

[0098] For example, such as Figure 4 As shown, along the second direction h12, at least a portion of the third output transistor T22 can be located on the side of the first capacitor C1 away from the first output transistor T21, so as to shorten the distance between the third output transistor T22 and the second level signal line VGL, and facilitate the connection of the third output transistor T22 to the second level signal connection line VGL respectively.

[0099] For example, such as Figure 4 , Figure 9 and Figure 10 As shown, Figure 9 for Figure 4 An enlarged schematic diagram of the central region E1. Figure 10 for Figure 9 A cross-sectional view along B1-B1' shows that the first output line OUT1 includes a first connecting portion OUT11 and a main body portion OUT10 connected to each other. Along a direction h2 perpendicular to the plane where the substrate 1 is located, the first connecting portion OUT11 overlaps with at least one electrode of the first capacitor C1. Furthermore, the first connecting portion OUT11 is located on the side of the first capacitor C1 away from the substrate 1.

[0100] For example, such as Figure 10As shown, the display panel includes a semiconductor layer S, a first gate metal layer M1, a capacitor metal layer MC, and a source / drain metal layer M2. The first gate metal layer M1 is located on the side of the semiconductor layer S away from the substrate 1, the capacitor metal layer MC is located on the side of the first gate metal layer M1 away from the semiconductor layer S, and the source / drain metal layer M2 is located on the side of the capacitor metal layer MC away from the first gate metal layer M1.

[0101] For example, the first plate C11 of the first capacitor C1 may be located on the side of the second plate C12 away from the substrate 1. Figure 10 The diagram illustrates a capacitor metal layer MC comprising the first electrode C11 of a first capacitor C1, and a first gate metal layer M1 comprising the second electrode C12 of a first capacitor C1.

[0102] Optionally, in embodiments of the present invention, the first connection portion OUT11 may be located on the side of the second electrode C12 of the first capacitor C1 away from the substrate 1. For example, in embodiments of the present invention, the first connection portion OUT11 and the first electrode C11 of the first capacitor C1 may be disposed in the same layer, or the first connection portion OUT11 may be located on the side of the first electrode C11 of the first capacitor C1 away from the substrate 1. The film layer position of the first connection portion OUT11 will be described in detail below, and will not be repeated here. Figure 10 The first connection part OUT11 and the first plate C11 of the first capacitor C1 are disposed in the same layer on the capacitor metal layer MC as an illustration.

[0103] In this embodiment of the invention, by having the first connection part OUT11 and at least one plate of the first capacitor C1 at least partially overlap in the direction h2 perpendicular to the plane where the substrate 1 is located, the total area occupied by the first connection part OUT11 and the first capacitor C1 in the display panel can be reduced, which is beneficial to compressing the area occupied by the driving circuit 2 in the display panel.

[0104] In embodiments of the present invention, such as Figure 9 As shown, the second terminal of the first output transistor T21 and the second terminal of the third output transistor T22 are connected at least through the first connection part OUT11.

[0105] Optional, such as Figure 9 As shown, in addition to the first connecting portion OUT11 and the main body portion OUT10, the first output line OUT1 also includes a first sub-connecting portion OUT12 and a second sub-connecting portion OUT13. Along the direction h2 perpendicular to the plane where the substrate 1 is located, the two plates of the first sub-connecting portion OUT12 and the first capacitor C1 do not overlap at least partially, and the two plates of the second sub-connecting portion OUT13 and the first capacitor C1 do not overlap at least partially.

[0106] For example, such as Figure 9As shown, the second terminal of the first output transistor T21 can be connected to the first plate C11 of the first capacitor C1 through the first sub-connection OUT12, and the second terminal of the third output transistor T22 can be connected to the first plate C11 of the first capacitor C1 through the second sub-connection OUT13.

[0107] For example, in embodiments of the present invention, at least a portion of the first plate C11 of the first capacitor C1 can be reused as the aforementioned first connection portion OUT11. For example... Figure 9 and Figure 10 As shown, in this embodiment of the invention, the first connection portion OUT11 can be located on the capacitor metal layer MC, that is, the first connection portion OUT11 is located on the side of the second electrode plate C12 of the first capacitor C1 away from the substrate 1. Based on this arrangement, it is equivalent to making the first electrode plate C11 of the first capacitor C1, together with the first sub-connection portion OUT12 and the second sub-connection portion OUT13, form a connection structure connecting the second electrode of the first output transistor T21 and the second electrode of the third output transistor T22. While realizing the electrical connection between the second electrode of the first output transistor T21 and the second electrode of the third output transistor T22, no additional connection structure is required, which helps to simplify the wiring structure of the driving unit 20.

[0108] For example, such as Figure 10 As shown, along the direction h2 perpendicular to the plane where the substrate 1 is located, the first sub-connection OUT12 and the second sub-connection OUT13 can be located on the side of the first capacitor C1 away from the substrate 1.

[0109] Optional, such as Figure 9 and Figure 10 As shown, in this embodiment of the invention, the first connecting part OUT11 can be connected to the first sub-connecting part OUT12 through the through hole K01, and the first connecting part OUT11 can be connected to the second sub-connecting part OUT13 through the through hole K02.

[0110] In another alternative embodiment, the present invention may also have at least a portion of the first connection portion OUT11 located on the side of the first electrode C11 of the first capacitor C1 away from the substrate 1. For example... Figure 11 , Figure 12 and Figure 13 As shown, Figure 11 This is a wiring diagram of another driving unit provided in an embodiment of the present invention. Figure 12 for Figure 11 An enlarged schematic diagram of region E2 in the middle. Figure 13 for Figure 12A schematic cross-sectional view along B2-B2' is shown, illustrating at least a portion of the first connection portion OUT11 within the source / drain metal layer M2. This arrangement increases the flexibility in the placement of the first connection portion OUT11; for example, a material with higher conductivity can be selected to form the first connection portion OUT11, which helps reduce its resistance and consequently reduces the delay of the first output signal transmitted through the first connection portion OUT11 during transmission. When at least a portion of the first connection portion OUT11 is located on the side of the first electrode C11 of the first capacitor C1 away from the substrate 1, the first connection portion OUT11 is electrically connected to the first electrode C11 of the first capacitor C1 via a via.

[0111] For example, in embodiments of the present invention, the first connecting portion OUT11 can be electrically connected to the first plate C11 of the first capacitor C1 through at least two vias, and the two vias are spaced apart. Figure 12 and Figure 13 As shown, one end of the first connection part OUT11 is electrically connected to the first plate C11 of the first capacitor C1 through via K01, and the other end is electrically connected to the first plate C11 of the first capacitor C1 through via K02. Based on this arrangement, it is equivalent to connecting the first connection part OUT11 in parallel with the first plate C11, which helps to further reduce the resistance of the first output line OUT1.

[0112] For example, such as Figure 13 As shown, the first connection portion OUT11 can be on the same layer as and directly connected to the first sub-connection portion OUT12, and also on the same layer as and directly connected to the second sub-connection portion OUT13. The via K01 connects both the second terminal of the first output transistor T21 and the first plate C11 of the first capacitor C1, and also connects the first connection portion OUT11 and the first plate C11 of the first capacitor C1. The via K02 connects both the second terminal of the third output transistor T22 and the first plate C11 of the first capacitor C1, and also connects the first connection portion OUT11 and the first plate C11 of the first capacitor C1.

[0113] like Figure 13 As shown, a first insulating layer L1 is included between the capacitor metal layer MC and the source / drain metal layer M2, and the vias K01 and K02 penetrate the first insulating layer L1.

[0114] Figure 12 and Figure 13 The explanation is based on the example of the first connection part OUT11 being electrically connected to the first plate C11 of the first capacitor C1 through two vias. Of course, the first connection part OUT11 and the first plate C11 of the first capacitor C1 can be electrically connected through a greater number of vias.

[0115] For example, such as Figure 14 and Figure 15 As shown, Figure 14 This is an enlarged schematic diagram of a first connecting part and a first capacitor provided in an embodiment of the present invention. Figure 15 for Figure 14 A cross-sectional schematic diagram along B00-B00' shows that the first connecting part OUT11 is electrically connected to the first electrode plate C11 through three vias. In addition to vias K01 and K02, the three vias also include via K03. Vias K01 and K02 can be located at both ends of the first connecting part OUT11, and via K03 can be located between vias K01 and K02 along the extending direction of the first connecting part OUT11.

[0116] When the first connection portion OUT11 is electrically connected to the first plate C11 of the first capacitor C1 through at least three vias, embodiments of the present invention allow the included angle α of the lines connecting at least three of the vias to satisfy α > 90°. Here, the lines connecting the vias refer to the lines connecting the geometric centers of the vias. (Combined with...) Figure 16 As shown, Figure 16 for Figure 14 This is a simplified schematic diagram of the distribution of three vias. Based on this arrangement, multiple vias can be distributed as dispersedly as possible in the area where the first capacitor C1 is located, which can improve the space utilization of the area where the first capacitor C1 is located, and also help reduce the difficulty of setting up the vias.

[0117] In another possible way, such as Figure 17 and Figure 18 As shown, Figure 17 An enlarged schematic diagram of another first connection portion OUT11 and first capacitor C1 provided in an embodiment of the present invention. Figure 18 for Figure 17 A cross-sectional view along B0-B0' shows that the first connection part OUT11 can also be electrically connected to the first plate C11 of the first capacitor C1 via a through hole K00. For example... Figure 17 and Figure 18 As shown, the first connecting part OUT11 and the first sub-connecting part OUT12 are on the same layer and directly connected, and the first connecting part OUT11 and the second sub-connecting part OUT13 are on the same layer and directly connected.

[0118] For example, in embodiments of the present invention, the width of the first connecting portion OUT11 in the first direction h11 may be greater than or equal to the line width of other portions of the first output line OUT1. Here, the line width of other portions of the first output line OUT1 refers to the width of the portions of the first output line OUT1 other than the first connecting portion OUT11 in a direction perpendicular to their respective extension directions.

[0119] For example, such as Figure 12, Figure 14 and Figure 17 As shown, in this embodiment of the invention, the width of the first connecting portion OUT11 can be equal to the width of at least one of the main body portion OUT10, the first sub-connecting portion OUT12, and the second sub-connecting portion OUT13. In this case, the first connecting portion OUT11 is a linear structure whose length in its extending direction is significantly greater than its width.

[0120] Or, such as Figure 9 , Figure 19 , Figure 20 and Figure 21 As shown, Figure 19 for Figure 9 A schematic diagram of the first output line in the circuit. Figure 20 This is a schematic diagram of yet another first connecting part and first capacitor provided in an embodiment of the present invention. Figure 21 for Figure 20 A schematic diagram of the first output line in the present invention. In this embodiment, the first connecting part OUT11 can also be a planar structure. The width of the first connecting part OUT11 in the first direction h11 is greater than the line width of other parts of the first output line OUT1, such as the main body part OUT10, the first sub-connecting part OUT12 and the second sub-connecting part OUT13.

[0121] By adopting this configuration, within the region where the first capacitor C1 is located, this embodiment of the invention can maximize the width of the first connection portion OUT11 in the first direction h11 to reduce the resistance of the first connection portion OUT11, thereby reducing the overall resistance of the first output line OUT1, including the first connection portion OUT11. While reducing the signal delay of the first output signal transmitted by the first output line OUT1, the space within the region where the first capacitor C1 is located can be fully utilized.

[0122] Optional, such as Figure 19 and Figure 21 As shown, in this embodiment of the invention, the shape of the orthographic projection of the first connection portion OUT11 onto the plane of the substrate 1 can be set to be the same as the shape of the orthographic projection of at least one plate of the first capacitor C1 onto the plane of the substrate 1.

[0123] It should be noted that the widths of different parts in the first connecting part OUT11 in the first direction h11 may be the same or different. Figure 19 The widths of the two parts of the first connecting part OUT11 in the first direction h11 are W11 and W12 respectively, and the line width of the main body part OUT10 is W2, as an illustration. Both W11 and W12 are greater than W2.

[0124] Optional, such as Figure 9As shown, at least a portion of the main body OUT10 may be located in the source-drain metal layer M2 to reduce the resistance of the first output line OUT1, thereby reducing the signal attenuation caused by voltage drop during the transmission of the first output signal transmitted by the first output line OUT1.

[0125] For example, such as Figure 3 As shown, the driving unit 20 also includes a first isolation transistor T11; the gate of the first isolation transistor T11 is connected to the second level signal terminal VGL, the first terminal is electrically connected to the first output terminal OUT1, and the second terminal is electrically connected to the second output module 42.

[0126] When the gate potential of the fourth output transistor T32 is coupled by parasitic capacitance to a third level signal that is lower than the potential of the second level signal provided by the second level signal terminal VGL, the first isolation transistor T11 can be turned off, thereby preventing the third level signal from being transmitted to the first output terminal OUT1, thus avoiding affecting the potential of the first output signal output by the first output terminal OUT1, which is beneficial to improving the stability of the first output signal. When the first output terminal OUT1 is electrically connected to the first input terminal IN1 of other driving units, the working stability of other driving units 20 can be improved.

[0127] like Figure 4 , Figure 9 , Figure 11 and Figure 12 As shown, the first connection portion OUT11 is also used to connect the first terminal of the first isolation transistor T11 and the second terminal of the third output transistor T22. When the third output transistor T22 is turned on, the first level signal provided by the second level signal connection line VGL can be transmitted to the first terminal of the first isolation transistor T11 through the turned-on third output transistor T22 and the first connection portion OUT11.

[0128] Optional, such as Figure 4 , Figure 9 , Figure 11 and Figure 12 As shown, the first isolation transistor T11 is located between the first output module 41 and the second output module 42, so that the first isolation transistor T11 can be connected to the first output module 41 and the second output module 42 respectively.

[0129] For example, such as Figure 9 and Figure 12 As shown, the display panel also includes a second connection portion 52, which connects the second electrode of the first isolation transistor T11 and the second output module 42; along the direction h2 perpendicular to the plane where the substrate 1 is located, the first output line OUT1 and the second connection portion 52 do not overlap, so as to reduce the coupling capacitance between them.

[0130] Optional, such as Figure 9 and Figure 12 As shown, along the first direction h11, the first output line OUT1 is at least partially located on the side of the second connection portion 52 away from the second output module 42, so that the first output line OUT1 can be connected to the first input terminal IN1 of the next stage drive unit 20, which helps to shorten the length of the first output line OUT1 and reduce the delay of the signal transmitted by the first output line OUT1.

[0131] For example, such as Figure 3 As shown, the driving unit 20 also includes a third node N3, a third node writing unit 203, and a first processing module 21. The third node writing unit 203 is electrically connected to the third node N3 and is used to electrically connect the first input terminal IN1 and the third node N3 under the control of the first clock signal terminal CK. The first processing module 21 is electrically connected to the first node N1.

[0132] The first processing module 21 includes a second capacitor C2 electrically connected to the first node N1 and a first node writing unit 201. The first node writing unit 201 includes a first subunit 2011, which is used to electrically connect a first-level signal terminal VGH and the first node N1 under the control of the third node N3. The second capacitor C2 is used to electrically connect a second-level signal terminal VGH and the first node N1, thereby improving the potential stability of the first node N1.

[0133] When setting the first subunit 2011, for example, as follows: Figure 9 and Figure 12 As shown, along the first direction h11, in this embodiment of the invention, the first subunit 2011 and the output module 4 can be located on both sides of the second capacitor C2.

[0134] Optional, such as Figure 9 and Figure 12 As shown, the display panel also includes a third connection portion 53, which connects the first sub-unit 2011 and the output module 4. Specifically, the third connection portion 53 can connect the output terminal of the first sub-unit 2011 and the gate of the first output transistor T21. The signal output from the output terminal of the first sub-unit 2011 can be transmitted to the gate of the first output transistor T21 through the third connection portion 53.

[0135] Optional, such as Figure 9 and Figure 22 As shown, Figure 22 for Figure 9A cross-sectional view along B3-B3' shows that the third connecting portion 53 includes a first sub-connecting portion 531, which includes the first electrode C21 of the second capacitor C2. In other words, the first electrode C21 of the second capacitor C2 can be reused as the first sub-connecting portion 531. Based on this arrangement, there is no need to additionally provide a connecting portion for connecting the first sub-unit 2011 and the output module 4, which simplifies the structure of the drive unit 20 and further reduces the area of ​​the drive unit 20.

[0136] In an embodiment of the present invention, at least one of the first output transistor T21 and the second output transistor T31 includes a top-bottom dual-gate structure. Figure 9 and Figure 22 The first output transistor T21 and the second output transistor T31 both include a top-bottom dual-gate structure as an illustration.

[0137] like Figure 22 As shown, the first output transistor T21 includes an active layer S21, and a top gate G212 and a bottom gate G211 located on both sides of the active layer S21 in a direction h2 perpendicular to the plane of the substrate 1. The second output transistor T31 includes an active layer S31, and a top gate G312 and a bottom gate G311 located on both sides of the active layer S31 in a direction h2 perpendicular to the plane of the substrate 1. The top-bottom dual-gate structure can improve the carrier mobility and subthreshold characteristics of the device.

[0138] For example, such as Figure 22 As shown, the semiconductor layer S includes the active layer S21 of the first output transistor T21 and the active layer S31 of the second output transistor T31. The display panel also includes a second gate metal layer M0, which is located on the side of the semiconductor layer S closest to the substrate 1. The second gate metal layer M0 includes the bottom gate G211 of the first output transistor T21 and the bottom gate G311 of the second output transistor T31. The first gate metal layer M1 includes the top gate G212 of the first output transistor T21 and the top gate G312 of the second output transistor T31.

[0139] Optional, such as Figure 22 As shown, the display panel also includes a first bottom gate connection portion F11, a first top gate connection portion F12, and a first gate connection portion F10, which are disposed in different layers.

[0140] Wherein, along the direction h2 perpendicular to the plane where the substrate 1 is located, the first bottom gate connection portion F11 and the first top gate connection portion F12 do not overlap with the active layer S21 of the first output transistor T21 at least partially; and the first bottom gate connection portion F11 and the first top gate connection portion F12 do not overlap with the active layer S31 of the second output transistor T31 at least partially.

[0141] In this embodiment of the invention, at least one of the top gate G212 of the first output transistor T21 and the top gate G312 of the second output transistor T31 is disposed on the same layer as and connected to the first top gate connection portion F12, that is, the first gate metal layer M1 includes the first top gate connection portion F12.

[0142] At least one of the bottom gate G211 of the first output transistor T21 and the bottom gate G311 of the second output transistor T31 is disposed on the same layer as and connected to the first bottom gate connection portion F11. That is, the second gate metal layer M0 includes the first bottom gate connection portion F11.

[0143] Optional, combined Figure 23 As shown, Figure 23 for Figure 9 A schematic cross-sectional view along B4-B4' shows that, along direction h2 perpendicular to the plane containing substrate 1, the first gate connection portion F10 is located on the side of the first gate metal layer M1 away from the second gate metal layer M0. Figure 23 The source / drain metal layer M2 includes a first gate connection portion F10 as an example. One end of the first gate connection portion F10 is electrically connected to the first top gate connection portion F12 through a via K21, and the other end of the first gate connection portion F10 is electrically connected to the first bottom gate connection portion F11 through a via K22. Based on this arrangement, the direct connection between the top and bottom gates of the first output transistor T21 through a via penetrating the insulating layer between them is avoided. This reduces the requirements for the etching process and lowers the possibility of wire breakage at the connection between the top and bottom gates of the first output transistor T21, thus improving process reliability.

[0144] Optional, such as Figure 9 As shown, along the first direction h11, the first gate connection portion F10 is located between the first output transistor T21 and the second output transistor T31. Based on this arrangement, the first gate connection portion F10 can be used to connect both the top gate G212 and the bottom gate G211 of the first output transistor T21, and also to connect the top gate G312 and the bottom gate G311 of the second output transistor T31. That is, the first gate connection portion F10 can be shared by the first output transistor T21 and the second output transistor T31, which can reduce the number of gate connections used to connect the top and bottom gates, simplifying the structure of the driving unit 20 and reducing the area occupied by the driving unit 20 in the display panel.

[0145] For example, such as Figure 3As shown, the first sub-unit 2011 includes a first transistor T1, whose gate is electrically connected to the third node N3, and whose first and second terminals are electrically connected to the first level signal terminal VGH and the first node N1, respectively. When the driving unit 20 is working, under the control of the third node N3, the first transistor T1 is turned on, and the second level signal provided by the first level signal terminal VGH can be written into the first node N1 through the first transistor T1. Optionally, the first transistor T1 includes a P-type transistor.

[0146] For example, such as Figure 9 As shown, the third connection part 53 is connected to the second electrode of the first transistor T1 and the output module 4.

[0147] Optional, such as Figure 9 As shown, the first transistor T1 is located on the side of the second capacitor C2 close to the first level signal connection line VGH, so as to shorten the distance between the first electrode of the first transistor T1 and the first level signal connection line VGH, and facilitate their connection.

[0148] Optionally, the first transistor T1 includes a top-bottom dual-gate structure. For example... Figure 9 As shown, the display panel also includes a gate connection portion F01, which is used to connect the top gate and bottom gate of the first transistor T1. Optionally, the gate connection portion F01 can be located in the source / drain metal layer M2. Based on this arrangement, the top gate and bottom gate of the first transistor T1 are avoided from being directly connected through a via penetrating the insulating layer between them, which reduces the requirements for the etching process and reduces the possibility of wire breakage at the connection between the top gate and bottom gate of the first transistor T1, thus improving process reliability.

[0149] For example, such as Figure 9 As shown, the gate connection portion F01 can be located between the second capacitor C2 and the first level signal connection line VGH.

[0150] Optional, such as Figure 9 and Figure 12 As shown, along the second direction h12, the second capacitor C2 and the first capacitor C1 at least partially overlap. Along the second direction h12, the second capacitor C2 is located on the side of the first capacitor C1 closer to the first level signal connection line VGH, so as to shorten the distance between the second capacitor C2 and the first level signal connection line VGH and facilitate their connection.

[0151] For example, such as Figure 3As shown, the driving unit 20 further includes a fourth node N4; the first processing module 21 further includes a fourth node writing unit 204 and a third capacitor C3; the fourth node writing unit 204 is used to electrically connect the second level signal terminal VGL and the fourth node N4 under the control of the first clock signal terminal CK; and, under the control of the third node N3, to electrically connect the first clock signal terminal CK and the fourth node N4.

[0152] like Figure 3 As shown, in addition to the first subunit 2011 mentioned above, the first node writing unit 201 also includes a second subunit 2012. The second subunit 2012 is used to electrically connect the second clock signal terminal CKB and the first node N1 under the control of the fourth node N4.

[0153] like Figure 3 As shown, the first plate C31 of the third capacitor C3 is electrically connected to the fourth node N4; the second plate C32 of the third capacitor C3 is electrically connected to the second subunit 2012.

[0154] Optional, such as Figure 24 As shown, Figure 24 for Figure 4 An enlarged schematic diagram of the central region E3 shows that, along the first direction h11, at least a portion of the aforementioned fourth node writing unit 204 and at least a portion of the second sub-unit 2012 are located on both sides of the third capacitor C3.

[0155] Wherein, along the first direction h11, the third capacitor C3 is located away from the second capacitor C2 (the first output transistor). Figure 24 On one side (not shown), at least a portion of the fourth node writing unit 204 is located on the side of the third capacitor C3 away from the first output transistor, and at least a portion of the second sub-unit 2012 is located on the side of the third capacitor C3 close to the first output transistor.

[0156] Optional, such as Figure 24 As shown, the display panel also includes a fourth connection part 54, which connects the fourth node writing unit 204 and the second sub-unit 2012.

[0157] For example, such as Figure 24 and Figure 25 As shown, Figure 25 for Figure 24 A cross-sectional view along B5-B5' shows that the fourth connection portion 54 includes a second sub-connection portion 541, which includes the first plate C31 of the third capacitor C3. This arrangement effectively reuses the first plate C31 of the third capacitor C3 as a connection structure connecting the fourth node writing unit 204 and the second sub-unit 2012, simplifying the structure of the driving unit 20.

[0158] For example, such as Figure 3 As shown, the second sub-unit 2012 includes a second transistor T2 and a third transistor T3; the gate of the second transistor T2 is electrically connected to the fourth node N4, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the third transistor T3; the first terminal of the second transistor T2 and the gate of the third transistor T3 are both electrically connected to the second clock signal terminal CKB; the second terminal of the third transistor T3 is electrically connected to the first node N1.

[0159] For example, such as Figure 24 As shown, the display panel also includes a second clock signal connection line CKB. At least a portion of the second clock signal connection line CKB extends along a first direction h11 and along a second direction h12. At least a portion of the second clock signal connection line CKB is located on the side of the second level signal connection line VGL near the main body OUT10 of the first output line OUT1.

[0160] Optionally, in this embodiment of the invention, at least one of the second transistor T2 and the third transistor T3 may include a top-bottom dual-gate structure to improve the carrier mobility and subthreshold characteristics of the device.

[0161] Optional, combined Figure 26 and Figure 27 As shown, Figure 26 for Figure 24 An enlarged schematic diagram of the central region E4. Figure 27 for Figure 26 A cross-sectional schematic diagram along B6-B6' shows that the display panel further includes a second bottom gate connection portion F21, a second top gate connection portion F22, and a second gate connection portion F20; wherein, along the direction h2 perpendicular to the plane where the substrate 1 is located, the second top gate connection portion F22 and the second bottom gate connection portion F21 do not overlap at least partially with the active layer S2 of the second transistor T2.

[0162] In this embodiment of the invention, the second bottom gate connection portion F21 is disposed on the same layer as and connected to the bottom gate G21 of the second transistor T2, that is, the second gate metal layer M0 includes the second bottom gate connection portion F21. The second top gate connection portion F22 is disposed on the same layer as and connected to the top gate G22 of the second transistor T2, that is, the first gate metal layer M1 includes the second top gate connection portion F22.

[0163] The second gate connection portion F20 is located on the side of the first gate metal layer M1 away from the second gate metal layer M0; Figure 26 and Figure 27 The second gate connection F20 is located in the source / drain metal layer M2 as an example.

[0164] like Figure 26 and Figure 27As shown, one end of the second gate connection portion F20 is connected to the second top gate connection portion F22 through a via K31; the other end of the second gate connection portion F20 is connected to the second bottom gate connection portion F21 through a via K32. Based on this arrangement, the direct connection between the top and bottom gates of the second transistor T2 through a via penetrating the insulating layer between them is avoided. This reduces the requirements for the etching process and lowers the possibility of wire breakage at the connection between the top and bottom gates of the second transistor T2, thus improving process reliability.

[0165] like Figure 25 and Figure 27 As shown, the first plate C31 of the third capacitor C3 is located in the first gate metal layer M1, and the second plate of the third capacitor C3 is located in the capacitor metal layer MC.

[0166] Optional, such as Figure 27 As shown, the second top gate connection part F22 includes the first plate C31 of the third capacitor C3. That is, the first plate C31 of the third capacitor C3 can be reused as a connection structure connecting the top gate G22 of the second transistor T2 and the second gate connection part F20. Based on this arrangement, the space in the area where the third capacitor C3 is located can be fully utilized, which is beneficial to simplifying the structure of the driving unit 20 and reducing the area occupied by the driving unit 20 in the display panel.

[0167] For example, such as Figure 26 , Figure 27 and Figure 28 As shown, Figure 28 for Figure 26 A cross-sectional view along B7-B7' shows that the display panel also includes a fifth connecting portion 55, which connects to the second electrode plate C32 of the third capacitor C3, the first electrode of the third transistor T3, and the second electrode of the second transistor T2. Figure 27 and Figure 28 As shown, the fifth connection part 55 is located on the side of the second plate C32 of the third capacitor C3 away from the substrate 1. Figure 27 and Figure 28 The fifth connection part 55 is located in the source / drain metal layer M2 as an example.

[0168] Optional, such as Figure 27 As shown, in this embodiment of the invention, the fifth connecting portion 55 and the second gate connecting portion F20 can be arranged on the same layer and spaced apart to avoid contact between them. For example, the distance between them can be set according to process capabilities, and this embodiment of the invention does not limit this.

[0169] Optional, such as Figure 29 and Figure 30 As shown, Figure 29 This is a partial wiring diagram of another driving unit provided in an embodiment of the present invention. Figure 30 for Figure 29 A cross-sectional view along B8-B8' shows that the fourth connection portion 54 further includes a third sub-connection portion 542. Along a direction h2 perpendicular to the plane of the substrate 1, the third sub-connection portion 542 is located on the side of the third capacitor C3 away from the substrate 1. The third sub-connection portion 542 is connected to the first electrode C31 of the third capacitor C3 through at least two vias. The arrangement of the third sub-connection portion 542 can reduce the resistance of the fourth connection portion 54, thereby reducing signal delay.

[0170] Optional, such as Figure 31 As shown, Figure 31 for Figure 29 An enlarged schematic diagram of the source / drain metal layer in region E5. In this embodiment of the invention, the third sub-connection portion 542 and the fifth connection portion 55 can be arranged on the same layer but spaced apart to avoid contact between them. For example... Figure 31 As shown, there is a distance m between the third sub-connecting part 542 and the fifth connecting part 55. For example, the distance between the two can be set according to the process capability, and the present invention does not limit this. Figure 31 To illustrate, both are set on the same layer in the source / drain metal layer M2.

[0171] For example, such as Figure 3 As shown, the first processing module 21 further includes a second isolation transistor T12. The gate of the second isolation transistor T12 is electrically connected to the second level signal terminal VGL; the first and second terminals are electrically connected to the fourth node writing unit 204 and the first plate C31 of the third capacitor C3, respectively. The second isolation transistor T12 is used to disconnect when the potential of the first plate C31 of the third capacitor C3 is pulled down to a potential lower than the first level signal, so as to isolate the connection between the fourth node writing unit 204 and the first plate C31 of the third capacitor C3, thereby improving the reliability of the transistor in the fourth node writing unit 204.

[0172] For example, such as Figure 24 and Figure 29 As shown, along the second direction h12, the second isolation transistor T12 is located on the side of the second level signal connection line VGL close to the first level signal connection line VGH. Furthermore, along the first direction h11, the second isolation transistor T12 is located on the side of the third capacitor C3 close to the fourth node write unit 204.

[0173] like Figure 24 and Figure 29 As shown, the fourth connection portion 54 is electrically connected to the fourth node writing unit 204 via the second isolation transistor T12.

[0174] Optionally, the second isolation transistor T12 includes a top-bottom dual-gate structure. For example... Figure 24 and Figure 29 As shown, the display panel also includes a gate connection portion F12, which connects the top gate and bottom gate of the second isolation transistor T12. Optionally, the gate connection portion F12 can be located in the source / drain metal layer M2. This arrangement avoids directly connecting the top and bottom gates of the second isolation transistor T12 through vias penetrating the insulating layer between them, reducing the requirements for the etching process and lowering the possibility of wire breakage at the connection between the top and bottom gates of the second isolation transistor T12, thus improving process reliability.

[0175] Optional, such as Figure 24 , Figure 26 and Figure 29 As shown, the length of the third capacitor C3 in the second direction h12 is greater than or equal to its length in the first direction h11. Based on this arrangement, on the one hand, the area of ​​the third capacitor C3 can be set as large as possible to increase the driving capability of the driving unit 20. On the other hand, it can also save the space occupied by the driving unit 20 in the first direction h11, making it easier to set more devices on both sides of the third capacitor C3 in the first direction h11.

[0176] Optional, such as Figure 3 As shown, the fourth node write unit 204 includes: a seventh transistor T7, whose gate is electrically connected to the first clock signal terminal CK, whose first terminal is electrically connected to the second level signal terminal VGL, and whose second terminal is electrically connected to the fourth node N4; and an eighth transistor T8, whose gate is electrically connected to the third node N3, whose first terminal is electrically connected to the first clock signal terminal CK, and whose second terminal is electrically connected to the fourth node N4. Figure 3 The eighth transistor T8 is illustrated as a dual-gate transistor.

[0177] like Figure 24 As shown, the display panel also includes a first clock signal connection line CK. Along the second direction h12, the first clock signal connection line CK is located between the first level signal connection line VGH and the second level signal connection line VGL. The seventh transistor T7 is located on the side of the eighth transistor T8 close to the second level signal connection line VGL, so as to shorten the distance between the seventh transistor T7 and the second level signal connection line VGL, and facilitate the connection between the first electrode of the seventh transistor T7 and the second level signal connection line VGL.

[0178] Optionally, at least one of the seventh transistor T7 and the eighth transistor T8 includes a top-bottom dual-gate structure to improve the carrier mobility and subthreshold characteristics of the device.

[0179] For example, such as Figure 24As shown, the display panel also includes a gate connection portion F7 and a gate connection portion F8. The gate connection portion F7 is used to connect the top gate and bottom gate of the seventh transistor T7, and the gate connection portion F8 is used to connect the top gate and bottom gate of the eighth transistor T8. Optionally, the gate connection portion F7 and the gate connection portion F8 can be located in the source / drain metal layer M2. Based on this arrangement, the direct connection between the top gate and bottom gate of the seventh transistor T7 through vias penetrating the insulating layer between them is avoided, as is the direct connection between the top gate and bottom gate of the eighth transistor T8 through vias penetrating the insulating layer between them. This reduces the requirements for the etching process and reduces the possibility of wire breakage at the connection between the top gate and bottom gate, which is beneficial to improving process reliability.

[0180] Optional, such as Figure 3 As shown, the drive unit 20 also includes a second processing module 22, which is electrically connected to the second node N2.

[0181] like Figure 3 As shown, the second processing module 22 includes a fourth capacitor C4 and a third sub-unit 221. The first plate C41 of the fourth capacitor C4 and the third node writing unit 203 are electrically connected to the second node N2. The third sub-unit 221 is electrically connected to the second plate C42 of the fourth capacitor C4.

[0182] For example, such as Figure 24 and Figure 29 As shown, along the second direction h12, the fourth capacitor C4 is located between the second level signal connection line VGL and the main body OUT10 of the first output line OUT1. Furthermore, the fourth capacitor C4 and the third capacitor C3 at least partially overlap in the second direction h12. And along the first direction h11, the fourth capacitor C4 is located on the side of the second clock signal connection line CKB away from the first capacitor C1.

[0183] Optional, such as Figure 4 As shown, along the first direction h11, the third node writing unit 203 and the first output module 41 are located on both sides of the fourth capacitor C4.

[0184] For example, such as Figure 32 and Figure 33 As shown, Figure 32 for Figure 4 An enlarged schematic diagram of region E6 in the middle area. Figure 33 for Figure 32 A cross-sectional schematic diagram along B10-B10' shows that the display panel also includes a sixth connecting part 56, which connects the aforementioned third node writing unit and the first output module.

[0185] Optional, such as Figure 32 and Figure 33As shown, the sixth connection portion 56 includes a fourth sub-connection portion 561, which includes the first plate C41 of the fourth capacitor C4. Based on this arrangement, the first plate C41 of the fourth capacitor C4 can be reused as part of the sixth connection portion 56, making full use of the space in the area where the fourth capacitor C4 is located, thus reducing the space occupied by the driving unit 20 in the display panel.

[0186] Optional, such as Figure 3 As shown, the second node N2 includes a first sub-node N21 and a second sub-node N22; the first sub-node N21 is electrically connected to the first plate C41 of the fourth capacitor C4, and the second sub-node N22 is electrically connected to the first output module 41.

[0187] like Figure 3 As shown, the second processing module 22 also includes an adjustment transistor T40. The gate of the adjustment transistor T40 is electrically connected to the first sub-node N21, and its first and second terminals are electrically connected to the first sub-node N21 and the second sub-node N22, respectively. When the potential of the first sub-node N21 is lower than the first level signal, for example, when the first sub-node N21 is pulled low to the third level signal under the coupling effect of the fourth capacitor C4, the isolation transistor T40 is turned on, and the third level signal of the first sub-node N21 can be written to the second sub-node N22 through the isolation transistor T40. When the potential of the first sub-node N21 is greater than or equal to the first level signal, the isolation transistor T40 is turned off, thereby allowing the second sub-node N22 to maintain the third level signal. Based on this setting, the duration of the second sub-node N22 being at the third level signal can be greater than the duration of the first sub-node N21 being at the third level signal, thereby allowing the third output transistor T22 to be stably turned on under the control of the second sub-node N22.

[0188] Optional, such as Figure 32 As shown, along the first direction h11, the regulating transistor T40 is located on the side of the fourth capacitor C4 near the third output transistor T22. Along the second direction h12, the regulating transistor T40 is located between the second level signal connection line VGL and the main body OUT10 of the first output line OUT1.

[0189] like Figure 32 As shown, the sixth connection part 56 is electrically connected to the third output transistor T22 via the regulating transistor T40.

[0190] Optional, such as Figure 32 and Figure 33 As shown, the regulating transistor T40 includes a top-bottom dual-gate structure to improve the carrier mobility and subthreshold characteristics of the regulating transistor T40.

[0191] Combination Figure 34 As shown, Figure 34 for Figure 32 A cross-sectional schematic diagram along B11-B11' shows that the display panel further includes a third gate connection portion F40, a third bottom gate connection portion F41, and a third top gate connection portion F42 disposed in different layers. Specifically, along direction h2 perpendicular to the plane of substrate 1, the third bottom gate connection portion F41 and the third top gate connection portion F42 are both connected to the active layer of the regulating transistor. Figure 34 (Not shown) At least partially non-overlapping.

[0192] In this embodiment of the invention, the bottom gate G401 of the regulating transistor T40 is disposed on the same layer and connected to the third bottom gate connection portion F41; that is, the second gate metal layer M0 includes the third bottom gate connection portion F41. The top gate G402 of the regulating transistor T40 is disposed on the same layer and connected to the third top gate connection portion F42; that is, the first gate metal layer M1 includes the third top gate connection portion F42.

[0193] The third gate connection portion F40 is located on the side of the first gate metal layer M1 away from the second gate metal layer M0. Figure 34 The source / drain metal layer M2 includes a third gate connection portion F40 as an example.

[0194] Optionally, one end of the third gate connection portion F40 is connected to the third bottom gate connection portion F41 through a via K52, and the other end of the third gate connection portion F40 is connected to the third top gate connection portion F42 through a via K51. This arrangement avoids directly connecting the top and bottom gates of the regulating transistor T40 through a via penetrating the insulating layer between them. This reduces the requirements for the etching process and lowers the possibility of wire breakage at the connection between the top and bottom gates of the regulating transistor T40, thus improving process reliability.

[0195] For example, such as Figure 32 As shown, along the first direction h11, the third gate connection F40 is located on the side of the fourth capacitor C4 away from the isolation transistor T40. Along the second direction h12, the third gate connection F40 is located between the second level signal connection line VGL and the second clock signal connection line CKB. Based on this arrangement, the space on the side of the fourth capacitor C4 away from the isolation transistor T40 can be fully utilized, which helps to reduce the difficulty of setting up the third gate connection F40.

[0196] Optional, such as Figure 33As shown, the third top gate connection portion F42 includes the first plate C41 of the fourth capacitor C4. That is, the first plate C41 of the fourth capacitor C4 can be reused as a connection structure connecting the top gate G402 of the regulating transistor T40 and the third gate connection portion F40. Based on this arrangement, the space in the area where the fourth capacitor C4 is located can be fully utilized, which helps to simplify the structure of the driving unit 20 and reduce the area occupied by the driving unit 20 in the display panel.

[0197] Optional, such as Figure 3 As shown, the second processing module 22 also includes a third isolation transistor T13. The gate of the third isolation transistor T13 is electrically connected to the second-level signal terminal VGL, and the first and second terminals are electrically connected to the third node writing unit 203 and the second node N2, respectively. Figure 2 As shown, when the second node N2 is split into the first child node N21 and the second child node N22, the second terminal of the third isolation transistor T13 can be electrically connected to the first child node N21.

[0198] The fourth capacitor C4 couples the potential of the first sub-node N21 to a potential lower than the second level signal terminal VGL. For example, when the potential of the first sub-node N21 is coupled to the third level signal, the third isolation transistor T13 is turned off, which can prevent the third level signal of the first sub-node N21 from affecting the reliability of the transistor in the third node writing unit 203.

[0199] Optionally, the third isolation transistor T13 includes a P-type transistor.

[0200] like Figure 32 As shown, the sixth connection portion 56 is connected to the third node writing unit ( ) via the third isolation transistor T13. Figure 32 Electrical connection (not shown).

[0201] Optional, such as Figure 3 As shown, the third node write unit 203 includes a fourth transistor T4, whose gate is electrically connected to the first clock signal terminal CK, its first terminal is electrically connected to the first input terminal IN1, and its second terminal is electrically connected to the third isolation transistor T13.

[0202] Optional, such as Figure 3 As shown, the third subunit 221 includes: a fifth transistor T5, whose gate is electrically connected to the fourth node N4, its first terminal is electrically connected to the first level signal terminal VGH, and its second terminal is electrically connected to the second plate C42 of the fourth capacitor C4; and a sixth transistor T6, whose gate is electrically connected to the first plate C41 of the fourth capacitor C4, its first terminal is electrically connected to the second clock signal terminal CKB, and its second terminal is electrically connected to the second plate C42 of the fourth capacitor C4.

[0203] For example, the fifth transistor T5 and the sixth transistor T6 include P-type transistors.

[0204] For example, such as Figure 24 and Figure 29 As shown, the sixth transistor T6 and the fourth capacitor C4 are arranged along the first direction h11, and the sixth transistor T6 is located on the side of the fourth capacitor C4 away from the regulating transistor T40. Along the second direction h12, the sixth transistor T6 is located between the second level signal connection line VGL and the second clock signal connection line CKB, so as to shorten the distance between the sixth transistor T6 and the second clock signal connection line CKB and facilitate their connection.

[0205] Continue to refer to Figure 24 and Figure 29 As shown, the fifth transistor T5 and the sixth transistor T6 are arranged along the second direction h12, and along the second direction h12, the fifth transistor T5 is located on the side of the sixth transistor T6 closer to the first level signal connection line VGH, so as to shorten the distance between the first electrode of the fifth transistor T5 and the first level signal connection line VGH, so as to facilitate the connection between the two.

[0206] For example, such as Figure 24 , Figure 29 and Figure 32 As shown, the gate of the sixth transistor T6 is connected to the gate of the third output transistor T22 through the first plate C41 of the fourth capacitor C4. That is, the first plate C41 of the fourth capacitor C4 can also be reused as the connection between the gate of the sixth transistor T6 and the gate of the third output transistor T22. Based on this arrangement, the wiring structure of the driving unit 20 can be simplified, which is beneficial to further reduce the area occupied by the driving unit 20 in the display panel.

[0207] For example, the fifth transistor T5 includes a top-bottom dual-gate structure to improve the carrier mobility and subthreshold characteristics of the fifth transistor T5.

[0208] like Figure 24 and Figure 29 As shown, the display panel also includes a gate connection portion F50, which connects the top gate and bottom gate of the fifth transistor T5. This arrangement avoids directly connecting the top and bottom gates of the fifth transistor T5 through vias penetrating the insulating layer between them, reducing the requirements for the etching process and lowering the possibility of wire breakage at the connection between the top and bottom gates, thus improving process reliability.

[0209] For example, the gate connection F50 and the third capacitor C3 are arranged along the first direction h11.

[0210] Optionally, the sixth transistor T6 includes a top-bottom dual-gate structure to improve the carrier mobility and subthreshold characteristics of the sixth transistor T6.

[0211] like Figure 24 , Figure 29 and Figure 32 As shown, the third gate connection portion F40 is also used to connect the top gate and bottom gate of the sixth transistor T6. That is, the third gate connection portion F40 can be shared by the first regulating transistor T40 and the sixth transistor T6, which can reduce the number of gate connection portions used to connect the top gate and bottom gate, which helps to simplify the structure of the driving unit 20 and reduce the area occupied by the driving unit 20 in the display panel.

[0212] Optional, such as Figure 3 As shown, the driving unit 20 also includes a fourth isolation transistor T14. The gate of the fourth isolation transistor T14 is electrically connected to the second level signal terminal VGL, and the first and second terminals are electrically connected to the third node N3 and the second node N2, respectively.

[0213] like Figure 22 , Figure 24 , Figure 29 and Figure 32 As shown, the fourth isolation transistor T14 includes a top-bottom dual-gate structure to improve the carrier mobility and subthreshold characteristics of the fourth isolation transistor T14.

[0214] like Figure 3 , Figure 22 , Figure 24 and Figure 29 As shown, the display panel also includes a gate connection portion F14, which connects the top and bottom gates of the fourth isolation transistor T14. Optionally, the fourth isolation transistor T14 can be located in the source / drain metal layer M2. This arrangement avoids directly connecting the top and bottom gates of the fourth isolation transistor T14 through vias penetrating the insulating layer between them, reducing the requirements for the etching process and decreasing the possibility of wire breakage at the connection between the top and bottom gates, thus improving process reliability.

[0215] For example, the first isolation transistor T11 may also include a top-bottom dual-gate structure to improve the carrier mobility and subthreshold characteristics of the first isolation transistor T11.

[0216] Optionally, the gate connection portion F14 can also be connected to the bottom gate and top gate of the first isolation transistor T11. Based on this arrangement, the gate connection portion F14 can be reused as a connection portion connecting the top gate and bottom gate of the first isolation transistor T11. That is, the gate connection portion F14 can be shared by the fourth isolation transistor T14 and the first isolation transistor T11, which can reduce the number of gate connection portions used to connect the top gate and bottom gate, which helps to simplify the structure of the driving unit 20 and reduce the area occupied by the driving unit 20 in the display panel.

[0217] Optional, such as Figure 4 As shown, the length of the fourth capacitor C4 in the first direction h11 is greater than or equal to the length in the second direction h12. Based on this arrangement, on the one hand, the area of ​​the fourth capacitor C4 can be set as large as possible to increase the driving capability of the driving unit 20. On the other hand, the space occupied by the fourth capacitor C4 in the second direction h12 can be reduced, making it easier to set more devices on both sides of the fourth capacitor C4 in the second direction h12.

[0218] For example, such as Figure 4 As shown, along the second direction h12, the fourth capacitor C4 and the third capacitor C3 at least partially overlap.

[0219] For example, such as Figure 4 As shown, in this embodiment of the invention, the fourth output transistor T32 and the third output transistor T31 can be arranged along the second direction h12, and the fourth output transistor T32 can be located on the side of the third output transistor T31 that is close to the first output line OUT1.

[0220] Optional, such as Figure 3 As shown, the second output module 42 also includes a fifth capacitor C5 electrically connected to the gate of the first control signal output terminal OUT2 and the fourth output transistor T32. During the process of the first output terminal OUT1 outputting an enable level to control the fourth output transistor T32 to turn on, when the potential of the first control signal output terminal OUT2 changes from a high level signal to a low level signal, under the action of the fifth capacitor C5, the potential of the gate of the fourth output transistor T32 will be coupled to a signal with a lower potential than the first level signal provided by the second level signal terminal VGL, thereby enhancing the conduction capability of the fourth output transistor T32.

[0221] Optional, such as Figure 4 As shown, the display panel also includes a first input line IN1, which is electrically connected to the first input terminal IN1 of the current stage driving unit 20. For example, along the second direction h12, at least a portion of the first input line IN1 is located on the side of the first clock signal connection line CK near the first level signal connection line VGH.

[0222] For example, for any one of the first to N-1 level drive units 20, the first output line OUT1 electrically connected to the first output terminal OUT1 of the corresponding drive unit 20 can be multiplexed as the first input line IN1 electrically connected to the first input terminal IN1 of the next level drive unit 20. That is, one end of the first output line OUT1_i is connected to the first output terminal OUT1 of drive unit 20_i, and the other end is connected to the first input terminal IN1 of drive unit 20_i+1. Here, i is an integer, and 1≤i≤N-1.

[0223] Optional, such as Figure 2 As shown, the driving unit 20 includes at least two third node writing units 203, one of which is electrically connected to the first processing module 21; the other is electrically connected to the second processing module 22. Based on this configuration, the potential disturbance of the second node N2 can be prevented from affecting the operational stability of the first processing module 21. Figure 3 The third node writing unit electrically connected to the first processing module 21 and the third node writing unit electrically connected to the second processing module 22 are distinguished by 203_1 and 203_2, and the fourth transistor electrically connected to the first processing module 21 and the fourth transistor electrically connected to the second processing module 22 are distinguished by T4_1 and T4_2.

[0224] Optional, such as Figure 4 As shown, at least two third node write units 203 are arranged adjacently. Fourth transistors T4_1 and T4_2 can be arranged adjacently along the first direction h11. Based on this arrangement, the distance between the two fourth transistors and the first input line IN1 can be shortened, facilitating the connection between the first input line IN1 and the two fourth transistors.

[0225] Optional, such as Figure 4 As shown, the display panel also includes a first control signal input line IN21, a second control signal input line IN22, and a first control signal output line OUT2. The first control signal output line OUT2 is connected to the first plate of the fifth capacitor C5 and the second plate of the fourth output transistor T32, respectively.

[0226] Optional, such as Figure 3 As shown, the driving unit 20 also includes a reset transistor T50, whose gate is electrically connected to the reset control signal terminal RST, and whose first and second terminals are electrically connected to the first level signal terminal VGH and the third node N3, respectively.

[0227] For example, such as Figure 4As shown, along the first direction h11, the reset transistor T50 is located between the fourth transistor T4 and the seventh transistor T7. Furthermore, along the second direction h12, the reset transistor T50 is located between the fourth transistor T4 and the second-level signal connection line VGL.

[0228] like Figure 4 As shown, the display panel also includes a reset control connection line RST, which is located between the first clock signal connection line CK and the second level signal connection line VGL along the second direction h12.

[0229] For example, such as Figure 4 As shown, the display panel also includes a third node connection line 6, which is located on the side of the first level signal connection line VGH near the third capacitor C3. The third node connection line 6 is connected to the second terminal of the fourth transistor T4_1, the gate of the eighth transistor T8, and the first terminal of the fourth isolation transistor T14, respectively. Optionally, the third node connection line 6 can be located in the first gate metal layer M1.

[0230] For example, such as Figure 4 As shown, the driving unit 20 includes a first region D1 and a second region D2 arranged along the second direction h12. The first region D1 includes at least a portion of the first processing module 21, and the second region D2 includes at least a portion of the second processing module 22. Based on this arrangement, the first processing module 21 and the second processing module 22 can be placed in different regions as much as possible, which is beneficial to increasing the distance between different structures in the first processing module 21 and the second processing module 22 and reducing coupling.

[0231] like Figure 4 As shown, the first region D1 includes a first sub-region D11, a second sub-region D12, and a third sub-region D13 arranged along the first direction h11. The third sub-region D13 is located on the side of the second sub-region D12 away from the first sub-region D11. The first sub-region D11 includes a third node writing unit 203 and a fourth node writing unit 204. The second sub-region D12 includes a third capacitor C3 and a second sub-unit 2012. The third sub-region D13 includes a second capacitor C2 and a first sub-unit 2011. Based on this arrangement, it is beneficial to reduce the width of the driving unit 20 in the second direction h12.

[0232] For example, such as Figure 1 As shown, the display panel includes a display area AA, and the display area AA includes the aforementioned pixel circuit 3. Optionally, as... Figure 1 As shown, in this embodiment of the invention, the driving unit 20 can be disposed in the display area AA. For example, as... Figure 1As shown, along the second direction h12, in this embodiment of the invention, the driving unit 20 can be located between two adjacent circuit units 30, and the circuit unit 30 includes at least one pixel circuit 3. Figure 1 The circuit unit 30 includes three pixel circuits 3 as an example. Based on this arrangement, there is no need to set up an additional area around the display area AA to accommodate the driving circuit 2, thus enabling a borderless design for the display panel. When multiple display panels are spliced ​​together to form a large-screen display device with a larger size, the visibility of the splicing seam between two adjacent display panels can be weakened or even eliminated, thereby improving the visual effect of the large-screen display device.

[0233] When configuring the first output module 41 and the second output module 42 as described above, for example, as follows: Figure 4 As shown, in this embodiment of the invention, the first output module 41 and the second output module 42 can be arranged along the first direction h11 to make full use of the space of the width where the multiple pixel circuits 3 are located, and to reduce the length of the driving unit 20 in the second direction h12.

[0234] Optional, such as Figure 4 As shown, the length of the driving unit 20 in the first direction h11 is d1, and the length in the second direction h12 is d2, where d1 > d2.

[0235] For example, such as Figure 4 As shown, the first input line IN1 includes a first extension IN11 extending along the second direction h12, and the second control signal input line IN22 includes a second extension IN221 extending along the second direction h12. The length of the driving unit 20 in the first direction h11 can be the distance between the first extension IN11 and the second extension IN221. The length of the driving unit 20 in the second direction h12 can be the distance between the main body OUT10 of the first level signal connection line VGH and the first output line OUT1 in the second direction h12.

[0236] For example, such as Figure 2 As shown, the display panel also includes a first clock line C1 and a second clock line C2. The first clock line C1 is electrically connected to the first clock signal terminal CK of the odd-level driving unit 20 and electrically connected to the second clock signal terminal CKB of the even-level driving unit 20. The second clock line C1 is electrically connected to the second clock signal terminal CKB of the odd-level driving unit 20 and electrically connected to the first clock signal terminal CK of the even-level driving unit 20.

[0237] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 35 As shown, Figure 35 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above.

[0238] For example, such as Figure 35 As shown, the display device includes a splicing display device. This splicing display device includes at least two of the aforementioned display panels 100, suitable for large-screen display devices with display functions. For example, a frameless splicing display device.

[0239] For example, this type of splicing display device can be applied in public information display (PID) scenarios such as train stations and airports. When the splicing display device includes the aforementioned display panel 100, the area occupied by the driving circuit can be reduced, thereby achieving a seamless / borderless splicing effect for the splicing display device.

[0240] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0241] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Substrate; A driving circuit and a first output line located on one side of the substrate; At least a portion of the first output line extends along a first direction; The driving circuit includes multiple cascaded driving units, which are arranged along a second direction; the second direction intersects the first direction. The driving unit includes a first output terminal; the first output line is connected to the first output terminal of the current-level driving unit; The driving unit includes an output module, the output module includes a first capacitor, the first plate of the first capacitor is electrically connected to the first output terminal, and the second plate of the first capacitor is electrically connected to the second level signal terminal. and, Along a direction perpendicular to the plane of the substrate, the first output line at least partially overlaps with at least one plate of the first capacitor; It also includes a pixel circuit, which receives a first control signal; The driving unit further includes a first control signal output terminal, which is used to output the first control signal under the control of the first output terminal; The output module includes a first output module and a second output module; The first output module is electrically connected to the first output terminal and the first level signal terminal in response to the signal of the first node, and is electrically connected to the first output terminal and the second level signal terminal in response to the signal of the second node; The second output module, in response to the signal from the first node, is electrically connected to the first control signal output terminal and the first control signal input terminal; and, in response to the signal from the first output terminal, is electrically connected to the first control signal output terminal and the second control signal input terminal.

2. The display panel according to claim 1, characterized in that, The pixel circuit includes a pulse width modulation module and a pulse amplitude modulation module, wherein the pulse width modulation module receives a frequency sweep signal; The first control signal includes the frequency sweep signal; The first control signal input terminal includes a constant signal terminal; The second control signal input terminal includes a frequency sweep input signal terminal.

3. The display panel according to claim 1, characterized in that, The first output line includes a first connection portion, which overlaps with at least one plate of the first capacitor along a direction perpendicular to the plane of the substrate; wherein the first connection portion is located on the side of at least one plate of the first capacitor away from the substrate.

4. The display panel according to claim 3, characterized in that, The first plate of the first capacitor is electrically connected to the first output terminal, the first connection portion is located on the side of the first plate away from the substrate, and the first connection portion is electrically connected to the first plate through a hole.

5. The display panel according to claim 4, characterized in that, The first connecting portion is electrically connected to the first electrode plate through at least two vias, and the two vias are spaced apart.

6. The display panel according to claim 3, characterized in that, The first electrode plate is located on the side of the second electrode plate away from the substrate, and at least a portion of the first electrode plate is reused as the first connection portion.

7. The display panel according to claim 3, characterized in that, The width of the first connecting portion in the first direction is greater than the line width of the other portions of the output line.

8. The display panel according to claim 1, characterized in that, The driving unit further includes a first isolation transistor; The gate of the first isolation transistor is connected to the second level signal terminal, the first terminal is connected to the first output line, and the second terminal is electrically connected to the second output module.

9. The display panel according to claim 8, characterized in that, The display panel further includes a second connection portion, which connects the second electrode of the first isolation transistor and the second output module; Along a direction perpendicular to the plane of the substrate, the first output line and the second connection portion do not overlap.

10. The display panel according to claim 9, characterized in that, Along the first direction, the first output line is at least partially located on the side of the second connection portion away from the second output module.

11. The display panel according to claim 1, characterized in that, The drive unit further includes: First input terminal; The third node; The third node writing unit is used to electrically connect the first input terminal and the third node under the control of the first clock signal terminal; A first processing module electrically connected to the first node, the first processing module including a second capacitor and a first node writing unit; the first node writing unit including a first sub-unit, the first sub-unit being used to electrically connect the first level signal terminal and the first node under the control of the third node.

12. The display panel according to claim 11, characterized in that, The display panel further includes a third connecting part, which connects the first subunit and the output module.

13. The display panel according to claim 12, characterized in that, The third connection portion includes a first sub-connection portion, and the first sub-connection portion includes the first plate of the second capacitor.

14. The display panel according to claim 12, characterized in that, The first output module includes a first output transistor, the gate of which is electrically connected to the first node; The second output module includes a second output transistor, the gate of which is electrically connected to the first node; At least one of the first output transistor and the second output transistor includes a top-bottom dual-gate structure.

15. The display panel according to claim 14, characterized in that, The display panel further includes a first gate connection portion, a first bottom gate connection portion, and a first top gate connection portion disposed in different layers, wherein... The bottom gate of at least one of the first output transistor and the second output transistor is disposed on the same layer as and connected to the first bottom gate connection portion; The top gate of at least one of the first output transistor and the second output transistor is disposed on the same layer as and connected to the first top gate connection portion; One end of the first gate connection portion is electrically connected to the first bottom gate connection portion through a via, and the other end of the first gate connection portion is electrically connected to the first top gate connection portion through a via.

16. The display panel according to claim 12, characterized in that, The first sub-unit includes a first transistor, whose gate is electrically connected to the third node, and whose first electrode and second electrode are electrically connected to the first level signal terminal and the first node, respectively. The third connection portion connects the first transistor and the output module.

17. The display panel according to claim 11, characterized in that, Along the second direction, the second capacitor and the first capacitor at least partially overlap.

18. The display panel according to claim 11, characterized in that, The drive unit also includes a fourth node; The first processing module also includes a fourth node writing unit and a third capacitor; The fourth node writing unit is used to electrically connect the second level signal terminal and the fourth node under the control of the first clock signal terminal; and to electrically connect the first clock signal terminal and the fourth node under the control of the third node. The first node writing unit also includes a second sub-unit. The first plate of the third capacitor is electrically connected to the fourth node; the second plate of the third capacitor is electrically connected to the second sub-unit. The second subunit is used to electrically connect the second clock signal terminal and the first node under the control of the fourth node.

19. The display panel according to claim 18, characterized in that, The display panel also includes a fourth connecting part. The fourth connection unit connects the fourth node writing unit and the second sub-unit.

20. The display panel according to claim 19, characterized in that, The fourth connection portion includes a second sub-connection portion, and the second sub-connection portion includes the first plate of the third capacitor.

21. The display panel according to claim 19, characterized in that, The second sub-unit includes a second transistor and a third transistor; The gate of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor; both the first terminal of the second transistor and the gate of the third transistor are electrically connected to the second clock signal terminal; the second terminal of the third transistor is electrically connected to the first node.

22. The display panel according to claim 21, characterized in that, The second transistor includes a top-bottom dual-gate structure; The display panel further includes a second gate connection portion, a second bottom gate connection portion, and a second top gate connection portion disposed in different layers; wherein... The bottom gate of the second transistor is disposed on the same layer as and connected to the second bottom gate connection portion; The top gate of the second transistor is disposed on the same layer as and connected to the second top gate connection portion; One end of the second gate connection portion is connected to the second top gate connection portion through a via; the other end of the second gate connection portion is connected to the second bottom gate connection portion through a via.

23. The display panel according to claim 22, characterized in that, The second top grid connection includes the first plate of the third capacitor.

24. The display panel according to claim 22, characterized in that, The display panel further includes a fifth connecting part, which connects the second plate of the third capacitor, the first electrode of the third transistor, and the second electrode of the second transistor. The fifth connection portion is located on the side of the third capacitor away from the substrate.

25. The display panel according to claim 24, characterized in that, The fifth connection portion and the second gate connection portion are on the same layer and spaced apart.

26. The display panel according to claim 24, characterized in that, The fourth connection portion further includes a third sub-connection portion, which is located on the side of the third capacitor away from the substrate along a direction perpendicular to the plane of the substrate. The third sub-connection portion is connected to the first plate of the third capacitor through at least two vias.

27. The display panel according to claim 26, characterized in that, The third sub-connecting part and the fifth connecting part are on the same layer and spaced apart.

28. The display panel according to claim 19, characterized in that, The first processing module also includes a second isolation transistor. The gate of the second isolation transistor is electrically connected to the second level signal terminal; The fourth connection portion is electrically connected to the fourth node writing unit via the second isolation transistor.

29. The display panel according to claim 18, characterized in that, The length of the third capacitor in the second direction is greater than or equal to its length in the first direction.

30. The display panel according to claim 18, characterized in that, The driving unit further includes a second processing module, which is electrically connected to the second node. The second processing module includes a fourth capacitor and a third sub-unit. The first plate of the fourth capacitor and the third node writing unit are electrically connected to the second node; The third subunit is electrically connected to the second plate of the fourth capacitor.

31. The display panel according to claim 30, characterized in that, The display panel further includes a sixth connection part, which connects the third node writing unit and the first output module; The sixth connecting part includes a fourth sub-connecting part, and the fourth sub-connecting part includes the first plate of the fourth capacitor.

32. The display panel according to claim 31, characterized in that, The second node includes a first child node and a second child node; The first sub-node is electrically connected to the first plate of the fourth capacitor, and the second sub-node is electrically connected to the first output module. The second processing module further includes an adjustment transistor electrically connected to the first sub-node and the second sub-node, wherein the gate of the adjustment transistor is connected to the first sub-node; The sixth connection part is electrically connected to the first output module through the regulating transistor.

33. The display panel according to claim 32, characterized in that, The regulating transistor includes a top-bottom dual-gate structure; The display panel further includes a third gate connection portion, a third bottom gate connection portion, and a third top gate connection portion disposed in different layers; wherein... The bottom gate of the regulating transistor is disposed on the same layer as and connected to the third bottom gate connection portion; The top gate of the regulating transistor is disposed on the same layer as and connected to the third top gate connection portion; One end of the third gate connection portion is connected to the third bottom gate connection portion through a via, and the other end of the third gate connection portion is connected to the third top gate connection portion through a via.

34. The display panel according to claim 33, characterized in that, The third top grid connection includes the first plate of the fourth capacitor.

35. The display panel according to claim 31, characterized in that, The second processing module further includes a third isolation transistor electrically connected between the third node writing unit and the second node, wherein the gate of the third isolation transistor is electrically connected to the second level signal terminal; The sixth connection portion is electrically connected to the third node writing unit via the third isolation transistor.

36. The display panel according to claim 35, characterized in that, The third node writing unit includes a fourth transistor, whose gate is electrically connected to the first clock signal terminal, whose first electrode is electrically connected to the first input terminal, and whose second electrode is electrically connected to the third isolation transistor through the sixth connection portion.

37. The display panel according to claim 31, characterized in that, The third subunit includes: The fifth transistor has its gate electrically connected to the fourth node, its first electrode electrically connected to the first level signal terminal, and its second electrode electrically connected to the second plate of the fourth capacitor. The sixth transistor has its gate electrically connected to the first plate of the fourth capacitor, its first plate electrically connected to the second clock signal terminal, and its second plate electrically connected to the second plate of the fourth capacitor. The gate of the sixth transistor is connected to the first output module through the first plate of the fourth capacitor.

38. The display panel according to claim 30, characterized in that, The length of the fourth capacitor in the first direction is greater than or equal to its length in the second direction.

39. The display panel according to claim 30, characterized in that, Along the second direction, the fourth capacitor and the third capacitor at least partially overlap.

40. The display panel according to claim 30, characterized in that, The drive unit includes a first region and a second region arranged along the second direction. The first region includes at least a portion of the first processing module; The second region includes at least a portion of the second processing module.

41. The display panel according to claim 40, characterized in that, The first region includes a first sub-region, a second sub-region, and a third sub-region arranged along the first direction, wherein the third sub-region is located on the side of the second sub-region away from the first sub-region; The first sub-region includes the third node writing unit and the fourth node writing unit; The second sub-region includes the third capacitor and the second sub-unit; The third sub-region includes the second capacitor and the first sub-unit.

42. The display panel according to claim 30, characterized in that, The driving unit includes at least two third node writing units, one of which is electrically connected to the first processing module; the other is electrically connected to the second processing module.

43. The display panel according to claim 42, characterized in that, At least two of the third node writing units are arranged adjacent to each other.

44. A display device, characterized in that, Includes the display panel as described in any one of claims 1-43.

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