Display panel and method for repairing display panel

Abstract

A display panel and a method of repairing the display panel are provided. The display panel includes a substrate layer, a data line, a first power line, a sensing line, first to third pixel circuits each including first to third transistors, a scan line, a first light emitting element overlapping the first pixel circuit, and a second light emitting element overlapping the second pixel circuit. A second light emitting element overlapping the second pixel circuit and connected to the second pixel circuit; and a third light emitting element overlapping the data line. The third pixel circuit is disconnected from the third light emitting element and connected to the first light emitting element, and at least any one of semiconductor patterns included in a first transistor, a second transistor, or a third transistor of the first pixel circuit is disconnected.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0151545, filed on November 6, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure herein relates to a display panel having improved display quality and a method of repairing a display panel. Background Art

[0004] The display panel includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels includes a light emitting element and a pixel circuit for controlling the light emitting element. The pixel circuit may include a plurality of organically connected transistors and at least one capacitor. Summary of the invention

[0005] The present disclosure provides a display panel having improved display quality and a method of repairing the display panel.

[0006] One or more embodiments of the present disclosure provide a display panel, comprising: a base layer; a data line, which is above the base layer, arranged along a first direction and extends along a second direction intersecting the first direction; a first power line, which extends along the first direction; a sensing line, which is spaced apart from the first power line in the second direction and extends along the first direction; a first pixel circuit, a second pixel circuit, and a third pixel circuit, each comprising a first transistor, a second transistor, and a third transistor including a semiconductor pattern, at least one of the semiconductor patterns of the first pixel circuit being disconnected; a scan line, which is spaced apart from the sensing line in the second direction and extends along the first direction, wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are between the scan line and the sensing line; a first light-emitting element, which overlaps with the first pixel circuit and is connected to the third pixel circuit; a second light-emitting element, which overlaps with the second pixel circuit and is connected to the second pixel circuit; and a third light-emitting element, which overlaps with the data line and is disconnected from the third pixel circuit.

[0007] The third light emitting element may be disconnected from the first pixel circuit and the second pixel circuit and may be configured not to emit light, and the first light emitting element and the second light emitting element are configured to emit light.

[0008] The first light-emitting element, the second light-emitting element, and the third light-emitting element may each include a first electrode, a second electrode above the first electrode, and a common layer between the first electrode and the second electrode, wherein the common layer and the second electrode are commonly located in the first light-emitting element, the second light-emitting element, and the third light-emitting element.

[0009] The display panel may further include a pixel defining layer over the base layer and defining an opening exposing the first electrode and including a first opening defining the first light emitting region, a second opening defining the second light emitting region, and a third opening defining the third light emitting region.

[0010] The first electrode of the third light emitting element may be disconnected.

[0011] In a plan view, the first electrode of the third light emitting element may be divided into a first portion and a second portion along a long side of the third opening extending in the second direction, wherein the first portion is connected to the third pixel circuit and wherein the second portion is disconnected from the third pixel circuit.

[0012] The scan line may include a scan pattern extending along the second direction and overlapping the semiconductor pattern in the second transistor.

[0013] The scan pattern may include a first pattern overlapping the second transistor of the first pixel circuit and a second pattern disconnected from the first pattern and overlapping the second transistor of the second pixel circuit and the second transistor of the third pixel circuit.

[0014] One end of the first portion may be connected to the first pattern via a first repair hole in the organic insulating layer, and the first electrode of the first light emitting element is connected to the first pattern via a second repair hole in the organic insulating layer spaced apart from the first repair hole.

[0015] The first electrode of the first light emitting element may be connected to the third pixel circuit via the first pattern and the first portion.

[0016] The display panel may further include a light control layer over the first light emitting element, the second light emitting element, and the third light emitting element, wherein the light control layer includes a color control layer including quantum dots and a color filter over the color control layer.

[0017] The first light emitting element may be configured to generate light that passes through the light management layer to provide green light, and the second light emitting element may be configured to generate light that passes through the light management layer to provide red light.

[0018] In one or more embodiments of the present disclosure, a method for repairing a display panel includes: forming a first pixel circuit, a second pixel circuit, and a third pixel circuit, each including a first transistor, a second transistor, and a third transistor; forming a scanning line including a scanning pattern overlapping a semiconductor pattern in the second transistor; checking signals of the first pixel circuit, the second pixel circuit, and the third pixel circuit; disconnecting the semiconductor pattern in the first transistor of the first pixel circuit, the semiconductor pattern in the second transistor of the first pixel circuit, and the semiconductor pattern in the third transistor of the first pixel circuit; dividing the scanning pattern into a first pattern overlapping a second transistor of the first pixel circuit and a second pattern overlapping a second transistor of the second pixel circuit and a second transistor of the third pixel circuit; forming an organic insulating layer covering the first pixel circuit, the second pixel circuit, and the third pixel circuit; forming a first repair hole and a second repair hole overlapping the first pattern in the organic insulating layer; forming a first electrode overlapping the first pixel circuit, the second pixel circuit, and the third pixel circuit on the organic insulating layer; dividing the first electrode overlapping the third pixel circuit into a first part connected to the third pixel circuit and a second part separated from the third pixel circuit; and connecting the third pixel circuit to a first electrode among the first electrodes overlapping the first pixel circuit.

[0019] Connecting the third pixel circuit to the one of the first electrodes overlapping the first pixel circuit may include irradiating the first repair hole and the second repair hole with a laser.

[0020] The one of the first electrodes overlapping the first pixel circuit may be located in the first repair hole and may be connected to the first pattern, and the first portion may be located in the second repair hole and may be connected to the first pattern.

[0021] The method may further include forming a pixel defining layer on the organic insulating layer that defines a first opening, a second opening, and a third opening that respectively expose a portion of the first electrode.

[0022] A boundary between the first portion and the second portion may be formed along one side of the third opening overlapping the third pixel circuit in a plan view.

[0023] The method may further include: forming a common layer on the first electrode; and forming a second electrode on the common layer.

[0024] A first opening overlapping with a first electrode among the first electrodes connected to a third pixel circuit can be configured to emit light, a second opening overlapping with another first electrode among the first electrodes connected to a second pixel circuit can be configured to emit light, and a third opening overlapping with another first electrode among the first electrodes overlapping with the third pixel circuit can be configured not to emit light.

[0025] The second opening and the third opening may be spaced apart from each other along a first direction in which the scan line extends, and the first opening may be spaced apart from the second opening along a second direction crossing the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the disclosure and together with the description serve to explain aspects of the disclosure.

[0027] In the attached picture:

[0028] Figure 1A is a perspective view of a display panel according to one or more embodiments of the present disclosure;

[0029] Figure 1B is a perspective view of a curved display panel according to one or more embodiments of the present disclosure;

[0030] Figure 2A is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0031] Figure 2B is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0032] Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0033] Figure 4A and Figure 4B is an enlarged plan view of a display area according to one or more embodiments of the present disclosure;

[0034] Figure 5 is a plan view according to a stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure;

[0035] Figure 6 It is along Figure 5 A cross-sectional view taken along line II';

[0036] 7A to 7I is a plan view showing, for each layer, a stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure;

[0037] Figure 8 is an equivalent circuit diagram illustrating a repair process of one pixel included in a repair unit pixel according to one or more embodiments of the present disclosure;

[0038] 9A to 9Cis a plan view illustrating a repair process of a conductive pattern included in a repair unit pixel according to one or more embodiments of the present disclosure; and

[0039] Fig.10 It is along Fig. 9C A cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0040] By referring to the detailed description of the embodiments and the accompanying drawings, it is easier to understand the various aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the various aspects of the present disclosure to those skilled in the art. Accordingly, redundant, irrelevant or unrelated to the description of the embodiments or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the various aspects of the present disclosure can be omitted. Unless otherwise stated, the same reference numerals, characters or combinations thereof represent the same elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0041] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. When describing an embodiment, the use of "may", "might", "may not" or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and substitutions within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various linkages and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in combination.

[0042] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for a particular material, material property, size, proportion, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements.

[0043] Various embodiments are described herein with reference to schematic cross-sectional illustrations of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are contemplated. In addition, the specific structural or functional descriptions disclosed herein are described only for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the illustrated elements, layers, or regions, but should include deviations in shapes, such as those caused by manufacturing.

[0044] For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0045] For ease of explanation, spatially relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side" and the like may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as being "below", "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can include both upper and lower orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, without being limited to the upper side of the second part based on the direction of gravity.

[0046] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapping" means that the first object can be above or below or to the side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing, extending above, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will recognize and understand. The expression "non-overlapping" may include meanings such as "separated from" or "set beside" or "offset from" and any other suitable equivalents that a person of ordinary skill in the art will recognize and understand.

[0047] It will be understood that when an element, layer, region or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region or component, the element, layer, region or component may be formed directly on, directly on, directly connected to or coupled to the other element, layer, region or component, or may be formed indirectly on, indirectly on, indirectly connected to or coupled to the other element, layer, region or component, such that one or more intervening elements, layers, regions or components may be present. Additionally, this may collectively mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, and / or capacitors, etc. When describing embodiments, expressions of connection represent electrical connections unless explicitly described as being directly connected, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or on another component without intermediate components.

[0048] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts such as "between" and "immediately between" or "adjacent to" and "directly adjacent to" can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0049] For the purposes of this disclosure, when following a list of elements, expressions such as "at least one of," "any one of," or "one or more of" modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when preceding or following a list of elements, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases modify the entire list of elements and do not modify the individual elements of the list.

[0050] It will be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish an element, member, component, area, region, layer, part or part from another element, member, component, area, region, layer, part or part. Therefore, the first element, component, area, layer or part described below can be referred to as the second element, component, area, layer or part, without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish elements of different classes or groups in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0051] In the example, the first direction, the second direction and / or the third direction are not limited to the directions corresponding to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction, the second direction and the third direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0052] The terms used in this article are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used in this article, the singular form "a" is intended to also include the plural form, and the plural form is also intended to include the singular form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprise", "include", "contain" and "have" indicate the presence of the described features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or increase of one or more other features, wholes, steps, operations, elements, parts and / or their groups.

[0053] When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described successively may be performed substantially simultaneously or in an order opposite to the described order.

[0054] As used herein, the terms "substantially", "approximately", "roughly" and similar terms are used as approximate terms and not as terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "roughly" as used herein include the value and mean within an acceptable deviation range for the particular value determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0055] In some embodiments, known structures and devices related to one or more functional blocks (e.g., block diagrams), units and / or modules may be described and shown in the drawings to avoid unnecessary blurring of various embodiments. Those skilled in the art will appreciate that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and can be optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules may be physically separated into two or more interacting separate blocks, units and / or modules without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and unless explicitly defined as such in this article, these terms should not be interpreted in an idealized or overly formal sense.

[0057] Figure 1A is a perspective view of a display panel according to one or more embodiments of the present disclosure. Figure 1B is a perspective view of a curved display panel according to one or more embodiments of the present disclosure. Figure 2A is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Figure 2B is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0058] The display surface DP-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) indicates a third direction DR3. The front surface (or top surface) and the rear surface (or bottom surface) of each layer or each unit described below are distinguished based on the third direction DR3.

[0059] The display panel DP may include a display area DA and a non-display area NDA. Figure 2B ) is located in the display area DA, and the pixels PX11 to PXnm (see Figure 2B ) is not located in the non-display area NDA. The non-display area NDA is defined along the edge of the display surface DP-IS. The non-display area NDA may surround the display area DA. In one or more embodiments of the present disclosure, the non-display area NDA may be omitted or may be located only on one side of the display area DA.

[0060] refer to Figure 1B According to one or more embodiments, the display panel DP-1 may be bent along the first direction DR1 relative to an imaginary axis AX extending in the second direction DR2. However, one or more embodiments of the present disclosure are not limited thereto, and the imaginary axis AX may extend in the first direction DR1, or the display panel DP-1 may be bent relative to a plurality of axes extending in different directions.

[0061] The display panels DP and DP-1 according to one or more embodiments may be rollable display panels, foldable display panels, or slidable display panels. Here, the display panels DP and DP-1 may have flexible properties, and when mounted on a display device, the display panels DP and DP-1 may be folded or rolled. Accordingly, the display panels DP and DP-1 may include a curved display surface DP-IS or a three-dimensional display surface DP-IS. The three-dimensional display surface DP-IS may include a plurality of display areas DA indicating different directions from each other.

[0062] According to one or more embodiments, the unit pixels PXU arranged along the first direction DR1 and the second direction DR2 may be located on the display surface DP-IS. One unit pixel PXU may include pixels PX11 to PXnm (see Figure 2B ) at least two pixels.

[0063] Pixels PX11 to PXnm (see Figure 2B ) The emission area, shape and arrangement form of each of the pixels included in one unit pixel PXU are not limited to any embodiment. For example, the pixels included in the unit pixel PXU may have different emission areas, respectively. In addition, the light-emitting areas may each have a circular shape or a polygonal shape in a plan view.

[0064] refer to Figure 2A, the display panel DP according to one or more embodiments of the present disclosure may include a base layer BS and a circuit element layer DP-CL, a display element layer DP-OLED, an encapsulation layer TFE, a light control layer OSL, and a window panel WD located on the base layer BS. The display panel DP may further include a functional layer such as an anti-reflection layer or a refractive index adjustment layer. The circuit element layer DP-CL may include at least a circuit element and a plurality of insulating layers. The insulating layer to be described below may include an organic layer and / or an inorganic layer.

[0065] The base layer BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may include at least any one of acrylate resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. In addition, the base layer BS may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0066] For the circuit element layer DP-CL, the insulating layer, the semiconductor layer and the conductive layer are formed by processes such as a coating process and a deposition process. Then, the insulating layer, the semiconductor layer and the conductive layer can be selectively patterned by a photolithography process and an etching process. Semiconductor patterns, conductive patterns or signal lines, etc. can be formed by such processes. Patterns located in the same layer can be formed by the same process.

[0067] The circuit element layer DP-CL may include a circuit element layer connected to the pixels PX11 to PXnm (see Figure 2B ) driving circuit or signal line. The display element layer DP-OLED may include a light emitting element OLED (see Figure 3 ) and pixel definition layer PDL (see Figure 6 ).

[0068] The encapsulation layer TFE may be located on the display element layer DP-OLED and may protect the light emitting element OLED (see Figure 3 ). The encapsulation layer TFE may include an inorganic layer and an organic layer between the inorganic layers. The inorganic layer may protect the light emitting element OLED (see Figure 3 ) from moisture and oxygen, and the organic layer protects the light-emitting element OLED (see Figure 3 ) from foreign matter such as dust particles.

[0069] The light control layer OSL may include a layer capable of switching between pixels PX11 to PXnm (see Figure 2B ) in an optical control pattern that modifies the optical characteristics of source light generated in the light control pattern. The light control pattern may include quantum dots and may also include a color filter that selectively transmits light passing through the light control pattern.

[0070] The window panel WD may be located at an upper portion of the display panel DP and may transmit an image provided from the display panel DP to the outside. Figure 1A As shown in , the display area DA and the non-display area NDA of the display surface DP-IS may be distinguished from each other. A boundary between the display area DA and the non-display area NDA may be located under the window panel WD and may be defined by a bezel pattern that absorbs light.

[0071] The window panel WD may include a base layer and a functional layer on the base layer. The functional layer may include a protective layer or an anti-fingerprint layer, etc. The base layer of the window panel WD may be composed of glass, sapphire or plastic, etc.

[0072] Figure 2B 1 shows a planar arrangement relationship of signal lines SL1 to SLn and DL1 to DLm and pixels PX11 to PXnm included in the display panel DP, where m and n are each a natural number greater than 0. The signal lines SL1 to SLn and DL1 to DLm may include a plurality of scan lines SL1 to SLn and a plurality of data lines DL1 to DLm.

[0073] The pixels PX11 to PXnm may be located in the display area DA. The pixels PX11 to PXnm may each be connected to a corresponding scan line among a plurality of scan lines SL1 to SLn and a corresponding data line among a plurality of data lines DL1 to DLm. The pixels PX11 to PXnm may each include a pixel circuit PC (see Figure 3 ) and light-emitting elements OLED (see Figure 3 ). Depending on the pixel circuit PC of each of the pixels PX11 to PXnm (see Figure 3 ) configuration, the display panel DP can be equipped with more types of signal lines.

[0074] The gate driving circuit GDC may be located in the non-display area NDA. The gate driving circuit GDC may be integrated in the display panel DP through an oxide silicon gate driving circuit (OSG) process or an amorphous silicon gate driving circuit (ASG) process.

[0075] Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure. Figure 3 Pixels PX11 to PXnm are shown (see Figure 2B ) is an equivalent circuit diagram of a pixel PXij in which i is a natural number greater than zero and less than or equal to n, and j is a natural number greater than zero and less than or equal to m. The three pixels PXij can be located Figure 1A. The pixels PXij may each include a pixel circuit PC and a light emitting element OLED to be described later. The pixel circuit PC may include a plurality of transistors T1, T2, and T3 and a capacitor Cst.

[0076] The plurality of transistors T1, T2 and T3 may be formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. The first to third transistors T1, T2 and T3 may each include any one of a silicon semiconductor and an oxide semiconductor. Here, although not limited to any embodiment, the oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor, and the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc.

[0077] Hereinafter, the first to third transistors T1, T2 and T3 will be described as n-type transistors, but one or more embodiments of the present disclosure are not limited thereto. Depending on the applied signal, each of the first to third transistors T1, T2 and T3 may be a p-type transistor or an n-type transistor. Here, the source and drain of the p-type transistor may correspond to the drain and source of the n-type transistor, respectively.

[0078] Figure 3 A pixel PXij connected to an i-th scan line SCLi, an i-th sensing line SSLi, a j-th data line DLj, and a j-th initialization line ILj is shown.

[0079] The pixel circuit PC may include a first transistor T1 (driving transistor), a second transistor T2 (switching transistor), a third transistor T3 (sensing transistor), and a capacitor Cst. However, the pixel circuit PC may further include additional transistors and additional capacitors, and is not limited.

[0080] The light emitting element OLED may be an organic light emitting element or an inorganic light emitting element including an anode (first electrode) and a cathode (second electrode). The anode (first electrode) of the light emitting element OLED may receive a first voltage ELVDD via a first transistor T1, and the cathode (second electrode) of the light emitting element OLED may receive a second voltage ELVSS. The light emitting element OLED may emit light by receiving the first voltage ELVDD and the second voltage ELVSS.

[0081] The first transistor T1 may include a drain D1 receiving a first voltage ELVDD, a source S1 connected to an anode of the light emitting element OLED, and a gate G1 connected to the capacitor Cst. The first transistor T1 may control a driving current flowing from a line supplying the first voltage ELVDD to the light emitting element OLED based on a value of a voltage stored in the capacitor Cst.

[0082] The second transistor T2 may include a drain D2 connected to the jth data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 for receiving the i-th first scan signal SCi. The second transistor T2 may provide the data voltage Vd to the first transistor T1 in response to the i-th first scan signal SCi.

[0083] The third transistor T3 may include a source S3 connected to the jth initialization line ILj, a drain D3 connected to the anode of the light emitting element OLED, and a gate G3 receiving the i-th second scan signal SSi. The jth initialization line ILj may receive an initialization voltage Vintit.

[0084] The capacitor Cst may store a voltage difference of different values ​​depending on an input signal. For example, the capacitor Cst may store a voltage corresponding to a difference between the first voltage ELVDD and a voltage received from the second transistor T2.

[0085] Figure 4A is an enlarged plan view of a display area according to one or more embodiments of the present disclosure. Figure 4A , the source light generated in the first pixel PX-G may be provided to the first pixel region PXA-G (first light emitting region), the source light generated in the second pixel PX-R may be provided to the second pixel region PXA-R (second light emitting region), and the source light generated in the third pixel PX-B may be provided to the third pixel region PXA-B (third light emitting region). The first to third pixel regions PXA-G, PXA-R, and PXA-B may be respectively connected to the pixel defining layer PDL (see Figure 6 ) defined in the opening PDL-OP (see Figure 6 ) corresponds to the opening PDL-OP (see Figure 6 ) may include a first opening defining a first light emitting area, a second opening defining a second light emitting area, and a third opening defining a third light emitting area.

[0086] exist Figure 4A For convenience of explanation, the first electrodes (eg, Figure 6 The shapes of AE-G) shown in FIG. 1 are referred to as the shapes of the first to third pixels PX-G, PX-R, and PX-B.

[0087] The first to third pixels PX-G, PX-R, and PX-B may each include a light emitting element OLED (see Figure 6 ), and the light emitting element OLED (see Figure 6 ) can emit source light of the same color. For example, the source light can be blue light. In the light emitting element OLED (see Figure 6 ) can be generated by including Figure 2AThe converted light can be emitted through the first pixel area PXA-G, the second pixel area PXA-R and the third pixel area PXA-B. When passing through the light control layer OSL (see Figure 2A ), green light may be provided to the first pixel region PXA-G, red light may be provided to the second pixel region PXA-R, and blue light may be provided to the third pixel region PXA-B. However, one or more embodiments of the present disclosure are not limited thereto, and the source lights generated in the first to third pixels PX-G, PX-R, and PX-B may have different colors.

[0088] According to one or more embodiments, the second pixel region PXA-R and the third pixel region PXA-B are located in the same row, and the first pixel region PXA-G is located in a row different from the row in which the second pixel region PXA-R and the third pixel region PXA-B are located. For example, the second pixel region PXA-R may be spaced apart from the third pixel region PXA-B along the first direction DR1, and the first pixel region PXA-G may be spaced apart from the second pixel region PXA-R and the third pixel region PXA-B in a corresponding oblique direction (e.g., a corresponding oblique direction oblique to the first direction DR1 and the second direction DR2). According to one or more embodiments, the area of ​​the second pixel region PXA-R may be smaller than the area of ​​the first pixel region PXA-G, and may be larger than the area of ​​the third pixel region PXA-B.

[0089] The first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B are illustrated as having a square shape, but the arrangement form and area of ​​the pixel regions PXA-G, PXA-R, and PXA-B are not limited thereto.

[0090] Figure 4A The arrangement of the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B within the unit pixel PXU shown in the figure is only an example and is not limited thereto. For example, the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B may be arranged along the first direction DR1 and may be located in the same row. In addition, the arrangement of the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B in each of the unit pixels PXU may not necessarily be the same.

[0091] Figure 4B is an enlarged plan view of a display area according to one or more embodiments of the present disclosure. Figure 4BThe repair unit pixel PXU-R and the normal unit pixel PXU-N in the normal state are shown. In this specification, the repair unit pixel PXU-R may be defined as the first to third pixels PX-G, PX-R and PX-B (see FIG. 1 ) included in one unit pixel PXU (see FIG. 1 ). Figure 4A ) is defective and the defective pixel is repaired.

[0092] The normal unit pixel PXU-N may include first to third normal pixels PX-G1, PX-R1, and PX-B1. The first to third normal pixels PX-G1, PX-R1, and PX-B1 may correspond to Figure 4A 1 to 3rd pixels PX-G, PX-R and PX-B are shown in FIG.

[0093] The first normal pixel PX-G1 may include a first normal pixel circuit PC-G1 and a first normal light emitting element OL-G1 connected to the first normal pixel circuit PC-G1. The second normal pixel PX-R1 may include a second normal pixel circuit PC-R1 and a second normal light emitting element OL-R1 connected to the second normal pixel circuit PC-R1. The third normal pixel PX-B1 may include a third normal pixel circuit PC-B1 and a third normal light emitting element OL-B1 connected to the third normal pixel circuit PC-B1.

[0094] That is, the first to third normal pixel circuits PC-G1, PC-R1, and PC-B1 included in the normal unit pixel PXU-N may be connected to the first to third normal light emitting elements OL-G1, OL-R1, and OL-B1 in a one-to-one correspondence.

[0095] The first to third normal pixel circuits PC-G1, PC-R1, and PC-B1 may each correspond to Figure 3 The pixel circuit PC shown in FIG. 1 and the first to third normal light emitting elements OL-G1, OL-R1 and OL-B1 may each have Figure 6 The structure of the first light emitting element OLED-G shown in FIG. 1 is the same as or substantially the same as that of the first light emitting element OLED-G shown in FIG. 1 . For ease of explanation, Figure 4B It is shown that the shapes of the first to third normal pixel circuits PC-G1, PC-R1, and PC-B1 are rectangular shapes extending in the first direction DR1.

[0096] The repair unit pixel PXU-R may include a repair pixel PX-GR, a second normal pixel PX-R2, a disconnected pixel circuit PC-N, and a disconnected light emitting element OL-N. The second normal pixel PX-R2 may include a second normal pixel circuit PC-R2 and a second normal light emitting element OL-R2 connected to the second normal pixel circuit PC-R2. Any one of the pixels included in the normal unit pixel PXU-N may emit source light after being repaired from a defective state. The semiconductor pattern included in the pixel circuit of the defective pixel may be disconnected.

[0097] For example, the semiconductor pattern included in the disconnected pixel circuit PC-N may be disconnected. In the present specification, as can be determined by a signal check test, the disconnected pixel circuit PC-N may be a defective pixel circuit among pixel circuits due to a short circuit defect, etc. Here, a defective pixel circuit in which the semiconductor pattern is disconnected may be defined as a disconnected pixel circuit PC-N. According to the present disclosure, the disconnected pixel circuit PC-N may be floated without being connected to any of the light-emitting elements located in the repair unit pixel PXU-R.

[0098] In executing the display panel DP (see Figure 1A ), the repair light emitting element OL-GR and the repair pixel circuit PC-GR may be connected so as to drive the repair light emitting element OL-GR that should have been connected to the existing disconnected pixel circuit PC-N. The repair pixel circuit PC-GR may correspond to the third normal pixel circuit PC-B1 in the normal unit pixel PXU-N, and may be a pixel circuit for basically driving the disconnected light emitting element OL-N. After performing the repair process, the repair pixel circuit PC-GR may be connected to the repair light emitting element OL-GR, and may drive the repair light emitting element OL-GR.

[0099] According to the present disclosure, the first electrode AE-G included in the disconnected light emitting element OL-N can be disconnected, and the portion connected to the repair pixel circuit PC-GR among the disconnected portions can be connected to the first electrode AE-G of the repair light emitting element OL-GR (see Figure 6 ) to connect the repair light-emitting element OL-GR to the repair pixel circuit PC-GR.

[0100] Accordingly, when the display panel DP (see Figure 1A ), the disconnected light emitting element OL-N included in the repair unit pixel PXU-R may become a dark spot, and the disconnected pixel circuit PC-N may be spaced apart from the light emitting element to be in a floating state. The process of connecting the repair light emitting element OL-GR to the repair pixel circuit PC-GR through the repair process may be performed by a laser process. This will be described later.

[0101] According to the present disclosure, source light generated in the first normal pixel PX-G1 and the repair pixel PX-GR may pass through the light control layer OSL (see Figure 2A ), and may be provided to a user as green light. The source light generated in the second normal pixel PX-R1 and the second normal pixel PX-R2 may pass through the light control layer OSL (see Figure 2A ), and can be provided to the user as red light. The source light generated in the third normal pixel PX-B1 can pass through the light control layer OSL (see Figure 2A ) and can be provided to the user as blue light. According to the present disclosure, when the display panel DP (see Figure 1A ), the disconnected light-emitting element OL-N within the repair unit pixel PXU-R can become a dark spot.

[0102] For example, when a pixel providing green light becomes a dark spot, blue light and red light may be provided from one unit pixel, and thus, the blue light and red light may be viewed as magenta light by the user. For another example, when a pixel providing blue light becomes a dark spot, green light and red light may be provided from one unit pixel, and thus, the green light and red light may be viewed as yellow light by the user. Figure 1A ), magenta light is easier to be viewed or noticed by the user than yellow light, so it may be appropriate to repair the pixels providing green light and make the pixels providing blue light become dark spots in the repair unit pixel PXU-R.

[0103] According to the present disclosure, since the pixel providing green light in the repair unit pixel PXU-R is repaired and the pixel providing blue light becomes a dark spot, the yield of the repair process and the display panel DP (see Figure 1A ) reliability.

[0104] Figure 5 is a plan view according to a stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure. Figure 6 It is along Figure 5 A cross-sectional view taken along line II'. 7A to 7I is a plan view showing a stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure for each layer.

[0105] refer to Figure 5 , a unit pixel PXU may include first to third pixels PX-G, PX-R, and PX-B. The first to third pixels PX-G, PX-R, and PX-B may each include the reference Figure 3 The pixel circuit PC and the light emitting element OLED are described.

[0106] The first to third pixels PX-G, PX-R, and PX-B may be connected to the first power line ED, the second power line EL, the initialization line IL, the scan line SCL, and the sensing line SSL, respectively. In addition, the first to third pixels PX-G, PX-R, and PX-B may be connected to the corresponding data lines DL-G, DL-R, and DL-B, respectively. The first power line ED may provide a first voltage ELVDD (see Figure 3 ), and the second power supply line EL can provide a voltage higher than the first voltage ELVDD (see Figure 3 ) low second voltage ELVSS (see Figure 3 ).

[0107] According to one or more embodiments, the data lines DL-G, DL-R, and DL-B, the initialization line IL, and the second power line EL may be spaced apart from each other along the first direction DR1, and may each extend along the second direction DR2. The first power line ED, the sensing line SSL, and the scan line SCL may be spaced apart from each other along the second direction DR2, and may each extend along the first direction DR1. The first power line ED may be spaced apart from the scan line SCL along the second direction DR2, wherein the sensing line SSL is between the first power line ED and the scan line SCL. The pixel circuit PC (see FIG. 1 ) included in the first to third pixels PX-G, PX-R, and PX-B Figure 3 ) may be located between the sensing line SSL and the scanning line SCL. The light emitting element OLED (see Figure 3 ) may overlap with the data lines DL-G, DL-R and DL-B.

[0108] refer to Figure 6 According to one or more embodiments, the display panel DP may include a base layer BS and a circuit element layer DP-CL, a display element layer DP-OLED, an encapsulation layer TFE, a light control layer OSL and a window panel WD located on the base layer BS (as used in this article, "on" may mean "above").

[0109] The circuit element layer DP-CL is located on the base layer BS. The circuit element layer DP-CL may include insulating layers 10, 20, 30, 40 and 50 located on the base layer BS and conductive patterns IL, IL-P, SS-P, EBR, A3-G, BML-G, C-G1, C-G2, B-P1 and A2-G located between the insulating layers 10, 20, 30, 40 and 50. According to one or more embodiments, the first to fourth insulating layers 10, 20, 30 and 40 may each be provided as an inorganic layer. The first to fourth insulating layers 10, 20, 30 and 40 may each be provided as a single layer of an inorganic layer or a plurality of layers including different inorganic layers, but are not limited to any embodiment. The fifth insulating layer 50 may be provided as an organic layer. During the above-mentioned repair process, the repair hole may be formed by penetrating a portion of the fifth insulating layer 50 and a portion of at least one of the inorganic insulating layers located under the fifth insulating layer 50. The conductive patterns IL, IL-P, SS-P, EBR, A3-G, BML-G, C-G1, C-G2, B-P1, and A2-G will be described later.

[0110] The first light shielding pattern BML-G may be connected to the first pixel PX-G (see Figure 5 ) in the first transistor T1 (see Figure 3 ) source, may receive a signal applied to the source and may form a synchronous structure under the semiconductor pattern. The first light shielding pattern BML-G may receive a bias voltage while overlapping the first active pattern. The first light shielding pattern BML-G may also receive a first voltage ELVDD (see Figure 3 ).

[0111] The first light shielding pattern BML-G may reduce or prevent the potential otherwise caused by polarization from affecting the first transistor T1 (see Figure 3 ). In addition, the first light shielding pattern BML-G can reduce or prevent external light from reaching the first transistor T1 (see Figure 3 ). In one or more embodiments of the present disclosure, the first light shielding pattern BML-G may be a floating electrode isolated from other electrodes or wirings. The description related to the first light shielding pattern BML-G may also be applied to the reference Fig. 7A The second light shielding pattern BML-R and the third light shielding pattern BML-B are described. Other conductive patterns will be described in detail later.

[0112] The display element layer DP-OLED may include a first light emitting element OLED-G and a second light emitting element OLED-G, wherein the first light emitting element OLED-G and the second light emitting element OLED-G are defined respectively with reference to Figure 4A The pixel defining layer PDL of the openings PDL-OP corresponding to the pixel areas PXA-G, PXA-R, and PXA-B are described. Figure 6The first light emitting element OLED-G shown in the reference Figure 4A Described is the first pixel PX-G.

[0113] According to one or more embodiments, the pixel defining layer PDL may have a light absorption characteristic, and for example, the pixel defining layer PDL may have a black color. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer PDL may correspond to a light shielding pattern having a light shielding characteristic.

[0114] The first electrode AE-G of the first light-emitting element OLED-G may be located on the fifth insulating layer 50. The second electrode CE-G of the first light-emitting element OLED-G may be located on / over the first electrode AE-G. The common layer CL-G of the first light-emitting element OLED-G may be located between the first electrode AE-G and the second electrode CE-G. The common layer CL-G may include a light-emitting layer including an organic material, a hole control layer located between the first electrode AE-G and the light-emitting layer, and an electron control layer located between the light-emitting layer and the second electrode CE-G. The hole control layer may include a hole transport layer and a hole injection layer. The electron control layer may include an electron transport layer and an electron injection layer. According to one or more embodiments, the common layer CL-G and the second electrode CE-G may each be commonly formed in the first to third pixels PX-G, PX-R, and PX-B (see Figure 4A ) in the public layer.

[0115] The encapsulation layer TFE may cover the display element layer DP-OLED. The encapsulation layer TFE may include an organic material or an inorganic material. The encapsulation layer TFE may have a multilayer structure in which an inorganic layer / organic layer is repeated. The encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 stacked sequentially. The first inorganic layer IOL1 and the second inorganic layer IOL2 may protect the light-emitting element OLED from external moisture and oxygen, and the organic layer OL may reduce or prevent the possibility of the light-emitting element OLED being recessed due to foreign matter introduced during the manufacturing process.

[0116] The first inorganic layer IOL1 and the second inorganic layer IOL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The first inorganic layer IOL1 and the second inorganic layer IOL2 may each have a multilayer structure. The organic layer OL may include an acrylate organic layer, but is not limited thereto. The inorganic layers IOL1 and IOL2 may protect the first light emitting element OLED-G from moisture and oxygen, and the organic layer OL may protect the first light emitting element OLED-G from foreign matter such as dust particles.

[0117] The light control layer OSL may be located on the encapsulation layer TFE. The light control layer OSL may be located between the encapsulation layer TFE and the window panel WD. The rear surface of the window panel WD may provide a substrate surface on which the components included in the light control layer OSL are formed. For ease of explanation, the components included in the light control layer OSL will be described in the order in which the components are formed on the rear surface of the window panel WD.

[0118] The color filter layer CFL may be located on the rear surface of the window panel WD. The color filter layer CFL may include a first color filter CF1 that transmits the first light, a second color filter CF2 that transmits the second light, and a third color filter CF3 that transmits the source light. In one or more embodiments, the first color filter CF1 may be a green filter, the second color filter CF2 may be a red filter, and the third color filter CF3 may be a blue filter.

[0119] The first to third color filters CF1, CF2, and CF3 may each include a polymer photosensitive resin and a colorant. The first color filter CF1 may include a green colorant, the second color filter CF2 may include a red colorant, and the third color filter CF3 may include a blue colorant. The first color filter CF1 may include a green pigment or a green dye, the second color filter CF2 may include a red pigment or a red dye, and the third color filter CF3 may include a blue pigment or a blue dye.

[0120] The first to third color filters CF1, CF2, and CF3 may be respectively connected to the first pixel regions PXA-G (see Figure 4A ), the second pixel area PXA-R (see Figure 4A ) and the third pixel area PXA-B (see Figure 4A ) corresponding to the first to third light-controlling patterns. That is, the first to third color filters CF1, CF2, and CF3 may overlap the corresponding openings PDL-OP, respectively. In addition, the first to third color filters CF1, CF2, and CF3 may correspond to the first to third light-controlling patterns, respectively. Figure 6 An example of a color control layer CCL-G disposed on the first color filter CF1 is shown.

[0121] In addition, a plurality of color filters CF1, CF2, and CF3 that transmit different lights may be located in the first to third pixel regions PXA-R, PXA-B, and PXA-G (see Figure 4A ) between the peripheral region NPXA (see Figure 4A) overlap each other. A plurality of color filters CF1, CF2, and CF3 may overlap each other in a third direction DR3 which is a thickness direction, and the boundaries between adjacent light emitting areas may be distinguished. Meanwhile, unlike what is shown, the color filter layer CFL may include a light shielding portion that distinguishes the boundaries between adjacent first to third color filters CF1, CF2, and CF3. The light shielding portion may be formed as a blue color filter, or may be formed to include an organic light shielding material or an inorganic light shielding material containing a black pigment or a black dye.

[0122] The low refractive layer LR may be located between the first to third color control layers and the color filter layer CFL. The low refractive layer LR may cover the first to third color filters CF1, CF2, and CF3.

[0123] The low refractive layer LR may include at least one inorganic layer. For example, the low refractive layer LR may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride or a metal film whose transmittance is ensured, etc. However, one or more embodiments of the present disclosure are not limited thereto, and the low refractive layer LR may include an organic film. The low refractive layer LR may have a structure in which, for example, a plurality of hollow particles are dispersed in an organic polymer resin. The low refractive layer LR may be composed of a single layer or a plurality of layers.

[0124] The barrier layer CAP1 may cover the low refractive layer LR. According to one or more embodiments, the barrier layer CAP1 may be provided as a plurality of inorganic layers. The barrier layer CAP1 may reduce or prevent the color control layer CCL-G from being permeated by moisture / oxygen and may improve the durability of the color control layer CCL-G.

[0125] The embankment BMP may be located below the barrier layer CAP1. The embankment BMP may include a base resin and an additive. The base resin may be composed of various resin compositions commonly referred to as adhesives. The additive may include a coupling agent and / or a photoinitiator. The additive may further include a dispersant. The embankment BMP may include a black colorant to block light. The embankment BMP may include a black dye and a black pigment mixed in the base resin. In one or more embodiments, the black colorant may include carbon black, or may include a metal such as chromium or an oxide thereof.

[0126] The bank BMP may include a bank opening corresponding to the opening PDL-OP. The color control layer CCL-G may be located in the bank opening. The color control layer CCL-G may include quantum dots for changing the optical characteristics of the source light. The color control layer CCL-G may include quantum dots for converting the source light into light of a different wavelength. In the color control layer CCL-G, the quantum dots may convert the blue light, which is the source light, into green light. According to one or more embodiments, quantum dots for converting the blue source light into red light may be included in the bank opening overlapping with the second color filter CF2.

[0127] The additional barrier layer CAP2 may cover the bank BMP and the color control layer CCL-G. The additional barrier layer CAP2 may be provided as an inorganic layer. The additional barrier layer CAP2 may seal the bank BMP and the color control layer (eg, CCL-G) together with the barrier layer CAP1.

[0128] The filling layer FML may be located between the additional barrier layer CAP2 and the encapsulation layer TFE. The filling layer FML may be used as a buffer between the display element layer DP-OLED and the light control layer OSL. According to one or more embodiments, the filling layer FML may perform a shock absorbing function, etc., and may improve the strength of the display panel DP. The filling layer FML may be formed of a filling resin including a polymer resin. For example, the filling layer FML may be formed of a filling resin including an acrylate resin or an epoxy resin, etc.

[0129] The filling layer FML is a separate component from both the encapsulation layer TFE located therebelow and the additional barrier layer CAP2 located thereon, and can therefore be formed in a process separate from the processes of the encapsulation layer TFE and the additional barrier layer CAP2. At the same time, the filling layer FML can be formed of a material different from that of the encapsulation layer TFE and the additional barrier layer CAP2.

[0130] 7A to 7I FIG. 1 shows a unit pixel PXU (see FIG. 1 ) on which a repair process is not performed. Figure 5 ) in the stacking order of the conductive patterns.

[0131] refer to Figure 5 , Figure 6 and Fig. 7A , the first conductive layer MSL1 may be located on the base layer BS and may be covered by the first insulating layer 10 .

[0132] The first conductive layer MSL1 may include a second power line EL, an initialization line IL, a power line EBR, first to third light shielding patterns BML-G, BML-R, and BML-B, and first to third data lines DL-G, DL-R, and DL-B.

[0133] The second power line EL, the initialization line IL, and the power line EBR may be arranged along the first direction DR1 and may extend along the second direction DR2. The initialization line IL may be located between the second power line EL and the power line EBR.

[0134] The first to third light shielding patterns BML-G, BML-R, and BML-B may be spaced apart from each other along the second direction DR2. The first to third light shielding patterns BML-G, BML-R, and BML-B may be located between the power line EBR and the first data line DL-G.

[0135] The first to third data lines DL-G, DL-R, and DL-B may be arranged along the first direction DR1 and may extend along the second direction DR2. The third data line DL-B may be located between the first data line DL-G and the second data line DL-R.

[0136] refer to Figure 5 , Figure 6 and Figure 7B , the second conductive layer MSL2 may be located on the first insulating layer 10 and may be covered by the second insulating layer 20 .

[0137] The second conductive layer MSL2 may include first to third active patterns A1-G, A2-G and A3-G included in the first pixel PX-G, first to third active patterns A1-R, A2-R and A3-R included in the second pixel PX-R, and first to third active patterns A1-B, A2-B and A3-B included in the third pixel PX-B.

[0138] refer to Figure 5 , Figure 6 and Figure 7C , the third conductive layer MSL3 may be located on the second insulating layer 20 and may be covered by the third insulating layer 30 .

[0139] The third conductive layer MSL3 may include a sensing pattern SS-P, a scanning pattern SC-P, and first to third lower capacitor patterns C-G1, C-R1, and C-B1. The sensing pattern SS-P may be connected to a sensing line SSL (see FIG. 1 ) to be described later. Fig. 7E ), and can be from the sensing line SSL (see Fig. 7E ) portion protruding along the second direction DR2.

[0140] The scan pattern SC-P may be connected to a scan line SCL (see Fig. 7E ) and can be from the scan line SCL (see Fig. 7E ) is a portion protruding or extending along the second direction DR2.

[0141] The first to third lower capacitor patterns C-G1, C-R1, and C-B1 may be arranged along the second direction DR2. The first to third lower capacitor patterns C-G1, C-R1, and C-B1 may overlap the corresponding first to third light shielding patterns BML-G, BML-R, and BML-B, respectively. The first to third lower capacitor patterns C-G1, C-R1, and C-B1 may overlap the corresponding first to third light shielding patterns BML-G, BML-R, and BML-B, respectively. Fig. 7E The first to third upper capacitor patterns C-G2, C-R2, and C-B2 described overlap and may define reference Figure 3 Capacitor Cst is described.

[0142] Fig.7D shows that by passing through the reference Figure 6 The contact holes CNT1, CNT2, CNT3, CNT4, and CNT5 are defined by at least any one of the first to third insulating layers 10, 20, and 30 described above.

[0143] The first contact hole CNT1 may be defined by passing through the first insulating layer 10. The first contact hole CNT1 may connect conductive patterns located in the first conductive layer MSL1 and the second conductive layer MSL2.

[0144] The second contact hole CNT2 may be defined by passing through the second insulating layer 20. The second contact hole CNT2 may connect conductive patterns located in the second conductive layer MSL2 and the third conductive layer MSL3.

[0145] The third contact hole CNT3 may be defined by penetrating the third insulating layer 30. The third contact hole CNT3 may be located between the third conductive layer MSL3 and the reference layer MSL4. Fig. 7E The conductive patterns in the fourth conductive layer MSL4 are described to be connected.

[0146] The fourth contact hole CNT4 may be defined by passing through the second insulating layer 20 and the third insulating layer 30. The fourth contact hole CNT4 may be located between the second conductive layer MSL2 and the reference layer MSL3. Fig. 7E The conductive patterns in the fourth conductive layer MSL4 are described to be connected.

[0147] The fifth contact hole CNT5 may be defined by passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fifth contact hole CNT5 may be located between the first conductive layer MSL1 and the reference layer MSL2. Fig. 7E The conductive patterns in the fourth conductive layer MSL4 are described to be connected.

[0148] refer to Figure 5 , Figure 6 and Fig. 7E , the fourth conductive layer MSL4 may be located on the third insulating layer 30 and may be covered by the fourth insulating layer 40 .

[0149] The fourth conductive layer MSL4 may include a first power line ED, a sensing line SSL, a scan line SCL, a power pattern EL-P, an initialization pattern IL-P, first to third power line patterns E-P1, E-P2 and E-P3, first to third upper capacitor patterns C-G2, C-R2 and C-B2, first to third bridge patterns B-P1, B-P2 and B-P3, and first to third data patterns D-P1, D-P2 and D-P3.

[0150] The first power line ED, the sensing line SSL, and the scan line SCL may be arranged along the second direction DR2 and may extend along the first direction DR1. The sensing line SSL may be located between the first power line ED and the scan line SCL. Figure 3 The described pixel circuit PC may be located between the sensing line SSL and the scanning line SCL.

[0151] The power pattern EL-P may overlap the second power line EL and may be connected to the second power line EL via the fifth contact hole CNT5 .

[0152] The initialization pattern IL-P may overlap the initialization line IL and may be connected to the initialization line IL via the fifth contact hole CNT5 .

[0153] The first to third power line patterns E-P1, E-P2, and E-P3 may overlap with the power line EBR. The first to third power line patterns E-P1, E-P2, and E-P3 may be spaced apart from each other along the second direction DR2. The first to third power line patterns E-P1, E-P2, and E-P3 may be connected to the power line EBR via the fifth contact hole CNT5.

[0154] The first power line pattern E-P1 may be connected to the first active patterns A1-G and A1-R via the fourth contact hole CNT4. The third power line pattern E-P3 may be connected to the first active pattern A1-B via the fourth contact hole CNT4.

[0155] The first to third upper capacitor patterns C-G2, C-R2, and C-B2 may overlap corresponding first to third lower capacitor patterns C-G1, C-R1, and C-B1, respectively.

[0156] The first to third bridge patterns B-P1, B-P2, and B-P3 may connect the second active patterns A2-G, A2-R, and A2-B to the first to third lower capacitor patterns C-G1, C-R1, and C-B1, respectively.

[0157] One end of the first bridge pattern B-P1 may be connected to the first lower capacitor pattern C-G1 via the third contact hole CNT3, and the other end of the first bridge pattern B-P1 may be connected to the second active pattern A2-G via the fourth contact hole CNT4.

[0158] One end of the second bridge pattern B-P2 may be connected to the second lower capacitor pattern C-R1 via the third contact hole CNT3, and the other end of the second bridge pattern B-P2 may be connected to the second active pattern A2-R via the fourth contact hole CNT4.

[0159] One end of the third bridge pattern B-P3 may be connected to the third lower capacitor pattern C-B1 via the third contact hole CNT3, and the other end of the third bridge pattern B-P3 may be connected to the second active pattern A2-B via the fourth contact hole CNT4.

[0160] The first to third data patterns D-P1, D-P2, and D-P3 may connect the second active patterns A2-G, A2-R, and A2-B to the first to third data lines DL-G, DL-R, and DL-B, respectively.

[0161] One end of the first data pattern D-P1 may be connected to the second active pattern A2-G via the fourth contact hole CNT4, and the other end of the first data pattern D-P1 may be connected to the first data line DL-G via the fifth contact hole CNT5.

[0162] One end of the second data pattern D-P2 may be connected to the second active pattern A2-R via the fourth contact hole CNT4, and the other end of the second data pattern D-P2 may be connected to the second data line DL-R via the fifth contact hole CNT5.

[0163] One end of the third data pattern D-P3 may be connected to the second active pattern A2-B via the fourth contact hole CNT4, and the other end of the third data pattern D-P3 may be connected to the third data line DL-B via the fifth contact hole CNT5.

[0164] Figure 7F shows that by passing through the reference Figure 6 The sixth contact hole CNT6 may be defined by the fourth insulating layer 40. The sixth contact hole CNT6 may overlap the power pattern EL-P and the first to third upper capacitor patterns C-G2, C-R2, and C-B2.

[0165] Figure 7G shows that by passing through the reference Figure 6 The seventh contact hole CNT7 may be defined by the fifth insulating layer 50 as described above. The seventh contact hole CNT7 may overlap with the sixth contact hole CNT6. The fifth insulating layer 50 may be provided as an organic layer.

[0166] refer to Figure 5 , Figure 6 and Figure 7H , the fifth conductive layer MSL5 may be located on the fifth insulating layer 50 and may be covered by the pixel defining layer PDL.

[0167] The fifth conductive layer MSL5 may include first electrodes AE-G, AE-R, and AE-B included in corresponding pixels. The first electrodes AE-G, AE-R, and AE-B may be connected to the first to third upper capacitor patterns C-G2, C-R2, and C-B2, respectively, via corresponding sixth and seventh contact holes CNT6 and CNT7.

[0168] The fifth conductive layer MSL5 may further include an additional power pattern EL-S. The additional power pattern EL-S may be connected to the power pattern EL-P via corresponding sixth and seventh contact holes CNT6 and CNT7.

[0169] Fig.7I Shown is a reference Figure 6 For ease of explanation, refer to the pixel definition layer PDL described above. Figure 6 The described opening PDL-OP is shown in dark shading. The opening PDL-OP (see FIG. 1 ) that exposes at least a portion of each of the first electrodes AE-G, AE-R, and AE-B Figure 6 ) may be defined in the pixel defining layer PDL. The opening PDL-OP (see Figure 6 ) may correspond to the first to third pixel regions PXA-G, PXA-R, and PXA-B. The first to third pixel regions PXA-G, PXA-R, and PXA-B may be regions in which the first to third pixels PX-G, PX-R, and PX-B (see Figure 4A ) is the area of ​​source light generated in .

[0170] An additional opening EL-OP exposing at least a portion of the additional power supply pattern EL-S may also be defined in the pixel defining layer PDL. The second electrode CE-G (see Figure 6 ) may be located in the additional opening EL-OP and may be connected to the second power line EL.

[0171] Figure 8 is an equivalent circuit diagram illustrating a repair process of one pixel included in a repair unit pixel according to one or more embodiments of the present disclosure. 9A to 9C is a plan view illustrating a repair process of a conductive pattern included in a repair unit pixel according to one or more embodiments of the present disclosure. Fig.10 It is along Fig. 9C A cross-sectional view taken along line II-II'.

[0172] Figure 8 shows included in the reference Figure 4B The equivalent circuit diagram of the pixels PX-R2 and PX-GR in the repair unit pixel PXU-R described above. The repair unit pixel PXU-R may include a repair pixel PX-GR, a second normal pixel PX-R2, a disconnected pixel circuit PC-N, and a disconnected light emitting element OL-N. Figure 4B ) may emit source light after being repaired from a defective state. A semiconductor pattern included in a pixel circuit of the defective pixel may be disconnected.

[0173] For example, in the off pixel circuit PC-N, the semiconductor patterns included in the first to third transistors T1, T2 and T3 may be off C-1, C-2 and C-3. In this specification, the wording "off" may mean a state in which a component is physically / electrically disconnected.

[0174] The repair process according to the present disclosure may include disconnecting the scanning pattern SC-P included in the repair unit pixel PXU-R (see Figure 7C ), an operation of disconnecting the first electrode included in disconnecting the light emitting element OL-N (operation RC2), and an operation of connecting the repair light emitting element OL-GR to the repair pixel circuit PC-GR (operation RW). 9A to 9C A method of repairing a display panel according to one or more embodiments of the present disclosure is described in detail.

[0175] According to the present disclosure, the method for repairing a display panel may include: an operation of forming first to third pixel circuits each having first to third transistors; an operation of forming a scan line having a scan pattern overlapping with a semiconductor pattern included in a second transistor; an operation of checking signals of the first to third pixel circuits; an operation of disconnecting the semiconductor patterns included in the first to third transistors of the first pixel circuit; an operation of performing disconnection to divide the scan pattern into a first pattern overlapping with a second transistor of the first pixel circuit and a second pattern overlapping with a second transistor of the second pixel circuit and a second transistor of the third pixel circuit; an operation of forming an organic insulating layer for covering the first to third pixel circuits; an operation of forming a first repair hole and a second repair hole overlapping with the first pattern in the organic insulating layer; an operation of forming a first electrode overlapping with the first to third pixel circuits on the organic insulating layer; an operation of performing disconnection to divide the first electrode overlapping with the third pixel circuit into a first part connected to the third pixel circuit and a second part separated from the third pixel circuit; and an operation of connecting one of the first electrodes overlapping with the first pixel circuit to the third pixel circuit. The operation of connecting the above-mentioned first electrode in the first electrode overlapping with the first pixel circuit to the third pixel circuit can be performed by irradiating the first repair hole and the second repair hole with laser, and through laser irradiation, the above-mentioned first electrode in the first electrode overlapping with the first pixel circuit can be located in the first repair hole and connected to the first pattern and the first part can be located in the second repair hole and connected to the first pattern.

[0176] In addition, the method for repairing a display panel according to one or more embodiments may further include an operation of forming a pixel defining layer having first to third openings for exposing at least a portion of each of the first electrodes on the organic insulating layer. Here, a boundary between the first portion and the second portion may be formed along an edge of the third opening overlapping the third pixel circuit in a plan view. Then, an operation of forming a common layer and a second electrode on the first electrode may be further included.

[0177] Fig. 9A Shown is a reference 7A to 7F A state in which the first to fourth insulating layers 10, 20, 30, and 40 and the first to fourth conductive layers MSL1, MSL2, MSL3, and MSL4 are formed is described.

[0178] After forming the fourth insulating layer 40, an operation of checking signals of the first to third pixel circuits may be performed. When a defect such as a short circuit defect occurs in the first pixel circuit among the first to third pixel circuits, the semiconductor patterns included in the first pixel circuit may be disconnected C-1, C-2, and C-3 by a laser process.

[0179] Then, an operation of disconnecting the scanning pattern SC-P (operation RC1) may be performed. The scanning pattern SC-P may be disconnected so that the scanning pattern SC-P is divided into a first pattern SP1 overlapping the second active pattern A2-G of the first pixel circuit and a second pattern SP2 overlapping the second active pattern A2-R of the second pixel circuit and the second active pattern A2-B of the third pixel circuit. The operation of disconnecting the scanning pattern SC-P (operation RC1) may be performed by a laser process.

[0180] Then, refer to Fig. 9B , the method may include forming a reference Figure 7G The method may further include an operation of forming a first repair hole CNT-R1 and a second repair hole CNT-R2 in the fifth insulating layer 50 (organic insulating layer) that overlap the first pattern SP1 and are spaced apart from each other along the second direction DR2. The first repair hole CNT-R1 and the second repair hole CNT-R2 may be formed by a laser process. Pre-forming the first repair hole CNT-R1 and the second repair hole CNT-R2 enables the first electrode overlapping the first pixel circuit to be connected to the first pattern SP1 in a subsequent process, and the first pattern SP1 to be connected to the first portion of the disconnected first electrode.

[0181] Thereafter, the method may include an operation of forming first electrodes AE-G, AE-R, and AE-B on the fifth insulating layer 50 and an operation of disconnecting the first electrode AE-B overlapping the third pixel circuit (operation RC2). The first electrode AE-B may be disconnected so that the first electrode AE-B is divided into a first portion AP1 and a second portion AP2 by a laser process. The first portion AP1 may be connected to the third pixel circuit, and the second portion AP2 may be spaced apart from the third pixel circuit. In a plan view, a boundary between the first portion AP1 and the second portion AP2 may be formed along an opening PDL-OP (see FIG. 1 ) formed in the pixel defining layer PDL. Figure 6 ) is formed by one side of the first portion AP1 and the second portion AP2. For example, the boundary between the first portion AP1 and the second portion AP2 may be based on the opening PDL-OP (see Figure 6 ) is formed by a long side extending along the second direction DR2.

[0182] Then, refer to Fig. 9C and Fig.10 , the method may include repairing the light-emitting element OL-GR (see Figure 8 ) is connected to the repair pixel circuit PC-GR (see Figure 8) operation (operation RW). Therefore, the first electrode AE-G overlapping the first pixel circuit can be connected to the first pattern SP1 by irradiating the first repair hole CNT-R1 with laser, and the first portion AP1 can be connected to the first pattern SP1 by irradiating the second repair hole CNT-R2 with laser.

[0183] When the first repair hole CNT-R1 is irradiated with laser, the first electrode AE-G overlapping the first pixel circuit may be melted in the first repair hole CNT-R1 and may be connected to one end of the first pattern SP1 (operation R1). When the second repair hole CNT-R2 is irradiated with laser, the first portion AP1 may be melted in the second repair hole CNT-R2 and may be connected to the other end of the first pattern SP1 (operation R2). Accordingly, the repair light-emitting element OL-GR including the first electrode AE-G overlapping the first pixel circuit (see Figure 8 ) can be connected to the repair pixel circuit PC-GR connected to the first part AP1 (see Figure 8 ), and can therefore operate normally.

[0184] In the method for repairing a display panel according to the present disclosure, a repair hole is formed in the organic insulating layer in advance, and thus a subsequent laser process for connecting a repair pixel circuit to a repair light-emitting element can be performed. Therefore, a method for repairing a display panel with improved repair process efficiency and reduced cost can be provided.

[0185] According to one or more embodiments of the present disclosure, since the repair hole is formed in the organic insulating layer in advance, the subsequent laser process for connecting the repair pixel circuit to the repair light-emitting element can be performed. Therefore, a method for repairing a display panel can be provided in which the display quality of the repaired display panel and the efficiency of the repair process are improved and the cost thereof is reduced.

[0186] In the above, the embodiments of the present disclosure have been described with reference to, but those skilled in the art or those of ordinary skill in the relevant technical field can understand that various modifications and changes can be made to the present disclosure without departing from the spirit and technical concept of the present disclosure described in the claims. Therefore, the scope of the present disclosure is not limited to the contents described in the detailed description of the specification, but should be determined by the claims whose functional equivalents should be included therein.

Claims

1. A display panel, comprising: Basal layer; a data line, arranged above the base layer along a first direction and extending along a second direction crossing the first direction; A first power line extending along the first direction; a sensing line spaced apart from the first power line in the second direction and extending along the first direction; A first pixel circuit, a second pixel circuit, and a third pixel circuit, each comprising a first transistor, a second transistor, and a third transistor including a semiconductor pattern, at least one of the semiconductor patterns of the first pixel circuit being disconnected; a scan line spaced apart from the sensing line in the second direction and extending along the first direction, wherein the first pixel circuit, the second pixel circuit and the third pixel circuit are between the scan line and the sensing line; a first light emitting element overlapping the first pixel circuit and connected to the third pixel circuit; a second light emitting element overlapping with and connected to the second pixel circuit; and The third light emitting element overlaps with the data line and is disconnected from the third pixel circuit.

2. The display panel according to claim 1, wherein: The third light emitting element is disconnected from the first pixel circuit and the second pixel circuit and is configured not to emit light, and Wherein, the first light emitting element and the second light emitting element are configured to emit light.

3. The display panel according to claim 1, wherein: The first light emitting element, the second light emitting element, and the third light emitting element each include a first electrode, a second electrode over the first electrode, and a common layer between the first electrode and the second electrode, and The common layer and the second electrode are commonly located in the first light-emitting element, the second light-emitting element and the third light-emitting element.

4. The display panel according to claim 3, further comprising: A pixel defining layer is above the base layer and defines an opening exposing the first electrode and including a first opening defining a first light emitting area, a second opening defining a second light emitting area, and a third opening defining a third light emitting area.

5. The display panel according to claim 4, wherein: The first electrode of the third light emitting element is disconnected.

6. The display panel according to claim 5, wherein: In a plan view, the first electrode of the third light emitting element is divided into a first portion and a second portion along a long side of the third opening extending in the second direction, wherein the first portion is connected to the third pixel circuit, and Wherein, the second part is disconnected from the third pixel circuit.

7. The display panel according to claim 6, wherein: The scan line includes a scan pattern extending along the second direction and overlapping the semiconductor pattern in the second transistor.

8. The display panel according to claim 7, wherein: The scanning pattern includes a first pattern overlapping the second transistor of the first pixel circuit and a second pattern disconnected from the first pattern and overlapping the second transistor of the second pixel circuit and the second transistor of the third pixel circuit.

9. The display panel according to claim 8, wherein: One end of the first portion is connected to the first pattern via a first repair hole in the organic insulating layer, and The first electrode of the first light-emitting element is connected to the first pattern via a second repair hole in the organic insulating layer that is spaced apart from the first repair hole.

10. The display panel according to claim 9, wherein: The first electrode of the first light emitting element is connected to the third pixel circuit via the first pattern and the first portion.

11. The display panel according to claim 10, further comprising: a light control layer, above the first light emitting element, the second light emitting element and the third light emitting element, The light control layer includes a color control layer including quantum dots and a color filter above the color control layer.

12. The display panel according to claim 11, wherein: The first light emitting element is configured to generate light that passes through the light control layer to provide green light, and Wherein, the second light emitting element is configured to generate light that passes through the light control layer to provide red light.

13. A method for repairing a display panel, the method comprising: forming a first pixel circuit, a second pixel circuit, and a third pixel circuit, each including a first transistor, a second transistor, and a third transistor; forming a scan line including a scan pattern overlapping the semiconductor pattern in the second transistor; checking signals of the first pixel circuit, the second pixel circuit, and the third pixel circuit; disconnecting a semiconductor pattern in the first transistor of the first pixel circuit, a semiconductor pattern in the second transistor of the first pixel circuit, and a semiconductor pattern in the third transistor of the first pixel circuit; dividing the scanning pattern into a first pattern overlapping the second transistor of the first pixel circuit and a second pattern overlapping the second transistor of the second pixel circuit and the second transistor of the third pixel circuit; forming an organic insulating layer covering the first pixel circuit, the second pixel circuit and the third pixel circuit; forming a first repair hole and a second repair hole overlapping the first pattern in the organic insulating layer; forming a first electrode on the organic insulating layer that overlaps the first pixel circuit, the second pixel circuit, and the third pixel circuit respectively; dividing the first electrode overlapping the third pixel circuit into a first portion connected to the third pixel circuit and a second portion spaced apart from the third pixel circuit; as well as The third pixel circuit is connected to one of the first electrodes that overlaps with the first pixel circuit.

14. The method according to claim 13, wherein: Connecting the third pixel circuit to the one of the first electrodes overlapping the first pixel circuit includes irradiating the first repair hole and the second repair hole with laser.

15. The method according to claim 14, wherein: The one of the first electrodes overlapping the first pixel circuit is located in the first repair hole and connected to the first pattern, and Wherein, the first portion is located in the second repair hole and is connected to the first pattern.

16. The method according to claim 13, further comprising: A pixel defining layer defining a first opening, a second opening, and a third opening respectively exposing a portion of the first electrode is formed on the organic insulating layer.

17. The method according to claim 16, wherein: A boundary between the first portion and the second portion is formed along one side of the third opening overlapping the third pixel circuit in a plan view.

18. The method according to claim 17, further comprising: forming a common layer on the first electrode; as well as A second electrode is formed on the common layer.

19. The method according to claim 17, wherein: The first opening overlapping with one of the first electrodes connected to the third pixel circuit is configured to emit light, wherein the second opening overlapping with another first electrode of the first electrodes connected to the second pixel circuit is configured to emit light, and The third opening overlapping with another first electrode among the first electrodes that overlaps with the third pixel circuit is configured not to emit light.

20. The method according to claim 19, wherein: The second opening and the third opening are spaced apart from each other along a first direction in which the scan line extends, and The first opening is spaced apart from the second opening along a second direction intersecting the first direction.

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