Command processing apparatus and display driving integrated circuit including same

Abstract

The present disclosure generally relates to a semiconductor integrated circuit, and more particularly, to a command processing device and a display driving integrated circuit including the same. A command processing apparatus includes an asynchronous first-in first-out (FIFO) unit, a mode configuration unit, and a post-processing unit. The asynchronous FIFO unit receives a plurality of commands from an external device and stores the plurality of commands. The mode configuration unit sets a command processing scheme for each of the plurality of commands as one of a first processing scheme or a second processing scheme different from the first processing scheme, and stores the command processing scheme for each of the plurality of commands. The post-processing unit determines a command processing scheme for each of the plurality of commands based on the mode configuration unit, and generates a plurality of control signals by processing the plurality of commands based on an input order of the plurality of commands and the determined command processing scheme.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor integrated circuits, and more particularly, to a command processing device and a display driver integrated circuit including the command processing device. Background Art

[0002] Typically, mobile devices such as smart phones are equipped with various functions suitable for high-end products. For example, in order to provide multimedia functions such as digital camera functions to mobile devices, higher resolution is expected for display devices used in mobile devices. In addition, as image resolution increases, data traffic between application processors (APs) and display driver (or driver) integrated circuits (DDICs) increases rapidly. The power consumed in APs and / or DDICs also gradually increases. Summary of the invention

[0003] At least one example of the present disclosure provides a command processing device that is capable of selectively, adaptively, and / or dynamically processing a command depending on the type of the command.

[0004] At least one example of the present disclosure provides a display driver integrated circuit including a command processing device.

[0005] According to an example, a command processing device includes an asynchronous first-in-first-out (FIFO) unit, a mode configuration unit, and a post-processing unit. The asynchronous FIFO unit receives a plurality of commands from an external device and stores the plurality of commands. The mode configuration unit sets a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme, and stores the command processing scheme for each of the plurality of commands. The post-processing unit determines a command processing scheme for each of the plurality of commands based on the mode configuration unit, and generates a plurality of control signals by processing the plurality of commands based on an input sequence of the plurality of commands and the determined command processing scheme.

[0006] According to an example, a display driver integrated circuit includes a command processing device and a display driver device. The command processing device generates a plurality of control signals based on a plurality of commands received from an external device. The display driver device drives a display panel based on the plurality of control signals. The command processing device includes an asynchronous first-in-first-out (FIFO) unit, a mode configuration unit, and a post-processing unit. The asynchronous FIFO unit receives a plurality of commands from an external device and stores the plurality of commands. The mode configuration unit sets a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme, and stores the command processing scheme for each of the plurality of commands. The post-processing unit determines a command processing scheme for each of the plurality of commands based on the mode configuration unit, and generates a plurality of control signals by processing the plurality of commands based on an input order of the plurality of commands and the determined command processing scheme.

[0007] According to an example, a command processing device includes an asynchronous first-in-first-out (FIFO) unit, a mode configuration unit, a control unit, a first processing unit, and a second processing unit. The asynchronous FIFO unit receives a plurality of commands and a plurality of data from an external device, and stores the plurality of commands and the plurality of data separately. The mode configuration unit sets a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme, sets an access scheme for each of the plurality of commands to one of a first access scheme or a second access scheme different from the first access scheme, and stores a plurality of setting values, each of which represents one of the first processing scheme and the second processing scheme and one of the first access scheme and the second access scheme. The control unit determines a command processing scheme for each of the plurality of commands and an access scheme for each of the plurality of commands based on a plurality of command identifiers (IDs) included in the plurality of commands and a plurality of setting values. When the command processing scheme for a first command among the plurality of commands is determined to be a first processing scheme, the first processing unit generates a first transaction by processing the first command based on the first processing scheme. When the command processing scheme for the first command is determined to be the second processing scheme, the second processing unit generates a first interrupt by processing the first command based on the second processing scheme. When the command processing scheme for the first command is determined to be the first processing scheme and the access scheme for the first command is determined to be the second access scheme, the first interrupt is additionally generated using the second processing unit. The first processing scheme is a fixed command processing scheme executed according to the structure of a plurality of logic circuits included in the first processing unit. The second processing scheme is a changeable command processing scheme executed by executing a program code stored in a memory by a microcontroller unit (MCU) included in the second processing unit.

[0008] In the command processing device and display driver integrated circuit according to the example, a hybrid processing scheme can be applied, adopted and adopted, wherein the command processing scheme is selectively, adaptively and / or dynamically determined as at least one of a hardware scheme or a software scheme, depending on the type of command. For example, dedicated hardware can be designed or implemented to process specific commands based on a hardware scheme, and thus the requirements for fast command processing speed and command response speed can be ensured or met. For example, additional paths can be implemented to process specific commands in a software scheme, and thus changes in the operation of specific commands can be easily performed. In addition, in order to maintain and / or obtain flexibility, configurable hardware can be implemented based on a memory-mapped system. Therefore, the advantages of the hardware scheme and the software scheme can be strengthened, the shortcomings of the hardware scheme and the software scheme can be improved, and thus command processing can be effectively performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating a command processing device according to an example embodiment.

[0011] Figure 2 It is shown that the Figure 1 A block diagram of an example of an asynchronous FIFO unit in a command processing device.

[0012] Figure 3 It is shown that the Figure 1 A block diagram of an example of a mode configuration unit in a command processing device.

[0013] Figure 4 It is shown that the Figure 1 A block diagram of an example of a post-processing unit in a command processing device.

[0014] Figure 5 is a flow chart illustrating a method of processing commands according to an example embodiment.

[0015] Figure 6 It is shown Figure 5 Flowchart of an example of determining a command processing scheme and an example of generating a control signal.

[0016] Fig. 7A , Figure 7B and Figure 7C Is used to describe Figure 4 Diagram of the operation of the post-processing unit.

[0017] Figure 8 It is shown Figure 5Flowchart of an example of determining a command processing scheme and an example of generating a control signal.

[0018] Fig.9A and 9B Is used to describe Figure 4 Diagram of the operation of the post-processing unit.

[0019] Fig.10 is a flow chart illustrating a method of processing commands according to an example embodiment.

[0020] Fig.11 and Fig.12 It is shown Fig.10 Flowcharts of examples of checking whether a command is valid, determining a command processing scheme, and generating a control signal.

[0021] Fig.13A , Fig. 13B and Fig. 13C Is used to describe Figure 4 Diagram of the operation of the post-processing unit.

[0022] Fig.14 and Fig.15 is a flow chart illustrating a method of processing commands according to an example embodiment.

[0023] Fig.16A and Fig. 16B is a diagram for describing an operation of a command processing device according to an example embodiment.

[0024] Fig.17 is a block diagram illustrating a display driving integrated circuit according to example embodiments.

[0025] Fig.18A and 18B It is shown that the Fig.17 A block diagram of an example of a display driver device in a display driver integrated circuit.

[0026] Fig.19 is a block diagram illustrating a display device according to example embodiments.

[0027] Fig. 20A and Fig. 20B It is shown that the Fig.19 A circuit diagram of an example of a pixel included in a display panel in a display device of the present invention.

[0028] Fig.21 is a block diagram illustrating a display system according to example embodiments.

[0029] Fig. 22 is a block diagram illustrating an electronic system including a display system according to example embodiments. DETAILED DESCRIPTION

[0030] Various examples will be described more fully with reference to the accompanying drawings in which embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0031] Figure 1 is a block diagram illustrating a command processing device according to an example embodiment.

[0032] Reference Figure 1 , the command processing device 100 includes an asynchronous first-in-first-out (FIFO) unit 120 , a mode configuration unit 140 , and a post-processing unit 160 .

[0033] In some examples, the command processing device 100 may be included in a display device and a display driver integrated circuit included therein, and may operate as a receiver that receives and processes a signal provided from a host processor to drive the display device. Fig.17 , Fig.18A , Fig.18B , Fig.19 , Fig. 20A and Fig. 20B Examples of display driver integrated circuits and display devices are described. Fig.21 and Fig. 22 An example of a system including a host processor and a display device is described.

[0034] The asynchronous FIFO unit 120 receives data from an external device or from the outside (e.g., Fig.21 The host processor 920 in the embodiment receives a plurality of signals IN_S and stores the plurality of signals IN_S. For example, the plurality of signals IN_S include a plurality of commands CMD, and the asynchronous FIFO unit 120 receives a plurality of commands CMD from an external device and stores the plurality of commands CMD. For example, although Figure 1 Although not shown in FIG. 1 , the plurality of signals IN_S may also include a plurality of data, and the asynchronous FIFO unit 120 may receive and store the plurality of data. Figure 2 An example of the asynchronous FIFO unit 120 is described.

[0035] In some example embodiments, the command processing device 100 may operate based on the Mobile Industry Processor Interface (MIPI) standard. In other words, the host processor and the display device (e.g., a display driver integrated circuit included in the display device) may exchange signals based on the MIPI standard (e.g., based on the Display Serial Interface (DSI) standard). For example, the plurality of signals IN_S received by the command processing device 100 included in the display device (e.g., the display driver integrated circuit) may be signals implemented based on the MIPI standard.

[0036] In some example embodiments, when the plurality of signals IN_S are signals implemented based on the MIPI standard, the plurality of commands CMD included in the plurality of signals IN_S may be MIPI Display Command Set (DCS) commands. For example, the command processing device 100 may be referred to as a MIPI DCS command processing device.

[0037] DSI is a specification of the MIPI alliance that aims to reduce the cost of display controllers in mobile devices. DSI is generally aimed at liquid crystal display (LCD) and similar display technologies, and it defines a serial bus and communication protocol between a host as the source of image data and a device as the destination. At the physical layer, DSI specifies a high-speed differential signaling point-to-point serial bus. The bus includes a high-speed clock channel and one or more data channels. The communication protocol describes two sets of instructions. DCS is a set of common commands for controlling display devices, and the manufacturer command set (MCS) is a device-specific command space whose definition is determined by the device manufacturer. The format of DCS is specified by the DSI standard, and DCS defines what registers can be addressed and their operations. MCS typically includes commands required to program non-volatile memory, set specific device registers (such as gamma correction), or perform other actions not described in the DSI standard.

[0038] The mode configuration unit 140 sets the command processing scheme for each of the plurality of commands CMD to one of a first processing scheme (or a first processing mode) or a second processing scheme (or a second processing mode) different from the first processing scheme, and stores the command processing scheme for each of the plurality of commands. For example, how to process, cope with, or treat each of the various types of commands that can be received by the command processing device 100 can be preset or set in advance, and the preset command processing scheme for each of the various types of commands can be stored as a plurality of setting values ​​SV in the mode configuration unit 140. Figure 3 An example of the mode configuration unit 140 is described.

[0039] The post-processing unit 160 determines a command processing scheme for each of the plurality of commands CMD received from the external device and stored in the asynchronous FIFO unit 120 based on the mode configuration unit 140, for example, based on the plurality of setting values ​​SV provided from the mode configuration unit 140. The post-processing unit 160 generates a plurality of control signals CONT by processing the plurality of commands CMD based on the input sequence (or order) of the plurality of commands CMD and the determined command processing scheme. For example, a command received first may be processed first, and a command received later may be processed later. For example, the type (or form) of each control signal corresponding to each command may be determined according to the command processing scheme.

[0040] In some example embodiments, depending on the internal structure of the post-processing unit 160, the first processing scheme may be a fixed, unchangeable, and predetermined command processing scheme, and the second processing scheme may be a flexible, changeable, and command processing scheme that is independent of (or independent of) the internal structure of the post-processing unit 160. Figure 4 As described, the first processing scheme may be based on a hardware configuration within the post-processing unit 160 and may be referred to as a hardware scheme (or hardware mode), and the second processing scheme may be based on software execution and may be referred to as a software scheme (or software mode).

[0041] In some example embodiments, as will be referred to Figure 6 , Fig. 7A , Figure 7B and Figure 7C As described, one of the first processing scheme and the second processing scheme may be selected and determined as a command processing scheme for a specific command, and a specific control signal may be generated by processing the specific command based on the selected and / or determined one of the first processing scheme and the second processing scheme.

[0042] In some example embodiments, as will be referred to Figure 8 , 9A As described in FIG. 9B , when a predetermined condition is met, both the first processing scheme and the second processing scheme may be selected and determined as command processing schemes for a specific command, and a specific control signal may be generated by processing the specific command based on both the first processing scheme and the second processing scheme.

[0043] In a conventional command processing device, a command processing scheme for all possible commands is implemented only in a hardware scheme or a software scheme. If the command processing scheme is implemented only in a hardware scheme, the command processing speed may be relatively fast, however, there may be a problem that the operations of all commands should be accurately defined in the chip design stage, and the chip should be redesigned when the operation of a specific command is to be changed. If the command processing scheme is implemented only in a software scheme, it can flexibly respond to changes in the operation of a specific command, however, there may be a problem that the command processing speed is relatively slow and the number and / or order of command transmissions should be limited to meet the requirements of the command response speed.

[0044] In the command processing device 100 according to the example embodiment, a hybrid processing scheme can be applied, adopted and adopted, wherein the command processing scheme is selectively, adaptively and / or dynamically determined as at least one of a hardware scheme and a software scheme, depending on the type of command. For example, dedicated hardware can be designed or implemented to process specific commands based on a hardware scheme, and thus the requirements for fast command processing speed and command response speed can be ensured or met. For example, additional paths can be implemented to process specific commands in a software scheme, and thus changes in the operation of specific commands can be easily performed. In addition, in order to maintain and / or obtain flexibility, configurable hardware can be implemented based on a memory-mapped system. Therefore, the advantages of hardware and software schemes can be strengthened, the disadvantages of hardware and software schemes can be improved, and thus command processing can be effectively performed.

[0045] Figure 2 It is shown that the Figure 1 A block diagram of an example of an asynchronous FIFO unit in a command processing device.

[0046] Reference Figure 2 , the asynchronous FIFO unit 120 a may include a command FIFO 122 and a data FIFO 124 .

[0047] The command FIFO 122 may sequentially receive a plurality of commands CMD1, CMD2, ..., CMDK (where K is a positive integer greater than or equal to 2), and may sequentially output the plurality of commands CMD1, CMD2, ..., CMDK based on the order or sequence of receiving the commands CMD1, CMD2, ..., CMDK. For example, all commands in the plurality of commands CMD1, CMD2, ..., CMDK may be commands of different types. For another example, at least some of the plurality of commands CMD1, CMD2, ..., CMDK may be commands of the same type.

[0048] The plurality of commands CMD1, CMD2, ..., CMDK may include a plurality of command identifications (IDs) ID1, ID2, ..., IDK for identifying and / or checking the type of the command. For example, the first command CMD1 may include a first command ID ID1, the second command CMD2 may include a second command ID ID2, and the Kth command CMDK may include a Kth command ID IDK.

[0049] The data FIFO 124 may sequentially receive a plurality of data DAT1, DAT2, ..., DATK corresponding to a plurality of commands CMD1, CMD2, ..., CMDK, and may sequentially output the plurality of data DAT1, DAT2, ..., DATK based on the sequence or order of receiving the plurality of data DAT1, DAT2, ..., DATK.

[0050] As described above, the asynchronous FIFO unit 120a can separately store commands CMD1, CMD2, ..., CMDK and data DAT1, DAT2, ..., DATK, and thus the asynchronous FIFO unit 120a may include two FIFO units (e.g., command FIFO 122 and data FIFO 124) implemented separately, independently and / or individually. However, example embodiments are not limited thereto, and the number of FIFO units included in the command processing device 100 may be determined differently according to example embodiments.

[0051] Figure 3 It is shown that the Figure 1 A block diagram of an example of a mode configuration unit in a command processing device.

[0052] Reference Figure 3 , the mode configuration unit 140a may store a plurality of setting values ​​SV1, SV2, ..., SVX (where X is a positive integer greater than or equal to 2) representing or indicating command processing schemes for all types of commands that may be received by the command processing device 100. For example, the first setting value SV1 may represent a command processing scheme for a first type of command, the second setting value SV2 may represent a command processing scheme for a second type of command, and the Xth setting value SVX may represent a command processing scheme for an Xth type of command. In other words, when the number or quantity of the setting values ​​SV1, SV2, ..., SVX stored in the mode configuration unit 140a is X, the number or quantity of types of commands that the command processing device 100 may receive may be X.

[0053] In some example embodiments, the mode configuration unit 140a may include at least one register for storing a plurality of setting values ​​SV1, SV2, ..., SVX. For example, the mode configuration unit 140a may be implemented in the form of a special function register (SFR).

[0054] In some example embodiments, the command processing scheme for each of the plurality of commands CMD1, CMD2, ... CMDK may be based on Figure 2 Multiple command IDs ID1, ID2, ..., IDK and Figure 3 For example, when the first command CMD1 is a command of the first type, a first setting value SV1 indicating a command processing scheme for the command of the first type may be obtained based on the first command ID ID1 of the first command CMD1, and the command processing scheme for the first command CMD1 may be determined based on the first setting value SV1.

[0055] In some example embodiments, command processing schemes for different types of commands may be determined based on different setting values, and command processing schemes for the same type of commands may be determined based on the same setting value. For example, when the first command CMD1 is a command of the first type and the second command CMD2 is a command of the second type that is different from the first type of command, the command processing scheme for the first command CMD1 and the command processing scheme for the second command CMD2 may be determined based on the first setting value SV1 and the second setting value SV2 (e.g., based on different setting values), respectively. For example, when both the first command CMD1 and the second command CMD2 are commands of the first type (e.g., commands of the same type), the command processing scheme for the first command CMD1 and the command processing scheme for the second command CMD2 may be determined based on the first setting value SV1 (e.g., based on the same setting value).

[0056] In some example embodiments, the number of setting values ​​SV1, SV2, ..., SVX stored in the mode configuration unit 140a may be changeable. For example, when a new command that did not previously exist is to be defined and used, new setting values ​​for the new command may be additionally stored in the mode configuration unit 140a, and thus the number of setting values ​​may increase. For example, when an existing command that has previously been used is no longer used, an existing setting value for the existing command may be deleted or removed from the mode configuration unit 140a, and thus the number of setting values ​​may decrease.

[0057] Figure 4 It is shown that the Figure 1 A block diagram of an example of a post-processing unit in a command processing device.

[0058] Reference Figure 4 The post-processing unit 160 a may include a control unit 162 , a first processing unit 164 , and a second processing unit 166 .

[0059] The control unit 162 may sequentially receive the plurality of commands CMD stored in the asynchronous FIFO unit 120 based on the input order of the plurality of commands CMD, may receive the plurality of setting values ​​SV from the mode configuration unit 140 based on the plurality of command IDs ID1, ID2, ..., IDK included in the plurality of commands CMD, may determine the command processing scheme for the plurality of commands CMD based on the plurality of setting values ​​SV, and may generate a mode signal MS indicating the command processing scheme for the plurality of commands CMD. For example, when a specific command is received, a specific setting value corresponding to the type of the specific command may be obtained based on the command ID of the specific command, and the command processing scheme for the specific command may be determined based on the specific setting value.

[0060] The first processing unit 164 may generate a plurality of transactions TRSC by processing a plurality of commands CMD based on a first processing scheme (e.g., a hardware scheme). For example, when the command processing scheme for a specific command is determined to be the first processing scheme, a specific transaction corresponding to the specific command may be generated by processing the specific command based on the first processing scheme, and the specific transaction may be output as a control signal corresponding to the specific command.

[0061] The first processing unit 164 may include a plurality of logic circuits 165 as hardware. The plurality of logic circuits 165 may be designed, arranged, connected, and manufactured according to the designer and manufacturer's specifications, and may be implemented to generate transactions by processing commands based on a predetermined scheme. For example, the plurality of logic circuits 165 may be implemented with a predetermined finite state machine (FSM). Therefore, depending on the structure or configuration of the plurality of logic circuits 165, the first processing scheme performed by the first processing unit 164 may be fixed, unchangeable, and predetermined.

[0062] The second processing unit 166 can generate a plurality of interrupts ITR by processing a plurality of commands CMD based on a second processing scheme (e.g., a software scheme). For example, when the command processing scheme for a specific command is determined to be the second processing scheme, a specific interrupt corresponding to the specific command can be generated by processing the specific command based on the second processing scheme, and the specific interrupt can be output as a control signal corresponding to the specific command.

[0063] The second processing unit 166 may include a program code (or instruction) PC as software. For example, the second processing unit 166 may include a microcontroller unit (MCU) 167 and a memory 168. For example, the program code PC may be stored in the memory 168 and may be loaded and executed by the MCU 167. For example, the second processing unit 166 may be implemented to generate an interrupt by flexibly processing commands based on the execution of the program code PC. Therefore, the second processing scheme executed by the second processing unit 166 may be flexible, configurable and independent of the fixed configuration of the plurality of logic circuits 165.

[0064] In some example embodiments, when the command processing scheme for a specific command is determined to be the first processing scheme, or thereafter, the control unit 162 may further determine an access scheme for the specific command. For example, it may be additionally determined whether the access scheme for the specific command is the first access scheme or a second access scheme different from the first access scheme. For example, the first access scheme may be a direct access scheme, in which command processing and corresponding data access are performed substantially simultaneously or concurrently. For example, the second access scheme may be an indirect access scheme, in which data access is performed after a certain period of time has passed after command processing. For example, when the access scheme for the specific command is determined to be the second access scheme, a transaction generation operation using the first processing unit 164 and an interrupt generation operation using the second processing unit 166 may be performed together.

[0065] In some example embodiments, the control unit 162 may also check or determine whether the plurality of commands CMD are valid. For example, only after checking that a specific command is valid, the operation of determining a command processing scheme, the operation of determining an access scheme, and the command processing operation may be performed on the specific command.

[0066] In some example embodiments, the control unit 162 may generate a FIFO control signal FCON for controlling the asynchronous FIFO unit 120 depending on a result of a command processing operation and / or a result of checking validity of a command.

[0067] Figure 5 is a flow chart illustrating a method of processing commands according to an example embodiment.

[0068] Reference Figure 5 In the method for processing commands according to the example embodiment, a plurality of commands are received from an external device (operation S100). The plurality of received commands may be stored internally. In addition, a command processing scheme for each of the plurality of commands may be preset to one of a first processing scheme or a second processing scheme different from the first processing scheme, and a plurality of setting values ​​may also be stored internally, each of the plurality of setting values ​​representing the command processing scheme for each of the plurality of commands.

[0069] A command processing scheme for each of a plurality of commands is determined based on a plurality of setting values ​​(operation S200 ), and a plurality of control signals are generated by processing the plurality of commands based on an input order of the plurality of commands and the determined command processing scheme (operation S300 ).

[0070] The method for processing a command according to an example embodiment may be performed according to the reference Figure 1 The command processing device 100 of the exemplary embodiment described above is executed. For example, operation S100 may be performed by Figure 1 The asynchronous FIFO unit 120 in the embodiment of the present invention is executed, and operation S200 can be performed by Figure 1 The mode configuration unit 140 and the post-processing unit 160 in the embodiment are performed, and operation S300 can be performed by Figure 1 The post-processing unit 160 in is executed.

[0071] Figure 6 It is shown Figure 5 Flowchart of an example of determining a command processing scheme and an example of generating a control signal.

[0072] Reference Figure 6 , shows an example in which a command processing scheme for a command is determined and a control signal is generated by processing the command.

[0073] For example, it may be determined whether the command processing scheme for a specific command is the first processing scheme or the second processing scheme (operation S210). For example, a specific setting value corresponding to the type of the specific command may be obtained based on the command ID of the specific command, and the command processing scheme for the specific command may be determined based on the specific setting value. For example, operation S210 may include Figure 5 In operation S200 in the embodiment. For example, operation S210 may be performed by Figure 3 The mode configuration unit 140a and Figure 4 The control unit 162 in is executed.

[0074] When the command processing scheme for the specific command is determined to be the first processing scheme (operation S210: yes), a specific transaction may be generated by processing the specific command based on the first processing scheme (operation S310), and the specific transaction may be output as a control signal corresponding to the specific command. For example, target information (e.g., direction, byte mode, length, etc.) of the specific command may be checked or identified, and an Advanced Microcontroller Bus Architecture (AMBA) transaction may be generated. For example, operation S310 may include Figure 5 In operation S300 in the embodiment. For example, operation S310 may be performed by Figure 4The first processing unit 164 in is executed.

[0075] When the command processing scheme for the specific command is determined to be the second processing scheme (operation S210: No), a specific interrupt corresponding to the specific command may be generated by processing the specific command based on the second processing scheme (operation S320), and the specific interrupt may be output as a control signal corresponding to the specific command. For example, a command interrupt may be generated, a command and corresponding data may be read from a command FIFO and a data FIFO, a software-designed command processing may be executed, and an interrupt service routine (ISR) writing may be completed. For example, operation S320 may include Figure 5 In operation S300 in the embodiment. For example, operation S320 may be performed by Figure 4 The second processing unit 166 in is executed.

[0076] After a specific command is processed through operation S310 or operation S320 (e.g., after a specific transaction or a specific interrupt is generated), the asynchronous FIFO unit 120 may be updated to delete the specific command (operation S330). For example, the processed command may be deleted from the asynchronous FIFO unit 120 based on the FIFO control signal FCON generated from the control unit 162. For example, operation S330 may include Figure 5 In operation S300.

[0077] Fig. 7A , Figure 7B and Figure 7C Is used to describe Figure 4 The operation of the post-processing unit is shown in Figure 1. Fig. 7A , Figure 7B and Figure 7C In, based on Figure 6 An example of determining a command processing scheme and generating a control signal is shown in Figure 4 Operation of the post-processing unit 160a.

[0078] Reference Figure 3 , Fig. 7A , Figure 7B and Figure 7C , each of the plurality of setting values ​​SV1, SV2, . . . , SVX stored in the mode configuration unit 140a may include a mode setting value indicating a command processing scheme.

[0079] For example, the first mode setting value included in the first setting value SV1 corresponding to the first command ID ID1 of the first command CMD1 may have a first value '0', and the second mode setting value included in the second setting value SV2 corresponding to the second command ID ID2 of the second command CMD2 may have a second value '1' different from the first value '0'. Fig. 7A An example is shown in which the first command CMD1 and the second command CMD2 are different types of commands.

[0080] When Figure 7B When the first command CMD1 is provided to the post-processing unit 160a, the control unit 162 may obtain the first setting value SV1 from the mode configuration unit 140a based on the first command ID ID1 of the first command CMD1. Since the first mode setting value included in the first setting value SV1 has the first value '0', the control unit 162 may determine the command processing scheme for the first command CMD1 as the first processing scheme, and may output the mode signal MS indicating the first processing scheme. The first processing unit 164 may generate a first transaction TRSC1 by processing the first command CMD1 based on the first processing scheme using a plurality of logic circuits 165, and may output the first transaction TRSC1 as a first control signal corresponding to the first command CMD1. After the first command CMD1 is processed, the control unit 162 may generate a FIFO control signal FCON for updating the asynchronous FIFO unit 120a (e.g., for deleting the first command CMD1 from the asynchronous FIFO unit 120a).

[0081] When Figure 7C When the second command CMD2 is provided to the post-processing unit 160a, the control unit 162 may obtain the second setting value SV2 from the mode configuration unit 140a based on the second command ID ID2 of the second command CMD2. Since the second mode setting value included in the second setting value SV2 has the second value "1", the control unit 162 may determine the command processing scheme for the second command CMD2 as the second processing scheme, and may output the mode signal MS indicating the second processing scheme. The second processing unit 166 may generate a second interrupt ITR2 by processing the second command CMD2 based on the second processing scheme using the program code PC stored in the memory 168 and executed by the MCU 167, and may output the second interrupt ITR2 as a second control signal corresponding to the second command CMD2. After the second command CMD2 is processed, the control unit 162 may generate a FIFO control signal FCON for updating the asynchronous FIFO unit 120a (e.g., for deleting the second command CMD2 from the asynchronous FIFO unit 120a).

[0082] In some example embodiments, when the first command CMD1 is first input to the asynchronous FIFO unit 120a and then the second command CMD2 is later input to the asynchronous FIFO unit 120a, the first command CMD1 may be executed. Figure 7B The operation of processing the first command CMD1 shown in FIG, and then can be performed later Figure 7C The operation of processing the second command CMD2 shown in FIG. When the second command CMD2 is first input to the asynchronous FIFO unit 120a and then the first command CMD1 is later input to the asynchronous FIFO unit 120a, the operation of processing the second command CMD2 can be performed first. Figure 7C The operation of processing the second command CMD2 is shown, and then it can be executed later Figure 7B The operation of processing the first command CMD1 is shown.

[0083] exist Figure 7B In FIG. 1 , the second processing unit 166 which is not used in the operation of processing the first command CMD1 is shown by a dotted line. Figure 7C , the first processing unit 164 that is not used in the operation of processing the second command CMD2 is shown by a dotted line. In some example embodiments, the components shown by the dotted lines may be deactivated or deactivated (for example, the components shown by the dotted lines may enter a low power mode or the power supplied to the components shown by the dotted lines may be blocked). However, example embodiments are not limited thereto.

[0084] Figure 8 It is shown Figure 5 For the sake of brevity, the flowcharts of the example of determining the command processing scheme and the example of generating the control signal are omitted. Figure 6 Descriptions of duplicate or overlapping descriptions.

[0085] Reference Figure 8 , shows an example in which a command processing scheme for a command is determined and a control signal is generated by processing a command. Operations S210, S310, S320, and S330 may be similar to those of reference Figure 6 The operations described are essentially the same.

[0086] When the command processing scheme for a specific command is determined to be the first processing scheme and a specific transaction is generated by processing the specific command based on the first processing scheme (operation S210: yes, and operation S310), it may be additionally determined whether the access scheme for the specific command is the first access scheme or the second access scheme (operation S220). For example, as in operation S210, a specific setting value corresponding to the type of the specific command may be obtained based on the command ID of the specific command, and the access scheme for the specific command may be determined based on the specific setting value. For example, operation S220 may include: Figure 5In operation S200 in the embodiment. For example, operation S220 may be performed by Figure 3 The mode configuration unit 140a and Figure 4 The control unit 162 in is executed.

[0087] When the access scheme for the specific command is determined to be the first access scheme (operation S220: YES), only the specific transaction generated by operation S310 may be output as a control signal corresponding to the specific command without an additional operation, and operation S330 may be performed thereafter.

[0088] When the access scheme for the specific command is determined to be the second access scheme (operation S220: No), operation S320 may be additionally performed after operation S310 is performed to generate a specific interrupt, and thereafter operation S330 may be performed. In other words, both the specific transaction generated by processing the specific command based on the first processing scheme and the specific interrupt generated by processing the specific command based on the second processing scheme may be output as a control signal corresponding to the specific command.

[0089] When the command processing scheme for the specific command is determined as the second processing scheme and the specific interrupt is generated by processing the specific command based on the second processing scheme (operation S210: No, and operation S320), the operation of determining the access scheme for the specific command in operation S220 may not be performed.

[0090] Fig.9A and 9B Is used to describe Figure 4 The operation of the post-processing unit is shown in Figure 1. Fig.9A and Fig. 9B In, based on Figure 8 An example of determining a command processing scheme and generating a control signal is shown in Figure 4 For the sake of brevity, the following description will be omitted. Fig. 7A , Figure 7B and Figure 7C Descriptions of duplicate or overlapping descriptions.

[0091] Reference Figure 3 , Fig.9A and Fig. 9B , each of the plurality of setting values ​​SV1, SV2, . . . , SVX stored in the mode configuration unit 140a may include a mode setting value indicating a command processing scheme and an access setting value indicating an access scheme.

[0092] For example, the first access setting value included in the first setting value SV1 corresponding to the first command ID ID1 of the first command CMD1 and the second access setting value included in the second setting value SV2 corresponding to the second command ID ID2 of the second command CMD2 may have a first value of '0'. The third mode setting value and the third access setting value included in the third setting value SV3 corresponding to the third command ID ID3 of the third command CMD3 may be a first value ('0') and a second value '1', respectively. Fig.9A An example is shown in which the first command CMD1 , the second command CMD2 , and the third command CMD3 are different types of commands.

[0093] When Fig. 9B When the third command CMD3 is provided to the post-processing unit 160a, the control unit 162 may obtain the third setting value SV3 from the mode configuration unit 140a based on the third command ID ID3 of the third command CMD3. Since the third mode setting value included in the third setting value SV3 has the first value '0', the control unit 162 may determine the command processing scheme for the third command CMD3 as the first processing scheme, and the first processing unit 164 may generate the third transaction TRSC3 by processing the third command CMD3 based on the first processing scheme using the plurality of logic circuits 165. In addition, since the third access setting value included in the third setting value SV3 has the second value '1', the control unit 162 may determine the access scheme for the third command CMD3 as the second access scheme, and the second processing unit 166 may additionally generate the third interrupt ITR3 by processing the third command CMD3 based on the second processing scheme using the program code PC stored in the memory 168 and executed by the MCU 167. Both the third transaction TRSC3 and the third interrupt ITR3 may be output as the third control signal corresponding to the third command CMD3. After the third command CMD3 is processed, the control unit 162 may generate a FIFO control signal FCON for updating the asynchronous FIFO unit 120 a (eg, for deleting the third command CMD3 from the asynchronous FIFO unit 120 a ).

[0094] Since the first access setting value included in the first setting value SV1 has the first value '0', the control unit 162 may determine the access scheme for the first command CMD1 as the first access scheme, and may output only the first transaction TRSC1 as the first control signal corresponding to the first command CMD1, as shown in FIG. Figure 7B When the command processing scheme for the second command CMD2 is determined as the second processing scheme, the control unit 162 may not determine the access scheme for the second command CMD2 regardless of the second access setting value included in the second setting value SV2.

[0095] Fig.10 is a flowchart illustrating a method of processing commands according to an example embodiment. Figure 5 Descriptions of duplicate or overlapping descriptions.

[0096] Reference Fig.10 In the method of processing a command according to an example embodiment, operation S100 may be related to reference Figure 5 The operations described are essentially the same.

[0097] After operation S100, it may be checked whether the plurality of commands are valid (operation S400). The operation of determining the command processing scheme in operation S200a and the operation of generating the control signal in operation S300 may be performed only for valid commands. Operation S200a may be performed with Figure 5 The operation S200 in FIG. 1 is substantially the same as that in FIG. 1 . For example, the operation S400 may be performed by Figure 1 The mode configuration unit 140 and the post-processing unit 160 are executed.

[0098] Fig.11 and Fig.12 It is shown Fig.10 For the sake of brevity, the flowcharts of the examples of checking whether a command is valid, determining a command processing scheme, and generating a control signal are omitted. Figure 6 and Figure 8 Descriptions of duplicate or overlapping descriptions.

[0099] Reference Fig.11 , shows an example in which a command processing scheme for a command is determined and a control signal is generated by processing a command. Operations S210, S310, S320, and S330 may be similar to those of reference Figure 6 The operations described are essentially the same.

[0100] Before determining the command processing scheme for the specific command, it may be checked whether the specific command is valid (operation S410). For example, a plurality of setting values ​​may be searched based on the command ID of the specific command to determine whether the specific command is a valid command. For example, operation S410 may include Fig.10 In operation S400 in the embodiment. For example, operation S410 may be performed by Figure 3 The mode configuration unit 140a and Figure 4 The control unit 162 in is executed.

[0101] When it is checked that the specific command is valid (operation S410: Yes), the reference command may be executed. Figure 6The operation steps S210, S310, S320, and S330 described above are described. When it is checked that the specific command is invalid (operation S410: No), operations S210, S310, S320, and S330 may not be performed, and the asynchronous FIFO unit 120 may be refreshed to delete the specific command (operation S420). For example, the invalid command may be deleted from the asynchronous FIFO unit 120 based on the FIFO control signal FCON generated from the control unit 162. For example, operation S420 may include Fig.10 In operation S400.

[0102] Reference Fig.12 , shows an example in which a command processing scheme for a command is determined and a control signal is generated by processing a command. Operations S210, S310, S320, and S330 may be similar to those of reference Figure 6 The operation described is substantially the same. Operation S220 may be the same as that described in reference Figure 8 The operations described are substantially the same. Operations S410 and S420 may be the same as those described in reference Fig.11 The operations described are essentially the same.

[0103] Fig.13A , Fig. 13B and Fig. 13C Is used to describe Figure 4 The operation of the post-processing unit is shown in Figure 1. Fig.13A , Fig. 13B and Fig. 13C In, based on Fig.11 and Fig.12 An example of checking whether a command is valid, determining a command processing scheme, and generating a control signal is shown in Figure 4 For the sake of brevity, the following description will be omitted. Fig. 7A , Figure 7B , Figure 7C , Fig.9A and Fig. 9B Descriptions of duplicate or overlapping descriptions.

[0104] Reference Figure 3 , Fig.13A , Fig. 13B and Fig. 13C Each of the plurality of setting values ​​SV1, SV2, ..., SVX stored in the mode configuration unit 140a may include Fig. 7A Mode setting values ​​similar to those described in the Fig.9A The mode setting values ​​and access setting values ​​described are similar to the mode setting values ​​and access setting values.

[0105] For example, the fourth setting value corresponding to the fourth command ID ID4 of the fourth command CMD4 may not exist or may have an invalid value. Fig.13A As shown in FIG. 1 , the fourth mode setting value included in the fourth setting value may not have a specific value. Fig. 13B As shown, the fourth mode setting value and the fourth access setting value included in the fourth setting value may not have specific values.

[0106] When Fig. 13C When the fourth command CMD4 is provided to the post-processing unit 160a, the control unit 162 may not obtain the fourth setting value from the mode configuration unit 140a based on the fourth command ID ID4 of the fourth command CMD4, and may receive an invalid setting value SV_IV, for example, a signal indicating that the fourth setting value does not exist or has an invalid value. The control unit 162 may determine that the fourth command (CMD4) is invalid, and may not perform an operation of determining a command processing scheme for the fourth command CMD4 and / or an operation of determining an access scheme for the fourth command CMD4. Therefore, the fourth command CMD4 may not be processed. Thereafter, the control unit 162 may generate a FIFO control signal FCON for refreshing the asynchronous FIFO unit 120a (for example, for deleting the fourth command CMD4 from the asynchronous FIFO unit 120a).

[0107] Fig.14 and Fig.15 is a flowchart illustrating a method of processing commands according to an example embodiment. Figure 5 and Fig.10 Descriptions of duplicate or overlapping descriptions.

[0108] Reference Fig.14 In the method of processing a command according to an example embodiment, operations S100, S200, and S300 may be similar to those of reference Figure 5 The operations described are essentially the same.

[0109] After operation S300, it may be checked whether the asynchronous FIFO unit in which the plurality of commands are stored is empty, for example, whether all received commands have been processed (operation S500).

[0110] When the asynchronous FIFO unit is empty (operation S500: Yes), for example, when all received commands have been processed, reception of at least one additional command may be waited (operation S600). Thereafter, when at least one additional command is received, operations S100, S200, and S300 may be repeatedly performed.

[0111] When the asynchronous FIFO unit is not empty (operation S500: No), for example, when all received commands have not been processed or other commands are additionally received during command processing, operations S200 and S300 may be repeatedly performed. For example, operations S500 and S600 may be performed by Figure 1 The asynchronous FIFO unit 120 and the post-processing unit 160 are executed.

[0112] Reference Fig.15 In the method of processing a command according to an example embodiment, operations S100 and S300 may be similar to those of reference Figure 5 The operations described are substantially the same, and operations S400 and S200a can be compared with those of reference Fig.10 The operations described are substantially the same, and operations S500 and S600 may be the same as those described in reference Fig.14 The operations described are essentially the same.

[0113] Fig.16A and Fig. 16B is a diagram for describing an operation of a command processing device according to an example embodiment.

[0114] Reference Fig.16A and Fig. 16B , shows an example of multiple DCS read commands and multiple DCS write commands defined in the MIPI DCS specification. Although not shown in detail, various other DCS commands may be defined. According to an example embodiment, such DCS commands may be input to and processed by the command processing device 100.

[0115] In some example embodiments, a plurality of DCS read commands may have a limited response speed (eg, should be processed relatively quickly), and thus command processing schemes for the plurality of DCS read commands may be preset and stored as a first processing scheme (eg, a hardware scheme).

[0116] In some example embodiments, command processing schemes of some DCS write commands used as triggers among a plurality of DCS write commands may be preset and stored as a second processing scheme (eg, a software scheme).

[0117] In some example embodiments, a command processing scheme for a command added as a customized specification (or customer-specific specification) may be set and stored as a second processing scheme (eg, software scheme).

[0118] In some example embodiments, a command processing scheme for a command requiring an indirect access scheme may be set and stored to use both a first processing scheme (e.g., a hardware scheme) and a second processing scheme (e.g., a software scheme). For example, when a large amount of data is to be received and processed, the first processing scheme may be used for command processing and data copying that require relatively fast processing, and the second processing scheme may be used later for operations such as image processing using actual data.

[0119] In the command processing device 100 according to the example embodiment, in the case where various types of the above-mentioned commands are randomly mixed and transmitted, these various types of commands can be processed separately by command (e.g., by command ID). Therefore, various DCS commands can be flexibly processed depending on the required characteristics, and thus the workload and requirements of the device and / or system can be reduced. In addition, the example embodiment can be easily implemented by manually setting the first processing scheme and the second processing scheme (e.g., hardware scheme and software scheme) for each command (e.g., for each command ID).

[0120] As will be appreciated by those skilled in the art, these ideas may be embodied as systems, methods, computer program products, and / or computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be any tangible medium that may contain or store a program used by or in conjunction with an instruction execution system, device, or apparatus. For example, a computer-readable medium may be a non-transitory computer-readable medium.

[0121] Fig.17 is a block diagram illustrating a display driving integrated circuit according to example embodiments.

[0122] Reference Fig.17 , the display driver integrated circuit 500 includes a command processing device 520 and a display driver device 540 .

[0123] The command processing device 520 receives a command from an external device (e.g., Fig.21 The host processor 920 in the embodiment receives a plurality of signals IN_S including a plurality of commands CMD and a plurality of data DAT, and generates a plurality of control signals CONT based on the plurality of commands CMD. For example, the command processing device 520 may be a processor according to the reference Figures 1 to 16BFor example, the command processing device 520 may generate a plurality of control signals CONT by processing a plurality of commands CMD based on a first processing scheme (eg, hardware scheme) or a second processing scheme (eg, software scheme), depending on the type of command.

[0124] The display driving device 540 generates a display driving signal DDS for driving the display panel based on a plurality of control signals CONT and a plurality of data DAT. Fig.18A and Fig.18B An example of the display driving device 540 is described.

[0125] In some example embodiments, the display driver integrated circuit 500 and the command processing device 520 and the display driver device 540 included in the display driver integrated circuit 500 may be implemented to comply with the MIPIDSI standard, the MIPID-PHY standard, and / or the MIPIDCS standard.

[0126] Fig.18A and 18B It is shown that the Fig.17 A block diagram of an example of a display driver device in a display driver integrated circuit.

[0127] Reference Fig.18A , the display driving device 540a may include an image processor 542. The image processor 542 may generate a data signal DS for displaying an image based on a plurality of control signals CONT and a plurality of data DAT. For example, the image processor 542 may selectively perform at least one of various image processing steps, such as image quality compensation, spot compensation, adaptive color correction (ACC) and / or dynamic capacitance compensation (DCC).

[0128] Reference Fig.18B , the display driving device 540b may include an image processor 542, a data driver 544, and a scan driver 546. The image processor 542 may be connected to a reference Fig.18A The image processor described is substantially the same. The data driver 544 may generate a plurality of data voltages DV applied to a plurality of data lines based on a plurality of control signals CONT and a data signal DS. The scan driver 546 may generate a plurality of scan signals SS applied to a plurality of scan lines based on a plurality of control signals CONT.

[0129] Fig.19 is a block diagram illustrating a display device according to example embodiments.

[0130] Reference Fig.19 , the display device 700 includes a display panel 710 and a display driver integrated circuit. The display driver integrated circuit may control the operation of the display panel 710 and may include a data driver 720, a scan driver 730, a power supply 740, and a timing controller 750.

[0131] The display panel 710 operates (e.g., displays an image) based on image data (e.g., based on frame data). The display panel 710 may be connected to a data driver 720 via a plurality of data lines D1, D2, ..., DM (where M is a positive integer greater than or equal to 2), and may be connected to a scan driver 730 via a plurality of scan lines S1, S2, ..., SN (where N is a positive integer greater than or equal to 2). The plurality of data lines D1, D2, ..., DM may extend in a first direction, and the plurality of scan lines S1, S2, ..., SN may extend in a second direction intersecting (e.g., substantially perpendicular to) the first direction.

[0132] The display panel 710 may include a plurality of pixels PX arranged in a matrix form having a plurality of rows and a plurality of columns. For example, each of the plurality of pixels PX may include a light emitting element and at least one transistor for driving the light emitting element. For another example, each of the plurality of pixels PX may include a liquid crystal capacitor and at least one transistor for driving the liquid crystal capacitor. Each of the plurality of pixels PX may be electrically connected to a corresponding one of a plurality of data lines D1, D2, ..., DM and a corresponding one of a plurality of scan lines S1, S2, ..., SN. Fig. 20A and Fig. 20B Describe an example for each pixel.

[0133] The timing controller 750 may control the overall operation of the display device 700. For example, the timing controller 750 may be configured to receive a timing signal from a host processor (e.g., Fig.21 The host processor 920 in the display device 700 receives a plurality of signals IN_S and may provide predetermined control signals CS1, CS2, and CS3 to the data driver 720, the scan driver 730, and the power supply 740 based on the plurality of signals IN_S to control the operation of the display device 700.

[0134] The timing controller 750 may include a command processing device CMD_PRC. The command processing device CMD_PRC may be based on the reference Figures 1 to 16B The command processing device CMD_PRC may process a plurality of commands (e.g., commands included in a plurality of signals IN_S) based on a first processing scheme (e.g., a hardware scheme) or a second processing scheme (e.g., a software scheme) depending on the type of the command. Figure 1command CMD) to generate multiple control signals (for example, Figure 1 For example, Fig.17 The control signals CS1, CS2 and CS3 in Figure 1 Corresponding to the control signal CONT in.

[0135] The timing controller 750 may generate a plurality of signals based on a plurality of data (eg, Figure 2 The data DAT1, DAT2, ..., DATK) (e.g., frame data) in the image display device generates a data signal DS for displaying an image. For example, the plurality of data may include red image data, green image data, and blue image data. In addition, the plurality of data may include white image data. Alternatively, the plurality of data may also include magenta image data, yellow image data, cyan image data, etc.

[0136] The data driver 720 may generate a plurality of data voltages based on the control signal CS1 and the data signal DS, and may apply the plurality of data voltages to the display panel 710 through the plurality of data lines D1, D2, ..., DM. For example, the data driver 720 may include a digital-to-analog converter (DAC) that converts the data signal DS in a digital form into a plurality of data voltages in an analog form.

[0137] The scan driver 730 may generate a plurality of scan signals based on the control signal CS2, and may apply the plurality of scan signals to the display panel 710 through the plurality of scan lines S1, S2, ..., SN. The plurality of scan lines S1, S2, ..., SN may be sequentially activated based on the plurality of scan signals.

[0138] In some example embodiments, the timing controller 750 may further include Fig.18A and 18B The image processor 542 in the image processor 542, and the data driver 720 and the scan driver 730 can be respectively Fig.18B The data driver 544 and the scan driver 546 correspond to each other.

[0139] In some example embodiments, the data driver 720, the scan driver 730, and the timing controller 750 may be implemented as one integrated circuit. In other example embodiments, the data driver 720, the scan driver 730, and the timing controller 750 may be implemented as two or more integrated circuits. A driving module including at least the timing controller 750 and the data driver 720 may be referred to as a timing controller embedded data driver (TED).

[0140] The power supply 740 may supply at least one power voltage PWR to the display panel 710 based on the control signal CS3 .

[0141] In some example embodiments, at least some of the elements included in the display driver integrated circuit may be disposed (e.g., directly mounted) on the display panel 710, or may be connected to the display panel 710 in a tape carrier package (TCP). Alternatively, at least some of the elements included in the display driver integrated circuit may be integrated on the display panel 710. In some example embodiments, the elements included in the display driver integrated circuit may be implemented with separate circuits / modules / chips, respectively. In other example embodiments, based on the function, some elements included in the display driver integrated circuit may be combined into one circuit / module / chip, or may be further divided into multiple circuits / modules / chips.

[0142] Although not shown in detail, the display device 700 may further include a frame buffer for storing frame data, a backlight unit, etc., depending on the type of the pixel PX, a driving scheme of the display panel 710, etc.

[0143] Fig. 20A and Fig. 20B It is shown that the Fig.19 A circuit diagram of an example of a pixel included in a display panel in a display device of the present invention.

[0144] Reference Fig. 20A , each pixel PXa may include a switching transistor TS, a storage capacitor CST, a driving transistor TD, and an organic light emitting diode EL.

[0145] The switching transistor TS may have a first electrode connected to the data line Di, a second electrode connected to the storage capacitor CST, and a gate electrode connected to the scan line Sj. The switching transistor TS may transmit the data voltage VDAT received from the data driver 720 to the storage capacitor CST in response to the scan signal SSC received from the scan driver 730.

[0146] The storage capacitor CST may have a first electrode connected to the first power voltage ELVDD and a second electrode connected to the gate electrode of the driving transistor TD. The storage capacitor CST may store the data voltage VDAT transferred through the switching transistor TS.

[0147] The driving transistor TD may have a first electrode connected to the first power voltage ELVDD, a second electrode connected to the organic light emitting diode EL, and a gate electrode connected to the storage capacitor CST. The driving transistor TD may be turned on or off depending on the data voltage VDAT stored in the storage capacitor CST.

[0148] The organic light emitting diode EL may have an anode electrode connected to the driving transistor TD and a cathode electrode connected to the second power supply voltage ELVSS. When the driving transistor TD is turned on, the organic light emitting diode EL may emit light based on a current flowing from the first power supply voltage ELVDD to the second power supply voltage ELVSS. The brightness of the pixel PXa may increase as the current flowing through the organic light emitting diode EL increases.

[0149] The first power supply voltage ELVDD and the second power supply voltage ELVSS may be included in Fig.19 For example, the first power voltage ELVDD may be a high power voltage, and the second power voltage ELVSS may be a low power voltage.

[0150] In some example embodiments, the display panel 710 including the pixel PXa may be a self-luminous display panel that emits light without using a backlight unit. For example, the display panel 710 may be an organic light emitting display panel including an organic light emitting diode (OLED) as a light emitting element.

[0151] In some example embodiments, the display panel 710 including the pixel PXa may have a relatively excellent retention characteristic capable of performing low-frequency driving. For example, the display panel 710 may be an oxide-based organic light-emitting display panel including an organic light-emitting diode as a light-emitting element and at least one transistor including a low-temperature polycrystalline oxide (LTPO).

[0152] In some example embodiments, the switch transistor TS and the drive transistor TD may include LTPO. For example, the drive transistor TD may be an LTPS thin film transistor (Thin Film Transistor, TFT) including low-temperature polysilicon (Low-Temperature Poly-Silicon, LTPS), and the switch transistor TS may be an oxide TFT including an oxide semiconductor. Due to the relatively high electron mobility (electron mobility), the LTPS TFT may be suitable for or suitable for current driving. Due to the relatively low leakage current (leakage current), the oxide TFT may be suitable for or suitable for switching. Therefore, when the LTPS TFT and the oxide TFT are used together, excellent characteristics (e.g., excellent retention characteristics) can be obtained. A pixel including both an LTPS TFT and an oxide TFT may be referred to as an LTPO pixel, and a display panel including an LTPO pixel may be referred to as a hybrid oxide panel (HOP). For example, the HOP can maintain an image for up to about one second in a single update, and therefore even if the display driver integrated circuit does not include a frame buffer, the HOP can be driven at a relatively low frequency, thereby reducing power consumption.

[0153] In some example embodiments, depending on the driving scheme of the display device 700, the pixel PXa can have various configurations. For example, the display device 700 can also be driven with an analog driving scheme or a digital driving scheme. The analog driving scheme uses a variable voltage level corresponding to the input data to generate grayscale, while the digital driving scheme uses a variable duration of light emitting diodes to generate grayscale. The analog driving scheme is difficult to implement because if the display is large and has a high resolution, the analog driving scheme requires the manufacture of a complex driver integrated circuit (IC). On the other hand, the digital driving scheme can easily achieve the required high resolution through a simpler IC structure.

[0154] Reference Fig. 20B , each pixel PXb may also include a switching transistor ST, a liquid crystal capacitor CL, and a storage capacitor CS.

[0155] The switching transistor ST may connect the capacitors CL and CST to the corresponding data line Di in response to a scan signal SSC transmitted through the corresponding gate line Sj. The liquid crystal capacitor CL may be connected between the switching transistor ST and a common voltage VCOM. The storage capacitor CST may be connected between the switching transistor ST and a ground voltage VGND. The liquid crystal capacitor CL may adjust the amount of light transmitted by the data voltage VDAT depending on the data stored in the storage capacitor CST.

[0156] The common voltage VCOM and the ground voltage VGND may be included in Fig.19 At least one power supply voltage PWR.

[0157] In some example embodiments, the display panel 710 including the pixels PXb may be an LCD panel using a backlight. The LCD panel may also operate based on low-frequency driving.

[0158] Fig.21 is a block diagram illustrating a display system according to example embodiments.

[0159] Reference Fig.21 , the display system 900 includes a channel 910 , a host processor 920 and a display device 940 .

[0160] The host processor 920 controls the overall operation of the display system 900. For example, the host processor 920 may be implemented in the form of an application processor (AP) or a system on chip (SoC).

[0161] The display device 940 includes a display driver integrated circuit 950 and a display panel 960. The display device 940 and the display driver integrated circuit 950 may be based on the reference Figures 17 to 20B The display device and the display driver integrated circuit of the exemplary embodiment described above. The display driver integrated circuit 950 may include a command processing device CMD_PRC. The command processing device CMD_PRC may be a command processing device CMD_PRC according to the reference Figures 1 to 16B The command processing device CMD_PRC of the described example embodiment may generate a plurality of control signals CONT by processing a plurality of commands CMD based on a first processing scheme (eg, hardware scheme) or a second processing scheme (eg, software scheme), depending on the type of the command CMD.

[0162] The host processor 920 and the display device 940 (eg, the display driver integrated circuit 950) may communicate via a channel 910. For example, the channel 910 may be implemented based on the MIPI standard, the host processor 920 may operate as a MIPI transmitter, and the display driver integrated circuit 950 may operate as a MIPI receiver.

[0163] Fig. 22 is a block diagram illustrating an electronic system including a display system according to example embodiments.

[0164] Reference Fig. 22, the electronic system 1000 may be implemented as a data processing device using or supporting a mobile industry processor interface (MIPI). The electronic system 1000 may include an application processor 1110, an image sensor 1140, a display device 1150, and the like. The electronic system 1000 may also include a radio frequency (RF) chip 1160, a global positioning system (GPS) 1120, a storage device 1170, a microphone (MIC) 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190. In addition, the electronic system 1000 may perform communication using an ultra-wideband (UWB) 1210, a wireless local area network (WLAN) 1220, a global microwave access interoperability (WIMAX) 1230, and the like.

[0165] The application processor 1110 may be a controller or a processor that controls operations of the image sensor 1140 and the display device 1150 .

[0166] The application processor 1110 may include a DSI host 1111 that performs serial communication with a display serial interface (DSI) device 1151 of the display device 1150, a CSI host 1112 that performs serial communication with a camera serial interface (CSI) device 1141 of the image sensor 1140, a physical layer (PHY) 1113 that performs data communication with a physical layer (PHY) 1161 of the RF chip 1160 based on MIPI DigRF, and a DigRF master device (DigRF MASTER) 1114 that controls data communication of the physical layer 1161. The DigRF slave device (DigRF SLAVE) 1162 of the RF chip 1160 can be controlled by the DigRF master device 1114.

[0167] In some example embodiments, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). In some example embodiments, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER).

[0168] The application processor 1110 may be a host processor according to an example embodiment, the DSI device 1151 may be a display driver integrated circuit according to an example embodiment, and the application processor 1110 and the DSI device 1151 may form a display system according to an example embodiment. The DSI device 1151 may include a command processing device according to an example embodiment.

[0169] Example embodiments may be applied to various electronic devices and systems including display devices. For example, example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, cars, etc.

[0170] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of the claimed protection. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. However, the various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although the features may be described as working in certain combinations above, one or more features from the combination may be deleted from the combination in some cases, and the combination may lead to a sub-combination or a variation of the sub-combination.

[0171] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without substantially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A command processing device, comprising: an asynchronous first-in-first-out FIFO circuit configured to receive a plurality of commands from an external device and store the plurality of commands; a mode configuration circuit configured to set a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme, the mode configuration circuit configured to store the command processing scheme for each of the plurality of commands; as well as A post-processor is configured to determine the command processing scheme for each of the plurality of commands based on the setting value sent by the mode configuration circuit, and the post-processor is configured to generate a plurality of control signals by processing the plurality of commands based on an input order of the plurality of commands and the determined command processing scheme.

2. The command processing device according to claim 1, in, The first processing scheme includes a fixed command processing scheme based on the internal structure of the post-processor, and Wherein, the second processing scheme includes a configurable command processing scheme based on the internal structure of the post-processor.

3. The command processing device according to claim 1, in, The plurality of commands include a plurality of command identification IDs, wherein the mode configuration circuit is configured to store a plurality of setting values ​​of the plurality of command IDs, and Wherein, the command processing scheme for each of the plurality of commands is determined based on the plurality of command IDs and the plurality of setting values.

4. The command processing device according to claim 1, wherein: The post-processor comprises: a controller configured to receive a first command from the asynchronous FIFO circuit, receive a first setting value for the first command from the mode configuration circuit based on a first command ID included in the first command, and determine a command processing scheme for the first command based on the first setting value; a first processor configured to generate a first control signal by processing the first command based on the first processing scheme based on the command processing scheme for the first command being determined as the first processing scheme; and The second processor is configured to generate the first control signal by processing the first command based on the second processing scheme based on the command processing scheme for the first command being determined as the second processing scheme.

5. The command processing device according to claim 4, in, The first processor includes a plurality of logic circuits, and Wherein, based on the command processing scheme for the first command being determined as the first processing scheme, a first transaction generated by processing the first command by the first processor is output as the first control signal.

6. The command processing device according to claim 4, in, The second processor includes program code stored in a memory and executed by a microcontroller unit, and Wherein, based on the command processing scheme for the first command being determined as the second processing scheme, a first interrupt generated by the second processor processing the first command is output as the first control signal.

7. The command processing device according to claim 4, in, The controller is configured to determine the command processing scheme for the first command as the first processing scheme based on the first setting value having a first value, and The controller is configured to determine the command processing scheme for the first command as the second processing scheme based on the first setting value having a second value different from the first value.

8. The command processing device according to claim 4, wherein: The controller is configured to determine an access scheme for the first command based on the first setting value based on the command processing scheme for the first command being determined as the first processing scheme.

9. The command processing device according to claim 8, in, The first processor is configured to generate the first control signal by processing the first command based on the access scheme for the first command being determined to be a first access scheme, and The first processor and the second processor are configured to generate the first control signal by processing the first command based on the access scheme for the first command being determined as a second access scheme different from the first access scheme.

10. The command processing device according to claim 9, wherein: Based on the access scheme for the first command being determined as the second access scheme, (i) a first transaction generated by processing the first command by the first processor and (ii) a first interrupt generated by processing the first command by the second processor are both output as the first control signal.

11. The command processing device according to claim 9, in, The controller is configured to determine the access scheme for the first command to be the first access scheme based on a first access setting value included in the first setting value having a first value, and The controller is configured to determine the access scheme for the first command as the second access scheme based on the first access setting value having a second value different from the first value.

12. The command processing device according to claim 4, wherein: The controller is configured to check whether the first command is valid based on the first setting value.

13. The command processing device according to claim 12, in, Based on the controller checking that the first command is valid, the command processing scheme for the first command is determined and the first control signal is generated, and Wherein, based on the controller checking that the first command is invalid, the asynchronous FIFO circuit is configured to be flushed to delete the first command without determining the command processing scheme for the first command and without generating the first control signal.

14. The command processing device according to claim 4, wherein: Based on the first control signal being generated, the asynchronous FIFO circuit is configured to be updated to delete the first command.

15. The command processing device according to claim 1, wherein: The command processing device is configured to operate based on the Mobile Industry Processor Interface MIPI standard.

16. The command processing device according to claim 15, wherein: The plurality of commands include MIPI Display Command Set DCS commands.

17. A display driver integrated circuit, comprising: a command processing device configured to generate a plurality of control signals based on a plurality of commands received from an external device; and A display driving device configured to drive a display panel based on the plurality of control signals, Wherein, the command processing device includes: an asynchronous first-in-first-out (FIFO) circuit configured to receive the plurality of commands from the external device and store the plurality of commands; a mode configuration circuit configured to set a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme, the mode configuration circuit configured to store the command processing scheme for each of the plurality of commands; and A post-processor is configured to determine the command processing scheme for each of the plurality of commands based on a setting value sent by the mode configuration circuit, and the post-processor is configured to generate the plurality of control signals by processing the plurality of commands based on an input order of the plurality of commands and the determined command processing scheme.

18. The display driver integrated circuit according to claim 17, wherein: The display driving device comprises: The image processor is configured to generate a data signal for displaying an image based on the plurality of control signals and the plurality of data.

19. The display driver integrated circuit according to claim 18, wherein: The display driving device further includes: a data driver configured to generate a plurality of data voltages applied to a plurality of data lines of the display panel based on the plurality of control signals and the data signal; and The scan driver is configured to generate a plurality of scan signals applied to a plurality of scan lines of the display panel based on the plurality of control signals.

20. A command processing device, comprising: an asynchronous FIFO circuit configured to receive a plurality of commands and a plurality of data from an external device and to separately store the plurality of commands and the plurality of data; a mode configuration circuit configured to set a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme, configured to set an access scheme for each of the plurality of commands to one of a first access scheme or a second access scheme different from the first access scheme, and configured to store a plurality of setting values, each of the plurality of setting values ​​indicating one of the first processing scheme or the second processing scheme and one of the first access scheme or the second access scheme; a controller configured to determine a command processing scheme for each of the plurality of commands and an access scheme for each of the plurality of commands based on a plurality of command identification IDs included in the plurality of commands and the plurality of setting values, a first processor configured to generate a first transaction by processing the first command among the plurality of commands based on the first processing scheme, based on the command processing scheme for the first command being determined as the first processing scheme; and a second processor configured to generate a first interrupt by processing the first command based on the second processing scheme based on the command processing scheme for the first command being determined as the second processing scheme, wherein, when the command processing scheme for the first command is determined to be the first processing scheme and the access scheme for the first command is determined to be the second access scheme, the first interrupt is additionally generated using the second processor, wherein the first processing scheme is a fixed command processing scheme executed depending on the structure of a plurality of logic circuits included in the first processor, and The second processing scheme is a configurable command processing scheme performed by executing a program code stored in a memory by a microcontroller unit included in the second processor.

Images