Emission gate driving circuit and driving method thereof, display panel and display device

Abstract

The present application discloses an emission gate drive circuit and its driving method, a display panel, and a display device, relating to the field of display technology. The circuit includes a signal input module and a signal output module, and the signal output module includes a first transistor, a second transistor, and a target transistor. The signal input module is configured to receive a high-level signal provided by a previous row signal line under the drive of a low-level signal provided by a first timing control line, and transmit the high-level signal to the gate terminal of the electrically connected first transistor and the gate terminal of the second transistor. When the first transistor and the second transistor maintain an off state under the high-level signal, the signal output module enables the target transistor to switch from an off state to an on state under the drive of a low-level signal provided by the gate signal line, thereby pulling down the low-level signal provided by the first level line to the current row signal line. The present application aims to optimize the design of the emission gate drive circuit to improve the display quality of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an emission gate drive circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] In the field of display technology, the emitter gate on array (Emit GOA) circuit is a core component for pixel driving and control. This means it's an integral part of the display panel and directly impacts image quality.

[0003] There is a special situation in the actual operation of the Emit GOA circuit. Since the current row signal line is electrically connected to the connection node of the two transistors, when both transistors are in the off state, the current row signal line will enter a suspended state. In the suspended state, the current row signal line is no longer effectively controlled by any transistor, which makes the current row signal line susceptible to external factors such as leakage and coupling effects between signals, so that the voltage on the current row signal line fluctuates and becomes very unstable, seriously affecting the luminous state of the display panel, resulting in abnormal display phenomena such as flickering and uneven brightness on the display panel.

[0004] Therefore, how to optimize the design of the Emit GOA circuit to improve the display quality of the display panel is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The main purpose of this application is to provide an emission gate drive circuit and a driving method thereof, a display panel and a display device, aiming to optimize the design of the Emit GOA circuit to improve the display quality of the display panel.

[0006] To achieve the above objectives, the present application provides an emission gate drive circuit, the emission gate drive circuit comprising:

[0007] a signal input module, wherein a signal access terminal of the signal input module is electrically connected to a previous row of signal lines, a signal control terminal of the signal input module is electrically connected to a first timing control line, and the signal input module is configured to receive a high-level signal provided by the previous row of signal lines under the drive of a low-level signal provided by the first timing control line;

[0008] A signal output module, the signal output module includes a first transistor, a second transistor and a target transistor, the signal output end of the signal input module is electrically connected to the gate end of the first transistor and the gate end of the second transistor respectively, the first path end of the first transistor is connected to a first level line, the second path end of the first transistor is connected to a connection node of the first path end of the second transistor and a current row signal line, the second path end of the second transistor is connected to a second level line, the first path end of the target transistor is electrically connected to the first level line, the second path end of the target transistor is electrically connected to the current row signal line, and the gate end of the target transistor is electrically connected to the gate signal line.

[0009] In one embodiment, the signal output module includes a third transistor and a first capacitor;

[0010] A first end of the first capacitor is electrically connected to the gate end of the first transistor and the signal output end of the signal input module respectively, and a second end of the first capacitor is electrically connected to the second timing control line;

[0011] The gate terminal of the third transistor is electrically connected to the signal output terminal of the signal input module, the first path terminal of the third transistor is connected to the second level line, and the second path terminal of the third transistor is electrically connected to the gate terminal of the second transistor.

[0012] In one embodiment, the emission gate driving circuit includes a first driving module and a second driving module;

[0013] The voltage input terminal of the first driving module is electrically connected to the signal output terminal of the signal input module, the driving control terminal of the first driving module is electrically connected to the connection intersection terminal of the second driving module, the first capacitor terminal of the first driving module is electrically connected to the gate terminal of the second transistor, and the second capacitor terminal of the first driving module is electrically connected to the second path terminal of the second transistor;

[0014] The driving control end of the second driving module is electrically connected to the signal output end of the signal input module.

[0015] In one embodiment, the first driving module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a second capacitor, and a third capacitor;

[0016] The gate terminal of the fourth transistor, the first path terminal of the fifth transistor and the gate terminal of the sixth transistor are electrically connected to the second timing control line respectively;

[0017] The first path end of the sixth transistor constitutes the voltage input end of the first driving module and is electrically connected to the signal output end of the signal input module. The second path end of the sixth transistor is electrically connected to the first path end of the seventh transistor. The second path end of the seventh transistor is electrically connected to the second level line. The gate ends of the seventh transistor are electrically connected to the gate end of the fifth transistor and the first end of the third capacitor, respectively.

[0018] The first end of the third capacitor constitutes the driving control end of the first driving module and is electrically connected to the connection intersection end of the second driving module, and the second end of the third capacitor is electrically connected to the second path end of the fifth transistor and the first path end of the fourth transistor respectively;

[0019] The first end of the second capacitor constitutes the first capacitor end of the first driving module and is electrically connected to the second path end of the fourth transistor and the gate end of the second transistor respectively;

[0020] The second end of the second capacitor constitutes the second capacitor end of the first driving module and is electrically connected to the second path end of the second transistor.

[0021] In one embodiment, the second driving module includes an eighth transistor and a ninth transistor;

[0022] The gate terminal of the eighth transistor constitutes the driving control terminal of the second driving module and is electrically connected to the signal output terminal of the signal input module;

[0023] The first pass terminal of the eighth transistor is electrically connected to the gate terminal of the ninth transistor, the first pass terminal of the ninth transistor is connected to the first level line, and the second pass terminal of the eighth transistor is electrically connected to the second pass terminal of the ninth transistor;

[0024] A connection node where the second path end of the eighth transistor is connected to the second path end of the ninth transistor constitutes a connection intersection end of the second driving module, and is electrically connected to the driving control end of the first driving module.

[0025] In one embodiment, the signal input module includes a tenth transistor;

[0026] The first path end of the tenth transistor constitutes the signal access end of the signal input module and is electrically connected to the previous row of signal lines;

[0027] The gate terminal of the tenth transistor constitutes the signal control terminal of the signal input module and is electrically connected to the first timing control line;

[0028] The second path end of the tenth transistor constitutes a signal output end of the signal input module and is electrically connected to the gate end of the first transistor and the gate end of the second transistor respectively.

[0029] In addition, to achieve the above-mentioned purpose, the present application also provides a driving method of an emission gate driving circuit, which is applied to the emission gate driving circuit described in any one of the above items, and the driving method includes:

[0030] When the first transistor and the second transistor in the signal output module maintain the off state under the high level signal output by the signal input module, the target transistor in the enable signal output module is switched from the off state to the on state under the driving of the low level signal provided by the gate signal line, so as to pull down the low level signal provided by the first level line to the current row signal line; wherein,

[0031] The high-level signal output by the signal input module is set to be provided by the previous row signal line to which the signal input module is connected under the drive of the low-level signal provided by the first timing control line.

[0032] In one embodiment, the driving method includes:

[0033] The emission gate drive circuit is enabled to perform drive control in a preset first drive stage, a second drive stage, a third drive stage, a fourth drive stage, a fifth drive stage, a sixth drive stage and a seventh drive stage in sequence; wherein,

[0034] The first driving stage is set such that the first timing control line, the previous row signal line, the current row signal line and the gate signal line all provide low-level signals, and the second timing control line provides a high-level signal;

[0035] The second driving stage is set as follows: the second timing control line, the previous row signal line, the current row signal line and the gate signal line all provide low-level signals, and the first timing control line provides a high-level signal;

[0036] The third driving stage is set as follows: the first timing control line, the current row signal line and the gate signal line all provide low-level signals, and the second timing control line and the previous row signal line all provide high-level signals;

[0037] The fourth driving stage is configured such that the second timing control line provides a low level signal, and the first timing control line, the previous row signal line, the current row signal line and the gate signal line all provide high level signals;

[0038] The fifth driving stage is configured such that the first timing control line provides a low level signal, and the second timing control line, the previous row signal line, the current row signal line and the gate signal line all provide high level signals;

[0039] The sixth driving stage is set to provide low-level signals to the second timing control line and the previous row signal line, and high-level signals to the first timing control line, the current row signal line and the gate signal line;

[0040] The seventh driving stage is set as follows: the first timing control line, the previous row signal line and the current row signal line all provide low-level signals, and the second timing control line and the gate signal line all provide high-level signals.

[0041] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the emission gate drive circuit described in any one of the above items.

[0042] In addition, to achieve the above-mentioned purpose, the present application further provides a display device, which includes the above-mentioned display panel; or,

[0043] The display device includes a processor, a memory, and a driver program stored in the memory and executable by the processor, wherein the driver program implements the steps of the above-mentioned driving method when executed by the processor.

[0044] The emission gate drive circuit set up in the present application only adds a target transistor in the signal output module, and electrically connects the first path end of the target transistor to the first level line, the second path end of the target transistor to the current row signal line, and the gate end of the target transistor to the gate signal line, thereby realizing the design of the optimized Emit GOA circuit, thereby effectively solving the floating phenomenon of the current row signal line when the first transistor and the second transistor are both in the cut-off state, and significantly improving the display quality of the display panel. Specifically, when the signal input module is driven by the low-level signal provided by the first timing control line to synchronously transmit the high-level signal provided by the previous row signal line to the gate end of the first transistor and the gate end of the second transistor in the signal output module, the first transistor and the second transistor always maintain the cut-off state under the action of the high-level signal. At this time, the target transistor is driven by the low-level signal provided by the gate signal line to switch from the cut-off state to the on state, thereby pulling down the stable low-level signal provided by the first level line to the current row signal line, thereby avoiding the current row signal line being susceptible to external interference due to the floating phenomenon and causing voltage fluctuations, ensuring the voltage stability of the current row signal line, and significantly improving the display quality of the display panel using the emission gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 This is a waveform diagram of the traditional Emit GOA circuit;

[0048] Figure 2 This is a signal waveform diagram of the Emit GOA circuit;

[0049] Figure 3 This is the schematic diagram of the Emit GOA circuit;

[0050] Figure 4 This is a structural block diagram of the first embodiment of the transmission gate drive circuit of the present application;

[0051] Figure 5 This is a circuit schematic diagram of the transmitting gate drive circuit of the present application;

[0052] Figure 6It is a waveform diagram of the transmitting gate drive circuit of the present application;

[0053] Figure 7 1. It is a circuit conduction diagram of the emission gate drive circuit in the first drive stage;

[0054] Figure 8 1. It is a schematic diagram of the circuit conduction of the emission gate drive circuit in the second drive stage;

[0055] Figure 9 1 is a schematic diagram of the circuit conduction of the emission gate drive circuit in the third drive stage;

[0056] Figure 10 1 is a schematic diagram of the circuit conduction of the emission gate drive circuit in the fourth drive stage;

[0057] Figure 11 1 is a schematic diagram of the circuit conduction of the emission gate drive circuit in the fifth drive stage;

[0058] Figure 12 1 is a schematic diagram of the circuit conduction of the emission gate drive circuit in the sixth drive stage;

[0059] Figure 13 1 is a schematic diagram of the conduction of the emission gate drive circuit in the seventh drive stage;

[0060] Figure 14 This is another circuit schematic diagram of the transmitting gate drive circuit of the present application;

[0061] Figure 15 This is a schematic diagram of the structure of the display device involved in the embodiment of the present application.

[0062] Description of Figure Numbers:

[0063] 10. Signal input module; 20. Signal output module; 30. First driving module; 40. Second driving module; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T10. Tenth transistor; Tn. Target transistor; EM(n-1), Previous row signal line; EM(n), Current row signal line; CK1, First timing control line; CK2, Second timing control line; B', Gate signal line; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; L, First level line; H, Second level line.

[0064] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0066] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0067] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0068] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0069] Reference Figure 1 , Figure 1 This is a waveform diagram of the traditional Emit GOA circuit. Figure 1 The dotted line portion shown represents the cut-off state of the transistor. At this time, the OLED (Organic Light Emitting Diode) device connected thereto does not emit light and is in a non-display state. Correspondingly, Figure 1 The solid line portion shown represents the on-state of the transistor, at which time the OLED device connected thereto emits light, realizing image display on the display panel. In other words, the conventional Emit GOA circuit can be operated as follows Figure 1 The signal waveform shown in the figure realizes the image display of the display panel. However, there is a special case in the actual operation of the Emit GOA circuit. Figure 2 The driving phase S3 shown, at this time Figure 3The two transistors T1 and T2 shown are both in the cut-off state. At this time, the current row signal line EM(n) will enter a suspended state, and in the suspended state, the current row signal line EM(n) is no longer effectively controlled by any transistor, which makes the current row signal line EM(n) susceptible to external factors, such as leakage and coupling effects between signals, so that the voltage on the current row signal line EM(n) fluctuates and becomes very unstable, seriously affecting the luminous state of the display panel, resulting in abnormal display phenomena such as flickering and uneven brightness on the display panel.

[0070] In addition, the width of the current row signal line EM(n) waveform is also one of the important factors affecting the OLED display quality. Figure 3 As shown in FIG, the width of the waveform of the current row signal line EM(n) is not only controlled by the first / second timing control lines CK1 / 2, but also affected by the waveform of the previous row signal line EM(n-1). This mutual influence mechanism ensures that the Emit GOA circuit can operate according to the predetermined timing. However, Figure 2 The driving stage S5 corresponds to the EM(n) storage capacitor reset stage, and the driving stage S6 corresponds to the EM(n) charging stage. If the voltage on the current row signal line EM(n) is unstable, the driving control from the driving stage S5 to the driving stage S6 will be disturbed, resulting in Figure 3 The storage capacitor C2 shown cannot be reset or charged correctly, thereby affecting the light-emitting state of the OLED pixel, further exacerbating the display abnormality problem, and seriously affecting the image quality and stability of the OLED display panel.

[0071] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art.

[0072] In order to solve the technical defects existing in the above content, the present application provides an emission gate drive circuit and a driving method thereof, a display panel and a display device.

[0073] The embodiment of the present application provides a transmission gate drive circuit, referring to Figure 4 As shown, Figure 4 This is a block diagram of the structure of the first embodiment of the transmission gate drive circuit of the present application. The transmission gate drive circuit includes:

[0074] A signal input module 10, wherein the signal access end of the signal input module 10 is electrically connected to the previous row signal line EM(n-1), and the signal control end of the signal input module 10 is electrically connected to the first timing control line CK1. The signal input module 10 is configured to access the high-level signal provided by the previous row signal line EM(n-1) under the drive of the low-level signal provided by the first timing control line CK1.

[0075] In this embodiment, referring to Figure 4 After the signal control end of the signal input module 10 is connected to the low-level signal provided by the first timing control line CK1, the signal input module 10 is switched from the off state to the on state under the drive of the low-level signal, so as to synchronously transmit the high-level signal provided by the previous row signal line EM(n-1) to the gate end of the first transistor T1 and the gate end of the second transistor T2 in the signal output module 20 through the signal output end of the signal input module 10, so as to ensure that the first transistor T1 and the second transistor T2 always maintain the off state under the action of the high-level signal.

[0076] It should be noted that the previous row of signal lines EM(n-1) can be understood as the previous row of signal lines of the current row of signal lines EM(n).

[0077] The signal output module 20 includes a first transistor T1, a second transistor T2, and a target transistor Tn. The signal output end of the signal input module 10 is electrically connected to the gate end of the first transistor T1 and the gate end of the second transistor T2, respectively. The first path end of the first transistor T1 is connected to the first level line L, the second path end of the first transistor T1 is connected to the connection node of the first path end of the second transistor T2 and the current row signal line EM(n), the second path end of the second transistor T2 is connected to the second level line H, the first path end of the target transistor Tn is electrically connected to the first level line L, the second path end of the target transistor Tn is electrically connected to the current row signal line EM(n), and the gate end of the target transistor Tn is electrically connected to the gate signal line B'.

[0078] In this embodiment, the signal output module 20 is configured to enable the target transistor Tn to switch from the off state to the on state under the drive of the low-level signal provided by the gate signal line B' when the first transistor T1 and the second transistor T2 maintain the off state under the high-level signal output by the signal input module 10, so as to pull down the low-level signal provided by the low-level line to the current row signal line EM(n). That is, after the gate end of the first transistor T1 and the gate end of the second transistor T2 receive the high-level signal provided by the previous row signal line EM(n-1) forwarded by the signal output end of the signal input module 10, the first transistor T1 and the second transistor T2 do not respond to the high-level signal, that is, at this time, the first transistor T1 and the second transistor T2 always maintain the off state. In order to avoid the current signal line electrically connected between the second channel end of the first transistor T1 and the first channel end of the second transistor T2 from being suspended in the off state of the first transistor T1 and the second transistor T2, the present application sets the first channel end of the target transistor Tn and the first level line L is electrically connected, the second path end of the target transistor Tn is electrically connected to the current row signal line EM(n), and the gate end of the target transistor Tn is electrically connected to the gate signal line B'. At this time, the target transistor Tn is switched from the off state to the on state under the drive of the low-level signal provided by the gate signal line B', thereby pulling down the stable low-level signal provided by the first level line L to the current row signal line EM(n), ensuring that the current row signal line EM(n) can continuously and stably provide a low-level voltage, avoiding the voltage fluctuation of the current row signal line EM(n) due to leakage and coupling effects between signals when it is suspended, thereby significantly improving the display quality of the display panel.

[0079] It should be noted that the first level line L can be understood as a low level line, and the second level line H can be understood as a high level line.

[0080] Further, in some feasible embodiments, referring to Figure 5 , Figure 5 This is a circuit schematic diagram of the transmit gate drive circuit of the present application. The signal output module 20 includes a third transistor T3 and a first capacitor C1. The first end of the first capacitor C1 is electrically connected to the gate end of the first transistor T1 and the signal output end of the signal input module 10, respectively. The second end of the first capacitor C1 is electrically connected to the second timing control line CK2. The gate end of the third transistor T3 is electrically connected to the signal output end of the signal input module 10. The first channel end of the third transistor T3 is connected to the second level line H. The second channel end of the third transistor T3 is electrically connected to the gate end of the second transistor T2.

[0081] In this embodiment, referring to Figures 5 and 6 , the emission gate drive circuit is provided with Figure 6 The first driving stage S1, the second driving stage S2, the third driving stage S3, the fourth driving stage S4, the fifth driving stage S5 and the sixth driving stage S6 are shown. In the first driving stage S1, since the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 provides a high-level signal. At this time, Figure 5 The third transistor T3 is shown switched from an off state to an on state.

[0082] In the second driving phase S2, since the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the first timing control line CK1 provides a high-level signal; Figure 5 The third transistor T3 shown is kept in the on state.

[0083] In the third driving stage S3, since the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 and the previous row signal line EM(n-1) all provide high-level signals; Figure 5 The third transistor T3 is shown switched from an on state to an off state.

[0084] In the fourth driving stage S4, since the second timing control line CK2 provides a low level signal, the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 The third transistor T3 shown is continuously maintained in the off state.

[0085] In the fifth driving stage S5, since the first timing control line CK1 provides a low level signal, the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 The third transistor T3 shown is continuously maintained in the off state.

[0086] In the sixth driving stage S6, since the second timing control line CK2 and the previous row signal line EM(n-1) all provide low-level signals, the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide high-level signals. Figure 5 The third transistor T3 shown is always kept in the off state.

[0087] In the seventh driving stage S7, since the first timing control line CK1, the previous row signal line EM(n-1) and the current row signal line EM(n) all provide low-level signals, the second timing control line CK2 and the gate signal line B' all provide high-level signals. Figure 5 The third transistor T3 is shown switched from an off state to an on state.

[0088] Furthermore, in some other feasible embodiments, referring to Figure 5 The transmitting gate driving circuit includes a first driving module 30 and a second driving module 40; the voltage input terminal of the first driving module 30 is electrically connected to the signal output terminal of the signal input module 10, the driving control terminal of the first driving module 30 is electrically connected to the connection intersection terminal of the second driving module 40, the first capacitor C1 terminal of the first driving module 30 is electrically connected to the gate terminal of the second transistor T2, and the second capacitor C2 terminal of the first driving module 30 is electrically connected to the second path terminal of the second transistor T2; the driving control terminal of the second driving module 40 is electrically connected to the signal output terminal of the signal input module 10.

[0089] Further, in some feasible embodiments, referring to Figure 5 The first driving module 30 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a second capacitor C2 and a third capacitor C3; the gate terminal of the fourth transistor T4, the first channel terminal of the fifth transistor T5 and the gate terminal of the sixth transistor T6 are respectively electrically connected to the second timing control line CK2; the first channel terminal of the sixth transistor T6 constitutes the voltage input terminal of the first driving module 30 and is electrically connected to the signal output terminal of the signal input module 10, the second channel terminal of the sixth transistor T6 is electrically connected to the first channel terminal of the seventh transistor T7, the second channel terminal of the seventh transistor T7 is electrically connected to the second level line H, and the gate terminals of the seven transistors are respectively electrically connected to the second timing control line CK2. The gate terminal of the fifth transistor T5 is electrically connected to the first terminal of the third capacitor C3; the first terminal of the third capacitor C3 constitutes the driving control terminal of the first driving module 30 and is electrically connected to the connection intersection terminal of the second driving module 40, and the second terminal of the third capacitor C3 is electrically connected to the second path terminal of the fifth transistor T5 and the first path terminal of the fourth transistor T4, respectively; the first terminal of the second capacitor C2 constitutes the first capacitor C1 terminal of the first driving module 30, and is electrically connected to the second path terminal of the fourth transistor T4 and the gate terminal of the second transistor T2, respectively; the second terminal of the second capacitor C2 constitutes the second capacitor C2 terminal of the first driving module 30 and is electrically connected to the second path terminal of the second transistor T2.

[0090] In this embodiment, referring to Figures 5 and 6In the first driving phase S1, since the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 provides a high-level signal. At this time, Figure 5 As shown, the fourth transistor T4 maintains the off state, the fifth transistor T5 switches from the off state to the on state, the sixth transistor T6 maintains the off state, and the seventh transistor T7 switches from the off state to the on state.

[0091] In the second driving phase S2, since the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the first timing control line CK1 provides a high-level signal; Figure 5 As shown, the fourth transistor T4 is switched from the off state to the on state, the fifth transistor T5 is switched from the on state to the off state, the sixth transistor T6 is switched from the off state to the on state, and the seventh transistor T7 is switched from the on state to the off state.

[0092] In the third driving stage S3, since the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 and the previous row signal line EM(n-1) all provide high-level signals; Figure 5 As shown, the fourth transistor T4 switches from the on state to the off state, the fifth transistor T5 switches from the off state to the on state, the sixth transistor T6 switches from the on state to the off state, and the seventh transistor T7 switches from the off state to the on state.

[0093] In the fourth driving stage S4, since the second timing control line CK2 provides a low level signal, the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 As shown, the fourth transistor T4 is switched from the off state to the on state, the fifth transistor T5 remains in the on state, the sixth transistor T6 is switched from the off state to the on state, and the seventh transistor T7 remains in the on state.

[0094] In the fifth driving stage S5, since the first timing control line CK1 provides a low level signal, the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 As shown, the fourth transistor T4 switches from the on state to the off state, the fifth transistor T5 remains in the on state, the sixth transistor T6 switches from the on state to the off state, and the seventh transistor T7 remains in the on state.

[0095] In the sixth driving stage S6, since the second timing control line CK2 and the previous row signal line EM(n-1) all provide low-level signals, the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide high-level signals. Figure 5 As shown, the fourth transistor T4 is switched from the off state to the on state, the fifth transistor T5 remains in the on state, the sixth transistor T6 is switched from the off state to the on state, and the seventh transistor T7 remains in the on state.

[0096] In the seventh driving stage S7, since the first timing control line CK1, the previous row signal line EM(n-1) and the current row signal line EM(n) all provide low-level signals, the second timing control line CK2 and the gate signal line B' all provide high-level signals. Figure 5 As shown, the fourth transistor T4 switches from the on state to the off state, the fifth transistor T5 remains in the on state, the sixth transistor T6 switches from the on state to the off state, and the seventh transistor T7 remains in the on state.

[0097] Furthermore, in some other feasible embodiments, referring to Figure 5 The second driving module 40 includes an eighth transistor T8 and a ninth transistor T9; the gate terminal of the eighth transistor T8 constitutes the driving control terminal of the second driving module 40 and is electrically connected to the signal output terminal of the signal input module 10; the first path terminal of the eighth transistor T8 is electrically connected to the gate terminal of the ninth transistor T9, the first path terminal of the ninth transistor T9 is connected to the first level line L, and the second path terminal of the eighth transistor T8 is electrically connected to the second path terminal of the ninth transistor T9; the connection node between the second path terminal of the eighth transistor T8 and the second path terminal of the ninth transistor T9 constitutes a connection intersection terminal of the second driving module 40 and is electrically connected to the driving control terminal of the first driving module 30.

[0098] In this embodiment, referring to Figures 5 and 6 In the first driving phase S1, since the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 provides a high-level signal. At this time, Figure 5 The eighth transistor T8 and the ninth transistor T9 are both switched from the off state to the on state.

[0099] In the second driving phase S2, since the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the first timing control line CK1 provides a high-level signal; Figure 5The eighth transistor T8 shown in the figure continuously maintains the on state, and the ninth transistor T9 switches from the on state to the off state.

[0100] In the third driving stage S3, since the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 and the previous row signal line EM(n-1) all provide high-level signals; Figure 5 The eighth transistor T8 is shown switched from the on state to the off state, and the ninth transistor T9 is switched from the off state to the on state.

[0101] In the fourth driving stage S4, since the second timing control line CK2 provides a low level signal, the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 The eighth transistor T8 shown in the figure continuously maintains the off state, and the ninth transistor T9 switches from the on state to the off state.

[0102] In the fifth driving stage S5, since the first timing control line CK1 provides a low level signal, the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 The eighth transistor T8 shown in the figure continuously maintains the off state, and the ninth transistor T9 switches from the off state to the on state.

[0103] In the sixth driving stage S6, since the second timing control line CK2 and the previous row signal line EM(n-1) all provide low-level signals, the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide high-level signals. Figure 5 The eighth transistor T8 shown in the figure continuously maintains the off state, and the ninth transistor T9 switches from the on state to the off state.

[0104] In the seventh driving stage S7, since the first timing control line CK1, the previous row signal line EM(n-1) and the current row signal line EM(n) all provide low-level signals, the second timing control line CK2 and the gate signal line B' all provide high-level signals. Figure 5 The eighth transistor T8 and the ninth transistor T9 are both switched from the off state to the on state.

[0105] Further, in some feasible embodiments, referring to Figure 5The signal input module 10 includes a tenth transistor T10; a first channel end of the tenth transistor T10 constitutes a signal access end of the signal input module 10 and is electrically connected to the previous row signal line EM(n-1); a gate end of the tenth transistor T10 constitutes a signal control end of the signal input module 10 and is electrically connected to the first timing control line CK1; a second channel end of the tenth transistor T10 constitutes a signal output end of the signal input module 10 and is electrically connected to the gate end of the first transistor T1 and the gate end of the second transistor T2, respectively.

[0106] In this embodiment, referring to Figures 5 and 6 In the first driving phase S1, since the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 provides a high-level signal. At this time, Figure 5 The tenth transistor T10 is shown switched from an off state to an on state.

[0107] In the second driving phase S2, since the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the first timing control line CK1 provides a high-level signal; Figure 5 The tenth transistor T10 is shown switched from an on state to an off state.

[0108] In the third driving stage S3, since the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide low-level signals, the second timing control line CK2 and the previous row signal line EM(n-1) all provide high-level signals; Figure 5 The tenth transistor T10 is shown switched from an off state to an on state.

[0109] In the fourth driving stage S4, since the second timing control line CK2 provides a low level signal, the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 The tenth transistor T10 is shown switched from an on state to an off state.

[0110] In the fifth driving stage S5, since the first timing control line CK1 provides a low level signal, the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high level signals. Figure 5 The tenth transistor T10 is shown switched from an off state to an on state.

[0111] In the sixth driving stage S6, since the second timing control line CK2 and the previous row signal line EM(n-1) all provide low-level signals, the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide high-level signals. Figure 5 The tenth transistor T10 is shown switched from an on state to an off state.

[0112] In the seventh driving stage S7, since the first timing control line CK1, the previous row signal line EM(n-1) and the current row signal line EM(n) all provide low-level signals, the second timing control line CK2 and the gate signal line B' all provide high-level signals. Figure 5 The tenth transistor T10 is shown switched from an off state to an on state.

[0113] It should be noted that Figure 5 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the target transistor Tn shown are all P-type thin-film transistors, and after the gate terminal of the P-type thin-film transistor is connected to a low-level signal, the P-type thin-film transistor switches from an off state to an on state.

[0114] In summary, the emission gate drive circuit set in the present application only adds a target transistor Tn in the signal output module 20, and electrically connects the first channel end of the target transistor Tn to the first level line L, the second channel end of the target transistor Tn is electrically connected to the current row signal line EM(n), and the gate end of the target transistor Tn is electrically connected to the gate signal line B', thereby realizing the design of the optimized Emit GOA circuit, thereby effectively solving the floating phenomenon of the current row signal line EM(n) when the first transistor T1 and the second transistor T2 are both in the cut-off state, and significantly improving the display quality of the display panel. Specifically, when the signal input module 10 is driven by the low-level signal provided by the first timing control line CK1 to synchronously transmit the high-level signal provided by the previous row signal line EM(n-1) to the gate end of the first transistor T1 and the gate end of the second transistor T2 in the signal output module 20, the first transistor T1 and the second transistor T2 are always maintained in the off state under the action of the high-level signal. At this time, the target transistor Tn is driven by the low-level signal provided by the gate signal line B' to switch from the off state to the on state, thereby pulling down the stable low-level signal provided by the first level line L to the current row signal line EM(n), thereby avoiding the current row signal line EM(n) from being susceptible to external interference due to the floating phenomenon and causing voltage fluctuations, ensuring the voltage stability of the current row signal line EM(n), and thus significantly improving the display quality of the display panel using the emission gate drive circuit.

[0115] Furthermore, based on the first embodiment of the emission gate driving circuit of the present application, a second embodiment of the driving method of the present application is proposed.

[0116] The driving method of the present application is applied to any of the above-mentioned emission gate driving circuits. The driving method of the present application is executed by a terminal device that drives and controls the emission gate driving circuit. The driving method of the present application includes the following implementation step S10.

[0117] Step S10: When the first transistor T1 and the second transistor T2 in the signal output module 20 maintain the cut-off state under the high-level signal output by the signal input module 10, the target transistor Tn in the enable signal output module 20 is switched from the cut-off state to the on state under the drive of the low-level signal provided by the gate signal line B', so as to pull down the low-level signal provided by the first level line L to the current row signal line EM(n); wherein, the high-level signal output by the signal input module 10 is set to be provided by the previous row signal line EM(n-1) connected to the signal input module 10 under the drive of the low-level signal provided by the first timing control line CK1.

[0118] In this embodiment, referring to Figure 4, after the signal control terminal of the signal input module 10 is connected to the low-level signal provided by the first timing control line CK1, the signal input module 10 is switched from the off state to the on state under the drive of the low-level signal, so as to synchronously transmit the high-level signal provided by the previous row signal line EM(n-1) to the gate terminal of the first transistor T1 and the gate terminal of the second transistor T2 in the signal output module 20 through the signal output terminal of the signal input module 10; after the gate terminal of the first transistor T1 and the gate terminal of the second transistor T2 receive the high-level signal provided by the previous row signal line EM(n-1) forwarded by the signal output terminal of the signal input module 10, the first transistor T1 and the second transistor T2 do not respond to the high-level signal, that is, at this time, the first transistor T1 and the second transistor T2 always maintain the off state, in order to avoid being electrically connected to the second path terminal of the first transistor T1 and the second The current signal line between the first channel end of the transistor T2 is suspended in the cut-off state of the first transistor T1 and the second transistor T2. Since the first channel end of the target transistor Tn is electrically connected to the first level line L, the second channel end of the target transistor Tn is electrically connected to the current row signal line EM(n), and the gate end of the target transistor Tn is electrically connected to the gate signal line B', at this time, the target transistor Tn is driven by the low-level signal provided by the gate signal line B' and switches from the cut-off state to the on state, thereby pulling down the stable low-level signal provided by the first level line L to the current row signal line EM(n), ensuring that the current row signal line EM(n) can continuously and stably provide a low-level voltage, avoiding voltage fluctuations of the current row signal line EM(n) due to leakage and coupling effects between signals when in the suspended state, thereby significantly improving the display quality of the display panel.

[0119] Furthermore, in some other feasible embodiments, the emission gate drive circuit is enabled to perform drive control in a preset first drive stage, a second drive stage, a third drive stage, a fourth drive stage, a fifth drive stage, a sixth drive stage and a seventh drive stage in sequence; wherein the first drive stage is set to the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, and the second timing control line CK2 provides a high-level signal; the second drive stage is set to the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, and the first timing control line CK1 provides a high-level signal; the third drive stage is set to the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide low-level signals, and the second timing control line CK2 and the previous row signal line EM(n-1) all provide high-level signals; The fourth driving stage is set to provide a low-level signal to the second timing control line CK2, and the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high-level signals; the fifth driving stage is set to provide a low-level signal to the first timing control line CK1, and the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide high-level signals; the sixth driving stage is set to provide a low-level signal to the second timing control line CK2 and the previous row signal line EM(n-1), and the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide high-level signals; the seventh driving stage is set to provide a low-level signal to the first timing control line CK1, the previous row signal line EM(n-1) and the current row signal line EM(n), and the second timing control line CK2 and the gate signal line B' all provide high-level signals.

[0120] In this embodiment, referring to Figure 6 , the first driving stage is set to the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, and the second timing control line CK2 provides a high-level signal; at this time, referring to Figure 7 , Figure 7 This is a schematic diagram of the conduction of the emission gate drive circuit in the first drive stage. Figure 7 The bold cross in the figure represents the cutoff state. Figure 7The symbol "L0" shown represents a low-level signal, and the symbol "H0" represents a high-level signal; at this time, when the emission gate drive circuit performs drive control in the first drive stage, the first transistor T1 and the target transistor Tn are both in the on state, and the second transistor T2 is in the off state. At this time, the low-level voltage output by the first level line L is provided from point A to the current row signal line EM(n) in two paths, wherein one of the two paths is the path from point A to the current row signal line EM(n) via the first transistor T1, and the other of the two paths is the path from point A to the current row signal line EM(n) via the second transistor T2, so as to ensure that a certain low-level voltage always exists on the current row signal line EM(n).

[0121] In another embodiment, referring to Figure 6 , the second driving stage is set to the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B' all provide low-level signals, and the first timing control line CK1 provides a high-level signal; at this time, referring to Figure 8 , Figure 8 This is a schematic diagram of the conduction of the emission gate drive circuit in the first drive stage. Figure 8 The bold cross in the figure represents the cutoff state. Figure 8 The symbol "L0" shown represents a low-level signal, and the symbol "H0" represents a high-level signal; at this time, when the emission gate drive circuit performs drive control in the second drive stage, the first transistor T1 and the target transistor Tn are both in the on state, and the second transistor T2 is in the off state. At this time, the low-level voltage output by the first level line L is provided from point A to the current row signal line EM(n) in two paths, wherein one of the two paths is the path from point A to the current row signal line EM(n) via the first transistor T1, and the other of the two paths is the path from point A to the current row signal line EM(n) via the second transistor T2, so as to ensure that a certain low-level voltage always exists on the current row signal line EM(n).

[0122] In yet another embodiment, referring to Figure 6 , the third driving stage is set to the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide low-level signals, and the second timing control line CK2 and the previous row signal line EM(n-1) all provide high-level signals; at this time, referring to Figure 9 , Figure 9 This is a schematic diagram of the conduction of the emission gate drive circuit in the third drive stage. Figure 9 The bold cross in the figure represents the cutoff state. Figure 9The symbol "L0" shown represents a low-level signal, and the symbol "H0" represents a high-level signal; at this time, when the emission gate drive circuit performs drive control in the third drive stage, the first transistor T1 and the second transistor T2 are both in the off state, and the target transistor Tn is in the on state; at this time, the low-level voltage output by the first level line L is provided from point A through the target transistor Tn to the current row signal line EM(n), so as to ensure that a certain low-level voltage always exists on the current row signal line EM(n).

[0123] In another embodiment, referring to Figure 6 , the fourth driving stage is set to provide a low-level signal to the second timing control line CK2, and the first timing control line CK1, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B'all provide high-level signals; at this time, referring to Figure 10 , Figure 10 This is a schematic diagram of the conduction of the emission gate drive circuit in the third drive stage. Figure 10 The bold cross in the figure represents the cutoff state. Figure 10 The symbol "L0" shown represents a low-level signal, and the symbol "H0" represents a high-level signal; when the emission gate drive circuit performs drive control in the fourth drive stage, the first transistor T1 and the target transistor Tn are both in the off state, and the second transistor T2 is in the on state; at this time, the high-level voltage output by the second level line H is provided from point C to the current row signal line EM(n) through the second transistor T2, so as to ensure that a certain high-level voltage always exists on the current row signal line EM(n).

[0124] In yet another embodiment, referring to Figure 6 , the fifth driving stage is set to provide a low-level signal to the first timing control line CK1, and a high-level signal to the second timing control line CK2, the previous row signal line EM(n-1), the current row signal line EM(n) and the gate signal line B'; at this time, referring to Figure 11 , Figure 11 This is a schematic diagram of the conduction of the emission gate drive circuit in the third drive stage. Figure 11 The bold cross in the figure represents the cutoff state. Figure 11 The symbol "L0" shown represents a low-level signal, and the symbol "H0" represents a high-level signal; when the emission gate drive circuit performs drive control in the fifth drive stage, the first transistor T1 and the target transistor Tn are both in the off state, and the second transistor T2 is in the on state; at this time, the high-level voltage output by the second level line H is provided from point C to the current row signal line EM(n) through the second transistor T2, so as to ensure that a certain high-level voltage always exists on the current row signal line EM(n).

[0125] In another embodiment, referring to Figure 6 , the sixth driving stage is set to the second timing control line CK2 and the previous row signal line EM(n-1) all provide low-level signals, the first timing control line CK1, the current row signal line EM(n) and the gate signal line B' all provide high-level signals; at this time, referring to Figure 12 , Figure 12 This is a schematic diagram of the conduction of the emission gate drive circuit in the third drive stage. Figure 12 The bold cross in the figure represents the cutoff state. Figure 12 The symbol "L0" shown represents a low-level signal, and the symbol "H0" represents a high-level signal; when the emission gate drive circuit performs drive control in the sixth drive stage, the first transistor T1 and the target transistor Tn are both in the off state, and the second transistor T2 is in the on state; at this time, the high-level voltage output by the second level line H is provided from point C to the current row signal line EM(n) through the second transistor T2, so as to ensure that a certain high-level voltage always exists on the current row signal line EM(n).

[0126] In another embodiment, the seventh driving stage is set to the first timing control line CK1, the previous row signal line EM(n-1) and the current row signal line EM(n) all provide low-level signals, and the second timing control line CK2 and the gate signal line B' all provide high-level signals. Figure 13 , Figure 13 This is a schematic diagram of the conduction of the emission gate drive circuit in the third drive stage. Figure 13 The bold cross in the figure represents the cutoff state. Figure 13 The symbol "L0" shown represents a low-level signal, and the symbol "H0" represents a high-level signal; when the emission gate drive circuit performs drive control in the seventh drive stage, the second transistor T2 and the target transistor Tn are both in the off state, and the first transistor T1 is in the on state; at this time, the high-level voltage output by the first level line L is provided from point A to the current row signal line EM(n) through the first transistor T1, so as to ensure that a certain low-level voltage always exists on the current row signal line EM(n).

[0127] For example, the emission gate drive circuit provided in the present application can also be as follows Figure 14 As shown, refer to Figure 14 If the gate terminal of the target transistor Tn is directly connected to the current row signal line EM(n), it can also avoid the voltage fluctuation phenomenon caused by the current row signal line EM(n) being susceptible to external interference due to the floating phenomenon, ensuring the voltage stability of the current row signal line EM(n), thereby significantly improving the display quality of the display panel using the emission gate drive circuit.

[0128] In addition, this application also provides a display device. Figure 15 , Figure 15 Schematic diagram of the structure of the display device involved in the embodiment of the present application. The display device of the embodiment of the present application can be a device for locally running the driving method.

[0129] like Figure 15 As shown, the display device of the embodiment of the present application may include: the above-mentioned emission gate drive circuit; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to implement connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0130] Memory 1005 is provided on the display device body and stores programs that, when executed by processor 1001, implement corresponding operations. Memory 1005 is also used to store parameters used by the display device. Memory 1005 can be high-speed RAM or non-volatile memory, such as disk storage. Memory 1005 can also optionally be a storage device independent of processor 1001.

[0131] Those skilled in the art will understand that Figure 15 The display device structure shown in the figure does not constitute a limitation on the display device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0132] like Figure 15 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a driver for a display device.

[0133] exist Figure 15 In the display device shown, the processor 1001 can be used to call the driver program of the display device stored in the memory 1005 and execute the steps of the driving method as described above.

[0134] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0135] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0136] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium such as ROM / RAM, magnetic disk, or optical disk as mentioned above, and includes a number of instructions for enabling a display device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0137] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An emission gate drive circuit, characterized in that: The emission gate drive circuit includes: a signal input module, wherein a signal access terminal of the signal input module is electrically connected to a previous row of signal lines, a signal control terminal of the signal input module is electrically connected to a first timing control line, and the signal input module is configured to receive a high-level signal provided by the previous row of signal lines under the drive of a low-level signal provided by the first timing control line; A signal output module, the signal output module includes a first transistor, a second transistor and a target transistor, the signal output end of the signal input module is electrically connected to the gate end of the first transistor and the gate end of the second transistor respectively, the first path end of the first transistor is connected to a first level line, the second path end of the first transistor is connected to a connection node of the first path end of the second transistor and a current row signal line, the second path end of the second transistor is connected to a second level line, the first path end of the target transistor is electrically connected to the first level line, the second path end of the target transistor is electrically connected to the current row signal line, and the gate end of the target transistor is electrically connected to the gate signal line.

2. The emission gate drive circuit according to claim 1, wherein: The signal output module includes a third transistor and a first capacitor; A first end of the first capacitor is electrically connected to the gate end of the first transistor and the signal output end of the signal input module respectively, and a second end of the first capacitor is electrically connected to the second timing control line; The gate terminal of the third transistor is electrically connected to the signal output terminal of the signal input module, the first path terminal of the third transistor is connected to the second level line, and the second path terminal of the third transistor is electrically connected to the gate terminal of the second transistor.

3. The emission gate driving circuit according to claim 1, wherein: The emission gate driving circuit includes a first driving module and a second driving module; The voltage input terminal of the first driving module is electrically connected to the signal output terminal of the signal input module, the driving control terminal of the first driving module is electrically connected to the connection intersection terminal of the second driving module, the first capacitor terminal of the first driving module is electrically connected to the gate terminal of the second transistor, and the second capacitor terminal of the first driving module is electrically connected to the second path terminal of the second transistor; The driving control end of the second driving module is electrically connected to the signal output end of the signal input module.

4. The emission gate driving circuit according to claim 3, wherein: The first driving module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a second capacitor and a third capacitor; The gate terminal of the fourth transistor, the first path terminal of the fifth transistor and the gate terminal of the sixth transistor are electrically connected to the second timing control line respectively; The first path end of the sixth transistor constitutes the voltage input end of the first driving module and is electrically connected to the signal output end of the signal input module. The second path end of the sixth transistor is electrically connected to the first path end of the seventh transistor. The second path end of the seventh transistor is electrically connected to the second level line. The gate ends of the seventh transistor are electrically connected to the gate end of the fifth transistor and the first end of the third capacitor, respectively. The first end of the third capacitor constitutes the driving control end of the first driving module and is electrically connected to the connection intersection end of the second driving module, and the second end of the third capacitor is electrically connected to the second path end of the fifth transistor and the first path end of the fourth transistor respectively; The first end of the second capacitor constitutes the first capacitor end of the first driving module and is electrically connected to the second path end of the fourth transistor and the gate end of the second transistor respectively; The second end of the second capacitor constitutes the second capacitor end of the first driving module and is electrically connected to the second path end of the second transistor.

5. The emission gate driving circuit according to claim 3, wherein: The second driving module includes an eighth transistor and a ninth transistor; The gate terminal of the eighth transistor constitutes the driving control terminal of the second driving module and is electrically connected to the signal output terminal of the signal input module; The first pass terminal of the eighth transistor is electrically connected to the gate terminal of the ninth transistor, the first pass terminal of the ninth transistor is connected to the first level line, and the second pass terminal of the eighth transistor is electrically connected to the second pass terminal of the ninth transistor; A connection node where the second path end of the eighth transistor is connected to the second path end of the ninth transistor constitutes a connection intersection end of the second driving module, and is electrically connected to the driving control end of the first driving module.

6. The emission gate driving circuit according to claim 1, wherein: The signal input module includes a tenth transistor; The first path end of the tenth transistor constitutes the signal access end of the signal input module and is electrically connected to the previous row of signal lines; The gate terminal of the tenth transistor constitutes the signal control terminal of the signal input module and is electrically connected to the first timing control line; The second path end of the tenth transistor constitutes a signal output end of the signal input module and is electrically connected to the gate end of the first transistor and the gate end of the second transistor respectively.

7. A driving method for an emission gate driving circuit, characterized in that: The driving method is applied to the emission gate driving circuit according to any one of claims 1 to 6, and the driving method includes: When the first transistor and the second transistor in the signal output module maintain the off state under the high level signal output by the signal input module, the target transistor in the enable signal output module is switched from the off state to the on state under the driving of the low level signal provided by the gate signal line, so as to pull down the low level signal provided by the first level line to the current row signal line; wherein, The high-level signal output by the signal input module is set to be provided by the previous row signal line to which the signal input module is connected under the drive of the low-level signal provided by the first timing control line.

8. The driving method according to claim 7, wherein: The driving method includes: The emission gate drive circuit is enabled to perform drive control in a preset first drive stage, a second drive stage, a third drive stage, a fourth drive stage, a fifth drive stage, a sixth drive stage and a seventh drive stage in sequence; wherein, The first driving stage is set such that the first timing control line, the previous row signal line, the current row signal line and the gate signal line all provide low-level signals, and the second timing control line provides a high-level signal; The second driving stage is set as follows: the second timing control line, the previous row signal line, the current row signal line and the gate signal line all provide low-level signals, and the first timing control line provides a high-level signal; The third driving stage is set as follows: the first timing control line, the current row signal line and the gate signal line all provide low-level signals, and the second timing control line and the previous row signal line all provide high-level signals; The fourth driving stage is configured such that the second timing control line provides a low level signal, and the first timing control line, the previous row signal line, the current row signal line and the gate signal line all provide high level signals; The fifth driving stage is configured such that the first timing control line provides a low level signal, and the second timing control line, the previous row signal line, the current row signal line and the gate signal line all provide high level signals; The sixth driving stage is set to provide low-level signals to the second timing control line and the previous row signal line, and high-level signals to the first timing control line, the current row signal line and the gate signal line; The seventh driving stage is set as follows: the first timing control line, the previous row signal line and the current row signal line all provide low-level signals, and the second timing control line and the gate signal line all provide high-level signals.

9. A display panel, characterized in that: The display panel includes a color filter substrate, a liquid crystal layer and an array substrate. The liquid crystal layer is provided between the array substrate and the color filter substrate. The array substrate includes the emission gate driving circuit according to any one of claims 1 to 6.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9; or The display device includes a processor, a memory, and a driver program stored in the memory and executable by the processor, wherein the driver program, when executed by the processor, implements the steps of the driving method according to any one of claims 7 to 8.

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