High-speed and high-precision memory data generation, detection and transmission method

Abstract

The invention provides a high-speed and high-precision memory data generation, detection and transmission method, and belongs to the technical field of memory data. Comprising the steps of data source generation based on a complex algorithm, multi-data source fusion, data preprocessing, data integrity detection, data accuracy detection, fault positioning detection, high-speed data transmission, signal integrity guarantee and data encryption transmission. In the aspect of data generation, a high-precision generation mechanism can reduce data errors and ensure the accuracy of initial data, and complex generation logic is beneficial to generation of diversified data types and meets the requirements of different application scenes. In the aspect of data detection, wrong data can be quickly positioned through a strict detection process, the reliability of the data is improved, and the probability that the wrong data flow into subsequent links is reduced. In the aspect of data transmission, the optimized transmission method can ensure high-speed and stable transmission of data, reduces transmission delay, ensures data integrity through complex logic, and does not distort data in long-distance transmission or complex network environment.

Description

Technical Field

[0001] The present invention relates to the field of memory data technology, and in particular to a high-speed and high-precision memory data generation, detection and transmission method. Background Art

[0002] The existing memory data generation, detection and transmission methods have the following problems:

[0003] Data generation:

[0004] Storage capacity limitation: Traditional memory, such as transistor-based storage cells, has limited storage capacity. For example, in flash memory, SLC, MLC, TLC, etc., the number of bits that can be expressed by each storage cell is limited by the number of floating gate layers, which makes it difficult to meet the growing data storage needs.

[0005] Energy consumption and heat dissipation during data generation: Traditional memory consumes a lot of energy and generates high heat during data generation, especially during data writing and erasing operations. This not only increases energy costs, but can also cause the device to overheat, affecting its performance and lifespan.

[0006] Data detection:

[0007] Limitations of detection tools: Different memory types and devices may require specific detection tools, and some detection tools may not be able to recognize or detect certain new types or special specifications of memory, resulting in the inability to accurately obtain memory status information.

[0008] False positive and false negative issues: Even if the appropriate detection tools are used, false positives or false negatives may occur. For example, the detection tool may mistakenly report a normal memory cell as faulty, or fail to detect an actual faulty cell, thus affecting the judgment of the memory reliability.

[0009] Difficulty in detection in complex environments: In some complex system environments, such as server clusters or embedded systems, accurate detection of memory problems becomes more difficult due to the interaction of multiple hardware components and software layers. For example, software compatibility issues and system resource conflicts may interfere with normal memory detection.

[0010] Potential failures are difficult to detect: Potential failures of some memories, such as performance degradation and weakened data retention due to long-term use, environmental factors, or manufacturing defects, may be difficult to detect in a timely manner during routine testing and may not be noticed until the failure actually occurs.

[0011] Data transmission:

[0012] Transmission speed bottleneck: With the continuous increase in data volume, traditional storage data transmission interfaces and protocols, such as USB and SATA, have gradually become data transmission bottlenecks and cannot meet the needs of high-speed data transmission. For example, when performing large-scale data backup or real-time data collection, slow transmission speeds will seriously affect work efficiency.

[0013] Data loss and errors during transmission: During data transmission, data loss or errors may occur due to various reasons, such as interference in the transmission line, loose interfaces, unstable power supply, etc. These problems are particularly common in mobile storage devices and network storage systems, and may cause damage to the integrity and availability of data.

[0014] Compatibility issues: There may be compatibility issues in data transmission between different storage devices, operating systems, and applications. For example, certain file system formats may not be read and written normally on different operating systems, or there may be incompatibility in data transmission protocols between different versions of software, resulting in data transmission failure.

[0015] Security issues: Data security is an important issue during data transmission. If data is not encrypted or other security measures are not taken, it may be stolen, tampered with or leaked during transmission, which may threaten the confidentiality and integrity of the data.

[0016] Therefore, there is an urgent need in the art for a high-speed and high-precision memory data generation, detection and transmission method.

[0017] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0018] The object of the present invention is to provide a high-speed and high-precision memory data generation, detection and transmission method.

[0019] To achieve the above object, the present invention provides the following solutions:

[0020] A high-speed and high-precision memory data generation, detection and transmission method, comprising:

[0021] A pseudo-random number generation algorithm is used, and the algorithm is started with a seed value. For each clock cycle, the algorithm is calculated according to the iterative formula to generate a number of pseudo-random numbers as initial data blocks;

[0022] The initial data block is converted into code, and an error correction coding method is adopted to map each k data symbols to n coding symbols, where n>k, so that error correction can be performed even if part of the data is damaged during data transmission; the selection of the coding generating polynomial g(x) is determined according to the characteristics of the memory and the error correction capability requirements, and a high-order g(x) is selected for a memory requiring high error correction capability;

[0023] Collect real-time data from external sensors, quantize and encode these sensor data, and fuse them with previous pseudo-random number data;

[0024] Before writing the data into the memory, the fused data is pre-emphasized;

[0025] When reading data from the memory, first perform a data integrity check; use the error correction code when writing to check; at the same time, use a cyclic redundancy check as an auxiliary check method, select a suitable cyclic redundancy check generator polynomial according to the size of the data block, calculate the cyclic redundancy check value and append it to the data block before writing the data to the memory, and recalculate the cyclic redundancy check value when reading the data and compare it with the stored cyclic redundancy check value;

[0026] Add a parity bit to the data block to detect whether there is an odd number of error bits in the data block;

[0027] Perform logical analysis on the read data. If the data is structured, check it according to predefined grammatical and semantic rules.

[0028] For numerical data, perform range checks and rationality analysis to determine the reasonable value range based on the physical meaning of the data. If the data exceeds this range, it may be that the data is wrong or the storage system is faulty.

[0029] If a data error is detected, fault location is performed, using built-in test circuits to determine where the error occurred;

[0030] The redundant structure of storage units is used for fault isolation. When a unit failure is detected, the data is transferred from the failed unit to the redundant unit by reconfiguring the memory mapping relationship, and the location of the failed unit is recorded for subsequent repair.

[0031] Using high-speed serial interface protocol, link initialization is performed before data transmission, including negotiation of link width and transmission rate;

[0032] Flow control based on data priority and type;

[0033] Use differential signal transmission for high-speed data transmission;

[0034] Terminate and match the transmission line to reduce signal reflection;

[0035] Before data is written to the memory, it is encrypted using the Advanced Encryption Standard algorithm. During data transmission, only the receiving end with the corresponding decryption key can decrypt the data, thus ensuring the security of the data during transmission.

[0036] Optionally, the error correction coding method includes:

[0037] Parity check codes, Hamming codes, cyclic redundancy check codes, and Reed-Solomon codes.

[0038] Optionally, the seed value includes:

[0039] A 128-bit binary number composed of multiple information such as the current system time and hardware serial number.

[0040] Optionally, the iterative formula of the algorithm includes:

[0041] The recursive formula in the Mersenne Twister algorithm: n+1 =(a×x n ) mod m, where a and m are algorithm-specific constants, and x n is the nth state value.

[0042] Optionally, the pre-emphasis processing on the fused data includes:

[0043] Standardization, normalization, missing value processing, outlier processing, data encoding and data enhancement.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] The present invention provides a high-speed and high-precision memory data generation, detection and transmission method, which can

[0046] Improve data transmission efficiency: By optimizing the transmission path, the overall time from data sampling to data reception on the software side can be reduced, thereby improving data transmission efficiency.

[0047] Enhanced data integrity: Error correction coding and verification mechanisms are used to detect and correct errors during data transmission to ensure data integrity.

[0048] Improve system reliability: Built-in test circuits and redundant structures can quickly locate and isolate faults, improving system reliability and fault tolerance.

[0049] Support high-speed and high-precision data processing: Through complex data generation and preprocessing steps, high-quality data can be generated to support high-speed and high-precision data analysis and processing.

[0050] Improve system performance: The use of high-speed serial interface protocol and differential signal transmission can increase data transmission rate and anti-interference ability, thereby improving the overall performance of the system.

[0051] Protect data security: Using encryption algorithms (such as AES) during transmission can protect data security and prevent data leakage and tampering. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0053] Figure 1 A schematic flow chart of a high-speed and high-precision memory data generation, detection and transmission method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The object of the present invention is to provide a high-speed and high-precision memory data generation, detection and transmission method.

[0056] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Embodiment 1:

[0058] This embodiment provides a high-speed and high-precision memory data generation, detection and transmission method, such as Figure 1 As shown, including:

[0059] Data generation sources based on complex algorithms:

[0060] First, a pseudo-random number generation algorithm (such as the Mersenne Twister algorithm) is used, which has a long cycle and good randomness. The algorithm is started with a very large seed value (for example, a 128-bit binary number composed of multiple information such as the current system time and the hardware serial number). For each clock cycle, the algorithm is calculated according to the iterative formula. For example, the recursive formula x in the Mersenne Twister algorithm is n+1 =(a×x n ) mod m, where a and m are algorithm-specific constants, and x n is the nth state value. Generate a series of pseudo-random numbers as the initial data block.

[0061] The initial data block is encoded and converted, and an error correction coding method similar to Reed-Solomon coding is adopted to map every k data symbols to n coding symbols, n>k. Even if some data is damaged during data transmission, error correction can be performed; the selection of the coding generating polynomial g(x) is determined according to the characteristics of the memory and the error correction capability requirements. For a memory requiring high error correction capability, a high-order g(x) is selected.

[0062] Fusion of multiple data sources:

[0063] In addition to the pseudo-random number generation source, other data sources are also introduced. For example, real-time data is collected from external sensors (such as temperature sensors, voltage sensors, etc.). These sensor data are quantized and encoded, and fused with the previous pseudo-random number data. The fusion method can be to add according to a certain weight or to interleave the data from different data sources to form the data to be written into the memory.

[0064] Data preprocessing:

[0065] Before writing the data to the memory, the fused data is pre-emphasized. Pre-emphasis is to compensate for high-frequency attenuation during high-speed signal transmission. It is implemented through a digital filter, and the filter coefficients are optimized according to the transmission line characteristics and data rate of the memory. For example, for a memory system with a data rate of 10Gbps, the filter coefficients are calculated based on the loss model of the transmission line so that the high-frequency components are appropriately boosted.

[0066] Data integrity check:

[0067] When reading data from the memory, the data integrity check is first performed. The error correction code used during writing is used for verification. For Reed-Solomon coding, the syndrome of the received data is calculated. If the syndrome is zero, it means that there is no error in the data; if the syndrome is not zero, it means that there is an error in the data during storage or transmission.

[0068] At the same time, a cyclic redundancy check (CRC) is used as an auxiliary verification method. According to the size of the data block, a suitable CRC generator polynomial is selected, such as CRC-32 (whose generator polynomial is x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1). The CRC value is calculated before the data is written to the memory and appended to the data block. When the data is read out, the CRC value is recalculated and compared with the stored CRC value.

[0069] Data accuracy check:

[0070] Perform logical analysis on the read data. If the data is structured data (such as instruction set, configuration data, etc.), check it according to predefined syntax and semantic rules. For example, if it is the instruction set data of the processor, check whether the opcode of the instruction is legal and whether the operand is within a reasonable range.

[0071] For numerical data, perform range checks and rationality analysis. Determine the reasonable value range based on the physical meaning of the data. For example, data representing temperature should be within a certain physical limit range (for example, -273.15°C to positive infinity, but in actual applications it may be between -50°C and 150°C). If the data exceeds this range, it may be that the data is wrong or the storage system is faulty.

[0072] Fault location detection:

[0073] If a data error is detected, fault location is required. A built-in self-test (BIST) circuit is used to determine the location of the error. The BIST circuit can test different memory cells, memory blocks, or data channels of the memory separately. For example, by sending specific test patterns (such as checkerboard patterns, all-0 or all-1 patterns, etc.) to different memory blocks, and then reading and analyzing the returned data, it is determined which memory block has a fault.

[0074] Fault isolation is performed using the redundant structure of storage units. Modern high-speed and high-precision memories usually have redundant storage units or storage blocks. When a storage unit failure is detected, the data can be transferred from the failed unit to the redundant unit by reconfiguring the memory mapping relationship, and the location of the failed unit is recorded for subsequent repair.

[0075] High-speed data transmission:

[0076] High-speed serial interface protocols are used, such as the PCI-Express (PCIe) protocol. Different versions of the PCIe protocol support different transfer rates, such as PCIe 5.0, which supports a transfer rate of 32GT / s (Gigatransfers per second) per channel. Before transmitting data, link initialization is required, including negotiation of link width (such as x1, x2, x4, etc. channel width), transfer rate and other parameters.

[0077] Traffic control is performed based on the priority and type of data. For example, data with high real-time requirements (such as control instructions) are given a higher priority and distinguished through the virtual channel (VC) mechanism in the PCIe protocol. Different VCs can set different quality of service (QoS) parameters to ensure timely transmission of important data.

[0078] Ensuring signal integrity:

[0079] During high-speed data transmission, the integrity of the signal must be ensured. Differential signal transmission methods such as low-voltage differential signaling (LVDS) are used. Differential signals can effectively resist external interference and improve the signal's anti-noise ability.

[0080] Terminate the transmission line to reduce signal reflection. Select the appropriate termination resistor according to the characteristic impedance of the transmission line (for example, the common 50Ω or 100Ω). For short-distance point-to-point transmission, source-end series termination can be used; for longer distance or multi-load transmission lines, terminal parallel termination or Thevenin equivalent termination may be required.

[0081] Data encryption transmission:

[0082] In order to ensure the security of data, encryption algorithms are used during the transmission process. For example, the Advanced Encryption Standard (AES) algorithm is used to encrypt data. Before the data is written to the memory, the data is encrypted using the AES encryption algorithm, and the encryption key can be a random key generated by a hardware security module (HSM). During the data transmission process, only the receiving end with the corresponding decryption key can decrypt the data, thereby ensuring the security of the data during the transmission process.

[0083] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0084] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A high-speed and high-precision memory data generation, detection and transmission method, characterized in that: include: A pseudo-random number generation algorithm is used, and the algorithm is started with a seed value. For each clock cycle, the algorithm is calculated according to the iterative formula to generate a number of pseudo-random numbers as initial data blocks; The initial data block is converted into code, and an error correction coding method is adopted to map each k data symbols to n coding symbols, where n>k, so that error correction can be performed even if part of the data is damaged during data transmission; the selection of the coding generating polynomial g(x) is determined according to the characteristics of the memory and the error correction capability requirements, and a high-order g(x) is selected for a memory requiring high error correction capability; Collect real-time data from external sensors, quantize and encode these sensor data, and fuse them with previous pseudo-random number data; Before writing the data into the memory, the fused data is pre-emphasized; When reading data from the memory, first perform a data integrity check; use the error correction code when writing to check; at the same time, use a cyclic redundancy check as an auxiliary check method, select a suitable cyclic redundancy check generator polynomial according to the size of the data block, calculate the cyclic redundancy check value and append it to the data block before writing the data to the memory, and recalculate the cyclic redundancy check value when reading the data and compare it with the stored cyclic redundancy check value; Add a parity bit to the data block to detect whether there is an odd number of error bits in the data block; Perform logical analysis on the read data. If the data is structured, check it according to predefined grammatical and semantic rules. For numerical data, perform range checks and rationality analysis to determine the reasonable value range based on the physical meaning of the data. If the data exceeds this range, it may be that the data is wrong or the storage system is faulty. If a data error is detected, fault location is performed, using built-in test circuits to determine where the error occurred; The redundant structure of storage units is used for fault isolation. When a unit failure is detected, the data is transferred from the failed unit to the redundant unit by reconfiguring the memory mapping relationship, and the location of the failed unit is recorded for subsequent repair. Using high-speed serial interface protocol, link initialization is performed before data transmission, including negotiation of link width and transmission rate; Flow control based on data priority and type; Use differential signal transmission for high-speed data transmission; Terminate and match the transmission line to reduce signal reflection; Before data is written to the memory, it is encrypted using the Advanced Encryption Standard algorithm. During data transmission, only the receiving end with the corresponding decryption key can decrypt the data, thus ensuring the security of the data during transmission.

2. The high-speed and high-precision memory data generation, detection and transmission method according to claim 1, characterized in that: The error correction coding method includes: Parity check codes, Hamming codes, cyclic redundancy check codes, and Reed-Solomon codes.

3. The high-speed and high-precision memory data generation, detection and transmission method according to claim 1, characterized in that: The seed values ​​include: A 128-bit binary number composed of multiple information such as the current system time and hardware serial number.

4. The high-speed and high-precision memory data generation, detection and transmission method according to claim 1, characterized in that: The iterative formula of the algorithm includes: The recursive formula in the Mersenne Twister algorithm: n+1 =(a×x n ) mod m, where a and m are algorithm-specific constants, and x n is the nth state value.

5. The high-speed and high-precision memory data generation, detection and transmission method according to claim 1, characterized in that: The pre-emphasis processing of the fused data includes: Standardization, normalization, missing value processing, outlier processing, data encoding and data enhancement.

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