Semiconductor packaging structure and manufacturing method thereof

Abstract

The invention provides a manufacturing method of a semiconductor packaging structure and the semiconductor packaging structure manufactured by the method. The manufacturing method of the semiconductor packaging structure comprises the following steps: providing a lower mold; arranging a plurality of semiconductor elements on the lower mold; arranging a plurality of first metal structures on the lower mold, wherein the first metal structures are positioned on two sides of the semiconductor elements; providing an upper mold which is jointed with the lower mold so as to accommodate the semiconductor elements and the first metal structures; filling a packaging material between the lower mold and the upper mold; and removing the upper mold, the lower mold and the first metal structures so as to form a plurality of through holes in the packaging material, and the through holes are located on the two sides of the semiconductor elements.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor package structure, and more particularly to a method for manufacturing a semiconductor package structure with a yield column and a semiconductor package structure manufactured by the method. Background Art

[0002] The current power modules formed with epoxy resins have the structural features of the products designed on the mold. However, for products with different structural features, different molds need to be designed accordingly, which means that the molds are not compatible in use, resulting in high mold manufacturing costs. Moreover, if you want to make products with more complex structural features, you will often be limited by the mold manufacturing process capabilities. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor packaging structure is provided, comprising: providing a lower mold; disposing a plurality of semiconductor elements on the lower mold; disposing a plurality of first metal structures on the lower mold, wherein the first metal structures are located on both sides of the semiconductor elements; providing an upper mold, which is engaged with the lower mold to accommodate the semiconductor elements and the first metal structures; filling a packaging material between the lower mold and the upper mold; and removing the upper mold, the lower mold, and the first metal structures to form a plurality of through holes in the packaging material, which are located on both sides of the semiconductor elements.

[0004] In some embodiments, the steps of disposing multiple semiconductor elements and multiple first metal structures on the lower mold include: providing a carrier; disposing a tape on the carrier; disposing the semiconductor elements and the first metal structures on the tape; and placing the carrier on the lower mold.

[0005] In some embodiments, the step of disposing a plurality of semiconductor elements on the lower mold includes: providing a carrier; disposing the semiconductor elements on the carrier; and transferring the semiconductor elements to the lower mold. In some embodiments, the method for manufacturing the semiconductor package structure also includes transferring the semiconductor elements to the lower mold by disposing a plurality of second metal structures on the lower mold. In some embodiments, the step of disposing a plurality of first metal structures on the lower mold includes: locking the first metal structures to the upper mold; and joining the upper mold and the lower mold.

[0006] In some embodiments, the method for manufacturing the semiconductor package structure further includes cutting the package material to form a plurality of semiconductor package structures, wherein each semiconductor package structure includes the semiconductor element, the package material covering the semiconductor element, and the through holes penetrating the package material. In some embodiments, in each semiconductor package structure, the package material has a first sidewall and a second sidewall, the second sidewall is opposite to the first sidewall, and the angle between the first sidewall and the second sidewall and a horizontal plane is 90 degrees.

[0007] According to an embodiment of the present disclosure, a semiconductor package structure is provided, which is manufactured by the above-mentioned method for manufacturing the semiconductor package structure.

[0008] In some embodiments, the packaging material has a first side wall and a second side wall, the second side wall is opposite to the first side wall, and an angle between the first side wall and the second side wall and a horizontal plane is 90 degrees.

[0009] In some embodiments, the semiconductor package structure further includes a plurality of positioning holes located on two sides of the semiconductor element, wherein the positioning holes are closer to the semiconductor element than the through holes.

[0010] In the present disclosure, when it is desired to produce products of different sizes or different structural features, it is not necessary to design different molds, that is, different products can share the same mold, and the required products can be produced only through the design of a detachable give-way column in the structure and the subsequent cutting process. Through the process technology disclosed in the present disclosure, the commonality of the mold can be increased, saving the cost of developing the mold. And because it is not necessary to design the structural features of the product on the mold, the structural strength of the mold is also improved, making the mold more tolerant. In addition, the present disclosure uses the cutting and molding technology after demoulding, which can easily produce products with vertical sides, overcoming the traditional process limitations. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are only used for illustration. In fact, the size of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present disclosure.

[0012] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0013] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0014] Figure 3A-3H is a cross-sectional schematic diagram of a method for manufacturing a semiconductor package structure according to an embodiment of the present disclosure; and

[0015] Figure 4A-4F The figure is a cross-sectional schematic diagram of a method for manufacturing a semiconductor package structure according to an embodiment of the present disclosure.

[0016] Description of Figure Numbers:

[0017] 10,100: Semiconductor structure with mold coating

[0018] 12,120: Lower mold

[0019] 14,140:Carrier board

[0020] 16: Tape

[0021] 18,180:Semiconductor components

[0022] 20,200: First Metal Structure

[0023] 22,200: Packaging materials

[0024] 22a, 220a: first side wall of packaging material

[0025] 22b, 220b: second side wall of packaging material

[0026] 24,240: Upper mold

[0027] 26,260:Substrate

[0028] 28,280: First metal layer

[0029] 30,300: Second metal layer

[0030] 32,320: Conductive element

[0031] 33,330: Chip

[0032] 34,340: Perforation

[0033] 36: First semiconductor package structure

[0034] 210: Second metal structure

[0035] 360: Second semiconductor package structure

[0036] 380: Positioning hole

[0037] P: Horizontal plane

[0038] α1, β1: The first angle between the first side wall of the packaging material and the horizontal plane

[0039] α2, β2: The second angle between the second side wall of the packaging material and the horizontal plane DETAILED DESCRIPTION

[0040] The following disclosure provides many different embodiments to implement the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosed embodiment describes a first characteristic component formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact.

[0041] It should be understood that additional operating steps may be implemented before, during or after the method, and in other embodiments of the method, some operating steps may be replaced or omitted.

[0042] In addition, spatially related words may be used, such as "below", "below", "lower", "above", "above", "higher" and similar words. These spatially related words are for the convenience of describing the relationship between one (some) element or feature component and another (some) element or feature component in the diagram. These spatially related words include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to different orientations (rotated 45 degrees or other orientations), the spatially related adjectives used therein will also be interpreted according to the orientation after the turning. In some embodiments of the present disclosure, terms such as "connect", "interconnect", etc. regarding joining and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures being arranged between the two structures. And the terms regarding joining and connection may also include situations where both structures are movable, or both structures are fixed.

[0043] In the specification, the terms "about", "approximately", "generally", "substantially", "same", and "similar" generally indicate that a characteristic value is within plus or minus 15%, or within plus or minus 10%, or within plus or minus 5%, or within plus or minus 3%, or within plus or minus 2%, or within plus or minus 1%, or within plus or minus 0.5% of a given value. The quantity given here is an approximate quantity, that is, in the absence of specific description of "about", "approximately", "generally", "substantially", the meaning of "about", "approximately", "generally", "substantially" can still be implied.

[0044] It should be understood that although the terms "first", "second", "third", etc. are used herein to describe different elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the technology disclosed herein, the first element, component, region, layer or section discussed below can be referred to as a second element, component, region, layer or section.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

[0046] See also Figure 1 According to one embodiment of the present disclosure, a semiconductor structure 10 including mold encapsulation is provided. Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor structure 10 including mold encapsulation.

[0047] like Figure 1 As shown, the semiconductor structure 10 with mold encapsulation includes a lower mold 12, a carrier 14, a tape 16, a plurality of semiconductor elements 18, a plurality of first metal structures 20, a packaging material 22, and an upper mold 24. The semiconductor element 18 is disposed on the lower mold 12. The carrier 14 is disposed between the lower mold 12 and the semiconductor element 18. The tape 16 is disposed between the carrier 14 and the semiconductor element 18. The first metal structure 20 is disposed on the lower mold 12 and is located on both sides of the semiconductor element 18. In more detail, the semiconductor element 18 and the first metal structure 20 are disposed on the tape 16 and contact the tape 16. The packaging material 22 is filled between the lower mold 12 and the upper mold 24. The first metal structure 20 penetrates the packaging material 22. The upper mold 24 is engaged with the lower mold 12 to accommodate the semiconductor element 18 and the first metal structure 20.

[0048] In some embodiments, the carrier 14 may include metal, but the disclosure is not limited thereto, and other suitable hard materials with heat resistance, pressure resistance and support properties are also applicable to the disclosure. In some embodiments, the tape 16 may include heat-resistant tape, but the disclosure is not limited thereto, and other suitable materials with heat resistance, pressure resistance and adhesion properties are also applicable to the disclosure.

[0049] In some embodiments, the semiconductor element 18 may include a power element, but the present disclosure is not limited thereto. In some embodiments, the semiconductor element 18 may include a substrate 26, a first metal layer 28, a second metal layer 30, a conductive element 32, and a chip 33. The first metal layer 28 and the second metal layer 30 are disposed on opposite sides of the substrate 26, the first metal layer 28 contacts the tape 16, the conductive element 32 is disposed on the second metal layer 30 and connected to an external circuit (not shown), and the chip 33 is disposed on the second metal layer 30, such as Figure 1 shown.

[0050] In some embodiments, the first metal structure 20 may include a columnar metal structure, for example, a cylindrical metal structure, but the present disclosure is not limited thereto, and other suitable three-dimensional shapes are also applicable to the present disclosure, and can be designed according to product requirements. In some embodiments, a plurality of first metal structures 20 may be included between adjacent semiconductor elements 18, for example, an even number of first metal structures 20 are provided between adjacent semiconductor elements 18, so that the semiconductor package structure formed after cutting has symmetrical through holes for subsequent screw locking, but the present disclosure is not limited thereto, and other suitable first metal structures 20 are also applicable to the present disclosure, and can be designed according to product requirements.

[0051] In some embodiments, the packaging material 22 may include solid molding material, liquid molding material, anisotropic conductive film (ACF), or sheet molding material, but the present disclosure is not limited thereto, and other suitable molding materials are also applicable to the present disclosure.

[0052] See also Figure 2 According to one embodiment of the present disclosure, a semiconductor structure 100 including mold encapsulation is provided. Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor structure 100 including mold encapsulation.

[0053] like Figure 2As shown, the semiconductor structure 100 with mold encapsulation includes a lower mold 120, a plurality of semiconductor devices 180, a plurality of first metal structures 200, a plurality of second metal structures 210, a packaging material 220, and an upper mold 240. The semiconductor device 180 is disposed on the lower mold 120. The first metal structure 200 is disposed on the lower mold 120 and is located on both sides of the semiconductor device 180. The second metal structure 210 is disposed on the lower mold 120 and is located on both sides of the semiconductor device 180. In more detail, the semiconductor device 180, the first metal structure 200, and the second metal structure 210 are disposed on the lower mold 120 and contact the lower mold 120, and the second metal structure 210 is closer to the semiconductor device 180 than the first metal structure 200. The packaging material 220 is filled between the lower mold 120 and the upper mold 240. The first metal structure 200 penetrates the packaging material 220. The upper mold 240 is coupled to the lower mold 120 to accommodate the semiconductor element 180 , the first metal structure 200 , and the second metal structure 210 .

[0054] In some embodiments, the semiconductor device 180 may include a power device, but the present disclosure is not limited thereto. In some embodiments, the device 180 may include a substrate 260, a first metal layer 280, a second metal layer 300, a conductive element 320, and a chip 330. The first metal layer 280 and the second metal layer 300 are disposed on opposite sides of the substrate 260, the first metal layer 280 contacts the lower mold 120, the conductive element 320 is disposed on the second metal layer 300 and connected to an external circuit (not shown), and the chip 330 is disposed on the second metal layer 300, as shown in FIG. Figure 2 shown.

[0055] In some embodiments, the first metal structure 200 may include a columnar metal structure, for example, a cylindrical metal structure, but the present disclosure is not limited thereto, and other suitable three-dimensional shapes are also applicable to the present disclosure, and can be designed according to product requirements. In some embodiments, a plurality of first metal structures 200 may be included between adjacent semiconductor elements 180, for example, an even number of first metal structures 200 are provided between adjacent semiconductor elements 180, so that the semiconductor package structure formed after cutting has symmetrical through holes for subsequent screw locking, but the present disclosure is not limited thereto, and other suitable first metal structures 200 are also applicable to the present disclosure, and can be designed according to product requirements.

[0056] In some embodiments, the second metal structure 210 may include a columnar metal structure, such as a cylindrical metal structure, but the present disclosure is not limited thereto, and other suitable three-dimensional shapes are also applicable to the present disclosure and can be designed according to product requirements. In the present disclosure, the second metal structure 210 is disposed at a specific position on the lower mold 120 as a positioning column for transferring the semiconductor element 180 to the lower mold 120, so that the semiconductor element 180 is smoothly disposed at a predetermined position on the lower mold 120.

[0057] In some embodiments, the packaging material 220 may include solid molding material, liquid molding material, anisotropic conductive film (ACF), or sheet molding material, but the present disclosure is not limited thereto, and other suitable molding materials are also applicable to the present disclosure.

[0058] See also Figure 3A-3H According to an embodiment of the present disclosure, a method for manufacturing a semiconductor package structure is provided. Figure 3A-3H A cross-sectional schematic diagram of a method for manufacturing a semiconductor packaging structure.

[0059] like Figure 3A As shown, a carrier board 14 is provided. An adhesive tape 16 is attached to the carrier board 14.

[0060] like Figure 3B As shown, a semiconductor element 18 is attached to the tape 16. The semiconductor element 18 includes a substrate 26, a first metal layer 28, a second metal layer 30, a conductive element 32, and a chip 33. The first metal layer 28 and the second metal layer 30 are disposed on opposite sides of the substrate 26, the first metal layer 28 contacts the tape 16, the conductive element 32 is disposed on the second metal layer 30 for subsequent connection to an external circuit, and the chip 33 is disposed on the second metal layer 30.

[0061] like Figure 3C As shown, a plurality of first metal structures 20 are attached to the tape 16, so that the first metal structures 20 are located on both sides of the semiconductor element 18. The position where the first metal structure 20 is attached to the tape 16 is the position where the through hole is formed later.

[0062] like Figure 3D As shown, a lower mold 12 is provided. A carrier 14 on which a tape 16 , a semiconductor element 18 , and a first metal structure 20 are disposed is placed on the lower mold 12 , that is, the semiconductor element 18 and the first metal structure 20 are disposed on the lower mold 12 .

[0063] like Figure 3EAs shown, an upper mold 24 is provided and joined with the lower mold 12 to accommodate the semiconductor device 18 and the first metal structure 20. After joining the upper mold 24 and the lower mold 12, the packaging material 22 is injected and filled between the lower mold 12 and the upper mold 24.

[0064] like Figure 3F As shown, after filling the packaging material 22 , the upper mold 24 , the lower mold 12 , the first metal structure 20 , the carrier 14 , and the tape 16 are removed to form a plurality of through holes 34 in the packaging material 22 , located on both sides of the semiconductor device 18 .

[0065] like Figure 3G As shown, the packaging material 22 is cut, for example, by laser cutting, to form a plurality of first semiconductor packaging structures 36. Each first semiconductor packaging structure 36 includes a semiconductor device 18, a packaging material 22 encapsulating the semiconductor device 18, and a through hole 34 penetrating the packaging material 22.

[0066] like Figure 3H As shown, in each first semiconductor package structure 36, the package material 22 has a first side wall 22a and a second side wall 22b, the second side wall 22b is opposite to the first side wall 22a, and the first side wall 22a and the second side wall 22b are respectively at an angle of 90 degrees with the horizontal plane P. For example, the first angle α1 between the first side wall 22a of the package material 22 and the horizontal plane P is 90 degrees, and the second angle α2 between the second side wall 22b of the package material 22 and the horizontal plane P is 90 degrees. At this point, the manufacturing of the semiconductor package structure disclosed in the present invention is completed.

[0067] See also Figure 4A-4F According to one embodiment of the present disclosure, a method for manufacturing a semiconductor package structure is provided. Figure 4A-4F A cross-sectional schematic diagram of a method for manufacturing a semiconductor packaging structure.

[0068] like Figure 4A As shown, a carrier 140 is provided. A semiconductor device 180 is disposed on the carrier 140. The semiconductor device 180 includes a substrate 260, a first metal layer 280, a second metal layer 300, a conductive element 320, and a chip 330. The first metal layer 280 and the second metal layer 300 are disposed on opposite sides of the substrate 260, the conductive element 320 is disposed on the second metal layer 300 for subsequent connection to an external circuit, and the chip 330 is disposed on the second metal layer 300.

[0069] like Figure 4BAs shown, a lower mold 120 is provided. A plurality of second metal structures 210 are disposed at specific positions on the lower mold 120 to serve as positioning posts for transferring the semiconductor element 180 on the carrier 140 to the lower mold 120. The semiconductor element 180 is transferred to the lower mold 120 by the second metal structures 210 disposed on the lower mold 120, so that the semiconductor element 180 is disposed at a predetermined position on the lower mold 120.

[0070] like Figure 4C As shown, an upper mold 240 is provided. The first metal structure 200 is locked to the upper mold 240. The upper mold 240 with the first metal structure 200 locked is joined to the lower mold 120 to accommodate the semiconductor element 180, the first metal structure 200, and the second metal structure 210. That is, the semiconductor element 180, the first metal structure 200, and the second metal structure 210 are arranged on the lower mold 120, wherein the first metal structure 200 and the second metal structure 210 are respectively located on both sides of the semiconductor element 180, and the second metal structure 210 is closer to the semiconductor element 180 than the first metal structure 200. The position of the first metal structure 200 is the position where the through hole is formed later. After the upper mold 240 and the lower mold 120 are joined, the packaging material 220 is injected and filled between the lower mold 120 and the upper mold 240.

[0071] like Figure 4D As shown, after filling the packaging material 220, the upper mold 240, the lower mold 120, the first metal structure 200, and the second metal structure 210 are removed to form a plurality of through holes 340 and a plurality of positioning holes 380 in the packaging material 220, wherein the through holes 340 and the positioning holes 380 are respectively located on both sides of the semiconductor element 180, wherein the positioning holes 380 are closer to the semiconductor element 180 than the through holes 340.

[0072] like Figure 4E As shown, the packaging material 220 is cut, for example, by laser cutting, to form a plurality of second semiconductor packaging structures 360. Each second semiconductor packaging structure 360 ​​includes a semiconductor element 180, a packaging material 220 covering the semiconductor element 180, a through hole 340 penetrating the packaging material 220, and a positioning hole 380 adjacent to the semiconductor element 180.

[0073] like Figure 4FAs shown, in each second semiconductor package structure 360, the package material 220 has a first side wall 220a and a second side wall 220b, the second side wall 220b is opposite to the first side wall 220a, and the first side wall 220a and the second side wall 220b respectively form an angle of 90 degrees with the horizontal plane P. For example, the first angle β1 between the first side wall 220a of the package material 220 and the horizontal plane P is 90 degrees, and the second angle β2 between the second side wall 220b of the package material 220 and the horizontal plane P is 90 degrees. At this point, the manufacturing of the semiconductor package structure disclosed in the present invention is completed.

[0074] In the present disclosure, when it is desired to produce products of different sizes or different structural features, it is not necessary to design different molds, that is, different products can share the same mold, and the required products can be produced only through the design of a detachable give-way column in the structure and the subsequent cutting process. Through the process technology disclosed in the present disclosure, the commonality of the mold can be increased, saving the cost of developing the mold. And because it is not necessary to design the structural features of the product on the mold, the structural strength of the mold is also improved, making the mold more tolerant. In addition, the present disclosure uses the cutting and molding technology after demoulding, which can easily produce products with vertical sides, overcoming the traditional process limitations.

[0075] The components of some of the above-mentioned embodiments are provided so that those skilled in the art to which the present disclosure belongs can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined by the scope of the appended claims. In addition, although the present disclosure has been disclosed as above with several preferred embodiments, it is not intended to limit the present disclosure.

[0076] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that may be realized using the present disclosure should or may be realized in any single embodiment of the present disclosure. Rather, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussion of features and advantages and similar language throughout this specification may, but does not necessarily, refer to the same embodiment.

[0077] Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner. Based on the description herein, one skilled in the relevant art will appreciate that the present disclosure may be implemented without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor packaging structure, comprising: Provide a lower mold; Disposing a plurality of semiconductor elements on the lower mold; Disposing a plurality of first metal structures on the lower mold, wherein the plurality of first metal structures are located on both sides of the plurality of semiconductor elements; Providing an upper mold, coupled with the lower mold, to accommodate the plurality of semiconductor elements and the plurality of first metal structures; Filling packaging material between the lower mold and the upper mold; as well as The upper mold, the lower mold, and the plurality of first metal structures are removed to form a plurality of through holes in the packaging material, which are located on both sides of the plurality of semiconductor elements.

2. The method for manufacturing a semiconductor package structure according to claim 1, wherein the step of disposing a plurality of semiconductor elements and a plurality of first metal structures on the lower mold comprises: Provide carrier board; Setting the adhesive tape on the carrier plate; Disposing the plurality of semiconductor elements and the plurality of first metal structures on the tape; as well as The carrier plate is placed on the lower mold.

3. The method for manufacturing a semiconductor package structure according to claim 1 , wherein the step of disposing a plurality of semiconductor elements on the lower mold comprises: Provide carrier board; Disposing the plurality of semiconductor components on the carrier; as well as The plurality of semiconductor elements are transferred to the lower mold. 4 . The method for manufacturing a semiconductor package structure according to claim 3 , further comprising transferring the plurality of semiconductor elements to the lower mold through a plurality of second metal structures disposed on the lower mold.

5. The method for manufacturing a semiconductor package structure according to claim 3, wherein the step of disposing a plurality of first metal structures on the lower mold comprises: Locking the plurality of first metal structures to the upper mold; as well as The upper mold and the lower mold are joined.

6. The method for manufacturing a semiconductor package structure according to claim 1, further comprising cutting the packaging material to form a plurality of semiconductor package structures, wherein each semiconductor package structure comprises the semiconductor element, the packaging material encapsulating the semiconductor element, and the plurality of through holes penetrating the packaging material.

7. The method for manufacturing a semiconductor package structure according to claim 6, wherein in each semiconductor package structure, the package material has a first side wall and a second side wall, the second side wall is opposite to the first side wall, and the angle between the first side wall and the second side wall and the horizontal plane is 90 degrees.

8. A semiconductor package structure manufactured by the method for manufacturing a semiconductor package structure according to claim 6. 9 . The semiconductor package structure according to claim 8 , wherein the package material has a first side wall and a second side wall, the second side wall is opposite to the first side wall, and an angle between the first side wall and the second side wall and a horizontal plane is 90 degrees.

10. The semiconductor package structure according to claim 8, further comprising a plurality of positioning holes located on both sides of the semiconductor element, wherein the plurality of positioning holes are closer to the semiconductor element than the plurality of through holes.

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