DC voltage conversion circuit and conversion method

Abstract

The invention provides a direct-current voltage conversion circuit and a conversion method, which can be applied to the technical field of voltage conversion. The circuit comprises a series-parallel switched capacitor current reduction module and a stacked switched capacitor module, wherein the series-parallel switched capacitor current-reducing module is electrically connected with the input power supply module, the series-parallel switched capacitor current-reducing module comprises a power inductor and N cascaded capacitor current-reducing units, and the series-parallel switched capacitor current-reducing module is used for regulating and controlling the potential difference between the two ends of the power inductor by controlling the charging and discharging states of the N capacitor current-reducing units. The inductance mean value current of the power inductor is reduced to the first current; the stacked switched capacitor module is electrically connected with the series-parallel switched capacitor current reduction module, the stacked switched capacitor module comprises M cascaded capacitor boosting units, and the stacked switched capacitor module is used for alternately controlling the charging and discharging states of the M capacitor boosting units based on the potential difference between the two ends of the power inductor and boosting the input voltage, and outputting the target voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage conversion, and more specifically to a direct current voltage conversion circuit and a conversion method. Background Art

[0002] Since the DC voltage conversion circuit can convert a small input voltage into a large output voltage, the DC voltage conversion circuit is widely used in the fields of diode driving, optical modules, and micro-robots. However, the existing DC voltage conversion circuit often requires the use of large-sized inductors to reduce inductor losses and the power conversion efficiency is low.

[0003] In the process of realizing the above-mentioned inventive concept, it was found through research that the voltage conversion of the existing DC voltage conversion circuit is relatively low and the power conversion efficiency is low. In addition, since the average current of the inductor and the voltage of the switch tube of the DC voltage conversion circuit are relatively high, it is necessary to use large-size, low-loss inductors and high-voltage-resistant switch tubes, which makes the power density of the DC voltage conversion circuit low and the cost high. Summary of the invention

[0004] In view of the above problems, the present invention provides a DC voltage conversion circuit and a conversion method.

[0005] According to a first aspect of the present invention, a DC voltage conversion circuit is provided, comprising: a series-parallel switched capacitor current reduction module and a stacked switched capacitor module; the series-parallel switched capacitor current reduction module is electrically connected to the input power supply module, the series-parallel switched capacitor current reduction module comprises a power inductor and N cascaded capacitor current reduction units, the series-parallel switched capacitor current reduction module is used to control the potential difference across the power inductor by controlling the charge and discharge states of the N capacitor current reduction units, so that the inductor mean current of the power inductor is reduced to a first current, N≥2, N is an integer; the stacked switched capacitor module is electrically connected to the series-parallel switched capacitor current reduction module, the stacked switched capacitor module comprises M cascaded capacitor boost units, the stacked switched capacitor module is used to alternately control the charge and discharge states of the M capacitor boost units based on the potential difference across the power inductor, boost the input voltage, and output a target voltage, M≥2, M is an integer.

[0006] According to an embodiment of the present invention, the cascaded N capacitor current reduction units include N-1 first capacitor shunt units and second capacitor shunt units; the first ends of the N-1 first capacitor shunt units are electrically connected to the input power supply module, and the second ends of the N-1 first capacitor shunt units are electrically connected to the first end of the second capacitor shunt unit; the second end of the second capacitor shunt unit is electrically connected to the first end of the power inductor, and the third end of the second capacitor shunt unit is electrically connected to the stacked switch capacitor module.

[0007] According to an embodiment of the present invention, the nth first capacitor shunt subunit among N-1 first capacitor shunt subunits includes a first switch, a second switch, a third switch and a first capacitor, 1≤n≤N-1; the first end of the first switch of the nth first capacitor shunt subunit is electrically connected to the first end of the first capacitor of the n+1th first capacitor shunt subunit, and the second end of the first switch is electrically connected to the second end of the first capacitor, wherein the first end of the N-1th first capacitor shunt subunit is electrically connected to the input power module; the first end of the second switch of the nth first capacitor shunt subunit is electrically connected to the input power module, and the second end of the second switch is electrically connected to the first end of the first capacitor; the first end of the third switch of the nth first capacitor shunt subunit is electrically connected to the second end of the first capacitor, and the second end of the third switch is grounded.

[0008] According to an embodiment of the present invention, the second capacitor shunt subunit includes a fourth switch, a fifth switch, a sixth switch and a second capacitor; the first end of the fourth switch of the second capacitor shunt subunit is electrically connected to the first end of the first capacitor in the first first capacitor shunt subunit, and the second end of the fourth switch is electrically connected to the second end of the second capacitor; the first end of the fifth switch of the second capacitor shunt subunit is electrically connected to the input power module, and the second end of the fifth switch is electrically connected to the first end of the second capacitor; the first end of the sixth switch of the second capacitor shunt subunit is electrically connected to the first end of the second capacitor, and the second end of the sixth switch is electrically connected to the stacked switch capacitor module; the first end of the second capacitor of the second capacitor shunt subunit is electrically connected to the second end of the fifth switch, and the second end of the second capacitor is electrically connected to the first end of the power inductor.

[0009] According to an embodiment of the present invention, the switching cycle of each switch includes a first time period and a second time period; in the first time period, N-1 first switches in the N-1 first capacitor shunt subunits are closed, N-1 second switches and N-1 third switches are opened, the fourth switch and the sixth switch of the second capacitor shunt subunit are closed, and the fifth switch is opened, so that the N-1 first capacitors are connected in series, and the second capacitor and the power inductor are connected in parallel. When the N-1 first capacitors are connected in series and the second capacitor and the power inductor are connected in parallel, the N-1 first capacitors are in a discharged state, and the voltage at the first end of the power inductor rises, so that the power inductor is in a magnetized state and the potential difference between the two ends of the power inductor is a positive number; in the second time period, the N-1 first capacitor shunt subunits are closed, and the N-1 second switches and the N-1 third switches of the second capacitor shunt subunits are closed, and the fourth switch and the sixth switch of the second capacitor shunt subunit are closed, and the fifth switch is opened, so that the N-1 first capacitors are connected in series, and the second capacitor and the power inductor are connected in parallel. The N-1 first switches in the subunit are disconnected, the N-1 second switches and the N-1 third switches are closed, the fourth switch and the sixth switch of the second capacitor shunt subunit are disconnected, and the fifth switch is closed, so that the N-1 first capacitors are connected in parallel, and the second capacitor and the power inductor are connected in series. When the N-1 first capacitors are connected in parallel and the second capacitor and the power inductor are connected in series, the N-1 first capacitors are in a charging state, and the voltage at the first end of the power inductor drops, so that the power inductor is in a demagnetized state and the potential difference across the power inductor is negative, wherein the first capacitor in the N-1 first capacitor shunt subunit is switched between the charging and discharging states in the first time period and the second time period, so that the inductor mean current of the power inductor is reduced to the first current.

[0010] According to an embodiment of the present invention, the cascaded M capacitor boosting units include a first capacitor boosting subunit and M-1 second capacitor boosting subunits; the first end of the first capacitor boosting unit is electrically connected to the series-parallel switching capacitor current reduction module, the second end of the first capacitor boosting unit is electrically connected to the first end of the M-1th second capacitor boosting subunit, and the third end of the first capacitor boosting unit is electrically connected to the power inductor; the first end of the mth second capacitor boosting subunit is electrically connected to the second end of the m+1th second capacitor boosting subunit, the second end of the mth second capacitor boosting subunit is electrically connected to the first end of the m-1th second capacitor boosting subunit, the third end of the mth second capacitor boosting subunit is grounded, and the fourth end of the mth second capacitor boosting subunit is electrically connected to the power inductor, wherein the first end of the M-1th second capacitor boosting subunit is electrically connected to the second end of the first capacitor boosting unit, and the second end of the first second capacitor boosting subunit is electrically connected to the output end, 2≤m≤M-1.

[0011] According to an embodiment of the present invention, the first capacitor boost subunit includes a seventh switch, an eighth switch and a third capacitor, and the mth second capacitor boost subunit includes a ninth switch, a tenth switch, a fourth capacitor and a fifth capacitor; the first end of the seventh switch of the first capacitor boost subunit is electrically connected to the series-parallel switch capacitor current reduction module, and the second end of the seventh switch is electrically connected to the first end of the third capacitor; the first end of the eighth switch of the first capacitor boost subunit is electrically connected to the first end of the third capacitor, and the second end of the eighth switch is electrically connected to the fourth capacitor of the M-1th second capacitor boost subunit; the second end of the third capacitor of the first capacitor boost subunit is electrically connected to the power inductor; the first end of the ninth switch in the mth second capacitor boost subunit is electrically connected to the first end of the fourth capacitor, and the second end of the ninth switch is electrically connected to the first end of the tenth switch; the first end of the tenth switch in the mth second capacitor boost subunit is electrically connected to the first end of the fifth capacitor, and the second end of the tenth switch is electrically connected to the first end of the ninth switch in the m-1th second capacitor boost subunit; the second end of the fourth capacitor in the mth second capacitor boost subunit is grounded, and the second end of the fifth capacitor is electrically connected to the power inductor.

[0012] According to an embodiment of the present invention, the circuit includes: in a first time period, the seventh switch in the first capacitor boost subunit is disconnected, the eighth switch is closed, the M-1 ninth switch in the M-1 second capacitor boost subunit is disconnected, the M-1 tenth switch is closed, the third capacitor in the first capacitor boost subunit is connected in series with the fourth capacitor in the M-1 second capacitor boost subunit, the fifth capacitor in the m-th second capacitor boost subunit is connected in series with the fourth capacitor in the m-1 second capacitor boost subunit, and the potential difference across the power inductor is a positive number, so that the third capacitor charges the fourth capacitor in the M-1 second capacitor boost subunit, and the fifth capacitor in the m-th second capacitor boost subunit charges the m-1 second capacitor boost subunit. The fourth capacitor in the unit is charged to facilitate boosting the input voltage and outputting the target voltage; in the second time period, the seventh switch in the first capacitor boosting subunit is closed, the eighth switch is opened, the M-1 ninth switches in the M-1 second capacitor boosting subunits are closed, and the M-1 tenth switches are opened, the third capacitor in the first capacitor boosting subunit is connected in parallel with the fourth capacitor and the fifth capacitor in the mth second capacitor boosting subunit, the fourth capacitor in the mth second capacitor boosting subunit is connected in series with the fifth capacitor in the mth second capacitor boosting subunit, and the potential difference across the power inductor is negative, so that the fourth capacitor in the mth second capacitor boosting subunit charges the fifth capacitor in the mth second capacitor boosting subunit.

[0013] According to an embodiment of the present invention, the circuit also includes a seventh capacitor; the first end of the seventh capacitor is electrically connected to the output end, and the second end of the seventh capacitor is grounded, and when the potential difference across the power inductor is positive, the fifth capacitor in the first second capacitor boosting subunit charges the seventh capacitor; when the potential difference across the power inductor is negative, the seventh capacitor discharges to the output end to maintain the target voltage.

[0014] The second aspect of the present invention provides a DC voltage conversion method, including: an input power supply module sends an input voltage to a series-parallel switch capacitor current reduction module; the series-parallel switch capacitor current reduction module boosts the input voltage to obtain a potential difference across a power inductor, wherein, in a first time period, the potential difference across the power inductor is a positive number, and in a second time period, the potential difference across the power inductor is a negative number; based on the potential difference across the power inductor, a stacked switch capacitor module is used to boost the input voltage to output a target voltage.

[0015] According to the DC voltage conversion circuit and conversion method of the present invention, a DC voltage conversion circuit is formed by using a series-parallel switch capacitor current reduction module and a stacked switch capacitor module, wherein the series-parallel switch capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units, and the stacked switch capacitor module includes M cascaded capacitor boost units. The circuit is powered by an input power supply module, and the charge and discharge states of the N capacitor current reduction units in the series-parallel switch capacitor current reduction module are controlled so that the voltage at the first end of the power inductor changes, thereby changing the charging and demagnetization state of the power inductor and regulating the positive and negative potential difference at both ends of the power inductor. In response to the positive and negative potential difference at both ends of the power inductor, the charge and discharge states of the M capacitor boost units are alternately controlled so that the voltage of each capacitor boost unit is stacked step by step, so as to achieve the effect of boosting the input voltage, obtain an output voltage that satisfies a high conversion ratio, and realize efficient amplification of the input voltage. In the case of a high voltage conversion ratio, the duty cycle of the circuit is reduced, thereby increasing the equivalent conduction time of the circuit and reducing the difficulty of circuit design, control and driving.

[0016] According to an embodiment of the present invention, further, by means of N capacitor current reduction units electrically connected to the power inductor, a current path other than the power inductor can be provided for the current, so that the power inductor does not need to bear all the input current and input charge of the input terminal, and the inductor mean current flowing through the power inductor in each switching cycle can be reduced, the conduction loss of the power inductor can be reduced, and the power conversion efficiency can be improved, so that a power inductor with a small size and a large on-resistance can be used in the DC voltage conversion circuit while maintaining a certain conduction loss of the inductor, so as to improve the power density of the DC voltage conversion circuit and reduce the circuit cost. Then, by alternately controlling the charge and discharge states of the M capacitor boost units cascaded in the stacked switch capacitor module, the withstand voltage value of the switch inside the M capacitor boost units can be reduced in the process of efficient voltage conversion, so that a switch with a low withstand voltage and a high quality factor can be used in the DC voltage conversion circuit, and the power-voltage conversion efficiency of the DC voltage conversion circuit can be further improved. At the same time, through the DC voltage conversion circuit of the present invention, even when achieving the same voltage conversion ratio, the present invention has a lower duty cycle, so that the equivalent conduction time of the circuit of the present invention is longer, making the circuit easier to control and drive. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0018] Figure 1 A schematic structural diagram of a DC voltage conversion circuit according to an embodiment of the present invention is shown.

[0019] Figure 2 A structural schematic diagram of a series-parallel switched capacitor current reduction module according to an embodiment of the present invention is shown.

[0020] Figure 3 A structural schematic diagram of an equivalent circuit of a stacked switch capacitor module in a second time period according to an embodiment of the present invention is shown.

[0021] Figure 4 A structural schematic diagram of an equivalent circuit of a stacked switched capacitor module in a first time period according to an embodiment of the present invention is shown.

[0022] Figure 5 A schematic structural diagram of a stacked switched capacitor module according to an embodiment of the present invention is shown.

[0023] Figure 6 A schematic structural diagram of a DC voltage conversion circuit including a seventh capacitor according to an embodiment of the present invention is shown.

[0024] Figure 7A schematic structural diagram of a DC voltage conversion circuit including a seventh capacitor is shown in the case of multiplexing the second capacitor current splitting subunit and the first capacitor voltage boosting subunit according to an embodiment of the present invention.

[0025] Figure 8 The structure diagram of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention is shown.

[0026] Fig. 9 The schematic diagram of the structure of the equivalent circuit of the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units in the first time period according to an embodiment of the present invention is shown.

[0027] Fig.10 A schematic structural diagram of an equivalent circuit of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units in a second time period according to an embodiment of the present invention is shown.

[0028] Fig.11 A schematic diagram showing the ratio of the inductor mean current to the input mean current of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention and a circuit in the prior art under a 2.5-5V voltage input and a 70V voltage output.

[0029] Fig.12 A schematic diagram shows the relationship between the voltage conversion ratio and the duty cycle obtained under 2.5-5V voltage input and 70V voltage output of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention and a circuit in the prior art.

[0030] Fig.13 The working state waveform diagram of the power inductor, the inductor current and the inductor voltage in multiple switching cycles of the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention is shown.

[0031] Fig.14 The schematic diagram of the structure of the whole circuit of the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention is shown.

[0032] Fig.15 A flow chart of a DC voltage conversion method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0033] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0034] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0035] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0036] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0037] In the technical solution of the present invention, the user information (including but not limited to user personal information, user image information, user device information, such as location information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved are all information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, invention and application of the relevant data comply with relevant laws, regulations and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0038] Since the DC voltage conversion circuit can convert a small input voltage into a large output voltage, the DC voltage conversion circuit is widely used in the fields of light-emitting diode driving, optical modules and micro-robots to provide high-voltage bias. Since the traditional boost DC-DC converter has the problems of low conversion efficiency, low power density and short conduction time, a hybrid topology DC-DC converter is proposed. The hybrid topology DC-DC converter reduces the withstand voltage of the switch tube and the mean current of the inductor by introducing a flying capacitor, so that a low withstand voltage switch tube with a high quality factor can be used and the dependence on large-sized high-performance inductors can be reduced.

[0039] However, the hybrid topology DC-DC converter with flying capacitors still has the technical problems of high inductor mean current and switch tube withstand voltage, and low power conversion efficiency. During the research and development process, it was found that the voltage conversion of the existing DC voltage conversion circuit is relatively low and the power conversion efficiency is poor. In addition, due to the high mean current of the inductor and the voltage of the switch tube in the DC voltage conversion circuit, it is necessary to use large-sized, low-loss inductors and high-voltage switch tubes, which makes the power density of the DC voltage conversion circuit low and the cost high.

[0040] In view of this, an embodiment of the present invention provides a DC voltage conversion circuit, including: a series-parallel switched capacitor current reduction module and a stacked switched capacitor module; wherein the series-parallel switched capacitor current reduction module is electrically connected to the input power supply module, the series-parallel switched capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units, the series-parallel switched capacitor current reduction module is used to control the potential difference across the power inductor by controlling the charge and discharge states of the N capacitor current reduction units, N≥2, N is an integer; the stacked switched capacitor module is electrically connected to the series-parallel switched capacitor current reduction module, the stacked switched capacitor module includes M cascaded capacitor boost units, the stacked switched capacitor module is used to alternately control the charge and discharge states of two adjacent capacitor boost units based on the potential difference across the power inductor, boost the input voltage, and output a target voltage, M≥2, M is an integer.

[0041] Figure 1 A schematic structural diagram of a DC voltage conversion circuit according to an embodiment of the present invention is shown.

[0042] like Figure 1 As shown, the DC voltage conversion circuit of this embodiment may include a series-parallel switch capacitor current reduction module 101 and a stacked switch capacitor module 102, V IN It can be the input voltage input by the input power module, V O Can be the output voltage.

[0043] According to an embodiment of the present invention, a series-parallel switched capacitor current reduction module 101 is electrically connected to an input power supply module, and the series-parallel switched capacitor current reduction module 101 includes a power inductor and N cascaded capacitor current reduction units. The series-parallel switched capacitor current reduction module 101 is used to control the potential difference across the power inductor by controlling the charging and discharging states of the N capacitor current reduction units so as to reduce the inductor mean current of the power inductor to a first current, where N≥2, and N is an integer.

[0044] According to an embodiment of the present invention, the first end of the cascaded N capacitor current reduction units is electrically connected to the input power module, the second end of the cascaded N capacitor current reduction units is electrically connected to the first end of the power inductor, and the second end of the power inductor is grounded.

[0045] According to an embodiment of the present invention, the capacitor current reduction unit can be characterized as a circuit unit for assisting in reducing the inductor mean current of the power inductor. The connection state between the circuit devices inside the series-parallel switch capacitor current reduction module 101 and the power inductor and the charge and discharge state of the N capacitor current reduction units can be switched by controlling multiple circuit switches inside the series-parallel switch capacitor current reduction module 101, so that the N capacitor current reduction units can replicate and multiply the charge flowing through the power inductor, and provide a current path other than the power inductor at the input end, so that the power inductor does not need to bear all the input current and input charge, thereby reducing the inductor mean current flowing through the power inductor in each switching cycle.

[0046] According to an embodiment of the present invention, further, by switching the connection state between the internal circuit devices of the N capacitor current reduction units and the power inductor and the charging and discharging state of the N capacitor current reduction units, the power inductor is switched between the magnetizing state and the demagnetizing state, thereby regulating the positive and negative potential difference across the power inductor.

[0047] According to an embodiment of the present invention, the stacked switched capacitor module 102 is electrically connected to the series-parallel switched capacitor current reduction module 101, and the stacked switched capacitor module 102 includes M cascaded capacitor boost units. The stacked switched capacitor module 102 is used to alternately control the charge and discharge states of the M capacitor boost units based on the potential difference across the power inductor, boost the input voltage, and output the target voltage, where M≥2, and M is an integer.

[0048] According to an embodiment of the present invention, the capacitor boost unit can be characterized as a circuit unit for boosting the input voltage. By alternately disconnecting the circuit components in the M capacitor boost units, the voltage value between the input end and the output end of the stacked switch capacitor module 102 can be evenly divided, so that the withstand voltage value of some circuit components in the M capacitor boost units is reduced.

[0049] According to an embodiment of the present invention, a DC voltage conversion circuit is formed by using a series-parallel switch capacitor current reduction module and a stacked switch capacitor module, wherein the series-parallel switch capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units, and the stacked switch capacitor module includes M cascaded capacitor boost units. The circuit is powered by an input power supply module to control the charge and discharge states of the N capacitor current reduction units in the series-parallel switch capacitor current reduction module, so that the voltage at the first end of the power inductor changes, thereby changing the charging and demagnetization state of the power inductor, and regulating the positive and negative potential difference at both ends of the power inductor. In response to the positive and negative potential difference at both ends of the power inductor, the charge and discharge states of the M capacitor boost units are alternately controlled so that the voltage of each capacitor boost unit is stacked step by step, so as to achieve the effect of boosting the input voltage, obtain an output voltage that satisfies a high conversion ratio, and realize efficient amplification of the input voltage. In the case of a high voltage conversion ratio, the duty cycle of the circuit is reduced, thereby increasing the equivalent conduction time of the circuit and reducing the difficulty of circuit design, control and driving.

[0050] According to an embodiment of the present invention, further, through the N capacitor current reduction units electrically connected to the power inductor, a current path other than the power inductor can be provided for the current, so that the power inductor does not need to bear all the input current and input charge of the input end, and the inductor mean current flowing through the power inductor in each switching cycle can be reduced, the conduction loss of the power inductor can be reduced, and the power conversion efficiency can be improved, so that a small-sized power inductor can be used in the DC voltage conversion circuit to improve the power density of the DC voltage conversion circuit and reduce the circuit cost. Then, by alternately controlling the charge and discharge state of the M capacitor boost units cascaded in the stacked switch capacitor module, the withstand voltage value of the circuit components inside the M capacitor boost units can be reduced in the process of efficient voltage conversion, so that a low withstand voltage and high quality factor switch can be used in the DC voltage conversion circuit, and the power voltage conversion efficiency of the DC voltage conversion circuit can be further improved. At the same time, through the DC voltage conversion circuit of the present invention, even when the same voltage conversion ratio is achieved, the present invention also has a lower duty cycle, so that the equivalent conduction time of the circuit of the present invention is longer, and the circuit is easier to control and drive.

[0051] According to an embodiment of the present invention, in a conversion cycle in which a DC voltage conversion circuit is used to increase and transform an input voltage, each conversion cycle may include a first time period and a second time period. By switching the working state of the circuit between the first time period and the second time period, the DC voltage conversion circuit completes the conversion of the input voltage to obtain a high-conversion output voltage.

[0052] According to an embodiment of the present invention, the cascaded N capacitor current reduction units include N-1 first capacitor current shunt sub-units and second capacitor current shunt sub-units.

[0053] According to an embodiment of the present invention, the first ends of N-1 first capacitor shunt subunits are electrically connected to the input power module, and the second ends of N-1 first capacitor shunt subunits are electrically connected to the first end of the second capacitor shunt subunit.

[0054] According to an embodiment of the present invention, the second end of the second capacitor shunt subunit is electrically connected to the first end of the power inductor, and the third end of the second capacitor shunt subunit is electrically connected to the stacked switch capacitor module.

[0055] According to an embodiment of the present invention, the cascaded N capacitor current reduction units can be characterized as a unit including N capacitors and 3N switches, the N-1 first capacitor shunt sub-units include N-1 capacitors and 3N-3 switches, and the second capacitor shunt sub-unit includes one capacitor and three switches.

[0056] According to an embodiment of the present invention, by setting N-1 first capacitor shunt sub-units and second capacitor shunt sub-units, the N-1 first capacitor shunt sub-units can be used to replicate or multiply the charge flowing through the inductor under different charging and discharging states, thereby providing a current path other than the inductor for the inductor at the input end, thereby reducing the average inductor current flowing through the inductor within one cycle, so that a small-sized inductor with a large conduction loss characteristic (large on-resistance) can be used, so as to improve the power density and power conversion efficiency of the circuit while achieving the target conversion ratio.

[0057] According to an embodiment of the present invention, the cascaded N capacitor current reduction units may include 3N switches and N capacitors.

[0058] According to an embodiment of the present invention, an nth first capacitor shunt subunit among N-1 first capacitor shunt subunits includes a first switch, a second switch, a third switch and a first capacitor, and n≥1.

[0059] According to an embodiment of the present invention, the first end of the first switch of the nth first capacitor shunt subunit is electrically connected to the first end of the first capacitor of the n+1th first capacitor shunt subunit, and the second end of the first switch is electrically connected to the second end of the first capacitor, wherein the first end of the first switch of the N-1th first capacitor shunt subunit is electrically connected to the input power supply module.

[0060] According to an embodiment of the present invention, a first end of the second switch of the nth first capacitor shunt subunit is electrically connected to the input power module, and a second end of the second switch is electrically connected to the first end of the first capacitor.

[0061] According to an embodiment of the present invention, a first end of the third switch of the nth first capacitor shunt subunit is electrically connected to a second end of the first capacitor, and a second end of the third switch is grounded.

[0062] According to an embodiment of the present invention, the second capacitor shunt subunit includes a fourth switch, a fifth switch, a sixth switch and a second capacitor.

[0063] According to an embodiment of the present invention, a first end of the fourth switch of the second capacitor shunt subunit is electrically connected to a first end of the first capacitor in the first first capacitor shunt subunit, and a second end of the fourth switch is electrically connected to a second end of the second capacitor.

[0064] According to an embodiment of the present invention, a first end of the fifth switch of the second capacitor shunt subunit is electrically connected to the input power module, and a second end of the fifth switch is electrically connected to a first end of the second capacitor.

[0065] According to an embodiment of the present invention, a first end of the sixth switch of the second capacitor shunt subunit is electrically connected to a first end of the second capacitor, and a second end of the sixth switch is electrically connected to the stacked switch capacitor module.

[0066] According to an embodiment of the present invention, a first end of the second capacitor of the second capacitor shunt subunit is electrically connected to a second end of the fifth switch, and a second end of the second capacitor is electrically connected to a first end of the power inductor.

[0067] Figure 2 A structural schematic diagram of a series-parallel switched capacitor current reduction module according to an embodiment of the present invention is shown.

[0068] like Figure 2 As shown, the series-parallel switch capacitor current reduction module includes N-1 first capacitor shunt subunit 201, second capacitor shunt subunit 202 and power inductor L, N-1 first capacitor shunt subunit 201 includes 3N-3 switches and N-1 capacitors, and the second capacitor shunt subunit 202 includes 3 switches and 1 capacitor. The negative electrode of the input power module is grounded GND, and the positive electrode of the input power module is connected to the first switch S of the N-1 first capacitor shunt subunit. 3N-2 and the second switch S 3N-1 The first end of the N-1th first capacitor shunt subunit is electrically connected to the first switch S 3N-2 The second end of the first capacitor C of the N-1th first capacitor shunt subunit FN The second end of the N-1th first capacitor shunt subunit is electrically connected to the second switch S 3N-1 The second end of the first capacitor C of the N-1th first capacitor shunt subunit FN The first end of the N-1th first capacitor shunt subunit is electrically connected to the first capacitor C FN The second end of the first capacitor shunt subunit is connected to the third switch S 3N The first end of the N-1th first capacitor shunt subunit is electrically connected to the third switch S 3N The second end is grounded GND.

[0069] According to an embodiment of the present invention, based on the above connection method, the N-2 th to the 3 rd first capacitor shunt subunits are all connected in the same way as the N-1 th first capacitor shunt subunit.

[0070] According to an embodiment of the present invention, the first switch S7 of the second first capacitor shunt subunit and the first capacitor C of the third first capacitor shunt subunit F4 The first end of the first switch S7 of the second first capacitor shunt subunit is electrically connected to the first capacitor C of the second first capacitor shunt subunit. F3 The second end of the second switch S8 of the second first capacitor shunt subunit is electrically connected to the positive electrode of the input power module, and the second end of the second switch S8 of the second first capacitor shunt subunit is electrically connected to the first capacitor C of the second first capacitor shunt subunit. F3 The first end of the first capacitor shunt subunit is electrically connected to the first capacitor C F3 The second end of is electrically connected to the first end of the third switch S9 of the second first capacitor shunt subunit, and the second end of the third switch S9 of the second first capacitor shunt subunit is grounded.

[0071] According to an embodiment of the present invention, the first switch S4 of the first first capacitor shunt subunit and the first capacitor C of the second first capacitor shunt subunit F3 The first end of the first switch S4 of the first first capacitor shunt subunit is electrically connected to the first capacitor C of the first first capacitor shunt subunit. F2 The first end of the second switch S5 of the first first capacitor shunt subunit is electrically connected to the positive electrode of the input power module, and the second end of the second switch S5 of the first first capacitor shunt subunit is electrically connected to the first capacitor C of the first first capacitor shunt subunit. F2 The first end of the first capacitor shunt subunit is electrically connected to the first capacitor C F2 The second end of is electrically connected to the first end of the third switch S6 of the first first capacitor shunt subunit, and the second end of the third switch S6 of the first first capacitor shunt subunit is grounded.

[0072] According to an embodiment of the present invention, the first end of the fourth switch S1 of the second capacitor shunt subunit 202 is connected to the first capacitor C of the first first capacitor shunt subunit. F2 The first end of the fourth switch S1 of the second capacitor shunt subunit 202 is electrically connected to the second capacitor C of the second capacitor shunt subunit 202. F1 The second end of the fifth switch S2 is electrically connected to the positive electrode of the input power module, the second end of the fifth switch S2 is electrically connected to the second capacitor C F1The first end of the sixth switch S3 is electrically connected to the second capacitor C F1 The first end of the sixth switch S3 is electrically connected to the stacked switch capacitor module, the second end of the second capacitor C F1 The second end of is electrically connected to the first end of the power inductor L, and the second end of the power inductor L is grounded.

[0073] According to an embodiment of the present invention, in a conversion cycle in which a DC voltage conversion circuit is used to increase the input voltage, each conversion cycle and switching cycle may include a first time period and a second time period. By switching the working state of the circuit between the first time period and the second time period, the DC voltage conversion circuit completes the conversion of the input voltage to obtain a high-conversion output voltage.

[0074] According to an embodiment of the present invention, in a first time period, N-1 first switches in N-1 first capacitor shunt subunits are closed, N-1 second switches and N-1 third switches are opened, the fourth switch and the sixth switch of the second capacitor shunt subunit are closed, and the fifth switch is opened, so that the N-1 first capacitors are connected in series and the second capacitor and the power inductor are connected in parallel. When the N-1 first capacitors are connected in series and the second capacitor and the power inductor are connected in parallel, the N-1 first capacitors are in a discharged state, and the voltage at the first end of the power inductor rises, so that the power inductor is in a magnetized state and the potential difference across the power inductor is a positive number.

[0075] According to an embodiment of the present invention, in the first time period, N-1 first capacitors in the N-1 first capacitor shunt subunits are connected in series with the combination of the second capacitor and the power inductor in parallel, and the N-1 first capacitors and the second capacitors are both in a discharge state. The N-1 first capacitors are used to discharge the charges accumulated in the second time period to the power inductor in the first time period, so that the power inductor is in a magnetized state, and the voltage at the first end of the power inductor increases to N V IN , and thus the potential difference across the power inductor is a positive number. In combination with the second time period, N-1 first capacitors are connected in parallel with the power inductor, and the second capacitor helps the power inductor share the charge to reduce the current flowing through the power inductor, thereby achieving the effect of reducing the average inductor current of the power inductor in one cycle. At the same time, the N-1 first capacitors can also discharge the charge accumulated in the second time period to the second capacitor in the first time period, and jointly transfer and output the charge to the stacked switch capacitor module in combination with the second capacitor in the discharge state.

[0076] According to an embodiment of the present invention, in the second time period, N-1 first switches in the N-1 first capacitor shunt subunits are disconnected, N-1 second switches and N-1 third switches are closed, the fourth switch and the sixth switch of the second capacitor shunt subunit are disconnected, and the fifth switch is closed, so that the N-1 first capacitors are connected in parallel, and the second capacitor and the power inductor are connected in series. When the N-1 first capacitors are connected in parallel and the second capacitor and the power inductor are connected in series, the N-1 first capacitors are in a charging state, and the voltage at the first end of the power inductor drops, so that the power inductor is in a demagnetized state and the potential difference across the power inductor is negative, wherein the first capacitor in the N-1 first capacitor shunt subunits switches the charging and discharging states in the first time period and the second time period, so that the inductor mean current of the power inductor is reduced to the first current.

[0077] According to an embodiment of the present invention, in the second time period, N-1 first capacitors in the N-1 first capacitor shunt sub-units are connected in parallel with a combination of a second capacitor and a power inductor in parallel, and both the N-1 first capacitors and the second capacitors are in a charging state. The N-1 first capacitors are used to accumulate charge in the second time period so as to discharge in the first time period. The potential difference across the power inductor is negative, and the power inductor is in a demagnetized state. Moreover, since the N-1 first capacitors are all connected in parallel with the power inductor, the charge flowing through the power inductor is reduced, thereby achieving the effect of reducing the mean inductor current of the power inductor within one cycle.

[0078] Figure 3 A structural schematic diagram of an equivalent circuit of a series-parallel switched capacitor current reduction module in a second time period according to an embodiment of the present invention is shown.

[0079] like Figure 3 As shown, the series-parallel switch capacitor current reduction module includes N-1 first capacitor shunt subunit 201, second capacitor shunt subunit 202 and power inductor L, N-1 first capacitor shunt subunit 201 includes 3N-3 switches and N-1 capacitors, and the second capacitor shunt subunit 202 includes 3 switches and 1 capacitor. In the second period, the N-1 first switches are disconnected, the N-1 second switches and the N-1 third switches are closed, the fourth switch and the sixth switch are disconnected, the fifth switch is closed, and the first capacitor C FN 、···First capacitor C F3 , the first capacitor C F2 With the second capacitor C F1 Connect in parallel with the power inductor L, input power V IN Power the capacitor and inductor, the first capacitor C in parallel FN 、···First capacitor C F3 , the first capacitor C F2 The accumulated charge in the second period is equal, that is, Q F2 = Q F3=···= Q FN , the second capacitor C F1 The accumulated charge is equal to the charge released by the power inductor L, both are third charges. The third charge can be expressed according to formula (1).

[0080] Q L2 =I LA (1-D)T (1);

[0081] Among them, Q L2 It can be characterized as the third charge, that is, the charge flowing through the power inductor L during the second period, I LA It can be represented by the current of the power inductor L in the first time period, D can be represented by the duty cycle, and T can be represented by the period.

[0082] Figure 4 A structural schematic diagram of an equivalent circuit of a series-parallel switched capacitor current reduction module in a first time period according to an embodiment of the present invention is shown.

[0083] like Figure 4 As shown, the series-parallel switch capacitor current reduction module includes N-1 first capacitor shunt subunit 201, second capacitor shunt subunit 202 and power inductor L, N-1 first capacitor shunt subunit 201 includes 3N-3 switches and N-1 capacitors, and the second capacitor shunt subunit 202 includes 3 switches and 1 capacitor. In the first period, the N-1 first switches are closed, the N-1 second switches and the N-1 third switches are opened, the fourth switch and the sixth switch are closed, the fifth switch is opened, and the first capacitor C FN 、···First capacitor C F3 , the first capacitor C F2 In series, the second capacitor C F1 Connect in parallel with the power inductor L, input power V IN Power is supplied to the capacitor and the inductor. The charge flowing through the power inductor L in the first period is the second charge. The second charge can be expressed according to formula (2). The first capacitor C in series FN 、···First capacitor C F3 , the first capacitor C F2 The charges released in the first period are equal, and are all first charges. The first charge can be expressed according to formula (3). The first end V of the power inductor L is SWL The voltage rises to N V IN , the second capacitor C F1 The charge released is Q CF1 .

[0084] Q L1 =I LA DT (2);

[0085] Among them, Q L1 It can be represented by the charge flowing through the power inductor L during the first time period, that is, the second charge, and D can be represented by the duty cycle.

[0086] Q CF2 = Q CF3 =···= Q CFN =I LA T (3);

[0087] Among them, Q CF2 It can be characterized as the first capacitance C F2 The released charge, Q CF3 It can be characterized as the first capacitance C F3 The released charge, Q CFN It can be characterized as the first capacitance C FN The released charge, I LA ·T can be characterized as the first charge. Therefore, from formula (1) and formula (2), it can be seen that the capacitance C F2 To C FN The charge flowing through the power inductor during one cycle can be replicated.

[0088] According to an embodiment of the present invention, based on the number N of capacitors in the series-parallel switched capacitor current reduction module and the charge amount of the power inductor in the first time period and the charge amount of the power inductor in the second time period, it can be obtained that within one cycle, the inductor average current in the series-parallel switched capacitor current reduction module can be reduced to a first current, and the inductor average current and the input current satisfy a first relationship, and the first relationship can be expressed according to formula (4).

[0089] (4);

[0090] Among them, I LA It can be characterized as a first current, that is, a voltage output by the series-parallel switch capacitor current reduction module when the second end of the series-parallel switch capacitor current reduction module is electrically connected to the output end, I INN It can be represented as the input current of the series-parallel switched capacitor current reduction module, and N can be represented as the number of capacitors included in the series-parallel switched capacitor current reduction module.

[0091] According to an embodiment of the present invention, by controlling the on / off states of the first switch, the second switch, and the third switch in N-1 first capacitor shunt subunits and the on / off states of the fourth switch, the fifth switch, and the sixth switch in the second capacitor shunt subunit respectively in the first time period and the second time period, the capacitor and the inductor in the series-parallel switch capacitor current reduction module are switched between the series-parallel state and the charge-discharge state, so that the first capacitor can be used to replicate and multiply the charge flowing through the power inductor, so that the inductor mean current is reduced to the first current while satisfying the first relationship. According to formula (4), the inductor mean current is always less than 1 / N of the input mean current, and the inductor conduction loss is reduced by N compared with the traditional boost converter. 2 times, so it is possible to use a small-size, high-on-resistance power inductor in the DC voltage conversion circuit while maintaining a certain inductor conduction loss. At the same time, by switching the capacitor and inductor in the series-parallel switch capacitor current reduction module between the series-parallel state and the charge-discharge state, the potential difference across the power inductor is regulated, so that the stacked switch capacitor module can control the circuit components in the stacked switch capacitor module according to the potential difference across the power inductor, amplify the input voltage, and obtain the target voltage.

[0092] According to an embodiment of the present invention, the cascaded M capacitor boosting units include a first capacitor boosting sub-unit and M-1 second capacitor boosting sub-units.

[0093] According to an embodiment of the present invention, the first end of the first capacitor boost unit is electrically connected to the series-parallel switched capacitor current reduction module, the second end of the first capacitor boost unit is electrically connected to the first end of the M-1th second capacitor boost sub-unit, and the third end of the first capacitor boost unit is electrically connected to the power inductor.

[0094] According to an embodiment of the present invention, the first end of the mth second capacitor boosting subunit is electrically connected to the second end of the m+1th second capacitor boosting subunit, the second end of the mth second capacitor boosting subunit is electrically connected to the first end of the m-1th second capacitor boosting subunit, the third end of the mth second capacitor boosting subunit is grounded, and the fourth end of the mth second capacitor boosting subunit is electrically connected to the power inductor, wherein the first end of the M-1th second capacitor boosting subunit is electrically connected to the second end of the first capacitor boosting unit, and the second end of the first second capacitor boosting subunit is electrically connected to the output end, 1≤m≤M-1.

[0095] According to an embodiment of the present invention, the cascaded M capacitor boosting units can be characterized as a unit including 2M-1 capacitors and 2M switches, the M-1 second capacitor boosting sub-units include 2M-2 capacitors and 2M-2 switches, and the first capacitor boosting unit includes one capacitor and two switches.

[0096] According to an embodiment of the present invention, by setting a first capacitor boost subunit and M-1 second capacitor boost subunits, the charge and discharge states of the first capacitor boost subunit and the M-1 second capacitor boost subunits can be alternately controlled in response to the potential difference across the power inductor, thereby utilizing the charge and discharge state inside the mth second capacitor boost subunit and utilizing the charge and discharge state of the mth second capacitor boost subunit to the m+1th second capacitor boost subunit, so that the voltage of the capacitor can be gradually raised, and then the input voltage can be amplified to output the target voltage, and further, the voltage input to the stacked switch capacitor module and the voltage output by the stacked switch capacitor module can be evenly divided by the capacitor devices in the M-1 second capacitor boost subunits, so as to reduce the withstand voltage of the switch devices in the stacked switch capacitor module. According to an embodiment of the present invention, the first capacitor boost subunit includes a seventh switch, an eighth switch and a third capacitor, and the mth second capacitor boost subunit includes a ninth switch, a tenth switch, a fourth capacitor and a fifth capacitor.

[0097] According to an embodiment of the present invention, a first end of the seventh switch of the first capacitor boost subunit is electrically connected to the series-parallel switch capacitor current reduction module, and a second end of the seventh switch is electrically connected to a first end of the third capacitor.

[0098] According to an embodiment of the present invention, the first end of the eighth switch of the first capacitor boosting subunit is electrically connected to the first end of the third capacitor, and the second end of the eighth switch is electrically connected to the fourth capacitor of the M-1th second capacitor boosting subunit.

[0099] According to an embodiment of the present invention, the second end of the third capacitor of the first capacitor boosting subunit is electrically connected to the power inductor.

[0100] According to the embodiment of the present invention, since the seventh switch and the eighth switch are both closed in the first time period, the voltages across the third capacitor are equal in the first time period. Therefore, the fifth switch, the sixth switch, and the second capacitor in the second capacitor shunting subunit and the seventh switch, the eighth switch, and the third capacitor in the first capacitor boosting subunit can be reused, thereby reducing the number of capacitors in the circuit.

[0101] According to an embodiment of the present invention, in the mth second capacitor boosting subunit, the first end of the ninth switch is electrically connected to the first end of the fourth capacitor, and the second end of the ninth switch is electrically connected to the first end of the tenth switch.

[0102] According to an embodiment of the present invention, the first end of the tenth switch in the mth second capacitor boosting subunit is electrically connected to the first end of the fifth capacitor, and the second end of the tenth switch is electrically connected to the first end of the ninth switch in the m-1th second capacitor boosting subunit.

[0103] According to an embodiment of the present invention, the second end of the fourth capacitor in the mth second capacitor boosting subunit is grounded, and the second end of the fifth capacitor is electrically connected to the power inductor.

[0104] Figure 5 A schematic structural diagram of a stacked switched capacitor module according to an embodiment of the present invention is shown.

[0105] like Figure 5 As shown, the stacked switch capacitor module includes a first capacitor boost subunit 501 and M-1 second capacitor boost subunits 502, the first capacitor boost subunit includes a seventh switch, an eighth switch and a third capacitor, and the M-1 second capacitor boost subunits include M-1 ninth switches, M-1 tenth switches, M-1 fourth capacitors and M-1 fifth capacitors. The seventh switch S of the first capacitor boost subunit 2M The first end of the first capacitor boost subunit is electrically connected to the series-parallel switch capacitor current reduction module, and the seventh switch S 2M The second end of the third capacitor C F（2M-1） The first end of the eighth switch S is electrically connected to 2M-1 The first end of the third capacitor C F（2M-1） The first end of the eighth switch S is electrically connected to 2M-1 The second end of the M-1 second capacitor boost subunit is connected to the fourth capacitor C F（2M-2） The first end of the third capacitor C F（2M-1） The second end is electrically connected to the power inductor L in the series-parallel switched capacitor current reduction module.

[0106] According to an embodiment of the present invention, the ninth switch S of the M-1th second capacitor boosting subunit 2M-2 The first end of the M-1 second capacitor boost subunit is connected to the fourth capacitor C F（2M-2） The second end of the M-1 second capacitor boost subunit is electrically connected to the ninth switch S 2M-2 The second end of the M-1 second capacitor boost subunit is connected to the tenth switch S 2M-3 The first end of the M-1 second capacitor boost subunit is electrically connected to the fourth capacitor C F（2M-2） The second end of the M-1 second capacitor boost subunit is grounded to GND, and the tenth switch S 2M-3 The first end of the capacitor C of the M-1 second capacitor boost subunit is connected to the fifth capacitor C of the M-1 second capacitor boost subunit. F（2M-3） The first end of the M-1 second capacitor boost subunit is electrically connected to the tenth switch S 2M-3 The second end of the M-2 second capacitor boost subunit is connected to the ninth switch S 2M-4 The first end of the M-1 second capacitor boost subunit is electrically connected to the fifth capacitor C F（2M-3） The second end is electrically connected to the power inductor L in the series-parallel switched capacitor current reduction module.

[0107] According to an embodiment of the present invention, based on the above connection mode, the M-2 second capacitor boosting subunit to the 2nd second capacitor boosting subunit are all connected in the same way as the M-1 second capacitor boosting subunit.

[0108] According to an embodiment of the present invention, the first end of the ninth switch S2 of the first second capacitor boosting subunit is connected to the fourth capacitor C of the first second capacitor boosting subunit. F（2M-（2M-2）） The first end of the ninth switch S of the first second capacitor boost subunit is electrically connected to 2M-（2M-2） The second end of the first second capacitor boost subunit is connected to the ninth switch S 2M-（2M-2） The first end of the first second capacitor boost subunit is electrically connected to the fourth capacitor C F（2M-（2M-2）） The second end of is grounded GND, and the tenth switch S of the first second capacitor boost subunit 2M-（2M-1） The first end of the first second capacitor boost subunit is connected to the fifth capacitor C F（2M-（2M-1）） The first end of the first second capacitor boost subunit is electrically connected to the tenth switch S 2M-（2M-1） The second end of the first second capacitor boost subunit is electrically connected to the output end, and the fifth capacitor C F（2M-（2M-1）） The second end is electrically connected to the power inductor L in the series-parallel switched capacitor current reduction module.

[0109] According to an embodiment of the present invention, in a first time period, the seventh switch in the first capacitor boosting subunit is disconnected, the eighth switch is closed, the M-1 ninth switch in the M-1 second capacitor boosting subunit is disconnected, the M-1 tenth switch is closed, the third capacitor in the first capacitor boosting subunit is connected in series with the fourth capacitor in the M-1 second capacitor boosting subunit, the fifth capacitor in the m-th second capacitor boosting subunit is connected in series with the fourth capacitor in the m-1 second capacitor boosting subunit, and the potential difference across the power inductor is a positive number, so that the third capacitor charges the fourth capacitor in the M-1 second capacitor boosting subunit, and the fifth capacitor in the m-th second capacitor boosting subunit charges the fourth capacitor in the m-1 second capacitor boosting subunit, so as to boost the input voltage and output the target voltage.

[0110] According to an embodiment of the present invention, in response to the potential difference across the power inductor being a positive number, in a first time period, the first capacitor boosting subunit and the third capacitor and the fourth capacitor in the M-1th second capacitor boosting subunit are connected in series, the third capacitor of the first capacitor boosting subunit is in a discharging state, the fourth capacitor in the M-1th second capacitor boosting subunit is in a charging state, and the third capacitor of the first capacitor boosting subunit discharges to the fourth capacitor in the M-1th second capacitor boosting subunit. The fifth capacitor in the M-1th second capacitor boosting subunit is connected in series with the fourth capacitor in the M-2th second capacitor boosting subunit, the fifth capacitor in the M-1th second capacitor boosting subunit is in a discharging state, the fourth capacitor in the M-2th second capacitor boosting subunit is in a charging state, and the fifth capacitor in the M-1th second capacitor boosting subunit is discharged with the fourth capacitor in the M-2th second capacitor boosting subunit.

[0111] According to an embodiment of the present invention, until the fifth capacitor in the second second capacitor boosting subunit is connected in series with the fourth capacitor in the first second capacitor boosting subunit, the fifth capacitor in the second second capacitor boosting subunit is in a discharging state, the fourth capacitor in the first second capacitor boosting subunit is in a charging state, the fifth capacitor in the second second capacitor boosting subunit and the fourth capacitor in the first second capacitor boosting subunit are discharged, and the fifth capacitor in the first second capacitor boosting subunit is in a discharging state and directly outputs the target voltage to the output end.

[0112] According to an embodiment of the present invention, during the second time period, the seventh switch in the first capacitor boosting subunit is closed, the eighth switch is opened, the M-1 ninth switches in the M-1 second capacitor boosting subunits are closed, the M-1 tenth switches are opened, the third capacitor in the first capacitor boosting subunit is connected in parallel with the fourth capacitor and the fifth capacitor in the m-th second capacitor boosting subunit, the fourth capacitor in the m-th second capacitor boosting subunit is connected in series with the fifth capacitor in the m-th second capacitor boosting subunit, and the potential difference across the power inductor is negative, so that the fourth capacitor in the m-th second capacitor boosting subunit charges the fifth capacitor in the m-th second capacitor boosting subunit.

[0113] According to an embodiment of the present invention, in response to the potential difference between the two ends of the power inductor being a positive number, in the second time period, the first capacitor boost subunit is disconnected from the M-1 second capacitor boost subunit, and the first second capacitor boost subunit is disconnected from the output terminal. The fourth capacitor in the M-1 second capacitor boost subunit is connected in series with the fifth capacitor in the M-1 second capacitor boost subunit, the fourth capacitor in the M-1 second capacitor boost subunit is in a discharge state, the fifth capacitor in the M-1 second capacitor boost subunit is in a charge state, and the fourth capacitor in the M-1 second capacitor boost subunit discharges to the fifth capacitor in the M-1 second capacitor boost subunit. Until the fourth capacitor in the first second capacitor boost subunit is connected in series with the fifth capacitor in the first second capacitor boost subunit, the fourth capacitor in the first second capacitor boost subunit is in a discharge state, the fifth capacitor in the first second capacitor boost subunit is in a charge state, and the fourth capacitor in the first second capacitor boost subunit discharges to the fifth capacitor in the first second capacitor boost subunit.

[0114] According to an embodiment of the present invention, by switching the charge and discharge state of each capacitor in the first capacitor boosting subunit and the M-1 second capacitor boosting subunits back and forth between the first time period and the second time period, the voltage of the capacitor is gradually increased, and the input voltage can be amplified to output the target voltage.

[0115] According to an embodiment of the present invention, the voltage input to the stacked switch capacitor module and the voltage output by the stacked switch capacitor module can be evenly divided by the third capacitor, M-1 fourth capacitors and M-1 fifth capacitors in the stacked switch capacitor module, so as to reduce the withstand voltage values ​​of the seventh switch, the eighth switch, M-1 ninth switches and M-1 tenth switches to the first withstand voltage value, and the first withstand voltage value can be expressed according to formula (5).

[0116] V m =(V OM -V INM ) / M(5);

[0117] Among them, V m It can be characterized as the first withstand voltage value, V OM It can be characterized as the voltage output by the stacked switched capacitor module when only the stacked switched capacitor module is included, that is, the voltage output by the stacked switched capacitor module when the first end of the first capacitor boost unit is electrically connected to the positive electrode of the input power module, V INM It can be represented by the voltage input to the stacked switched capacitor module, and M can be represented by the number of capacitor boosting units in the stacked switched capacitor module.

[0118] According to an embodiment of the present invention, by responding to the potential difference between the two ends of the power inductor, the seventh switch, the eighth switch in the first capacitor boost subunit and the ninth switch, the tenth switch in the M-1 second capacitor boost subunits are controlled in the first time period and the second time period respectively. The capacitor in the stacked switch capacitor module is switched in the state of charging and discharging, so that the voltage of the capacitor can be gradually raised, and then the input voltage can be amplified to output the target voltage. At the same time, the voltage input to the stacked switch capacitor module and the voltage output by the stacked switch capacitor module can be evenly divided through the third capacitor, M-1 fourth capacitors and M-1 fifth capacitors, so as to reduce the withstand voltage value of each switch in the stacked switch capacitor module, so that low withstand voltage and high quality factor switch tube devices can be used to improve the efficiency of power conversion of the conversion circuit.

[0119] According to an embodiment of the present invention, the circuit also includes a seventh capacitor, a first end of the seventh capacitor is electrically connected to the output end, and a second end of the seventh capacitor is grounded. When the potential difference across the power inductor is positive, the fifth capacitor in the first second capacitor boosting subunit charges the seventh capacitor; when the potential difference across the power inductor is negative, the seventh capacitor discharges to the output end to maintain the target voltage.

[0120] According to an embodiment of the present invention, when the DC voltage conversion circuit includes a series-parallel switched capacitor current reduction module, a stacked switched capacitor module and a seventh capacitor, the inductor mean current of the power inductor can be calculated based on the cascaded N capacitor current reduction units, the cascaded M capacitor boost units, the duty cycle and the input current, and the inductor mean current can be expressed according to formula (6). The target voltage and the voltage conversion ratio can be calculated based on the cascaded N capacitor current reduction units, the cascaded M capacitor boost units, the duty cycle and the input voltage, and the target voltage and the voltage conversion ratio can be expressed according to formula (7).

[0121] (6);

[0122] Among them, I L It can be represented as the inductor mean current of the power inductor, I, when the DC voltage conversion circuit includes a parallel switched capacitor current reduction module, a stacked switched capacitor module and a seventh capacitor. IN It can be characterized as the input mean current, Q, of the DC voltage conversion circuit when the DC voltage conversion circuit includes a parallel switched capacitor current reduction module, a stacked switched capacitor module and a seventh capacitor. L It can be characterized as the mean inductance charge of the power inductor, Q, when the DC voltage conversion circuit includes a parallel switched capacitor current reduction module, a stacked switched capacitor module and a seventh capacitor. INIt can be characterized as the input charge of the DC voltage conversion circuit when the DC voltage conversion circuit includes a parallel switched capacitor current reduction module, a stacked switched capacitor module and a seventh capacitor.

[0123] (7);

[0124] Among them, VCR can be characterized as the voltage conversion ratio, V O It can be represented as an output voltage, which is the voltage output by the DC voltage conversion circuit when the DC voltage conversion circuit includes a parallel switched capacitor current reduction module, a stacked switched capacitor module and a seventh capacitor, V IN It can be characterized as an input voltage input by the input power module, which is the voltage input by the input power module to the circuit when the DC voltage conversion circuit includes a parallel switched capacitor current reduction module, a stacked switched capacitor module and a seventh capacitor.

[0125] According to the embodiment of the present invention, different numbers of capacitor current reduction units and capacitor voltage boost units can be cascaded to achieve an expected voltage conversion ratio, and the switch withstand voltage and inductor mean current can be further reduced.

[0126] According to an embodiment of the present invention, by improving the voltage conversion ratio, the equivalent conduction time of the switch in the circuit can be equivalently increased. Generally speaking, the equivalent conduction time of the present invention can be increased by a multiple similar to the value of the voltage conversion ratio compared to the traditional boost converter, thereby reducing the risks brought by extremely short conduction time to the control and drive circuit, and reducing the control difficulty and design difficulty of the circuit.

[0127] Figure 6 A schematic structural diagram of a DC voltage conversion circuit including a seventh capacitor according to an embodiment of the present invention is shown.

[0128] like Figure 6 As shown, Figure 6 Included in Figure 2 The structure of the series-parallel switch capacitor current reduction module 101 is as shown in FIG. Figure 5 The structure of the stacked switched capacitor module 102 and the connection mode of its circuit components are shown in FIG. 1 , wherein the seventh switch S of the first capacitor boost subunit 2M The first end of the seventh capacitor C0 is electrically connected to the second end of the sixth switch S3 of the second capacitor shunt subunit, the first end of the seventh capacitor C0 is electrically connected to the output end, and the second end of the seventh capacitor C0 is grounded. In the first period, in response to the potential difference between the two ends of the power inductor being a positive number, the fifth capacitor C0 in the first second capacitor boost subunit is electrically connected to the output end. F（2M-（2M-1））The target voltage is output to the output terminal, and the seventh capacitor C0 is charged. The seventh capacitor C0 is in the charging state. In the second period, in response to the potential difference between the two ends of the power inductor being a negative number, the tenth switch S of the first second capacitor boost subunit is turned on. 2M-（2M-1） Disconnect, the fifth capacitor C in the first second capacitor boost subunit F（2M-（2M-1）） The seventh capacitor C0 is in a charging state and is disconnected from the output end. The seventh capacitor C0 is in a discharging state. The output end is powered by the seventh capacitor C0 to maintain the output of the target voltage.

[0129] Figure 7 A schematic structural diagram of a DC voltage conversion circuit including a seventh capacitor is shown in the case of multiplexing the second capacitor current splitting subunit and the first capacitor voltage boosting subunit according to an embodiment of the present invention.

[0130] like Figure 7 As shown, Figure 7 Included in Figure 2 The structure of the series-parallel switch capacitor current reduction module 101 is as shown in FIG. Figure 5 The structure of the stacked switched capacitor module 102 and the connection method of its circuit components also include the following: Figure 6 The seventh capacitor C0 is connected in the manner shown in FIG. F1 and the seventh switch S in the first capacitor boost subunit 2M , the eighth switch S 2M-1 , the third capacitor C F（2M-1） Specifically, by directly connecting the second end of the sixth switch S3 in the second capacitor current shunting subunit to the fourth capacitor C of the M-1th second capacitor boosting subunit, F（2M-2） The first end of the switch S is electrically connected to the circuit, and the seventh switch S in the circuit is removed. 2M , the eighth switch S 2M-1 , the third capacitor C F（2M-1） , so that the fifth switch S2 and the seventh switch S 2M Multiplexing, the sixth switch S3, the eighth switch S 2M-1 Multiplexing, the second capacitor C F1 , the third capacitor C F（2M-1） In the first period, the fifth switch S2 (S 2M ) is disconnected, the sixth switch S3 (S 2M-1 ) is closed, the second capacitor C F1 (C F(2M-1) ) is in the discharge state, the fourth capacitor C of the M-1th second capacitor boost subunit F（2M-2） In charging state, the second capacitor C F1 (C F(2M-1) ) directly to the fourth capacitor C of the M-1 second capacitor boost subunitsF（2M-2） Charging, in the second period, the fifth switch S2 (S 2M ) is closed, the sixth switch S3 (S 2M-1 ) is disconnected, the second capacitor C F1 (C F(2M-1) ) is in a charging state, so that the voltage drop at the first end of the power inductor L is negative, so that the voltage difference between the two ends of the power inductor L is negative, and the fourth capacitor C of the M-1 second capacitor boost subunit F（2M-2） The fifth capacitor C of the M-1th second capacitor boosting subunit is in the discharge state. F（2M-3） The fourth capacitor C of the M-1th second capacitor boosting subunit is in the charging state. F（2M-2） To the fifth capacitor C of the M-1th second capacitor boost subunit F（2M-3） Discharge.

[0131] According to an embodiment of the present invention, a seventh capacitor is connected to the output end so that the seventh capacitor can be charged in the first time period and the target voltage of the output end is maintained in the second time period, thereby maintaining the continuous output of the target voltage in one cycle.

[0132] Figure 8 The structure diagram of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention is shown.

[0133] like Figure 8 As shown, Figure 8 The DC voltage conversion circuit including three capacitor current reduction units 801 and three capacitor voltage boost units 801 is shown in the case of multiplexing the second capacitor current shunting subunit and the first capacitor voltage boosting subunit. The circuit can be applied to 2.5-5V input, 40-70V output high conversion ratio voltage boosting application scenarios. The three capacitor current reduction units 801 include two first capacitor current shunting subunits and a second capacitor current shunting subunit (because they have the same structure as the first capacitor voltage boosting subunit, the structure is reused and used as the first capacitor voltage boosting subunit in the three capacitor voltage boosting units at the same time), and the three capacitor voltage boosting units 802 include a first capacitor voltage boosting subunit and two second capacitor voltage boosting subunits.

[0134] According to an embodiment of the present invention, the first switch S of the second first capacitor shunt subunit 11 The first end is connected to the input power module V IN The positive electrode of the first capacitor shunt subunit is electrically connected to the first switch S 11 The second end of the first capacitor C F7 The second end of the second first capacitor shunt subunit is electrically connected to the second switch S 12 The first end is connected to the input power module V INThe positive electrode of the second first capacitor shunt subunit is electrically connected to the second switch S 12 The second end of the first capacitor C F7 The first end of the first capacitor shunt subunit is electrically connected to the third switch S 13 The first end of the first capacitor C of the second first capacitor shunt subunit F7 The second end of the first capacitor shunt subunit is electrically connected to the third switch S 13 The first end of the first switch S8 of the first first capacitor shunt subunit is connected to the first capacitor C of the second first capacitor shunt subunit. F7 The first end of the first switch S8 of the first first capacitor shunt subunit is electrically connected to the first capacitor C of the first first capacitor shunt subunit. F6 The first end of the second switch S9 of the first first capacitor shunt subunit is electrically connected to the input power module V IN The positive electrode of the first capacitor shunt subunit is electrically connected to the second end of the second switch S9 of the first first capacitor shunt subunit and the first capacitor C F6 The first end of the first capacitor shunt subunit is electrically connected to the third switch S 10 The first end of the first capacitor shunt subunit is connected to the first capacitor C F6 The second end of the first capacitor shunt subunit is electrically connected to the third switch S 10 The second end is grounded.

[0135] According to an embodiment of the present invention, the first end of the fourth switch S5 of the second capacitor shunt subunit is connected to the first capacitor C of the first first capacitor shunt subunit. F6 The first end of the fourth switch S5 is electrically connected to the first end of the power inductor L, and the first end of the fifth switch S6 is electrically connected to the input power module V IN The positive electrode of the fifth switch S6 is electrically connected to the positive electrode of the second capacitor C F5 The first end of the second capacitor C F5 The second end of the sixth switch S7 is electrically connected to the first end of the power inductor L, the second end of the power inductor L is grounded, and the first end of the sixth switch S7 is electrically connected to the second capacitor C F5 The first end of the sixth switch S7 is electrically connected to the fourth capacitor C of the second second capacitor boosting subunit. F4 The first end is electrically connected to the

[0136] According to an embodiment of the present invention, the first end of the ninth switch S4 of the second second capacitor boosting subunit is connected to the fourth capacitor C of the second second capacitor boosting subunit. F4The first end of the ninth switch S4 of the second second capacitor boosting subunit is electrically connected to the fifth capacitor C of the second second capacitor boosting subunit. F3 The first end of the second capacitor boost subunit is electrically connected to the fourth capacitor C F4 The second end of the second capacitor boost subunit is grounded, and the fifth capacitor C F3 The second end of the tenth switch S3 of the second second capacitor boosting subunit is electrically connected to the first end of the power inductor L, and the first end of the tenth switch S3 of the second second capacitor boosting subunit is electrically connected to the fifth capacitor C of the second second capacitor boosting subunit. F3 The first end of the tenth switch S3 of the second second capacitor boosting subunit is electrically connected to the fourth capacitor C of the first second capacitor boosting subunit. F2 The first end of the ninth switch S2 of the first second capacitor boosting subunit is electrically connected to the fourth capacitor C of the first second capacitor boosting subunit. F2 The first end of the ninth switch S2 of the first second capacitor boosting subunit is electrically connected to the fifth capacitor C of the first second capacitor boosting subunit. F1 The first end of the first second capacitor boost subunit is electrically connected to the fourth capacitor C F2 The second end of the first second capacitor boost subunit is grounded, and the fifth capacitor C F1 The second end of the first capacitor boost subunit is electrically connected to the first end of the power inductor L, and the first end of the tenth switch S1 of the first second capacitor boost subunit is electrically connected to the fifth capacitor C of the first second capacitor boost subunit. F1 The first end of the seventh capacitor C is electrically connected to the output end, the second end of the tenth switch S1 of the second capacitor boost subunit is electrically connected to the output end, and the seventh capacitor C F0 The first end of the seventh capacitor C is electrically connected to the output end. F0 The second end is grounded.

[0137] Fig. 9 The schematic diagram of the structure of the equivalent circuit of the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units in the first time period according to an embodiment of the present invention is shown.

[0138] like Fig. 9 As shown, Fig. 9 and Figure 8 The first switch S 11 , the first switch S8, the fourth switch S5, the sixth switch S7, the tenth switch S3, and the tenth switch S1 are closed, and the remaining switches are opened, and the first capacitor C F7 , the first capacitor C F6 The second capacitor C is connected in series and in discharge state. F5 With the fourth capacitor C F4 In series, the fifth capacitor C F3 With the fourth capacitor CF2 In series, the fifth capacitor C F1 To supply power to the output terminal, the second capacitor C F5 , the fifth capacitor C F3 , the fifth capacitor C F1 In the discharge state, the fourth capacitor C F4 , the fourth capacitor C F2 In the charging state, the power inductor L is magnetized, the current at the first end of the power inductor increases, and the input voltage increases.

[0139] Fig.10 A schematic structural diagram of an equivalent circuit of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units in a second time period according to an embodiment of the present invention is shown.

[0140] like Fig.10 As shown, Fig.10 and Figure 8 The second switch S 12 , the third switch S 13 , the second switch S9, the third switch S 10 , the fifth switch S6, the ninth switch S4, and the ninth switch S2 are closed, and the remaining switches are opened, and the first capacitor C F7 , the first capacitor C F6 , the second capacitor C F5 The fourth capacitor C is connected in parallel and is in a charging state. F4 With the fifth capacitor C F3 In series, the fourth capacitor C F2 With the fifth capacitor C F1 In series, the seventh capacitor C F0 Connected to the output terminal, the fifth capacitor C F3 , the fifth capacitor C F1 The fourth capacitor C is in charging state. F4 , the fourth capacitor C F2 In the discharge state, the power inductor L is demagnetized, the current at the first end of the power inductor decreases, and the input voltage is controlled by the seventh capacitor C F0 Maintain power supply.

[0141] According to an embodiment of the present invention, based on Fig. 9 and Fig.10The steady-state voltage of each capacitor and the withstand voltage values ​​of multiple switches can be obtained from the two time periods, so that the maximum withstand voltage value of each switch under this circuit structure is the second withstand voltage. Compared with the withstand voltage of the switch in the prior art, it is reduced by more than 67%, so that a switch tube with low withstand voltage and high quality factor can be used to achieve high power conversion efficiency. The steady-state voltage of each capacitor can be expressed according to formulas (8) to (13), the withstand voltage values ​​of multiple switches can be expressed according to formulas (14) to (17), and the second withstand voltage can be expressed according to formula (18).

[0142] V CF1 = V O3 - 3V IN3 (8);

[0143] Among them, V CF1 Can be characterized as the fifth capacitor C F1 The steady-state voltage, V O3 It can be represented as the target voltage output by the DC voltage conversion circuit including 3 capacitor current reduction units and 3 capacitor voltage boost units, V IN3 It can be characterized as an input voltage input to a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units.

[0144] V CF2 = (2V O 3 + V IN3 ) / 3(9);

[0145] Among them, V CF2 It can be characterized as the fourth capacitor C F2 The steady-state voltage.

[0146] V CF3 = (2V O3 - 8V IN3 ) / 3(10);

[0147] Among them, V CF3 Can be characterized as the fifth capacitor C F3 The steady-state voltage.

[0148] V CF4 = (V O3 +2V IN3 ) / 3 (11);

[0149] Among them, V CF4 It can be characterized as the fourth capacitor C F4 The steady-state voltage.

[0150] V CF5 = (V O3 - 7V IN3 ) / 3 (12);

[0151] Among them, V CF5 It can be characterized as the second capacitance C F5 The steady-state voltage.

[0152] V CF6 = V CF7 = V IN3 (13);

[0153] Among them, V CF6 It can be characterized as the first capacitance C F6 The steady-state voltage.

[0154] V φ1（S1-S4、S6-S7） = (V O3 -V IN3 ) / 3 (14);

[0155] Among them, V φ1（S1-S4、S6-S7） It can be represented by the withstand voltage values ​​of the tenth switch S1 , the ninth switch S2 , the tenth switch S3 , the ninth switch S4 , the fifth switch S6 , and the sixth switch S7 in the first time period.

[0156] V φ1（S5） = (V O3 -7V IN3 ) / 3 (15);

[0157] Among them, V φ1（S5） It can be characterized by the withstand voltage value of the fourth switch S5 in the first time period.

[0158] V φ2（S9-S10） = 2V IN3 (16);

[0159] Among them, V φ2（S9-S10） It can be characterized as the second switch S9 and the third switch S 10 The withstand voltage value.

[0160] V φ2（S3、S5-S7） = V IN3 (17);

[0161] Among them, V φ2（S3、S5-S7） It can be represented by the withstand voltage values ​​of the tenth switch S3, the ninth switch S4, the fifth switch S6, and the sixth switch S7 in the second time period.

[0162] V S = (V O3 -V IN3 ) / 3 (18);

[0163] Among them, V SIt can be characterized as the withstand voltage value of each switch in the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units, that is, the second withstand voltage.

[0164] According to an embodiment of the present invention, based on the charge conservation of the capacitor, the ratio of the inductor mean current to the input current in the DC voltage conversion circuit including three capacitor step-down units and three capacitor step-up units can be obtained. The ratio of the inductor mean current to the input mean current can be expressed according to formula (19).

[0165] (19);

[0166] Among them, I L3 It can be represented as the target current output by the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units, I IN3 It can be characterized as the input mean current, Q, input to the DC voltage conversion circuit including 3 capacitor current reduction units and 3 capacitor voltage boost units. L3 It can be characterized as the target charge flowing out of the DC voltage conversion circuit including 3 capacitor current reduction units and 3 capacitor voltage boost units, Q IN3 It can be characterized as the inflow charge input to the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units.

[0167] Fig.11 A schematic diagram showing the ratio of the inductor mean current to the input mean current of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention and a circuit in the prior art under a 2.5-5V voltage input and a 70V voltage output.

[0168] like Fig.11 As shown, the horizontal axis can be represented by the input voltage, and the vertical axis can be represented by the ratio of the inductor mean current to the input mean current. Compared with the circuits of the hybrid trapezoidal DC-DC converter of the prior art 1 and the hybrid Dickson-Fibonacci DC-DC converter of the prior art 2, even when the duty cycle gradually increases, the ratio of the inductor mean current output by the circuit of the present invention to the input mean current is greatly reduced, that is, the inductor mean current output by the circuit of the present invention is lower. Compared with the prior art, the inductor mean current of the present invention can be reduced by 66.7%, thereby fully reducing the conduction loss. While maintaining high power conversion efficiency, a small-sized, large-on-resistance inductor can be used to reduce the volume of the circuit and improve the power density.

[0169] Fig.12A schematic diagram shows the relationship between the voltage conversion ratio and the duty cycle obtained under 2.5-5V voltage input and 70V voltage output of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention and a circuit in the prior art.

[0170] like Fig.12 As shown, compared with the circuit of the prior art, the duty cycle of the circuit of the present invention can be 0~1, and as the duty cycle gradually increases, it can be seen from the figure that the voltage conversion ratio of the present invention is higher than that of the prior art (traditional circuit, hybrid trapezoidal DC-DC converter, hybrid Dickson-Fibonacci DC-DC converter), which is conducive to increasing the equivalent conduction time. At 2.5V voltage input and 28 times the conversion ratio required for 70V voltage output. The duty cycle D of the circuit of the present invention is 0.67, 1-D is 0.33, and the traditional boost DC-DC converter D is 0.96, 1-D is 0.04. When the DC-DC converter needs to work at a frequency of 1MHz and a period of 1μs, the equivalent conduction time of the traditional circuit is only 40ns, which puts forward higher requirements on the drive and control circuit. However, since the circuit of the present invention has a higher voltage conversion ratio, the equivalent conduction time can be made 330ns, which can reduce the difficulty of the drive and control circuit. Moreover, this on-time is also improved by 32% compared with the equivalent on-time of 250ns of the hybrid Dickson-Fibonacci DC-DC converter, so the present invention is suitable for application scenarios with high conversion ratios.

[0171] Fig.13 The working state waveform diagram of the power inductor, the inductor current and the inductor voltage in multiple switching cycles of the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention is shown.

[0172] like Fig.13 As shown, Fig.13 The timing diagram of the circuit of the present invention in multiple cycles is shown, the horizontal axis can be represented by time t, and the vertical axis can be represented by the inductor current I of the power inductor L The vertical axis of the following figure can be represented as the first end V of the power inductor L In the first period φ1 of each cycle, the capacitor in the series-parallel switched capacitor current reduction module is in a discharge state, the power inductor is in a magnetizing state, and the inductor current of the power inductor gradually increases. In the first period φ1, the voltage at the first end of the power inductor is 3V. IN3 , the inductor average current rising slope is 3V IN3 / L, in the second period φ2 of each cycle, the capacitor in the series-parallel switched capacitor current reduction module is in a charging state, the power inductor is in a demagnetized state, the inductor current of the power inductor drops rapidly, and the voltage at the first end of the power inductor is -(V O3-10V IN3 ) / 3, the average current drop slope of the inductor in the second period φ2 is -(V O3 -10V IN3 ) / 3L.

[0173] According to an embodiment of the present invention, a voltage conversion ratio in a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units can be obtained based on the volt-second balance of the inductor. The volt-second balance can be expressed according to formula (20), and the voltage conversion ratio can be expressed according to formula (21).

[0174] (20);

[0175] (twenty one);

[0176] Among them, VCR3 can be characterized as a voltage conversion ratio of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units.

[0177] According to the embodiments of the present invention, it can be known that in a DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units, the minimum voltage conversion ratio is 10, and the equivalent conduction time is increased by approximately 10 times compared with the prior art, which can reduce the risk of extremely short conduction time to the control and drive circuits. Since the volume of the inductor is much larger than that of the flying capacitor, the mean current of the inductor of the present invention can be greatly reduced, so that a smaller size inductor can be used. The prior art generally uses an inductor with a volume of 1.6×0.8×0.8mm 3 Therefore, compared with the hybrid ladder DC-DC converter, the working 3 The inductor, 8 capacitors achieve a 4x improvement, and the hybrid Dickson-Fibonacci DC-DC converter works using 2 3×3×1.4mm 3 The inductor and 5 flying capacitors can achieve a 7-fold improvement. The present invention can use a 3×3×1.4mm 3 The inductor and 7 capacitors are increased by 10 times, and the passive devices are smaller in size, which can achieve higher power density and reduce costs. It is also more suitable for high conversion ratio boost application scenarios.

[0178] Fig.14 The schematic diagram of the structure of the whole circuit of the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention is shown.

[0179] like Fig.14As shown, the output end of the DC voltage conversion circuit 1401 is electrically connected to the output voltage via a resistor divider network 1402, the output voltage is electrically connected to the control stage circuit 1403 via the resistor divider network 1402, the control stage circuit 1403 is electrically connected to the bootstrap circuit and the drive circuit 1404, wherein the target voltage is sampled by the resistor divider network 1402 to generate a feedback signal, the control stage circuit 1403 is controlled according to the feedback signal and generates a pulse width signal PWM, and a gate drive signal is generated via the bootstrap circuit and the drive circuit 1404.

[0180] Fig.15 A flow chart of a DC voltage conversion method according to an embodiment of the present invention is shown.

[0181] like Fig.15 As shown, the data signal amplification and resetting method of this embodiment includes operations S1510 to S1530.

[0182] In operation S1510 , the input power module sends an input voltage to the series-parallel switched capacitor current reduction module.

[0183] In operation S1520, the series-parallel switched capacitor current reduction module boosts the input voltage to obtain a potential difference across the power inductor, wherein the potential difference across the power inductor is positive in a first period, and is negative in a second period.

[0184] In operation S1530 , based on the potential difference across the power inductor, the stacked switched capacitor module is used to boost the input voltage and output a target voltage.

[0185] According to an embodiment of the present invention, the cascaded N capacitor current reduction units and the cascaded M capacitor boost units required for the DC voltage conversion circuit can be determined according to the required output voltage, thereby building a DC voltage conversion circuit so as to use the DC voltage conversion circuit to boost the input voltage and output the target voltage.

[0186] It will be appreciated by those skilled in the art that the features described in the various embodiments of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features described in the various embodiments of the present invention may be combined and / or combined in various ways. All of these combinations and / or combinations fall within the scope of the present invention.

Claims

1. A DC voltage conversion circuit, characterized in that: include: Series-parallel switch capacitor current reduction module, stacked switch capacitor module; wherein, The series-parallel switch capacitor current reduction module is electrically connected to the input power module, and the series-parallel switch capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units. The series-parallel switch capacitor current reduction module is used to control the potential difference across the power inductor by controlling the charge and discharge states of the N capacitor current reduction units, so that the inductor mean current of the power inductor is reduced to a first current, N≥2, and N is an integer; The stacked switched capacitor module is electrically connected to the series-parallel switched capacitor current reduction module, and includes M cascaded capacitor boost units. The stacked switched capacitor module is used to alternately control the charge and discharge states of the M capacitor boost units based on the potential difference across the power inductor, boost the input voltage, and output a target voltage, where M≥2, and M is an integer.

2. The DC voltage conversion circuit according to claim 1, characterized in that: The cascaded N capacitor current reduction units include N-1 first capacitor current shunt sub-units and second capacitor current shunt sub-units; The first ends of N-1 of the first capacitor shunt sub-units are electrically connected to the input power module, and the second ends of N-1 of the first capacitor shunt sub-units are electrically connected to the first end of the second capacitor shunt sub-unit; The second end of the second capacitor shunt subunit is electrically connected to the first end of the power inductor, and the third end of the second capacitor shunt subunit is electrically connected to the stacked switch capacitor module.

3. The DC voltage conversion circuit according to claim 2, characterized in that: The nth first capacitor shunt subunit among the N-1 first capacitor shunt subunits includes a first switch, a second switch, a third switch and a first capacitor, 1≤n≤N-1; The first end of the first switch of the nth first capacitor shunt subunit is electrically connected to the first end of the first capacitor of the n+1th first capacitor shunt subunit, and the second end of the first switch is electrically connected to the second end of the first capacitor, wherein the first end of the first switch of the N-1th first capacitor shunt subunit is electrically connected to the input power module; A first end of the second switch of the nth first capacitor current shunt sub-unit is electrically connected to the input power module, and a second end of the second switch is electrically connected to the first end of the first capacitor; The first end of the third switch of the nth first capacitor current splitter unit is electrically connected to the second end of the first capacitor, and the second end of the third switch is grounded.

4. The DC voltage conversion circuit according to claim 3, characterized in that: The second capacitor shunt subunit includes a fourth switch, a fifth switch, a sixth switch and a second capacitor; A first end of the fourth switch of the second capacitor shunt subunit is electrically connected to a first end of a first capacitor in the first capacitor shunt subunit, and a second end of the fourth switch is electrically connected to a second end of the second capacitor; A first end of the fifth switch of the second capacitor shunt subunit is electrically connected to the input power module, and a second end of the fifth switch is electrically connected to a first end of the second capacitor; A first end of the sixth switch of the second capacitor shunt subunit is electrically connected to a first end of the second capacitor, and a second end of the sixth switch is electrically connected to the stacked switch capacitor module; The first end of the second capacitor of the second capacitor shunt subunit is electrically connected to the second end of the fifth switch, and the second end of the second capacitor is electrically connected to the first end of the power inductor.

5. The DC voltage conversion circuit according to claim 4, characterized in that: The switching cycle of each switch includes a first time period and a second time period; In the first time period, N-1 of the first switches in the N-1 first capacitor shunt subunits are closed, N-1 of the second switches and N-1 of the third switches are opened, the fourth switch and the sixth switch of the second capacitor shunt subunit are closed, and the fifth switch is opened, so that the N-1 first capacitors are connected in series, and the second capacitor and the power inductor are connected in parallel. When the N-1 first capacitors are connected in series and the second capacitor and the power inductor are connected in parallel, the N-1 first capacitors are in a discharge state, and the voltage at the first end of the power inductor rises, so that the power inductor is in a magnetized state and the potential difference across the power inductor is a positive number; In the second time period, N-1 of the first switches in the N-1 first capacitor shunt subunits are disconnected, N-1 of the second switches and N-1 of the third switches are closed, the fourth switch and the sixth switch of the second capacitor shunt subunit are disconnected, and the fifth switch is closed, so that the N-1 first capacitors are connected in parallel, and the second capacitor and the power inductor are connected in series. When the N-1 first capacitors are connected in parallel and the second capacitor and the power inductor are connected in series, the N-1 first capacitors are in a charging state, and the voltage at the first end of the power inductor drops, so that the power inductor is in a demagnetized state and the potential difference across the power inductor is negative, wherein the first capacitors in the N-1 first capacitor shunt subunits switch the charging and discharging states in the first time period and the second time period, so that the inductor average current of the power inductor is reduced to the first current.

6. The DC voltage conversion circuit according to claim 1, characterized in that: The cascaded M capacitor boosting units include a first capacitor boosting subunit and M-1 second capacitor boosting subunits; The first end of the first capacitor boost unit is electrically connected to the series-parallel switch capacitor current reduction module, the second end of the first capacitor boost unit is electrically connected to the first end of the M-1th second capacitor boost subunit, and the third end of the first capacitor boost unit is electrically connected to the power inductor; The first end of the mth second capacitor boosting subunit is electrically connected to the second end of the m+1th second capacitor boosting subunit, the second end of the mth second capacitor boosting subunit is electrically connected to the first end of the m-1th second capacitor boosting subunit, the third end of the mth second capacitor boosting subunit is grounded, and the fourth end of the mth second capacitor boosting subunit is electrically connected to the power inductor, wherein the first end of the M-1th second capacitor boosting subunit is electrically connected to the second end of the first capacitor boosting subunit, and the second end of the first second capacitor boosting subunit is electrically connected to the output end, 1≤m≤M-1.

7. The DC voltage conversion circuit according to claim 6, characterized in that: The first capacitor boost subunit includes a seventh switch, an eighth switch and a third capacitor, and the mth second capacitor boost subunit includes a ninth switch, a tenth switch, a fourth capacitor and a fifth capacitor; A first end of the seventh switch of the first capacitor boost subunit is electrically connected to the series-parallel switch capacitor current reduction module, and a second end of the seventh switch is electrically connected to a first end of the third capacitor; A first end of the eighth switch of the first capacitor boosting subunit is electrically connected to a first end of the third capacitor, and a second end of the eighth switch is electrically connected to a fourth capacitor of the M-1th second capacitor boosting subunit; The second end of the third capacitor of the first capacitor boost subunit is electrically connected to the power inductor; The first end of the ninth switch in the mth second capacitor boosting subunit is electrically connected to the first end of the fourth capacitor, and the second end of the ninth switch is electrically connected to the first end of the tenth switch; The first end of the tenth switch in the mth second capacitor boosting subunit is electrically connected to the first end of the fifth capacitor, and the second end of the tenth switch is electrically connected to the first end of the ninth switch in the (m-1)th second capacitor boosting subunit; The second end of the fourth capacitor in the mth second capacitor boosting subunit is grounded, and the second end of the fifth capacitor is electrically connected to the power inductor.

8. The DC voltage conversion circuit according to claim 7, characterized in that: The DC voltage conversion circuit comprises: In a first time period, the seventh switch in the first capacitor boost subunit is disconnected, the eighth switch is closed, the ninth switch of the M-1 of the M-1 second capacitor boost subunits is disconnected, the tenth switch of the M-1 is closed, the third capacitor in the first capacitor boost subunit is connected in series with the fourth capacitor in the M-1 second capacitor boost subunit, the fifth capacitor in the m-th second capacitor boost subunit is connected in series with the fourth capacitor in the m-1 second capacitor boost subunit, and the potential difference across the power inductor is a positive number, so that the third capacitor charges the fourth capacitor in the M-1 second capacitor boost subunit, and the fifth capacitor in the m-th second capacitor boost subunit charges the fourth capacitor in the m-1 second capacitor boost subunit, so as to boost the input voltage and output the target voltage; In the second time period, the seventh switch in the first capacitor boosting subunit is closed, the eighth switch is opened, the M-1 ninth switches in the M-1 second capacitor boosting subunits are closed, and the M-1 tenth switches are opened, the third capacitor in the first capacitor boosting subunit is connected in parallel with the fourth capacitor and the fifth capacitor in the m-th second capacitor boosting subunit, and the fourth capacitor in the m-th second capacitor boosting subunit is connected in series with the fifth capacitor in the m-th second capacitor boosting subunit, and the potential difference across the power inductor is negative, so that the fourth capacitor in the m-th second capacitor boosting subunit charges the fifth capacitor in the m-th second capacitor boosting subunit.

9. The DC voltage conversion circuit according to claim 1, characterized in that: The DC voltage conversion circuit also includes a seventh capacitor; The first end of the seventh capacitor is electrically connected to the output end, and the second end of the seventh capacitor is grounded. When the potential difference across the power inductor is positive, the fifth capacitor in the first second capacitor boost subunit charges the seventh capacitor; when the potential difference across the power inductor is negative, the seventh capacitor discharges to the output end to maintain the target voltage.

10. A DC voltage conversion method for a DC voltage conversion circuit according to any one of claims 1 to 9, characterized in that: The DC voltage conversion method comprises: The input power module sends an input voltage to the series-parallel switched capacitor current reduction module; The series-parallel switched capacitor current reduction module performs a voltage-boosting process on the input voltage to obtain a potential difference across the power inductor, wherein, in a first time period, the potential difference across the power inductor is a positive number, and in a second time period, the potential difference across the power inductor is a negative number; Based on the potential difference between the two ends of the power inductor, the input voltage is boosted by using a stacked switch capacitor module to output a target voltage.

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