A high-efficiency, high-ratio non-isolated hybrid buck converter circuit

Abstract

This invention relates to a high-efficiency, high-ratio non-isolated hybrid buck converter circuit. The circuit includes: an input filter unit, an auxiliary power supply unit, a voltage ratio conversion unit, an intermediate filter unit, a power conversion unit, an energy storage inductor, an output filter unit, an output sampling unit, a feedback compensation unit, and a PWM control unit. This invention solves the problems of low duty cycle, long conduction time, and unstable operation of a single-stage buck converter under high-ratio conditions. By using an open-loop buck converter in the front stage, it increases the duty cycle and conduction time of the subsequent buck converter, thereby improving circuit efficiency. This invention is primarily designed based on actual user application needs. It can directly convert the bus voltage to the input voltage of the low-voltage controller and achieve high current output within a small package.

Description

Technical Field

[0001] This invention relates to the field of power supply and power drive technology, and specifically to a high-efficiency, high-ratio, non-isolated hybrid buck converter circuit. Background Technology

[0002] With the increasing informatization, integration, and intelligence of information systems in my country, the requirements for power supply systems are also becoming more stringent. Simultaneously, the widespread application of high-performance digital chips such as FPGAs is placing increasingly higher demands on low-voltage, high-current output DC / DC regulated power supplies. Low operating voltage reduces internal power losses in integrated chips, while high current output meets the power requirements of high-performance digital chips, improving system performance. However, the ever-increasing functionality and integration of chips necessitate power supplies providing ever-increasing current.

[0003] In traditional power supply architectures, the low-voltage, high-current power supply requirements of controllers such as FPGAs and DSPs typically employ a combined secondary and tertiary power supply architecture. This two-stage architecture requires two power converters, and the efficiency of the power supply system decreases with each conversion, while also resulting in a larger and more expensive system. Existing power supply architectures can no longer meet the demands for improved system performance and miniaturization; therefore, there is an urgent need for a higher-performance low-voltage output power supply solution. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a high-efficiency, high-ratio, non-isolated hybrid buck converter circuit.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A high-efficiency, high-ratio non-isolated hybrid buck converter circuit is disclosed, comprising: an input filter unit, a voltage ratio converter unit, an intermediate filter unit, a power conversion unit, an energy storage inductor, an output filter unit, an auxiliary power supply unit, a PWM control unit, an output sampling unit, and a feedback compensation unit. The output terminal of the input filtering unit is connected to the input terminal of the voltage proportional conversion unit and the input terminal of the auxiliary power supply unit, respectively; the output terminal of the auxiliary power supply unit is connected to the input terminal of the voltage proportional conversion unit; the output terminal of the voltage proportional conversion unit is connected to the input terminal of the intermediate filtering unit and the input terminal of the PWM control unit, respectively; the output terminal of the intermediate filtering unit is connected to the input terminal of the power conversion unit, the output terminal of the power conversion unit is connected to the input terminal of the energy storage inductor, the output terminal of the energy storage inductor is connected to the input terminal of the output filtering unit and the input terminal of the output sampling unit, the output terminal of the output filtering unit is connected to the input terminal of the output sampling unit, the output terminal of the output sampling unit is connected to the input terminal of the PWM control unit, the output terminal of the PWM control unit is connected to the control terminal of the power conversion unit, and the PWM control unit is interactively connected to the feedback compensation unit.

[0007] As a further improvement to the above technical solution, the voltage ratio conversion unit includes a voltage conversion module N1, a voltage conversion module N2, a resistor R1, a resistor R2, and a resistor R3.

[0008] The voltage conversion module N1 has its input power supply terminal Vin leading to the circuit input terminal Vin, its power ground GND leading to the circuit ground terminal GND, and its enable terminal EN leading to the circuit disable terminal INH via the resistor R1. The voltage conversion module N1 is connected to the input power supply terminal Vin of the voltage conversion module N2, the power ground GND of the voltage conversion module N2, the output terminal Vo of the voltage conversion module N1 and the voltage conversion module N2, the enable terminal EN of the voltage conversion module N1 and the voltage conversion module N2, the synchronization terminal SYNC of the voltage conversion module N1 and the voltage conversion module N2, and the indicator pin PGOOD of the voltage conversion module N1 and the voltage conversion module N2.

[0009] As a further improvement to the above technical solution, the input filtering unit includes capacitor C1; the intermediate filtering unit includes capacitor C2; one end of capacitor C1 is connected to the input power supply terminal Vin of the voltage conversion module N1, and the other end is connected to GND; one end of capacitor C2 is connected to the output terminal Vo of the voltage conversion module N1, and the other end is connected to GND; one end of resistor R2 is connected to the enable terminal EN of the voltage conversion module N1, and the other end is connected to the network VCC; one end of resistor R3 is connected to the indicator pin PGOOD of the voltage conversion module N1, and the other end is connected to the network VCC; the output terminal Vo of the voltage conversion module N1 is connected to the input power supply terminal Vin of the synchronization BUCK chip N3.

[0010] As a further improvement to the above technical solution, the auxiliary power supply unit includes a resistor R19, a Zener diode D5, a transistor Q9, and a capacitor C18; the PWM control unit includes a synchronous BUCK chip N3, a synchronous BUCK chip N4, a resistor R7, a resistor R10, a capacitor C6, a diode D1, a capacitor C7, a diode D2, a resistor R15, a resistor R17, a capacitor C13, a diode D3, a capacitor C15, and a diode D4.

[0011] The synchronous BUCK chip N3 has its feedback terminal FB leading out as the circuit adjustment terminal Trim, and its ground terminal GND leading out as the circuit ground terminal GND. The synchronous BUCK chip N3 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the ground terminal GND of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the soft-start input pin 1 TK / SS1 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the soft-start input pin 2 TK / SS2 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error amplifier compensation pin 1 ITH1 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error amplifier compensation pin 2 ITH2 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error feedback input pin 1 VFB1 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error feedback input pin 2 VFB1 of the synchronous BUCK chip N4. VFB2 is connected. The enable control pin 1 RUN1 of the synchronization BUCK chip N3 is connected to the enable control pin 2 RUN2 of the synchronization BUCK chip N4. The error amplifier compensation pin 1 ITH1 of the synchronization BUCK chip N3 is connected to the error amplifier compensation pin 2 ITH2. The soft start input pin 1 TK / SS1 of the synchronization BUCK chip N3 is connected to the soft start input pin 2 TK / SS2. The error feedback input pin 1 VFB1 of the synchronization BUCK chip N3 is connected to the error feedback input pin 2 VFB2. The enable control pin 1 RUN1 of the synchronization BUCK chip N3 is connected to the enable control pin 2 RUN2.

[0012] The anode of diode D1 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N3; the cathode of diode D1 is connected to the bootstrap power supply 1 BOOST1 of the synchronous BUCK chip N3; the cathode of diode D2 is connected to the bootstrap power supply 2 BOOST2 of the synchronous BUCK chip N3; the anode of diode D2 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N3; the cathode of diode D3 is connected to the bootstrap power supply 1 BOOST1 of the synchronous BUCK chip N4; the anode of diode D3 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N4; the anode of diode D4 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N4; and the cathode of diode D4 is connected to the bootstrap power supply 2 BOOST2 of the synchronous BUCK chip N4.

[0013] As a further improvement to the above technical solution, the energy storage inductor unit includes inductors L1, L2, L3 and L4; the output filtering unit includes capacitors C9, C11, C14 and C17; and the output sampling unit includes resistors R8, R9, C8, R13, R14, C12, R5 and R6.

[0014] One end of the resistor R5 is connected to the error feedback input pin 1 VFB1 of the synchronous BUCK chip N3, and the other end is connected to the differential telemetry amplifier output pin DIFFOUT of the synchronous BUCK chip N3; one end of the resistor R5 is connected to the error feedback input pin 1 VFB1 of the synchronous BUCK chip N3, and the other end is connected to GND.

[0015] The positive input pin DIFFP of the differential telemetry amplifier of the synchronous BUCK chip N3 is connected to the second terminal of the inductor L1; the negative input pin DIFFN of the differential telemetry amplifier of the synchronous BUCK chip N3 is connected to GND; the enable control pin 1 RUN1 of the synchronous BUCK chip N3 is connected to the indicator pin PGOOD of the voltage conversion module N1.

[0016] One end of the resistor R10 is connected to the indicator pin PGOOD of the synchronous BUCK chip N3, and the other end is connected to the output pin INTVcc of the internal voltage regulator of the synchronous BUCK chip N3.

[0017] The clock output pin CLKOUT of the synchronous BUCK chip N3 is connected to the mode selection pin MODE / PLLIN of the synchronous BUCK chip N4; the mode selection pin MODE / PLLIN of the synchronous BUCK chip N3 is connected to GND; the positive input pin DIFFP of the differential telemetry amplifier of the synchronous BUCK chip N4 is connected to GND; and the negative input pin DIFFN of the differential telemetry amplifier of the synchronous BUCK chip N4 is connected to GND.

[0018] One end of the resistor R7 is connected to the frequency pin FREQ of the synchronous BUCK chip N3, and the other end is connected to GND.

[0019] One end of capacitor C8 is connected to the second end of inductor L1, and the other end is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronization BUCK chip N3; resistor R9 is connected in parallel with capacitor C8; one end of capacitor C9 is connected to the second end of inductor L1, and the other end is connected to GND; the negative input pin sense1- of the current sensing comparator 1 of the synchronization BUCK chip N3 is connected to the second end of inductor L1; the second end of inductor L1 is connected to the circuit input terminal Vo.

[0020] One end of capacitor C10 is connected to the second end of inductor L1, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronization BUCK chip N3; resistor R11 is connected in parallel with capacitor C10; one end of capacitor C11 is connected to the second end of inductor L1, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronization BUCK chip N3 is connected to the second end of inductor L2; the second end of inductor L2 is connected to the lead-out circuit input terminal Vo.

[0021] One end of resistor R15 is connected to the indicator pin PGOOD of the synchronous BUCK chip N4, and the other end is connected to the output pin INTVcc of the internal voltage regulator of the synchronous BUCK chip N4; one end of resistor R17 is connected to the frequency pin FREQ of the synchronous BUCK chip N4, and the other end is connected to GND.

[0022] One end of capacitor C12 is connected to the second end of inductor L3, and the other end is connected to the positive input pin sense1+ of current sensing comparator 1 of synchronous BUCK chip N4; resistor R14 is connected in parallel with capacitor C12; one end of capacitor C14 is connected to the second end of inductor L3, and the other end is connected to GND; the negative input pin sense2- of current sensing comparator 2 of synchronous BUCK chip N4 is connected to the second end of inductor L3; the second end of inductor L3 is connected to the circuit input terminal Vo.

[0023] One end of capacitor C16 is connected to the second end of inductor L3, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronization BUCK chip N4; resistor R14 is connected in parallel with capacitor C16; one end of capacitor C17 is connected to the second end of inductor L3, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronization BUCK chip N4 is connected to the second end of inductor L4; the second end of inductor L4 is connected to the circuit input terminal Vo.

[0024] One end of resistor R19 is connected to the input power supply terminal Vin of the sync BUCK chip N4, and the other end is connected to the cathode of the Zener diode D5 and the base of the transistor Q9; the anode of the Zener diode D5 is connected to GND; the collector of the transistor Q9 is connected to the input power supply terminal Vin of the sync BUCK chip N4, and the emitter is connected to the network Vcc; one end of capacitor C18 is connected to the network Vcc, and the other end is connected to GND.

[0025] As a further improvement to the above technical solution, the power conversion unit includes MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8.

[0026] The source of MOSFET Q1 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3; the gate of MOSFET Q1 is connected to the high-side gate drive output pin TG1 of the synchronous BUCK chip N3; the source of MOSFET Q1 is connected to the switching node SW1 of the synchronous BUCK chip N3, the first terminal of capacitor C6, the drain of MOSFET Q2, the first terminal of inductor L1, and the first terminal of resistor R8; the second terminal of capacitor C6 is connected to the bootstrap power supply BOOST1 of the synchronous BUCK chip N3; the second terminal of resistor R8 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N3; the gate of MOSFET Q2 is connected to the low-side gate drive output pin BG1 of the synchronous BUCK chip N3; and the source of MOSFET Q2 is connected to GND.

[0027] The source of MOSFET Q3 is connected to the input power supply terminal Vin of synchronous BUCK chip N3; the gate of MOSFET Q3 is connected to the high-side gate drive output pin 2 TG2 of synchronous BUCK chip N3; the source of MOSFET Q3 is connected to the switching node SW2 of synchronous BUCK chip N3, the first terminal of capacitor C7, the drain of MOSFET Q4, the first terminal of inductor L2, and the first terminal of resistor R12; the second terminal of capacitor C7 is connected to the bootstrap power supply 2 BOOST2 of synchronous BUCK chip N3; the second terminal of resistor R12 is connected to the positive input pin sense2+ of current sensing comparator 2 of synchronous BUCK chip N3; the gate of MOSFET Q4 is connected to the low-side gate drive output pin 2 BG2 of synchronous BUCK chip N3; the source of MOSFET Q4 is connected to GND.

[0028] The source of MOSFET Q5 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of MOSFET Q5 is connected to the high-side gate drive output pin TG1 of the synchronous BUCK chip N4; the source of MOSFET Q5 is connected to the switching node SW1 of the synchronous BUCK chip N4, the first terminal of capacitor C13, the drain of MOSFET Q6, the first terminal of inductor L3, and the first terminal of resistor R13; the second terminal of capacitor C13 is connected to the bootstrap power supply BOOST1 of the synchronous BUCK chip N4; the second terminal of resistor R13 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N4; the gate of MOSFET Q6 is connected to the low-side gate drive output pin BG1 of the synchronous BUCK chip N4; the source of MOSFET Q6 is connected to GND; the source of MOSFET Q7 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of MOSFET Q7 is connected to the high-side gate drive output pin TG1 of the synchronous BUCK chip N4. TG2 is connected; the source of the MOSFET Q7 is connected to the switching node SW2 of the synchronous BUCK chip N4, the first terminal of capacitor C15, the drain of the MOSFET Q8, the first terminal of inductor L4, and the first terminal of resistor R18; the second terminal of capacitor C15 is connected to the bootstrap power supply 2 BOOST2 of the synchronous BUCK chip N4; the second terminal of resistor R18 is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N4; the gate of the MOSFET Q8 is connected to the low-side gate drive output pin 2 BG2 of the synchronous BUCK chip N4; the source of the MOSFET Q8 is connected to GND.

[0029] As a further improvement to the above technical solution, the feedback compensation unit includes capacitor C3, capacitor C4, capacitor C5 and resistor R4.

[0030] One end of capacitor C3 is connected to the soft-start input pin 1 TK / SS1 of the synchronous BUCK chip N3, and the other end is connected to GND; one end of capacitor C4 is connected to GND, and the other end is connected to the second end of resistor R4; the first end of resistor R4 is connected to the error amplifier compensation pin 1 ITH1 of the voltage conversion module N1; one end of capacitor C5 is connected to the error amplifier compensation pin 1 ITH1 of the synchronous BUCK chip N3, and the other end is connected to GND.

[0031] As a further improvement to the above technical solution, the circuit also includes an adjustable resistor RSET; the two ends of the adjustable resistor RSET are respectively connected to the circuit Trim terminal and the ground terminal GND; by adjusting the resistance value of the adjustable resistor RSET, different output voltages are determined, forming an adjustment circuit closed loop.

[0032] Compared with the prior art, the advantages of the present invention are:

[0033] (1) This invention solves the problems of low duty cycle, long conduction time, and unstable operation of single-stage BUCK under high transformation ratio conditions. By using open-loop step-down in the front stage, the duty cycle of the subsequent BUCK is increased, the conduction time is increased, and the circuit efficiency is improved. This invention is mainly designed based on the actual application needs of users. It can directly convert the bus voltage into the input voltage of the low-voltage controller and can achieve high current output in a small package.

[0034] (2) The main control chips N3 and N4 used in this invention are the same synchronous BUCK controller, which is typically used in step-down circuits and can only achieve stable output and output voltage adjustment under low voltage input. However, this invention can improve the circuit input voltage range by adding a voltage ratio conversion unit.

[0035] (3) The circuit structure used in this invention is easy to expand, thereby increasing the circuit power and improving the circuit output current capability. Attached Figure Description

[0036] Figure 1 This is a block diagram of the high-efficiency, high-ratio non-isolated hybrid buck converter circuit in this invention.

[0037] Figure 2 This is the circuit schematic diagram of the high-efficiency, high-ratio non-isolated hybrid buck converter circuit in this invention;

[0038] Figure 3 This is a schematic diagram of the adjustment function of the high-efficiency, high-ratio non-isolated hybrid buck converter circuit in this invention;

[0039] Figure 4 This is an application diagram of the high-efficiency, high-ratio, non-isolated hybrid buck converter circuit in this invention.

[0040] in:

[0041] 1. Input filtering unit; 2. Voltage proportional conversion unit; 3. Intermediate filtering unit; 4. Power conversion unit; 5. Energy storage inductor; 6. Output filtering unit; 7. Auxiliary power supply unit; 8. PWM control unit; 9. Output sampling unit; 10. Feedback compensation unit. Detailed Implementation

[0042] The present invention will be further described below with reference to the accompanying drawings:

[0043] like Figure 1The circuit shown is a high-efficiency, high-ratio non-isolated hybrid step-down converter, which includes: an input filter unit 1, a voltage ratio conversion unit 2, an intermediate filter unit 3, a power conversion unit 4, an energy storage inductor unit 5, an output filter unit 6, an auxiliary power supply unit 7, a PWM control unit 8, an output sampling unit 9, and a feedback compensation unit 10. The output terminal of the input filtering unit 1 is connected to the input terminals of the voltage proportional conversion unit 2 and the auxiliary power supply unit 7. The output terminal of the auxiliary power supply unit 7 is connected to the input terminal of the voltage proportional conversion unit 2. The output terminal of the voltage proportional conversion unit 2 is connected to the input terminals of the intermediate filtering unit 3 and the PWM control unit 8. The output terminal of the intermediate filtering unit 3 is connected to the input terminal of the power conversion unit 4. The output terminal of the power conversion unit 4 is connected to the input terminal of the energy storage inductor unit 5. The output terminal of the energy storage inductor unit 5 is connected to the input terminals of the output filtering unit 6 and the output sampling unit 9. The output terminal of the output filtering unit 6 is connected to the input terminal of the output sampling unit 9. The output terminal of the output sampling unit 9 is connected to the input terminal of the PWM control unit 8. The output terminal of the PWM control unit 8 is connected to the control terminal of the power conversion unit 4. The PWM control unit 8 is connected to the feedback compensation unit 10.

[0044] Specifically, the input filtering unit 1 is used to filter the circuit input signal, reduce the AC component in the input signal, and obtain a DC input signal; the auxiliary power supply unit 7 is used to provide the internal Vcc level of the circuit, providing a low-voltage input for the internal circuit; the voltage ratio conversion unit 2 is used to convert the input voltage into an intermediate voltage at a 4:1 ratio, providing the input voltage for the power conversion unit 4; the intermediate filtering unit 3 is used to filter the intermediate voltage signal, reducing its AC signal; the power conversion unit 4 is used to convert the stable DC intermediate voltage into the required AC voltage by changing the switching duty cycle; the energy storage inductor unit 5 is used for energy conversion and storage; the output filtering unit 6 is used to filter and rectify the output signal to obtain a stable DC output; the output sampling unit 9 is used to detect the circuit output signal and feed it back to the PWM control chip; the feedback compensation unit 10 is used for circuit loop compensation to ensure stable circuit operation; and the PWM control unit 8 is used for output signal feedback adjustment to provide a control signal for the power conversion unit 4. The voltage proportional conversion unit 2 adopts a switched capacitor structure, which can achieve a 4:1 input-output conversion, significantly reducing the input voltage, that is, reducing the input-output voltage difference of the power conversion unit 4 and improving efficiency. To solve the problem that the voltage proportional conversion unit 2 cannot start under load, this invention uses the power indication function signal of the voltage proportional conversion unit 2 as the enable control signal of the PWM control unit 8, thereby realizing the direct start-up of the entire circuit under load, without the need to start the circuit under no-load before connecting the load.

[0045] like Figure 2 As shown, the input filtering unit 1 includes capacitor C1; the voltage conversion unit 2 includes voltage conversion module N1, voltage conversion module N2, resistor R1, resistor R2, and resistor R3; the intermediate filtering unit 3 includes capacitor C2; the power conversion unit 4 includes MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8; the energy storage inductor unit 5 includes inductors L1, L2, L3, and L4; the output filtering unit 6 includes capacitors C9, C11, C14, and C17; the auxiliary... The auxiliary power supply unit 7 includes a resistor R19, a Zener diode D5, a transistor Q9, and a capacitor C18; the PWM control unit 8 includes a synchronous BUCK chip N3, a synchronous BUCK chip N4, a resistor R7, a resistor R10, a capacitor C6, a diode D1, a capacitor C7, a diode D2, a resistor R15, a resistor R17, a capacitor C13, a diode D3, a capacitor C15, and a diode D4; the output sampling unit 9 includes a resistor R8, a resistor R9, a capacitor C8, a resistor R13, a resistor R14, a capacitor C12, a resistor R5, and a resistor R6; the feedback compensation unit 10 includes capacitors C3, C4, and C5.

[0046] Figure 1 for Figure 2 Simplified diagram of functional modules Figure 1 The input filtering unit in is Figure 2 Capacitor C1 in the middle; Figure 1 The auxiliary power supply unit 7 in the middle is Figure 2 The components in the circuit are resistor R19, Zener diode D5, transistor Q9, and capacitor C18. Figure 1 The voltage proportional conversion unit 2 in the middle is Figure 2 The voltage conversion module N1, voltage conversion module N2, resistor R1, resistor R2, and resistor R3 are included. Figure 1 Intermediate filter unit 3 in the middle is Figure 2 C2 in the middle; Figure 1 The power conversion unit 4 in the middle is Figure 2 The MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are listed in the diagram. Figure 1 The energy storage inductor unit 5 in the middle is Figure 2 The inductors are L1, L2, L3, and L4. Figure 1 The output filter unit 6 in the middle is Figure 2 Capacitors C9, C11, C14, and C17 are included. Figure 1 The output sampling unit 9 in the middle is Figure 2The resistors are R8, R9, C8, R13, R14, C12, R5, and R6. Figure 1 The feedback compensation unit 10 in the middle is Figure 2 Capacitors C3, C4, and C5 are included. Figure 1 The PWM control unit 8 in the middle is Figure 2 The components are: synchronous BUCK chip N3, synchronous BUCK chip N4, resistor R7, resistor R10, capacitor C6, diode D1, capacitor C7, diode D2, resistor R15, resistor R17, capacitor C13, diode D3, capacitor C15, and diode D4.

[0047] exist Figure 2In the high-efficiency, high-ratio non-isolated hybrid buck converter circuit shown, capacitor C1 acts as an input filter to remove pulsating current at the input terminal, providing a stable voltage to the input terminals of voltage conversion modules N1 and N2. N1 and N2 are voltage conversion modules with a 4:1 input-to-output voltage conversion ratio, providing a DC output voltage. This DC voltage provides the input voltage for synchronous BUCK chips N3 and N4, and also provides enable control signals for them. Capacitor C2 acts as a filter to remove pulsating current at the input terminals of synchronous BUCK chips N3 and N4, providing them with a stable voltage. Resistor R19, capacitor C5, Zener diode D5, and transistor Q9 constitute an auxiliary power supply circuit, realizing the voltage conversion from input voltage to Vcc, used to power internal circuitry or as an internal TTL high level. Resistor R3 is used for setting the status of the voltage conversion modules, and this status is transmitted to the synchronous BUCK chips. When the status is good, the synchronous BUCK chips start working. Capacitors C6, C7, C13, and C15, along with diodes D1, D2, D3, and D4, constitute a bootstrap circuit, providing drive voltage to the internal MOSFETs of the synchronous BUCK chip. Inductors L1, L2, L3, and L4 are output filter inductors, storing energy and generating a back electromotive force to stabilize the output voltage. They also filter the current, reducing ripple. Capacitors C9, C11, C14, and C17 are output capacitors, used to withstand inductor current fluctuations, reducing output voltage ripple and adjusting both steady-state and dynamic characteristics. Resistors R1 and R2 limit current; when the voltage at the circuit's disable terminal INH is low, they limit the current, preventing a direct short circuit in the voltage conversion module and potential device burnout. Resistor R4, capacitors C4 and C5 form a loop compensation circuit, ensuring stable overall circuit operation. Resistors R8, R9, R11, R12, R13, R14, R16, and R18, along with capacitors C8, C10, C12, and C16, constitute a current sampling circuit used to transmit the inductor's current signal to the synchronization BUCK chip. Resistors R7 and R17 are used to adjust the frequency of the synchronization BUCK chip. Resistors R10 and R15 are used to indicate the operating status of the synchronization BUCK chip.

[0048] Figure 3 In order to be in Figure 2 Based on the circuit shown, an external adjustable resistor RSET is connected to the circuit's Trim terminal and the circuit's output ground terminal GNDO. By adjusting the resistance value of RSET, different output voltages can be determined, forming a closed loop of the adjustment circuit.

[0049] To achieve adjustable output voltage, resistors R5, R6, and RSET form an output voltage adjustment circuit, which outputs a constant voltage and adjusts the output voltage value via RSET. Figure 3 The box contains the adjustment circuit.

[0050] Depend on Figure 3 As shown in the circuit diagram, the output voltage Vo is obtained using the following formula:

[0051]

[0052] Output voltage V O With resistance R SET The calculation formula is:

[0053]

[0054] As can be seen from the above formula, the output voltage V can be adjusted by setting different RSET values. O This enables adjustable output.

[0055] The working principle of the high-efficiency, high-ratio non-isolated hybrid buck converter circuit described in this invention is as follows:

[0056] The input voltage VIN provides the power supply voltage for the voltage conversion module N1, and the output of the voltage conversion module N1 provides the power supply voltage for the synchronous BUCK chips N3 and N4. When the main power switch MOSFET is turned on, the input power supply supplies power to the output load through the main power switch MOSFET and the inductor, while the inductor stores energy. When the main power switch MOSFET is turned off, the energy stored in the inductor is released to the output load and forms a freewheeling circuit through the internal synchronous rectifier MOSFET to continue supplying power to the output load. Then, it is rectified and filtered by the output filter unit to ensure continuous current and voltage output at the output terminal, while maintaining output signal stability. The output sampling unit feeds the output signal back to the synchronous BUCK chips N3 and N4, and the PWM control unit adjusts the chip's duty cycle to achieve stable output voltage and output current.

[0057] Typical applications of the high-efficiency, high-ratio non-isolated hybrid buck converter circuit described in this invention include: Figure 4 As shown, the external resistance R to ground is achieved through the Trim terminal. SET The settings affect the feedback loop of the synchronous BUCK chip, controlling the output voltage. The operating state is controlled by the inhibit terminal INH. When the inhibit terminal is low, the circuit is inactive by default; when the inhibit terminal INH is empty or the voltage is high, the circuit is active.

[0058] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A high-efficiency, high-ratio non-isolated hybrid buck converter circuit, characterized in that, The circuit includes: an input filtering unit (1), a voltage ratio conversion unit (2), an intermediate filtering unit (3), a power conversion unit (4), an energy storage inductor unit (5), an output filtering unit (6), an auxiliary power supply unit (7), a PWM control unit (8), an output sampling unit (9), and a feedback compensation unit (10). The output terminal of the input filtering unit (1) is connected to the input terminal of the voltage proportional conversion unit (2) and the input terminal of the auxiliary power supply unit (7), respectively; the output terminal of the auxiliary power supply unit (7) is connected to the input terminal of the voltage proportional conversion unit (2); the output terminal of the voltage proportional conversion unit (2) is connected to the input terminal of the intermediate filtering unit (3) and the input terminal of the PWM control unit (8), respectively; the output terminal of the intermediate filtering unit (3) is connected to the input terminal of the power conversion unit (4), and the output terminal of the power conversion unit (4) is connected to the storage unit (8). The energy storage inductor unit (5) is connected to the input terminal of the energy storage inductor unit (5), the output terminal of the energy storage inductor unit (5) is connected to the input terminal of the output filter unit (6) and the input terminal of the output sampling unit (9), the output terminal of the output filter unit (6) is connected to the input terminal of the output sampling unit (9), the output terminal of the output sampling unit (9) is connected to the input terminal of the PWM control unit (8), the output terminal of the PWM control unit (8) is connected to the control terminal of the power conversion unit (4), and the PWM control unit (8) is interactively connected to the feedback compensation unit (10). The voltage ratio conversion unit (2) includes a voltage conversion module N1, a voltage conversion module N2, a resistor R1, a resistor R2, and a resistor R3; The voltage conversion module N1 has its input power supply terminal Vin leading to the circuit input terminal Vin, its power ground GND leading to the circuit ground terminal GND, and its enable terminal EN leading to the circuit disable terminal INH via the resistor R1. The voltage conversion module N1 is connected to the input power supply terminal Vin of the voltage conversion module N2, the power ground GND of the voltage conversion module N2, the output terminal Vo of the voltage conversion module N1 and the voltage conversion module N2, the enable terminal EN of the voltage conversion module N1 and the voltage conversion module N2, the synchronization terminal SYNC of the voltage conversion module N1 and the voltage conversion module N2, and the indicator pin PGOOD of the voltage conversion module N1 and the voltage conversion module N2. The PWM control unit (8) includes a synchronous BUCK chip N3 and a synchronous BUCK chip N4; the voltage conversion module N1 and the voltage conversion module N2 output DC voltage with an input-output voltage conversion ratio of 4:

1. This DC voltage provides input voltage for the synchronous BUCK chip N3 and the synchronous BUCK chip N4, and provides enable control signals for the synchronous BUCK chip N3 and the synchronous BUCK chip N4.

2. The high-efficiency, high-ratio non-isolated hybrid buck converter circuit according to claim 1, characterized in that, The input filtering unit (1) includes a capacitor C1; the intermediate filtering unit (3) includes a capacitor C2; one end of the capacitor C1 is connected to the input power supply terminal Vin of the voltage conversion module N1, and the other end is connected to GND; one end of the capacitor C2 is connected to the output terminal Vo of the voltage conversion module N1, and the other end is connected to GND; one end of the resistor R2 is connected to the enable terminal EN of the voltage conversion module N1, and the other end is connected to the network VCC; one end of the resistor R3 is connected to the indicator pin PGOOD of the voltage conversion module N1, and the other end is connected to the network VCC; the output terminal Vo of the voltage conversion module N1 is connected to the input power supply terminal Vin of the synchronization BUCK chip N3.

3. The high-efficiency, high-ratio non-isolated hybrid buck converter circuit according to claim 2, characterized in that, The auxiliary power supply unit (7) includes a resistor R19, a Zener diode D5, a transistor Q9, and a capacitor C18.

4. The high-efficiency, high-ratio non-isolated hybrid buck converter circuit according to claim 3, characterized in that, The PWM control unit (8) also includes resistor R7, resistor R10, capacitor C6, diode D1, capacitor C7, diode D2, resistor R15, resistor R17, capacitor C13, diode D3, capacitor C15 and diode D4; The synchronous BUCK chip N3 has its feedback terminal FB leading out as the circuit adjustment terminal Trim, and its ground terminal GND leading out as the circuit ground terminal GND. The synchronous BUCK chip N3 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the ground terminal GND of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the soft-start input pin 1 TK / SS1 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the soft-start input pin 2 TK / SS2 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error amplifier compensation pin 1 ITH1 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error amplifier compensation pin 2 ITH2 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error feedback input pin 1 VFB1 of the synchronous BUCK chip N4. The synchronous BUCK chip N3 is connected to the error feedback input pin 2 VFB1 of the synchronous BUCK chip N4. VFB2 is connected; the enable control pin 1 RUN1 of the synchronous BUCK chip N3 is connected to the enable control pin 2 RUN2 of the synchronous BUCK chip N4; the error amplifier compensation pin 1 ITH1 of the synchronous BUCK chip N3 is connected to the error amplifier compensation pin 2 ITH2; the soft start input pin 1 TK / SS1 of the synchronous BUCK chip N3 is connected to the soft start input pin 2 TK / SS2; the error feedback input pin 1 VFB1 of the synchronous BUCK chip N3 is connected to the error feedback input pin 2 VFB2; and the enable control pin 1 RUN1 of the synchronous BUCK chip N3 is connected to the enable control pin 2 RUN2. The anode of diode D1 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N3; the cathode of diode D1 is connected to the bootstrap power supply 1 BOOST1 of the synchronous BUCK chip N3; the cathode of diode D2 is connected to the bootstrap power supply 2 BOOST2 of the synchronous BUCK chip N3; the anode of diode D2 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N3; the cathode of diode D3 is connected to the bootstrap power supply 1 BOOST1 of the synchronous BUCK chip N4; the anode of diode D3 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N4; the anode of diode D4 is connected to the output pin INTVcc of the internal regulator of the synchronous BUCK chip N4; and the cathode of diode D4 is connected to the bootstrap power supply 2 BOOST2 of the synchronous BUCK chip N4.

5. The high-efficiency, high-ratio non-isolated hybrid buck converter circuit according to claim 4, characterized in that, The energy storage inductor unit (5) includes inductors L1, L2, L3 and L4; the output filter unit (6) includes capacitors C9, C11, C14 and C17; the output sampling unit (9) includes resistors R8, R9, C8, R13, R14, C12, R5 and R6. One end of the resistor R5 is connected to the error feedback input pin 1 VFB1 of the synchronous BUCK chip N3, and the other end is connected to the differential telemetry amplifier output pin DIFFOUT of the synchronous BUCK chip N3; one end of the resistor R5 is connected to the error feedback input pin 1 VFB1 of the synchronous BUCK chip N3, and the other end is connected to GND. The positive input pin DIFFP of the differential telemetry amplifier of the synchronous BUCK chip N3 is connected to the second terminal of the inductor L1; the negative input pin DIFFN of the differential telemetry amplifier of the synchronous BUCK chip N3 is connected to GND; the enable control pin 1 RUN1 of the synchronous BUCK chip N3 is connected to the indicator pin PGOOD of the voltage conversion module N1. One end of the resistor R10 is connected to the indicator pin PGOOD of the synchronous BUCK chip N3, and the other end is connected to the output pin INTVcc of the internal voltage regulator of the synchronous BUCK chip N3. The clock output pin CLKOUT of the synchronous BUCK chip N3 is connected to the mode selection pin MODE / PLLIN of the synchronous BUCK chip N4; the mode selection pin MODE / PLLIN of the synchronous BUCK chip N3 is connected to GND; the positive input pin DIFFP of the differential telemetry amplifier of the synchronous BUCK chip N4 is connected to GND; the negative input pin DIFFN of the differential telemetry amplifier of the synchronous BUCK chip N4 is connected to GND. One end of the resistor R7 is connected to the frequency pin FREQ of the synchronous BUCK chip N3, and the other end is connected to GND; One end of resistor R8 is connected to the second end of inductor L1, and the other end is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronization BUCK chip N3; resistor R9 is connected in parallel with capacitor C8; one end of capacitor C9 is connected to the second end of inductor L1, and the other end is connected to GND; the negative input pin sense1- of the current sensing comparator 1 of the synchronization BUCK chip N3 is connected to the second end of inductor L1; the second end of inductor L1 is connected to the circuit input terminal Vo. One end of capacitor C10 is connected to the second end of inductor L1, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronization BUCK chip N3; resistor R11 is connected in parallel with capacitor C10; one end of capacitor C11 is connected to the second end of inductor L1, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronization BUCK chip N3 is connected to the second end of inductor L2; the second end of inductor L2 is connected to the circuit input terminal Vo. One end of resistor R15 is connected to the indicator pin PGOOD of the synchronous BUCK chip N4, and the other end is connected to the output pin INTVcc of the internal voltage regulator of the synchronous BUCK chip N4; one end of resistor R17 is connected to the frequency pin FREQ of the synchronous BUCK chip N4, and the other end is connected to GND. One end of capacitor C12 is connected to the second end of inductor L3, and the other end is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronization BUCK chip N4; resistor R14 is connected in parallel with capacitor C12; one end of capacitor C14 is connected to the second end of inductor L3, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronization BUCK chip N4 is connected to the second end of inductor L3; the second end of inductor L3 is connected to the circuit input terminal Vo. One end of capacitor C16 is connected to the second end of inductor L3, and the other end is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronization BUCK chip N4; resistor R14 is connected in parallel with capacitor C16; one end of capacitor C17 is connected to the second end of inductor L3, and the other end is connected to GND; the negative input pin sense2- of the current sensing comparator 2 of the synchronization BUCK chip N4 is connected to the second end of inductor L4; the second end of inductor L4 is connected to the circuit input terminal Vo; One end of resistor R19 is connected to the input power supply terminal Vin of the sync BUCK chip N4, and the other end is connected to the cathode of the Zener diode D5 and the base of the transistor Q9; the anode of the Zener diode D5 is connected to GND; the collector of the transistor Q9 is connected to the input power supply terminal Vin of the sync BUCK chip N4, and the emitter is connected to the network Vcc; one end of capacitor C18 is connected to the network Vcc, and the other end is connected to GND.

6. The high-efficiency, high-ratio non-isolated hybrid buck converter circuit according to claim 5, characterized in that, The power conversion unit (4) includes MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q8; The source of MOSFET Q1 is connected to the input power supply terminal Vin of the synchronous BUCK chip N3; the gate of MOSFET Q1 is connected to the high-side gate drive output pin TG1 of the synchronous BUCK chip N3; the source of MOSFET Q1 is connected to the switching node SW1 of the synchronous BUCK chip N3, the first terminal of capacitor C6, the drain of MOSFET Q2, the first terminal of inductor L1, and the first terminal of resistor R8; the second terminal of capacitor C6 is connected to the bootstrap power supply BOOST1 of the synchronous BUCK chip N3; the second terminal of resistor R8 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N3; the gate of MOSFET Q2 is connected to the low-side gate drive output pin BG1 of the synchronous BUCK chip N3; and the source of MOSFET Q2 is connected to GND. The source of MOSFET Q3 is connected to the input power supply terminal Vin of synchronous BUCK chip N3; the gate of MOSFET Q3 is connected to the high-side gate drive output pin 2 TG2 of synchronous BUCK chip N3; the source of MOSFET Q3 is connected to the switching node SW2 of synchronous BUCK chip N3, the first terminal of capacitor C7, the drain of MOSFET Q4, the first terminal of inductor L2, and the first terminal of resistor R12; the second terminal of capacitor C7 is connected to the bootstrap power supply 2 BOOST2 of synchronous BUCK chip N3; the second terminal of resistor R12 is connected to the positive input pin sense2+ of current sensing comparator 2 of synchronous BUCK chip N3; the gate of MOSFET Q4 is connected to the low-side gate drive output pin 2 BG2 of synchronous BUCK chip N3; the source of MOSFET Q4 is connected to GND. The source of MOSFET Q5 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of MOSFET Q5 is connected to the high-side gate drive output pin TG1 of the synchronous BUCK chip N4; the source of MOSFET Q5 is connected to the switching node SW1 of the synchronous BUCK chip N4, the first terminal of capacitor C13, the drain of MOSFET Q6, the first terminal of inductor L3, and the first terminal of resistor R13; the second terminal of capacitor C13 is connected to the bootstrap power supply BOOST1 of the synchronous BUCK chip N4; the second terminal of resistor R13 is connected to the positive input pin sense1+ of the current sensing comparator 1 of the synchronous BUCK chip N4; the gate of MOSFET Q6 is connected to the low-side gate drive output pin BG1 of the synchronous BUCK chip N4; the source of MOSFET Q6 is connected to GND; the source of MOSFET Q7 is connected to the input power supply terminal Vin of the synchronous BUCK chip N4; the gate of MOSFET Q7 is connected to the high-side gate drive output pin TG1 of the synchronous BUCK chip N4. TG2 is connected; the source of the MOSFET Q7 is connected to the switching node SW2 of the synchronous BUCK chip N4, the first terminal of capacitor C15, the drain of the MOSFET Q8, the first terminal of inductor L4, and the first terminal of resistor R18; the second terminal of capacitor C15 is connected to the bootstrap power supply 2 BOOST2 of the synchronous BUCK chip N4; the second terminal of resistor R18 is connected to the positive input pin sense2+ of the current sensing comparator 2 of the synchronous BUCK chip N4; the gate of the MOSFET Q8 is connected to the low-side gate drive output pin 2 BG2 of the synchronous BUCK chip N4; the source of the MOSFET Q8 is connected to GND.

7. The high-efficiency, high-ratio non-isolated hybrid buck converter circuit according to claim 6, characterized in that, The feedback compensation unit (10) includes capacitor C3, capacitor C4, capacitor C5 and resistor R4; One end of capacitor C3 is connected to the soft-start input pin 1 TK / SS1 of the synchronous BUCK chip N3, and the other end is connected to GND; one end of capacitor C4 is connected to GND, and the other end is connected to the second end of resistor R4; the first end of resistor R4 is connected to the error amplifier compensation pin 1 ITH1 of the voltage conversion module N1; one end of capacitor C5 is connected to the error amplifier compensation pin 1 ITH1 of the synchronous BUCK chip N3, and the other end is connected to GND.

8. The high-efficiency, high-ratio non-isolated hybrid buck converter circuit according to claim 7, characterized in that, The circuit also includes an adjustable resistor RSET; the two ends of the adjustable resistor RSET are connected to the circuit Trim terminal and the ground terminal GND, respectively; by adjusting the resistance value of the adjustable resistor RSET, different output voltages are determined, forming an adjustment circuit closed loop.

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