On-chip oscillator
By using preset resistors and capacitors in the on-chip oscillator, and controlling the start and operation of the ring oscillator through voltage, the problem of the oscillation frequency being affected by process parameters and temperature is solved, and a more accurate oscillation frequency and lower power consumption are achieved.
Patent Information
- Application Number
- CN202411907967.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-05-06
AI Technical Summary
The oscillation frequency of existing on-chip oscillators is greatly affected by process parameters and temperature, resulting in poor circuit stability.
The oscillation signal of the on-chip oscillator is controlled by preset resistors and capacitors, achieving a more accurate oscillation frequency, and controlling the start and operation of the ring oscillator through different voltages.
It realizes low temperature drift and more accurate oscillation frequency, expands the operating voltage range, reduces power consumption, reduces area, and simplifies the structure for easy integration.
Smart Images
Figure CN119945326A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to an on-chip oscillator. Background Art
[0002] At present, the research on on-chip oscillators using CMOS technology mainly focuses on LC oscillators and ring oscillators. Among them, the structure of the ring oscillator is simpler than that of the LC oscillator and is more conducive to integration, but the oscillation frequency of the ring oscillator is greatly affected by process parameters and temperature, which has a great impact on the stability of the circuit. Summary of the invention
[0003] The purpose of the embodiments of the present disclosure is to provide an on-chip oscillator, which controls the oscillation signal of the on-chip oscillator by pre-setting resistors and capacitors to obtain a more accurate oscillation frequency and achieve low temperature drift. In addition, the startup and operation of the ring oscillator are controlled by different voltages, so that the operating voltage range of the on-chip oscillator is wider, the power consumption is lower, the area is smaller, the structure is simple, and it is easy to integrate.
[0004] In order to achieve the above-mentioned purpose, the first aspect of the embodiment of the present disclosure provides an on-chip oscillator, comprising: a voltage generating circuit, a voltage limiting circuit, a charge-discharge circuit and a ring oscillator. The voltage generating circuit is configured to generate a turn-on voltage and a charge voltage based on a reference current and a preset resistor, and provide the turn-on voltage to the voltage limiting circuit via a first node, and provide the charge voltage to the charge-discharge circuit via a second node; the voltage limiting circuit is configured to generate a required voltage for the ring oscillator based on the turn-on voltage and the reference voltage, wherein when the ring oscillator is in a startup state, the required voltage is a startup voltage required for the ring oscillator to start, and when the ring oscillator is in a working state, the required voltage is an oscillator working voltage, and the required voltage is provided to the ring oscillator via a third node, wherein the startup voltage is less than the oscillator working voltage; the ring oscillator is configured to output an oscillation signal according to the startup voltage and the oscillator working voltage; the charge-discharge circuit comprises a second capacitor, and the charge-discharge circuit is configured to charge and discharge the second capacitor according to the charge voltage and the oscillation signal.
[0005] In some embodiments of the present disclosure, the voltage generating circuit includes: first, second, and third current mirror circuits and a resistance module. The first current mirror circuit is configured to mirror the reference current and provide it to the third current mirror circuit; the second current mirror circuit is configured to mirror the reference current and provide it to the third current mirror circuit, while generating the on-voltage; the resistance module is configured to provide the preset resistance to the third current mirror circuit; the third current mirror circuit is configured to generate the charging voltage according to the preset resistance and the reference current obtained by mirroring.
[0006] In some embodiments of the present disclosure, the voltage limiting circuit includes: a voltage following circuit and an oscillator voltage limiting circuit. The voltage following circuit is configured to follow the conduction voltage to obtain a following voltage; the oscillator voltage limiting circuit is configured to generate the starting voltage less than the following voltage when the ring oscillator is in a starting state, and to generate the oscillator working voltage equal to the following voltage when the ring oscillator is in a working state.
[0007] In some embodiments of the present disclosure, the first current mirror circuit includes: a first transistor and a second transistor, wherein the control electrode of the first transistor is coupled to the second electrode of the first transistor, the control electrode of the second transistor and the input end of the reference current, and the first electrode of the first transistor is coupled to the first voltage end; the first electrode of the second transistor is coupled to the first voltage end, and the second electrode of the second transistor is coupled to the output end of the first current mirror circuit; the second current mirror circuit includes: a first transistor and a third transistor, wherein the control electrode of the third transistor is coupled to the input end of the reference current, the first electrode of the third transistor is coupled to the first voltage end, and the second electrode of the third transistor is coupled to the first node; the third current mirror circuit includes: a fourth transistor, a fifth transistor and a first capacitor, wherein the control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor, the control electrode of the fifth transistor and the output end of the first current mirror circuit, and the first electrode of the fourth transistor is coupled to the first end of the resistor module; the first electrode of the fifth transistor is coupled to the second node, and the second electrode of the fifth transistor is coupled to the first node; the first end of the first capacitor is coupled to the second node, and the second end of the first capacitor is coupled to the second voltage end.
[0008] In some embodiments of the present disclosure, the second end of the resistor module is coupled to the second voltage end, and the resistor module includes a first resistor and a parallel resistor group. The first end of the first resistor is coupled to the first end of the resistor module, the second end of the first resistor is coupled to the first end of the parallel resistor group; the second end of the parallel resistor group is coupled to the second end of the resistor module; and the resistance value of the first resistor is greater than the resistance value of the resistors in the parallel resistor group.
[0009] In some embodiments of the present disclosure, the voltage follower circuit includes: a sixth transistor, wherein a control electrode of the sixth transistor is coupled to the first node, a first electrode of the sixth transistor is coupled to an output terminal of the follower voltage, and a second electrode of the sixth transistor is coupled to the first voltage terminal.
[0010] In some embodiments of the present disclosure, the oscillator voltage limiting circuit includes: a seventh transistor, wherein a control electrode of the seventh transistor is coupled to an input terminal of the reference voltage, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to an output terminal of the follower voltage.
[0011] In some embodiments of the present disclosure, the charge and discharge circuit further includes: an eighth transistor and a ninth transistor. The control electrode of the eighth transistor is coupled to the control electrode of the ninth transistor and the output end of the ring oscillator, the first electrode of the eighth transistor is coupled to the second node, the second electrode of the eighth transistor is coupled to the second electrode of the ninth transistor and the first end of the second capacitor; the first electrode of the ninth transistor is coupled to the second voltage end; and the second end of the second capacitor is coupled to the second voltage end.
[0012] In some embodiments of the present disclosure, the ring oscillator includes an odd number of inverters connected end to end, each inverter is connected to the input of the next inverter through its output, and the output of the last inverter is coupled to the input of the first inverter and the output of the oscillation signal.
[0013] In some embodiments of the present disclosure, the on-chip oscillator also includes a shaping circuit, an input end of the shaping circuit is coupled to an output end of the ring oscillator, an output end of the shaping circuit serves as an output end of the oscillation signal, and the shaping circuit is configured to correct the output signal of the ring oscillator.
[0014] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the accompanying drawings:
[0016] Figure 1 is a schematic block diagram of an on-chip oscillator according to an embodiment of the present disclosure;
[0017] Figure 2 is an exemplary circuit diagram of an on-chip oscillator according to an embodiment of the present disclosure;
[0018] Figure 3 is an exemplary circuit diagram of a resistance module of a voltage generating circuit in an on-chip oscillator according to an embodiment of the present disclosure.
[0019] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION
[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.
[0021] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as a control electrode, and the remaining two ends of the MOS transistor are referred to as a first electrode and a second electrode, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).
[0022] Figure 1 FIG. 1 shows a schematic block diagram of an on-chip oscillator 100 provided according to an embodiment of the present disclosure. Figure 1 As shown, the on-chip oscillator 100 may include: a voltage generating circuit 110 , a voltage limiting circuit 120 , a charging and discharging circuit 130 and a ring oscillator 140 .
[0023] The voltage generating circuit 110 can be coupled to the voltage limiting circuit 120, the charge and discharge circuit 130, the first voltage terminal V1, and the second voltage terminal V2. The voltage generating circuit 110 is configured to generate a conduction voltage V4 and a charge voltage V6 based on a reference current IBIAS and a preset resistor, and provide the conduction voltage V4 to the voltage limiting circuit 120 via a first node N1, and provide the charge voltage V6 to the charge and discharge circuit 130 via a second node N2.
[0024] The voltage limiting circuit 120 can be coupled to the voltage generating circuit 110, the ring oscillator 140, the reference voltage input terminal VBIAS and the first voltage terminal V1. The voltage limiting circuit 120 is configured to generate a required voltage V7 of the ring oscillator based on the conduction voltage V4 and the reference voltage VBIAS, wherein when the ring oscillator is in a startup state, the required voltage is a startup voltage required for starting the ring oscillator, and when the ring oscillator is in a working state, the required voltage is an oscillator working voltage, and the required voltage V7 is provided to the ring oscillator 140 via the third node N3, wherein the startup voltage is less than the oscillator working voltage.
[0025] The ring oscillator 140 can be coupled to the voltage limiting circuit 120, the second voltage terminal V2, and the output terminal CK_OUT of the oscillation signal. The ring oscillator 140 is configured to output the oscillation signal CK_OUT according to the startup voltage and the oscillator operating voltage.
[0026] The charge-discharge circuit 130 may be coupled to the voltage generating circuit 110, the ring oscillator 140 and the second voltage terminal V2. The charge-discharge circuit 130 may include a second capacitor, and the charge-discharge circuit 130 is configured to charge and discharge the second capacitor according to the charging voltage V6 and the oscillation signal CK_OUT.
[0027] Through the on-chip oscillator 100 of the embodiment of the present disclosure, the oscillation signal of the on-chip oscillator is controlled by using preset resistors and capacitors, thereby achieving low temperature drift and more accurate oscillation frequency. In addition, a smaller starting voltage is used to start the ring oscillator in the on-chip oscillator, and when the ring oscillator is in a working state, an oscillator working voltage greater than the starting voltage is used, thereby making the on-chip oscillator have a wider working voltage range, lower power consumption, smaller area, simple structure, and easy integration.
[0028] Figure 2 FIG. 1 shows an exemplary circuit diagram of an on-chip oscillator 100 provided according to an embodiment of the present disclosure. Figure 2As shown, the voltage generating circuit 110 may include: first, second, and third current mirror circuits 111, 112, and 113 and a resistor module 114. The first current mirror circuit 111 is configured to mirror the reference current IBIAS and provide it to the third current mirror circuit 113. The second current mirror circuit 112 is configured to mirror the reference current IBIAS and provide it to the third current mirror circuit 113, while generating the on-voltage V4. The resistor module 114 is configured to provide the preset resistor to the third current mirror circuit 113. The third current mirror circuit 113 is configured to generate the charging voltage V6 according to the preset resistor and the reference current IBIAS obtained by mirroring.
[0029] The first current mirror circuit 111 may include: a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is coupled to the second electrode of the first transistor M1, the control electrode of the second transistor M2 and the input terminal of the reference current IBIAS, and the first electrode of the first transistor M1 is coupled to the first voltage terminal V1. The first electrode of the second transistor M2 is coupled to the first voltage terminal V1, and the second electrode of the second transistor M2 is coupled to the output terminal of the first current mirror circuit 111. The second current mirror circuit 112 may include: a first transistor M1 and a third transistor M3. The control electrode of the third transistor M3 is coupled to the input terminal of the reference current IBIAS, the first electrode of the third transistor M3 is coupled to the first voltage terminal V1, and the second electrode of the third transistor M3 is coupled to the first node N1. The third current mirror circuit 113 may include: a fourth transistor M4, a fifth transistor M5 and a first capacitor C1. The control electrode of the fourth transistor M4 is coupled to the second electrode of the fourth transistor M4, the control electrode of the fifth transistor M5 and the output end of the first current mirror circuit 111, the first electrode of the fourth transistor M4 is coupled to the first end of the resistor module 114; the first electrode of the fifth transistor M5 is coupled to the second node N2, and the second electrode of the fifth transistor M5 is coupled to the first node N1; the first end of the first capacitor C1 is coupled to the second node N2, and the second end of the first capacitor C1 is coupled to the second voltage end V2. The second end of the resistor module 114 is coupled to the second voltage end V2. The on-chip oscillator 100 in the embodiment of the present disclosure generally adopts frequency jittering technology to reduce EMI (Electromagnetic Interference), so the resistor module can adopt the following method: Figure 3In the structure shown, the resistor module 114 may include a first resistor R1 and a parallel resistor group R2k. The first end of the first resistor R1 is coupled to the first end of the resistor module 114, and the second end of the first resistor R1 is coupled to the first end of the parallel resistor group R2k; the second end of the parallel resistor group R2k is coupled to the second end of the resistor module 114; the resistance of the first resistor R1 is greater than the resistance of the resistors in the parallel resistor group R2k. In the embodiment of the present disclosure, the number and resistance of the resistors in the parallel resistor group R2k can be determined according to the frequency range of the frequency jitter.
[0030] The voltage limiting circuit 120 may include: a voltage follower circuit 121 and an oscillator voltage limiting circuit 122. The voltage follower circuit 121 is configured to follow the conduction voltage V4 to obtain a follow voltage V5; the oscillator voltage limiting circuit 122 is configured to generate the start-up voltage less than the follow voltage V5 when the ring oscillator 140 is in the start-up state, and generate the oscillator working voltage equal to the follow voltage V5 when the ring oscillator is in the working state. The voltage follower circuit 121 may include: a sixth transistor M6. The control electrode of the sixth transistor M6 is coupled to the first node N1, the first electrode of the sixth transistor M6 is coupled to the output end of the follow voltage 121, and the second electrode of the sixth transistor M6 is coupled to the first voltage end V1. The oscillator voltage limiting circuit 122 may include: a seventh transistor M7. The control electrode of the seventh transistor M7 is coupled to the input end of the reference voltage VBIAS, the first electrode of the seventh transistor M7 is coupled to the third node N3, and the second electrode of the seventh transistor M7 is coupled to the output end of the follow voltage 121.
[0031] The charge-discharge circuit 130 further includes: an eighth transistor M8 and a ninth transistor M9. The control electrode of the eighth transistor M8 is coupled to the control electrode of the ninth transistor M9 and the output end of the ring oscillator 140, the first electrode of the eighth transistor M8 is coupled to the second node N2, the second electrode of the eighth transistor M8 is coupled to the second electrode of the ninth transistor M9 and the first end of the second capacitor C2; the first electrode of the ninth transistor M9 is coupled to the second voltage end V2; and the second end of the second capacitor C2 is coupled to the second voltage end V2.
[0032] The ring oscillator 140 may include an odd number of inverters connected end to end, each inverter is connected to the input of the next inverter through its output, and the output of the last inverter is coupled to the input of the first inverter and the output of the oscillation signal CK_OUT. In the embodiment of the present disclosure, the ring oscillator may include three, five, or other odd number of inverters, such as Figure 2As shown, taking a three-stage cascade of odd-numbered inverters as an example, the three-stage cascade of odd-numbered inverters includes: a first-stage inverter, a second-stage inverter, and a third-stage inverter. The first-stage inverter includes a tenth transistor M10 and an eleventh transistor M11, the control electrode of the tenth transistor M10 and the control electrode of the eleventh transistor M11 are coupled as the input terminal of the first-stage inverter, and the second electrode of the tenth transistor M10 and the second electrode of the eleventh transistor M11 are coupled as the output terminal of the first-stage inverter; the second-stage inverter includes a twelfth transistor M12 and a thirteenth transistor M13, the control electrode of the twelfth transistor M12 and the control electrode of the thirteenth transistor M13 are coupled as the input terminal of the second-stage inverter, and the second electrode of the twelfth transistor M12 and the second electrode of the thirteenth transistor M13 are coupled as the output terminal of the second-stage inverter; the third-stage inverter includes a fourteenth transistor M14 and a fifteenth transistor M15, the control electrode of the fourteenth transistor M14 and the control electrode of the fifteenth transistor M15 are coupled as the input terminal of the third-stage inverter, and the second electrode of the fourteenth transistor M14 and the second electrode of the fifteenth transistor M15 are coupled as the output terminal of the third-stage inverter. Among them, the first electrode of the tenth transistor M10, the first electrode of the twelfth transistor M12 and the first electrode of the fourteenth transistor M14 are all coupled to the third node N3, and the first electrode of the eleventh transistor M11, the first electrode of the thirteenth transistor M13 and the first electrode of the fifteenth transistor M15 are all coupled to the second voltage terminal V2.
[0033] In order to improve the performance of the on-chip oscillator in the embodiment of the present disclosure, as Figure 2 As shown, the on-chip oscillator 100 may further include a shaping circuit 150, the input end of the shaping circuit 150 is coupled to the output end of the ring oscillator 140, the output end of the shaping circuit 150 serves as the output end of the oscillation signal CK_OUT, the power supply end of the shaping circuit 150 may be coupled to the third voltage end V3, and the shaping circuit 150 is configured to correct the output signal of the ring oscillator 140. The shaping circuit includes at least one level of shaping module, and the specific circuit structure of each shaping module is not limited in the embodiment of the present disclosure, as long as it can correct the output signal of the ring oscillator 140, for example, it can be a CMOS inverter or a Schmitt trigger, etc. Figure 2 As shown, when the shaping circuit 150 includes two-stage shaping modules, the output signal V8 of the first-stage shaping module can be used as the input of the control electrodes of the eighth transistor M8 and the ninth transistor M9 in the charge and discharge circuit 130, and the output signal CK_OUT′ of the second-stage shaping module is used as the oscillation signal CK_OUT of the on-chip oscillator 100.
[0034] exist Figure 2 and Figure 3 In the example, a VDD1 voltage signal is input from the first voltage terminal V1, for example, 5V, the second voltage terminal V2 is grounded, and the third voltage terminal V3 inputs a VDD1 voltage signal or a VDD2 voltage signal. Further, in order to reduce the power consumption of the shaping circuit 150, the third voltage terminal V3 can input a VDD2 voltage signal, for example, 1.8V. The input terminal of the reference current IBIAS can be coupled to a reference current source, and the input terminal of the reference voltage VBIAS inputs a bias voltage, which is generally set to 2V. In addition, the capacitance of the first capacitor C1 is much greater than the capacitance of the second capacitor C2. The first transistor M1 to the third transistor M3, the eighth transistor M8, the tenth transistor M10, the twelfth transistor M12, and the fourteenth transistor M14 are all PMOS transistors. The fourth transistor M4 to the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, the thirteenth transistor M13, and the fifteenth transistor M15 are all NMOS transistors. In addition, in order to improve the stability and consistency of the on-chip oscillator 100, the transistors in the ring oscillator 140 are all low-voltage transistors. Those skilled in the art should understand that based on the above-mentioned inventive concept Figure 2 , 3 Variations of the circuit shown in the figure should also fall within the scope of protection of the present disclosure. In this variation, the transistor and the voltage terminal may also have the same Figure 2 , 3 Examples of different setups are shown.
[0035] Combine the following Figure 2 , 3 The working process of the on-chip oscillator 100 according to the embodiment of the present disclosure is explained by way of example.
[0036] In the embodiment of the present disclosure, since there is a current mirror circuit in the voltage generating circuit 110, and the sizes of the first transistor M1, the second transistor M2 and the third transistor M3 are the same, and the sizes of the fourth transistor M4 and the fifth transistor M5 are also the same, the current flowing through the first transistor M1 is the reference current IBIAS, and the current flowing through the fourth transistor M4 and the fifth transistor M5 is also the reference current IBIAS, and the source voltages of the fourth transistor M4 and the fifth transistor M5 are equal. When the equivalent resistance value of the resistance module is R, the charging voltage V6 can be expressed by the following formula (1):
[0037] V6=R*IBIAS Formula (1)
[0038] Assuming that the oscillation frequency of the ring oscillator is f, the charge of the second capacitor C2 is equal in one cycle (assuming its capacitance is C2), the following formulas (2) and (3) can be obtained:
[0039] C2*R*IBIAS=IBIAS*1 / f Formula (2)
[0040] f=1 / (R*C2) Formula (3)
[0041] Therefore, the oscillation frequency output by the on-chip oscillator 100 in the embodiment of the present disclosure is determined only by the low temperature drift resistor R and the second capacitor C2, that is, the low temperature drift oscillation frequency is achieved. In addition, since the oscillation frequency is determined by the above two values, a higher and more accurate oscillation frequency can be easily obtained.
[0042] When the ring oscillator is in the startup state, the gate voltage of the third transistor M3 is extremely low, so it is turned on, and the on-voltage V4 is equal to the input voltage of the first voltage terminal V1, that is, V4=VDD1, and the follower voltage V5 follows the change of the on-voltage V4. Because there is a sixth transistor M6 between the follower voltage V5 and the on-voltage V4, the follower voltage V5 is smaller than the on-voltage V4 by the gate-source voltage VGS of the sixth transistor M6. Because the gate-source voltage VGS is generally a fixed value, and there are inherent characteristics of the transistor, the follower voltage V5≈VDD1, and the seventh transistor M7 works in the saturation region at this time, so the required voltage V7 of the ring oscillator is the starting voltage required for the ring oscillator to start, and the starting voltage is much smaller than the follower voltage V5, so that the ring oscillator can start quickly. When the ring oscillator is in the working state, the seventh transistor M7 works in the deep linear region, so the required voltage V7 of the ring oscillator is the oscillator working voltage, which is basically equal to the follower voltage V5. Due to the presence of the seventh transistor M7, the starting voltage of the ring oscillator can be set to a lower value, for example, 1.3-1.5V, which can not only widen the working range of the input voltage of the first voltage terminal V1, but also improve the starting speed of the ring oscillator. In addition, since the transistors in the ring oscillator are all low-voltage transistors, the power consumption of the entire on-chip oscillator can be reduced and the overall area of the on-chip oscillator can be reduced.
[0043] The on-chip oscillator described in the embodiments of the present disclosure can be applied in the fields of digital isolators, isolated power supplies, etc., and no excessive restrictions are made in the present disclosure.
[0044] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.
[0045] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.
[0046] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.
Claims
1. An on-chip oscillator, characterized in that: include: Voltage generating circuit, voltage limiting circuit, charging and discharging circuit and ring oscillator, The voltage generating circuit is configured to generate a conduction voltage and a charging voltage based on a reference current and a preset resistance, and provide the conduction voltage to the voltage limiting circuit via a first node, and provide the charging voltage to the charge-discharge circuit via a second node; The voltage limiting circuit is configured to generate a required voltage for the ring oscillator based on the conduction voltage and a reference voltage, wherein when the ring oscillator is in a startup state, the required voltage is a startup voltage required for starting the ring oscillator, and when the ring oscillator is in a working state, the required voltage is an oscillator working voltage, and the required voltage is provided to the ring oscillator via a third node, wherein the startup voltage is less than the oscillator working voltage; The ring oscillator is configured to output an oscillation signal according to the start-up voltage and the oscillator operating voltage; The charge and discharge circuit includes a second capacitor, and the charge and discharge circuit is configured to charge and discharge the second capacitor according to the charging voltage and the oscillation signal.
2. The on-chip oscillator according to claim 1, characterized in that The voltage generating circuit comprises: first, second and third current mirror circuits and a resistance module. wherein the first current mirror circuit is configured to mirror the reference current and provide it to the third current mirror circuit; The second current mirror circuit is configured to mirror the reference current and provide it to the third current mirror circuit, while generating the on-voltage; The resistance module is configured to provide the preset resistance to the third current mirror circuit; The third current mirror circuit is configured to generate the charging voltage according to the preset resistor and the reference current obtained by mirroring.
3. The on-chip oscillator according to claim 1, characterized in that: The voltage limiting circuit comprises: a voltage follower circuit and an oscillator voltage limiting circuit; The voltage follower circuit is configured to follow the conduction voltage to obtain a following voltage; The oscillator voltage limiting circuit is configured to generate the startup voltage which is less than the following voltage when the ring oscillator is in the startup state, and to generate the oscillator operating voltage which is equal to the following voltage when the ring oscillator is in the operating state.
4. The on-chip oscillator according to claim 2, characterized in that: The first current mirror circuit comprises: a first transistor and a second transistor, wherein a control electrode of the first transistor is coupled to a second electrode of the first transistor, a control electrode of the second transistor and an input terminal of the reference current, a first electrode of the first transistor is coupled to a first voltage terminal; a first electrode of the second transistor is coupled to the first voltage terminal, and a second electrode of the second transistor is coupled to an output terminal of the first current mirror circuit; The second current mirror circuit comprises: a first transistor and a third transistor, wherein a control electrode of the third transistor is coupled to an input terminal of the reference current, a first electrode of the third transistor is coupled to a first voltage terminal, and a second electrode of the third transistor is coupled to the first node; The third current mirror circuit includes: a fourth transistor, a fifth transistor and a first capacitor, wherein the control electrode of the fourth transistor is coupled to the second electrode of the fourth transistor, the control electrode of the fifth transistor and the output end of the first current mirror circuit, and the first electrode of the fourth transistor is coupled to the first end of the resistance module; the first electrode of the fifth transistor is coupled to the second node, and the second electrode of the fifth transistor is coupled to the first node; the first end of the first capacitor is coupled to the second node, and the second end of the first capacitor is coupled to the second voltage end.
5. The on-chip oscillator according to claim 2, characterized in that: The second end of the resistance module is coupled to the second voltage end, and the resistance module includes a first resistor and a parallel resistor group. Wherein, the first end of the first resistor is coupled to the first end of the resistor module, and the second end of the first resistor is coupled to the first end of the parallel resistor group; The second end of the parallel resistor group is coupled to the second end of the resistor module; The resistance of the first resistor is greater than the resistance of the resistors in the parallel resistor group.
6. The on-chip oscillator according to claim 3, characterized in that: The voltage follower circuit comprises: a sixth transistor, The control electrode of the sixth transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the output end of the follower voltage, and the second electrode of the sixth transistor is coupled to the first voltage end.
7. The on-chip oscillator according to claim 3, characterized in that: The oscillator voltage limiting circuit comprises: a seventh transistor, The control electrode of the seventh transistor is coupled to the input end of the reference voltage, the first electrode of the seventh transistor is coupled to the third node, and the second electrode of the seventh transistor is coupled to the output end of the follower voltage.
8. The on-chip oscillator according to claim 1, characterized in that: The charge and discharge circuit further includes: an eighth transistor and a ninth transistor, wherein the control electrode of the eighth transistor is coupled to the control electrode of the ninth transistor and the output end of the ring oscillator, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the second electrode of the ninth transistor and the first end of the second capacitor; The first electrode of the ninth transistor is coupled to the second voltage terminal; The second terminal of the second capacitor is coupled to the second voltage terminal.
9. The on-chip oscillator according to claim 1, characterized in that: The ring oscillator includes an odd number of inverters connected end to end, each inverter is connected to the input of the next inverter through its output, and the output of the last inverter is coupled to the input of the first inverter and the output of the oscillation signal.
10. The on-chip oscillator according to claim 1, characterized in that: The on-chip oscillator further comprises a shaping circuit, an input end of the shaping circuit is coupled to an output end of the ring oscillator, an output end of the shaping circuit serves as an output end of the oscillation signal, and the shaping circuit is configured to modify the output signal of the ring oscillator.