Airspace adaptive filtering method and device based on FPGA and power inversion criterion

Abstract

The invention discloses an airspace adaptive filtering method and device based on an FPGA (Field Programmable Gate Array) and a power inversion criterion, and relates to the field of signal processing. Comprising an array signal data preprocessing module, an auto-covariance matrix calculation module, a cross-covariance matrix calculation module, an optimal weight vector calculation module, a floating-point number-to-fixed-point number module and an optimal weight vector weighting module. Deep nulling can be formed in the coming direction of the suppressive interference signals, the suppressive interference signals occurring in the communication process are effectively filtered out, and expected signals are reserved; the method is high in calculation precision, small in resource occupation, extremely high in real-time processing capacity, high in module integration degree, convenient to transplant on an existing spread spectrum communication receiver, and still high in interference suppression capacity in a complex or dynamically changing interference environment.

Description

Technical Field

[0001] The present invention belongs to the field of array signal processing, and in particular relates to a spatial domain adaptive filtering FPGA algorithm acceleration module and a device based on a power inversion criterion. Background Art

[0002] In spread spectrum communication systems, electromagnetic interference threats are a major challenge to communication integrity and reliability, especially intentional suppressive interference, which seriously affects the performance of spread spectrum communication systems, increases the bit error probability of spread spectrum communication systems, and even causes the spread spectrum communication systems to lose lock.

[0003] Spatial adaptive filtering is a technology that combines adaptive signal processing and array antenna technology. When the useful signal and the interference signal come from different directions in space, the weighted parameters of each element antenna are sensitively controlled to adaptively adjust the antenna's directivity pattern, form a null in the interference direction, and ensure that the gain of the useful signal is not affected. This method reduces the power of the interference signal entering the receiver, improves the interference-to-noise ratio of the system, and achieves the purpose of eliminating interference.

[0004] Spatial adaptive filtering based on the power inversion criterion is suitable for processing situations where the expected signal level is low and the signal-to-interference ratio (SINR) is less than 0dB. The total output power is minimized by appropriately adjusting the weights of the array antenna. In spread spectrum communication systems, since the power of the expected signal is very low and almost submerged in the environmental noise, the algorithm will suppress the interference signal with stronger power by minimizing the output power. A deep null is formed in the direction from which the interference signal comes, while maintaining a relatively flat response in the direction of the useful signal. This means that the interference signal is effectively suppressed, while the useful signal remains as unchanged as possible. Thereafter, the spread spectrum communication receiver further enhances the signal through subsequent processing steps such as despreading, thereby improving the final signal-to-interference ratio. At the same time, spatial adaptive filtering based on the power inversion criterion does not require the exact structure or arrival angle of the signal to be known in advance, which makes it particularly suitable for scenarios where signal parameters may be unknown or difficult to predict, such as in complex or dynamically changing interference environments.

[0005] The spatial adaptive filtering algorithm includes the calculation of the sampling signal covariance matrix, the calculation of the optimal weight vector, and the sampling signal weighting step. Most of the current spatial adaptive filtering algorithms are implemented on CPU and DSP processors. Due to the limitation of serial computing speed, such processors cannot meet the real-time requirements of the algorithm. With the development of semiconductor technology, FPGA integrates more and more configurable logic resources, various external bus interfaces and rich internal RAM resources. At the same time, its parallel operation characteristics make it more flexible in implementing various algorithms. Therefore, using FPGA to accelerate the implementation of spatial adaptive filtering algorithms has gradually become a trend. Summary of the invention

[0006] In view of the technical problem of poor real-time performance in implementing the existing spatial adaptive filtering algorithm, the present invention proposes a spatial adaptive filtering FPGA algorithm acceleration module and device based on the power inversion criterion. Combining the structural characteristics of the spatial adaptive filtering algorithm and making full use of the FPGA parallel operation characteristics, the real-time performance of the spatial adaptive filtering algorithm is guaranteed without losing data accuracy, and the repressive interference can be effectively suppressed.

[0007] In order to achieve the above-mentioned invention object, the following technical scheme is adopted:

[0008] A spatial domain adaptive filtering method based on FPGA and power inversion criterion comprises the following steps:

[0009] Step 1: Convert the radio frequency signal received by the array antenna into a digital intermediate frequency signal, and convert the obtained digital intermediate frequency signal from a fixed point number to a single precision floating point number;

[0010] Step 2: Calculate the cross-covariance matrix between the digital intermediate frequency signal of the first element of the array antenna and the digital intermediate frequency signals of other elements And the autocovariance matrix of the digital intermediate frequency signal of other array elements

[0011] Step 3: Use the LDL matrix decomposition method to invert the autocovariance matrix obtained in step 2 Calculate its inverse matrix

[0012] Step 4: The inverse matrix obtained in step 3 The cross-covariance matrix obtained in step 2 is Calculate the optimal weight vector w of the array antenna according to the power inversion criterion;

[0013] Step 5: Use the optimal weight vector w of the array antenna obtained in step 4 to weight the received digital intermediate frequency signal to suppress the interference signal.

[0014] Furthermore, the specific process of step 1 is as follows:

[0015] S11. By configuring each array antenna RF front-end chip, the RF signal received by the array antenna is converted into a digital intermediate frequency signal. Each array antenna generates a set of I / Q signal data. The signal data received by the array antenna is represented as x(n), where x(n) = [x1(n) x2(n) … x M (n)] T It is composed of the received signals of M array antennas, x i (n) represents the signal received by the i-th array antenna;

[0016] S12. The I / Q signal data corresponding to each array antenna is converted to a single-precision floating-point number module, and the on-chip block RAM of the FPGA is used to open a corresponding buffer area for each array antenna signal data. Starting from the starting address of each buffer area, signal data with a length of snapshot number N is stored.

[0017] Furthermore, the specific process of step 2 is as follows:

[0018] S21, record the signal data in the buffer area corresponding to the first array antenna as matrix X1, and record the signal data in the buffer area corresponding to other array antennas as matrix X2, where

[0019] X1=[x1(1) x1(2) … x1(N)]

[0020]

[0021] Calculate the cross-covariance matrix of the digital intermediate frequency signal of the first array element and the digital intermediate frequency signals of other array elements in N represents the number of fast sampling rows of the signal received by the array antenna; There is only one column. When FPGA calculates the multiplication of matrix X2 and matrix X1, it only needs to calculate and multiply each row of matrix X2 with the column of X1, and then add the calculated matrix Element data is stored in the FPGA’s on-chip block RAM;

[0022] S22, because FPGA has the characteristics of parallel operation, in step S21, calculate At the same time, parallel computing On the FPGA, the same matrix multiplication is performed to make X2 and The corresponding rows and columns of Element data is also stored in the FPGA's on-chip block RAM.

[0023] Furthermore, the specific process of step 3 is as follows:

[0024] S31. Calculate the autocovariance matrix Then, using the matrix LDL decomposition principle Among them, if you remember

[0025]

[0026] Then there is

[0027]

[0028] a jj As calculated djj The basis value of , which represents the matrix The diagonal matrix element with the j-th row and j-th column in ;

[0029] l jk , d kk Used for recursive calculation of d jj and l ij ; Among them, l jk represents the matrix element at the jth row and kth column in the lower triangular matrix L obtained by decomposing the matrix LDL; Represented as l jk The conjugate transpose of kk represents the diagonal matrix element at the kth row and kth column in the diagonal matrix D obtained by matrix LDL decomposition;

[0030] d jj Used to construct the diagonal matrix D and calculate l ij , represents the diagonal matrix element of the j-th row and j-th column in the diagonal matrix D obtained by matrix LDL decomposition;

[0031] a i1 As the calculation i1 The basis value of , which represents the matrix The matrix element at row i and column 1 in ;

[0032] l i1 , l ij Used to construct the lower triangular matrix L. Among them, l i1 represents the matrix element at the i-th row and the first column in the lower triangular matrix L obtained by decomposing the matrix LDL; l ij represents the matrix element at the i-th row and j-th column in the lower triangular matrix L obtained by decomposing the matrix LDL;

[0033] Use the FPGA's on-chip block RAM to create two caches for the lower triangular matrix L and the diagonal matrix D. When defining the RAM cache, set the diagonal element values ​​of the lower triangular matrix L to 1. Since the matrix D is a diagonal matrix, it is only necessary to cache the diagonal elements of the matrix D in the form of vectors.

[0034] According to the above formula, when calculating the lower triangular matrix L and the diagonal matrix D in the FPGA, we start from the first column j=1 of the L and D matrices. When the variable k accumulates from 0 to j-1, the corresponding matrix data is continuously taken out from the RAM area of ​​the FPGA to calculate the cumulative sum. Then, d can be calculated jj The value of is stored in the RAM buffer of matrix D;

[0035] At this time, the calculation starts from the i=j+1th row of the lower triangular matrix L. When the variable k accumulates from 0 to j-1, the corresponding matrix data is continuously taken out from the RAM area of ​​FPGA to calculate the cumulative sum Then, calculate l ij The value of is stored in the RAM buffer of matrix L, and i is incremented, and l is calculated in the same way as above. ij , until i=M-1 is calculated; calculate the second column j=2 matrix data of L and D matrices in the above manner until the last column j=M-1 matrix data of L and D matrices is calculated;

[0036] S32. Calculate the inverse matrix L of the lower triangular matrix L according to the lower triangular matrix inversion formula -1

[0037]

[0038] In the formula

[0039]

[0040] r ij Used to construct the inverse matrix L -1 , represents the inverse matrix L -1 The matrix element at row i and column j in

[0041] l ii As the calculation r ij The basis value of represents the diagonal matrix element of the i-th row and i-th column in the lower triangular matrix L.

[0042] l ik 、r kj Used for recursive calculation of r ij , l ik represents the matrix element in the i-th row and k-th column of the lower triangular matrix L; r kj Represents the inverse matrix L -1 The matrix element at the kth row and jth column in .

[0043] Using the on-chip block RAM of the FPGA as the inverse matrix L -1 After opening a cache area, first start from L -1 The calculation starts from the first row i=1 and the first column j=1 of the matrix. When the variable k accumulates from 0 to i-1, the corresponding matrix data is continuously taken out from the RAM area of ​​FPGA to calculate the cumulative sum. Then, calculate r ij The value is stored in the matrix L -1 In the RAM cache area, let j increase and calculate r in the above way. ij , until j=i-1 is calculated; calculate L in the same way as above -1The second row of the matrix i = 2 matrix data until L is calculated -1 The last row of the matrix i = M-1 matrix data;

[0044] S33. Due to the parallel computing characteristics of FPGA, the inverse matrix L of the lower triangular matrix L is calculated. -1 At the same time, the inverse matrix D of the diagonal matrix D is calculated in parallel -1 . Inverse matrix D -1 is the reciprocal of the diagonal elements of the D matrix, that is

[0045]

[0046] Using the on-chip block RAM of the FPGA as the inverse matrix D -1 After a cache is created, the diagonal element values ​​of matrix D are taken out from the RAM area of ​​FPGA in turn, and the reciprocal is calculated and the result is stored in matrix D. -1 In the RAM cache area;

[0047] S34, calculate the inverse matrix L -1 and D -1 after, The inverse matrix Expressed as Take out the matrix (L H ) -1 The element value of D -1 The element values ​​of (L H ) -1 With D -1 The corresponding rows and columns of the matrix are multiplied and accumulated, and the results are temporarily stored in the on-chip block RAM area of ​​the FPGA. H ) -1 With D -1 After matrix multiplication, the resulting matrix is ​​multiplied by L according to the principle of matrix multiplication. -1 Multiply the calculated matrix Element data is stored in the FPGA's on-chip block RAM.

[0048] Furthermore, the specific process of step 4 is as follows:

[0049] S41. According to the power inversion criterion, the optimal weight vector can be obtained Get the matrix from the FPGA RAM area and The value of is calculated according to the principle of matrix multiplication, so that and The corresponding rows and columns of are multiplied and accumulated to obtain the optimal weight vector w;

[0050] S42, converting the obtained optimal weight vector w from single-precision floating point to fixed point, and storing it using register resources of FPGA.

[0051] Furthermore, the specific process of step 5 is as follows:

[0052] S51. The signal data received by the array antenna is weighted by the optimal weight vector w, that is, each array antenna is multiplied by the corresponding optimal weight and then accumulated to obtain the output signal, that is, the output signal y(n)=w H (n)x(n).

[0053] A spatial domain adaptive filtering device based on FPGA and power inversion criterion, the device comprises: a front-end radio frequency chip, an FPGA algorithm acceleration module, and a signal demodulation module. After receiving the signal, the front-end radio frequency chip transmits it to the FPGA algorithm acceleration module for filtering, and then transmits the filtered signal to the signal demodulation module for demodulation;

[0054] The FPGA algorithm acceleration module includes: an array signal data preprocessing module, an autocovariance matrix calculation module, an autocovariance matrix inversion module, a cross-covariance matrix calculation module, an optimal weight vector calculation module, a floating point number conversion fixed point number module, and an optimal weight vector weighting module.

[0055] The front-end radio frequency chip transmits the received signal to the array signal data preprocessing module and the optimal weight vector weighting module; the array signal data preprocessing module converts the received radio frequency signal into a digital intermediate frequency signal, and then transmits the digital intermediate frequency signal to the autocovariance matrix calculation module and the cross-covariance matrix calculation module respectively; the autocovariance matrix calculation module calculates the autocovariance of the signal and transmits the result to the autocovariance matrix inversion module; the outputs of the autocovariance matrix inversion module and the cross-covariance matrix calculation module are jointly transmitted to the optimal weight vector calculation module; the output of the optimal weight vector calculation module is transmitted to the floating-point number conversion fixed-point number module; the optimal weight vector weighting module weights the received signal of the front-end radio frequency chip and the output of the floating-point number conversion fixed-point number module and outputs the weighted signal to the signal demodulation module.

[0056] Compared with the prior art, the present invention has the following significant advantages: hardware acceleration of a spatial domain adaptive filtering algorithm based on a power inversion criterion in array signal processing is performed, and interference suppression with low power consumption, high energy efficiency and strong real-time performance is achieved according to the high parallel characteristics of FPGA; in the process of calculating the inverse of the sampling autocorrelation matrix, the LDL matrix decomposition inversion principle is used to decompose the sampling matrix into a lower triangular matrix L and a diagonal matrix D and then calculate its inverse matrix, which greatly reduces the complexity of hardware implementation; the present invention converts fixed-point data into floating-point numbers for representation during the entire calculation process, thereby ensuring the accuracy of data during the calculation process; the FPGA algorithm acceleration module and device of the present invention are easy to integrate, have low resource consumption, are convenient to be transplanted on an existing spread spectrum communication receiver, perform interference suppression before demodulating the received signal, and improve the sensitivity of the receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of the structure of a spatial domain adaptive filtering FPGA algorithm acceleration device based on the power inversion criterion provided by the present invention.

[0058] Figure 2 It is a schematic diagram of the array antenna arrangement of the present invention taking a 10-unit linear array as an example.

[0059] Figure 3 It is a structural diagram of the signal data preprocessing module of the present invention.

[0060] Figure 4 It is a structural diagram of the autocorrelation matrix inversion module of the present invention.

[0061] Figure 5 It is a flow chart of FPGA implementation of LDL matrix decomposition of the present invention.

[0062] Figure 6 It is a flow chart of FPGA implementation of L matrix inversion of the present invention.

[0063] Figure 7 It is a flow chart of FPGA implementation of the matrix multiplication module in the autocorrelation matrix inversion module of the present invention.

[0064] Figure 8 It is a structural diagram of the optimal weight vector weighting module of the present invention.

[0065] Fig. 9 It is a directional diagram of the optimal weight vector calculated under an example of the present invention.

[0066] Fig.10 It is the original signal spectrum of the received signal in one embodiment of the present invention.

[0067] Fig.11 It is a signal spectrum of a received signal after spatial domain adaptive filtering in an example of the present invention.

[0068] Fig.12 It is the result of demodulating the received signal after spatial domain adaptive filtering in an example of the present invention.

[0069] Fig.13 This is the resource consumption of the FPGA algorithm acceleration module in an example of the present invention. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0071] like Figure 1 As shown in the figure, a schematic diagram of the results of a spatial adaptive filtering FPGA algorithm acceleration device based on the power inversion criterion is shown, taking a 10-element linear array as an example. Figure 2 As shown, the array spacing d is half of the wavelength of the received signal, and the method comprises the steps of:

[0072] Step 1: Transmit spread spectrum communication signal with a center frequency of 2.361GHz and a bandwidth of 1.023MHZ. The general environmental noise power is -110dBm. The measurement and control signal power is generally about 20dB lower than the noise power, so the measurement and control signal power is -130dBm, and the signal incident angle is 10°; transmit single-tone interference signal with a center frequency of 2.362GHz and a single-tone interference signal power of -60dBm, which is incident on the array element at a direction of 50°; transmit broadband interference signal with a center frequency of 2.361GHz and a bandwidth of 1MHz and a broadband interference signal power of -60dBm, which is incident on the array element at a direction of -30°.

[0073] Step 2: Perform array antenna signal data preprocessing. The signal data preprocessing structure is as follows: Figure 3 As shown, by configuring the AD9361 RF chip under each array antenna, the RF signal received by the array antenna is converted into a digital intermediate frequency signal. At this time, the digital intermediate frequency signal is a 12-bit fixed-point number. The 12-bit fixed-point number obtained by each array antenna is converted into a 32-bit single-precision floating-point number. The on-chip block RAM of the FPGA is used to open a corresponding buffer area for each array antenna signal data. Starting from the starting address of each buffer area, signal data with a length of snapshot number N=32 is stored.

[0074] Step 3: Take out the corresponding data from the first array element signal data buffer and other array element signal data buffers in turn, and calculate the cross-covariance matrix of the first array element signal data and other array element signal data at the same time And the autocovariance matrix of the signal data of other array elements

[0075] Step 4: Use the LDL matrix decomposition inversion method to invert the autocovariance matrix obtained in the third step Calculate its inverse matrix like Figure 4 As shown, the specific steps include: LDL matrix decomposition, L matrix inversion, D matrix inversion, and matrix multiplication.

[0076] Specifically, the calculation flow chart of FPGA to realize LDL matrix decomposition is as follows: Figure 5 As shown; the calculation flow chart of FPGA to realize L matrix inversion is as follows Figure 6 As shown; the calculation flow chart of FPGA matrix multiplication is as follows Figure 7 shown.

[0077] Since the D matrix is ​​a diagonal matrix, its inverse matrix D -1 To calculate the reciprocal of the diagonal elements, take the diagonal element values ​​of matrix D from the RAM area of ​​FPGA, calculate the reciprocal, and store the result in matrix D -1 in the RAM cache area.

[0078] Step 5: Calculate the optimal weight vector based on the power inversion criterion Get the matrix from the FPGA RAM area and The value of is calculated according to the principle of matrix multiplication, so that and The corresponding rows and columns of are multiplied and accumulated to obtain the optimal weight vector w. The obtained optimal weight vector w is converted from single-precision floating point to fixed point and stored in the register resources of FPGA.

[0079] Step 6: Weight the signal data received by the array antenna using the optimal weight vector w, such as Figure 8 As shown, each array day is multiplied by the corresponding optimal weight value and then the cumulative sum is calculated to obtain an output signal, which is then transmitted to the signal demodulation module.

[0080] Figures 9-10 The spectrum of the received signal before and after spatial adaptive filtering. At this time, both single-tone interference and broadband interference are filtered out, and the spread spectrum communication signal is submerged in the noise. Fig.11 is the directional diagram of the optimal weight vector calculated in this example, with a null depth of -86.15 dB in the incident direction of single-tone interference and a null depth of -60.38 dB in the incident direction of broadband interference; Fig.12 As a result of demodulating the spread spectrum communication signal after spatial adaptive filtering, the signal after weighted filtering can be captured and tracked, and the original data can be restored.

[0081] In order to further illustrate the performance of the FPGA algorithm acceleration device proposed in the present invention, the receiver uses the Xilinx KCU105 development board, and the FPGA chip model is XCKU040. Table 1 shows the results of the PC host (CPU model is Intel (R) Core (TM) i7-8750H CPU, clock frequency is 2.21GHz) to perform a 10-element linear array optimal weight calculation and compares it with the processing results of the present invention. Under the condition of ensuring data accuracy, the algorithm calculation speed of the present invention is 26 times that of the PC host. At the same time, the resource consumption of the FPGA algorithm acceleration module is shown in Table 1. Fig.13 As shown, the entire lookup table LUT consumes 5%, the trigger FF consumes 5%, the on-chip BRAM consumes 5%, and the digital signal processor DSP consumes 5%, and the required resources are very few.

[0082] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0083] Table 1 is a comparison table of the performance of the PC host and the present invention in running the spatial adaptive filtering algorithm based on the power inversion criterion under an example.

[0084]

Claims

1. A spatial domain adaptive filtering method based on FPGA and power inversion criterion, comprising the following steps: Step 1: Convert the radio frequency signal received by the array antenna into a digital intermediate frequency signal, and convert the obtained digital intermediate frequency signal from a fixed point number to a single precision floating point number; Step 2: Calculate the cross-covariance matrix between the digital intermediate frequency signal of the first element of the array antenna and the digital intermediate frequency signals of other elements And the autocovariance matrix of the digital intermediate frequency signal of other array elements Step 3: Use the LDL matrix decomposition method to invert the autocovariance matrix obtained in step 2 Calculate its inverse matrix Step 4: Substitute the inverse matrix obtained in step 3 The cross-covariance matrix obtained in step 2 is Calculate the optimal weight vector w of the array antenna according to the power inversion criterion; Step 5: Use the optimal weight vector w of the array antenna obtained in step 4 to weight the received digital intermediate frequency signal to suppress the interference signal.

2. A spatial domain adaptive filtering method based on FPGA and power inversion criterion as claimed in claim 1, characterized in that: The specific process of step 1 is as follows: S11. By configuring each array antenna RF front-end chip, the RF signal received by the array antenna is converted into a digital intermediate frequency signal. Each array antenna generates a set of I / Q signal data. The signal data received by the array antenna is represented as x(n), where x(n) = [x1(n) x2(n)…x M (n)] T It is composed of the received signals of M array antennas, x i (n) represents the signal received by the i-th array antenna; S12. The I / Q signal data corresponding to each array antenna is converted to a single-precision floating-point number module, and the on-chip block RAM of the FPGA is used to open a corresponding buffer area for each array antenna signal data. Starting from the starting address of each buffer area, signal data with a length of snapshot number N is stored.

3. The spatial domain adaptive filtering method based on FPGA and power inversion criterion as claimed in claim 1, characterized in that: The specific process of step 2 is as follows: S21, record the signal data in the buffer area corresponding to the first array antenna as matrix X1, and record the signal data in the buffer area corresponding to other array antennas as matrix X2, where X1=[x1(1) x1(2)…x1(N)] Calculate the cross-covariance matrix of the digital intermediate frequency signal of the first array element and the digital intermediate frequency signals of other array elements in N represents the number of fast sampling rows of the signal received by the array antenna; There is only one column. When FPGA calculates the multiplication of matrix X2 and matrix X1, it only needs to calculate and multiply each row of matrix X2 with the column of X1, and then add the calculated matrix Element data is stored in the FPGA’s on-chip block RAM; S22, because FPGA has the characteristics of parallel operation, in step S21, calculate At the same time, parallel computing On the FPGA, the same matrix multiplication is performed to make X2 and The corresponding rows and columns of Element data is also stored in the FPGA's on-chip block RAM.

4. The spatial domain adaptive filtering method based on FPGA and power inversion criterion as claimed in claim 1, characterized in that: The specific process of step 3 is as follows: S31. Calculate the autocovariance matrix Then, using the matrix LDL decomposition principle Among them, if you remember Then there is a jj As calculated d jj The basis value of , which represents the matrix The diagonal matrix element with the j-th row and j-th column in ; l jk , d kk Used for recursive calculation of d jj and l ij ; Among them, l jk represents the matrix element at the jth row and kth column in the lower triangular matrix L obtained by decomposing the matrix LDL; Represented as l jk The conjugate transpose of kk represents the diagonal matrix element at the kth row and kth column in the diagonal matrix D obtained by matrix LDL decomposition; d jj Used to construct the diagonal matrix D and calculate l ij , represents the diagonal matrix element of the j-th row and j-th column in the diagonal matrix D obtained by matrix LDL decomposition; a i1 As the calculation i1 The basis value of , which represents the matrix The matrix element at row i and column 1 in ; l i1 , l ij Used to construct the lower triangular matrix L, l i1 represents the matrix element at the i-th row and the first column in the lower triangular matrix L obtained by decomposing the matrix LDL; l ij Represents the matrix element of the i-th row and j-th column in the lower triangular matrix L obtained by decomposing the matrix LDL; use the on-chip block RAM of the FPGA to open two cache areas for the lower triangular matrix L and the diagonal matrix D. When defining the RAM cache area, let the element value of the diagonal position of the lower triangular matrix L be 1. At the same time, since the matrix D is a diagonal matrix, it is only necessary to cache the diagonal elements of the matrix D in the form of vectors; According to the above formula, when calculating the lower triangular matrix L and the diagonal matrix D in the FPGA, we start from the first column j=1 of the L and D matrices. When the variable k accumulates from 0 to j-1, the corresponding matrix data is continuously taken out from the RAM area of ​​the FPGA to calculate the cumulative sum. Then, d can be calculated jj The value of is stored in the RAM buffer area of ​​the matrix D; at this time, the calculation starts from the i=j+1th row of the lower triangular matrix L. When the variable k accumulates from 0 to j-1, the corresponding matrix data is continuously taken out from the RAM area of ​​the FPGA to calculate the cumulative sum Then, calculate l ij The value of is stored in the RAM buffer of matrix L, and i is incremented, and l is calculated in the same way as above. ij , until i=M-1 is calculated; calculate the second column j=2 matrix data of L and D matrices in the above manner until the last column j=M-1 matrix data of L and D matrices is calculated; S32. Calculate the inverse matrix L of the lower triangular matrix L according to the lower triangular matrix inverse formula -1 In the formula r ij Used to construct the inverse matrix L -1 , represents the inverse matrix L -1 The matrix element at row i and column j in l ii As the calculation r ij The basis value of represents the diagonal matrix element of the i-th row and i-th column in the lower triangular matrix L. l ik 、r kj Used for recursive calculation of r ij , l ik represents the matrix element in the i-th row and k-th column of the lower triangular matrix L; r kj Represents the inverse matrix L -1 The matrix element at the kth row and jth column in ; Using the on-chip block RAM of the FPGA as the inverse matrix L -1 After opening a cache area, first start from L -1 The calculation starts from the first row i=1 and the first column j=1 of the matrix. When the variable k accumulates from 0 to i-1, the corresponding matrix data is continuously taken out from the RAM area of ​​FPGA to calculate the cumulative sum. Then, calculate r ij The value is stored in the matrix L -1 In the RAM cache area, let j increase and calculate r in the above way. ij , until j=i-1 is calculated; calculate L in the same way as above -1 The second row of the matrix i = 2 matrix data until L is calculated -1 The last row of the matrix i = M-1 matrix data; S33. Due to the parallel computing characteristics of FPGA, the inverse matrix L of the lower triangular matrix L is calculated. -1 At the same time, the inverse matrix D of the diagonal matrix D is calculated in parallel -1 ; Inverse matrix D -1 is the reciprocal of the diagonal elements of the D matrix, that is Using the on-chip block RAM of the FPGA as the inverse matrix D -1 After a cache is created, the diagonal element values ​​of matrix D are taken out from the RAM area of ​​FPGA in turn, and the reciprocal is calculated and the result is stored in matrix D. -1 In the RAM cache area; S34, calculate the inverse matrix L -1 and D -1 after, The inverse matrix Expressed as Take out the matrix (L H ) -1 The element value of D -1 The element values ​​are calculated according to the principle of matrix multiplication, so that (L H ) -1 With D -1 The corresponding rows and columns of the matrix are multiplied and accumulated, and the results are temporarily stored in the on-chip block RAM area of ​​the FPGA. H ) -1 With D -1 After matrix multiplication, the resulting matrix is ​​multiplied by L according to the principle of matrix multiplication. -1 Multiply the calculated matrix Element data is stored in the FPGA's on-chip block RAM.

5. The spatial domain adaptive filtering method based on FPGA and power inversion criterion as claimed in claim 1, characterized in that: The specific process of step 4 is as follows: S41. According to the power inversion criterion, the optimal weight vector can be obtained Get the matrix from the FPGA RAM area and The value of is calculated according to the principle of matrix multiplication, so that and The corresponding rows and columns of are multiplied and accumulated to obtain the optimal weight vector w; S42, converting the obtained optimal weight vector w from single-precision floating point to fixed point, and storing it using register resources of FPGA.

6. The spatial domain adaptive filtering method based on FPGA and power inversion criterion as claimed in claim 1, characterized in that: The specific process of step 5 is as follows: S51. The signal data received by the array antenna is weighted by the optimal weight vector w, that is, each array antenna is multiplied by the corresponding optimal weight and then accumulated to obtain the output signal, that is, the output signal y(n)=w H (n)x(n).

7. A device for the spatial domain adaptive filtering method based on FPGA and power inversion criterion as claimed in claim 1, the device comprising: Front-end RF chip, FPGA algorithm acceleration module, signal demodulation module. After receiving the signal, the front-end RF chip transmits it to the FPGA algorithm acceleration module for filtering, and then transmits the filtered signal to the signal demodulation module for demodulation; The FPGA algorithm acceleration module includes: an array signal data preprocessing module, an autocovariance matrix calculation module, an autocovariance matrix inversion module, a cross-covariance matrix calculation module, an optimal weight vector calculation module, a floating point number conversion fixed point number module, and an optimal weight vector weighting module.

Images