An X-band asymmetric single-pole double-throw switch
By using asymmetric circuit topology design, differentiated transmit and receive paths, and employing dual parallel and series stacked high electron mobility transistors, along with parallel resonant inductors to form an LC resonant circuit, the problems of insufficient power capacity and high loss of single-pole double-throw switches in X-band high-power applications are solved, achieving a balance between high isolation and low loss.
Patent Information
- Application Number
- CN202510435805.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2045-04-09
AI Technical Summary
Existing single-pole double-throw switches struggle to simultaneously optimize power handling and low loss, especially in X-band high-power applications, where traditional techniques worsen insertion loss and isolation when transistor size is increased.
An asymmetric circuit topology is adopted, and the transmit and receive paths are designed differently. The transmit channel uses two parallel stacked high electron mobility transistors, and the receive channel uses two series stacked high electron mobility transistors. An LC resonant circuit is formed by connecting a resonant inductor in parallel between the source and drain of the transistors. A small capacitor is connected in series in the design to reduce the off-state capacitance.
It improves the power capacity and isolation of the switch, reduces insertion loss, and achieves a balance between high power handling capability and low loss.
Smart Images
Figure CN119945411B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to the field of radio frequency microelectronics, in particular to an X-band asymmetric single-pole double-throw switch. BACKGROUND
[0002] In radio frequency communication and radar systems, single-pole double-throw switches (SPDT) are the core components for switching signals between transmit (Tx) and receive (Rx) modes, especially in high-power applications at the X-band, which requires high power handling capability, low insertion loss and fast switching speed. Symmetric high electron mobility transistor (HEMT) switches use the same topology for the transmit (Tx) and receive (Rx) paths, and increasing transistor size is required to improve switch power capacity, but this will worsen insertion loss and isolation, making it difficult to optimize power handling and low loss at the same time. Traditional technologies face multiple challenges under such demands.
[0003] To solve the problems existing in the prior art, the application provides an X-band asymmetric single-pole double-throw switch, which uses an asymmetric circuit topology, differentiates the design of the transmit (Tx) and receive (Rx) paths, and solves the problem in a targeted manner. SUMMARY
[0004] The application aims to solve the problem that existing single-pole double-throw switches cannot simultaneously optimize power handling and low loss, and provides an X-band asymmetric single-pole double-throw switch.
[0005] The application is achieved by the following technical solutions:
[0006] An X-band asymmetric single-pole double-throw switch, comprising a first radio frequency input / output terminal, a second radio frequency input / output terminal, a third radio frequency input / output terminal, a transmit channel circuit, a matching circuit, a receive channel circuit, a first control voltage source, and a second control voltage source.
[0007] The transmit channel circuit is used to receive high-power radio frequency signals input by the first radio frequency input / output terminal and output them from the second radio frequency input / output terminal. The transmit channel circuit comprises a first parallel module and a first series module.
[0008] The matching circuit is used to realize impedance matching between the second radio frequency input / output terminal and the transmit channel circuit and the receive channel circuit.
[0009] The receive channel circuit is used to receive radio frequency signals input by the second radio frequency input / output terminal and output them from the third radio frequency input / output terminal. The receive channel circuit comprises a second series module and a second parallel module.
[0010] The first control voltage source is connected with the first series module of the transmitting channel circuit and the second parallel module of the receiving channel circuit; the second control voltage source is connected with the first parallel module of the transmitting channel circuit and the second series module of the receiving channel circuit.
[0011] The transmitting channel circuit is controlled by the first control voltage source and the second control voltage source, and when the first control voltage source is high level and the second control voltage source is low level, the transmitting channel circuit is in the on state, and vice versa; the receiving channel circuit is controlled by the first control voltage source and the second control voltage source, and when the first control voltage source is low level and the second control voltage source is high level, the receiving channel circuit is in the on state, and vice versa.
[0012] Further, the transmitting channel circuit comprises a first parallel module and a first series module.
[0013] The input end of the first parallel module is connected with the first radio frequency input and output end, and the output end is connected with the input end of the first series module; the input end of the first series module is connected with the first parallel module, and the output end is connected with one end of the matching circuit.
[0014] Further, the first parallel module comprises a first transistor to a fourth transistor, a first resistor to a fourth resistor, a first transmission line to a third transmission line, and a first capacitor.
[0015] One end of the first transmission line is connected with the first radio frequency input and output end, and the other end is connected with the drain of the first transistor and the second transmission line; the gate of the first transistor is connected with the first resistor, and the source is connected with the drain of the second transistor; the gate of the second transistor is connected with the second resistor, and the source is connected with one end of the first capacitor; the other end of the first resistor and the second resistor is connected with the second control voltage source; the other end of the first capacitor is grounded; the other end of the second transmission line is connected with the drain of the third transistor and the third transmission line; the gate of the third transistor is connected with the third resistor, and the source is connected with the drain of the fourth transistor; the gate of the fourth transistor is connected with the fourth resistor, and the source is grounded; the other end of the third resistor and the fourth resistor is connected with the second control voltage source; the other end of the third transmission line is connected with the input end of the first series module; the first transistor to the fourth transistor are high electron mobility transistors.
[0016] Further, the first series module comprises a fifth transistor, a fifth resistor, and a first inductor.
[0017] The drain of the fifth transistor is connected with the output of the first parallel module, and the gate is connected with the fifth resistor; the first inductor is connected in parallel with the fifth transistor, and the two ends are connected with the drain and the source of the fifth transistor respectively; the other end of the fifth resistor is connected with the first control voltage source; and the fifth transistor is a high electron mobility transistor.
[0018] Further, the matching circuit comprises a second capacitor, a fourth transmission line to a sixth transmission line;
[0019] One end of the second capacitor is connected with the second radio frequency input and output end, and the other end is connected with the fifth transmission line; the other end of the fifth transmission line is connected with one end of the fourth transmission line and the sixth transmission line respectively; the other end of the fourth transmission line is connected with the output of the transmitting channel circuit; and the other end of the sixth transmission line is connected with the input of the receiving channel circuit.
[0020] Further, the receiving channel circuit comprises a second series module and a second parallel module;
[0021] The input of the second series module is connected with the matching circuit, and the output is connected with the input of the second parallel module; the input of the second parallel module is connected with the output of the second series module, and the output is connected with the third radio frequency input and output end.
[0022] Further, the second series module comprises a sixth transistor, a seventh transistor, a sixth resistor, a seventh resistor and a second inductor;
[0023] The drain of the sixth transistor is connected with the right end of the matching circuit, the source is connected with the drain of the seventh transistor, and the gate is connected with one end of the sixth resistor; the drain of the seventh transistor is connected with the source of the sixth transistor, the source is connected with the input of the second parallel module, and the gate is connected with one end of the seventh resistor; one end of the first inductor is connected with the drain of the sixth transistor, and the other end is connected with the source of the seventh transistor;
[0024] The other end of the sixth resistor and the seventh resistor is connected with the second control voltage source; and the sixth transistor and the seventh transistor are high electron mobility transistors.
[0025] Further, the second parallel module comprises an eighth transistor, a ninth transistor, an eighth resistor, a ninth resistor, a third capacitor, a seventh transmission line, an eighth transmission line and a ninth transmission line;
[0026] The one end of the seventh transmission line is connected with the output end of the second series module, and the other end is connected with the drain of the eighth transistor and the eighth transmission line; the gate of the eighth transistor is connected with the eighth resistor, and the source is grounded; the other end of the eighth transmission line is connected with the drain of the ninth transistor and the ninth transmission line; the gate of the ninth transistor is connected with the ninth resistor, and the source is connected with one end of the third capacitor; the other end of the eighth resistor and the ninth resistor is connected with the first control voltage source; the other end of the third capacitor is grounded; the other end of the ninth transmission line is connected with the third radio frequency input and output end; the eighth transistor and the ninth transistor are high electron mobility transistors.
[0027] Further, the first control voltage source and the second control voltage source comprise a first direct current voltage source and a first direct current voltage source.
[0028] The beneficial effects of the present application are:
[0029] (1) High power capacity: in the present application, the transmitting channel circuit adopts the design of double-parallel stacked high electron mobility transistors, which divides the high voltage swing by stacking transistors, solves the problem of insufficient power capacity caused by the breakdown voltage limitation of single transistor, and improves the power capacity of the switch transmitting channel circuit without significantly increasing the topology complexity;
[0030] (2) High isolation: in the present application, the receiving channel circuit adopts the design of two series stacked high electron mobility transistors, which makes the off-state capacitances of the two transistors series, thereby presenting a smaller off-state capacitance as a whole, reducing the signal leakage to the receiving channel when the transmitting channel is turned on, and effectively improving the switch isolation;
[0031] (3) Low insertion loss: in the present application, by connecting a resonant inductor in parallel with the source and drain of the series high electron mobility transistor, an LC resonant circuit is formed with the off-state parasitic capacitance of the transistor, which cancels out the capacitance effect at the target frequency band (such as X-band), improves the isolation and reduces the loss; by connecting a small capacitor in series with the source of the transistor at the farthest end from the second radio frequency input and output end, the off-state capacitance of the transistor is connected in series, thereby presenting a smaller off-state capacitance as a whole, reducing the signal leakage when the switch is turned on, and further reducing the conduction loss. BRIEF DESCRIPTION OF DRAWINGS
[0032] Figure 1 It is the structure principle diagram of the X-band asymmetric single-pole double-throw switch of the present application;
[0033] Figure 2 It is the circuit diagram of the X-band asymmetric single-pole double-throw switch of the present application;
[0034] Figure 3A transmission channel circuit and a receiving channel circuit conduction loss simulation curve of an X-band asymmetric single-pole double-throw switch are provided for the embodiment of the present application.
[0035] Figure 4 An isolation degree simulation curve when the transmission channel circuit and the receiving channel circuit are turned off of an X-band asymmetric single-pole double-throw switch is provided for the embodiment of the present application.
[0036] Figure 5 An input and output port voltage standing wave ratio simulation curve when the transmission channel is turned on of an X-band asymmetric single-pole double-throw switch is provided for the embodiment of the present application.
[0037] Figure 6 An input and output port voltage standing wave ratio simulation curve when the receiving channel is turned on of an X-band asymmetric single-pole double-throw switch is provided for the embodiment of the present application.
[0038] Figure 2 The first radio frequency input and output port Port1, the second radio frequency input and output port Port2, the third radio frequency input and output port Port3, the transmission channel circuit 1, the matching circuit 2, the receiving channel circuit 3, the first control voltage source 4, the second control voltage source 5, the first parallel module A1, the first series module B1, the second parallel module A2 and the second series module B2, the first transistor M1 to the ninth transistor M9, the first transmission line TL1 to the ninth transmission line TL9, the first capacitor C1 to the third capacitor C3, the first resistor R1 to the ninth resistor R9, the first inductor L1 and the first inductor L2, and the direct current bias power supply V1 and V2. DETAILED DESCRIPTION
[0039] The technical solutions of the present application will be described clearly and completely in combination with the embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.
[0040] Reference Figure 1 The X-band asymmetric single-pole double-throw switch provided for the embodiment includes the first radio frequency input and output port Port1, the second radio frequency input and output port Port2, the third radio frequency input and output port Port3, the transmission channel circuit 1, the matching circuit 2, the receiving channel circuit 3, the first control voltage source 4 and the second control voltage source 5.
[0041] The transmission channel circuit 1 is used to receive the high-power radio frequency signal input by the first radio frequency input and output port Port1 and output it from the second radio frequency input and output port Port2. The transmission channel circuit 1 includes the first parallel module A1 and the first series module B1.
[0042] The matching circuit 2 is used to realize impedance matching between the second radio frequency input / output terminal Port2 and the transmitting channel circuit 1 and the receiving channel circuit 3.
[0043] The receiving channel circuit 3 is used to receive the radio frequency signal input by the second radio frequency input / output terminal Port2 and output it from the third radio frequency input / output terminal Port3; the receiving channel circuit 3 comprises a second series module B2 and a second parallel module A2.
[0044] The first control voltage source 4 is connected with the first series module B1 of the transmitting channel circuit 1 and the second parallel module A2 of the receiving channel circuit 3.
[0045] The second control voltage source 5 is connected with the first parallel module A1 of the transmitting channel circuit 1 and the second series module B2 of the receiving channel circuit 3.
[0046] The main body of the embodiment adopts the mode of asymmetric topology design switch, and the transmitting Tx and receiving Rx channel circuits are designed differently.
[0047] As shown in Figure 2 The transmitting channel circuit 1 comprises a first parallel module A1 and a first series module B1.
[0048] The input end of the first parallel module A1 is connected with the first radio frequency input / output terminal Port1, and the output end is connected with the input end of the first series module B1.
[0049] The input end of the first series module B1 is connected with the first parallel module A1, and the output end is connected with the input end of the matching circuit 2.
[0050] The first parallel module A1 comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transmission line TL1, a second transmission line TL2, a third transmission line TL3, and a first capacitor C1.
[0051] One end of the first transmission line TL1 is connected with the first radio frequency input / output terminal Port1, and the other end is connected with the drain of the first transistor M1 and the second transmission line TL2.
[0052] The gate of the first transistor M1 is connected with the first resistor R1, and the source is connected with the drain of the second transistor M2.
[0053] The gate of the second transistor M2 is connected with the second resistor R2, and the source is connected with one end of the first capacitor C1.
[0054] The other end of the first resistor R1 and the second resistor R2 is connected with the second control voltage source 5;
[0055] The other end of the second transmission line TL2 is connected with the drain of the third transistor M3 and the third transmission line TL3;
[0056] The gate of the third transistor M3 is connected with the third resistor R3, and the source is connected with the drain of the fourth transistor M4;
[0057] The gate of the fourth transistor M4 is connected with the fourth resistor R4, and the source is grounded;
[0058] The other end of the first capacitor C1 is grounded;
[0059] The other end of the third resistor R3 and the fourth resistor R4 is connected with the second control voltage source 5;
[0060] The other end of the third transmission line TL3 is connected with the input end of the first series module B1;
[0061] The transistors are all high electron mobility transistors HEMT;
[0062] When the first parallel module A1 is in the on state, the insertion loss is mainly caused by the off-state capacitance (C off ) of the transistor, and the design of the parallel stacking of the first transistor M1, the second transistor M2 and the third transistor M3 and the fourth transistor M4 makes the off-state capacitance (C off ) in series, so as to present a smaller off-state capacitance as a whole, reduce the signal leakage when the switch is turned on, and effectively reduce the insertion loss.
[0063] The first capacitor C1 in the series at the farthest end of the source of the second transistor M2 from the second radio frequency input and output end Port2 further reduces the on insertion loss without affecting the isolation degree;
[0064] As shown in Figure 2 The first series module B1 includes the fifth transistor M5, the fifth resistor R5 and the first inductor L1;
[0065] The drain of the fifth transistor M5 is connected with the output end of the first parallel module A1, and the gate is connected with the fifth resistor R5;
[0066] The first inductor L1 is connected in parallel with the fifth transistor M5, and the two ends are respectively connected with the drain and the source of the fifth transistor M5;
[0067] The other end of the fifth resistor R5 is connected with the first control voltage source 4;
[0068] The transistors are all high electron mobility transistors HEMT;
[0069] The isolation of the first series module B1 in the off state is mainly caused by the off-state capacitance (C off ) of the transistor, and the first inductor L1 connected in parallel with the source and drain of the fifth transistor M5 and the off-state parasitic capacitance (C off ) form an LC resonance circuit to offset the capacitance effect in the target frequency band, improve the off-state isolation, and reduce the loss.
[0070] As shown in Figure 2 , the matching circuit 2 comprises a second capacitor C2, a fourth transmission line TL4, a fifth transmission line TL5, and a sixth transmission line TL6.
[0071] One end of the second capacitor C2 is connected with the second radio frequency input and output end Port2, and the other end is connected with the fifth transmission line TL5.
[0072] The other end of the fifth transmission line TL5 is connected with one end of the fourth transmission line TL4 and one end of the sixth transmission line TL6, respectively.
[0073] The other end of the fourth transmission line TL4 is connected with the output end of the transmitting channel circuit 1.
[0074] The other end of the sixth transmission line TL6 is connected with the input end of the receiving channel circuit 3.
[0075] The receiving channel circuit 3 comprises a second series module B2 and a second parallel module A2.
[0076] The input end of the second series module B2 is connected with the matching circuit 2, and the output end is connected with the input end of the second parallel module A2.
[0077] The input end of the second parallel module A2 is connected with the output end of the second series module B2, and the output end is connected with the third radio frequency input and output end Port3.
[0078] The second series module B2 comprises a sixth transistor M6, a seventh transistor M7, a sixth resistor R6, a seventh resistor R7, and a second inductor L2.
[0079] The drain of the sixth transistor M6 is connected with the right end of the matching circuit 2, the source is connected with the drain of the seventh transistor M7, and the gate is connected with one end of the sixth resistor R6.
[0080] The drain of the seventh transistor M7 is connected with the source of the sixth transistor M6, the source is connected with the input end of the second parallel module A2, and the gate is connected with one end of the seventh resistor R7.
[0081] One end of the first inductor L1 is connected with the drain of the sixth transistor M6, and the other end is connected with the source of the seventh transistor M7.
[0082] The other end of the sixth resistor R6 and the seventh resistor R7 is connected with the second control voltage source 5;
[0083] The transistor is high electron mobility transistor HEMT;
[0084] When the second series module B2 is in the off state, the isolation degree is mainly caused by the off-state capacitance (C off ) of the transistor, the design of the sixth transistor M6 and the seventh transistor M7 in series stack makes the off-state capacitance (C off ) in series, so as to present a smaller off-state capacitance as a whole, reduce the signal leakage from the transmitting channel to the receiving channel, and effectively improve the off-state isolation degree of the receiving channel.
[0085] The second inductor L2 connected in parallel with the drain of the sixth transistor M6 and the source of the seventh transistor M7 forms an LC resonance circuit with the off-state parasitic capacitance (C off ) of the transistor, which cancels out the capacitance effect in the target frequency band, further limits the signal leakage to the receiving channel, and improves the isolation degree and reduces the loss to a higher degree.
[0086] The second parallel module A2 includes the eighth transistor M8, the ninth transistor M9, the eighth resistor R8, the ninth resistor R9, the third capacitor C3, the seventh transmission line TL7, the eighth transmission line TL8, and the ninth transmission line TL9;
[0087] One end of the seventh transmission line TL7 is connected with the output end of the second series module B2, and the other end is connected with the drain of the eighth transistor M8 and the eighth transmission line TL8;
[0088] The gate of the eighth transistor M8 is connected with the eighth resistor R8, and the source is grounded;
[0089] The other end of the eighth transmission line TL8 is connected with the drain of the ninth transistor M9 and the ninth transmission line TL9;
[0090] The gate of the ninth transistor M9 is connected with the ninth resistor R9, and the source is connected with one end of the second capacitor C2;
[0091] The other end of the eighth resistor R8 and the ninth resistor R9 is connected with the first control voltage source 4;
[0092] The other end of the third capacitor C3 is grounded;
[0093] The other end of the ninth transmission line TL9 is connected with the third radio frequency input and output end Port3;
[0094] The transistor is high electron mobility transistor HEMT;
[0095] The insertion loss of the second parallel module B2 in the on state is mainly caused by the off-state capacitance (C off ) of the transistor. In the design, a small capacitor is connected in series with the source of the ninth transistor M9 farthest from the second radio frequency input / output terminal Port2, so that the off-state capacitance of the transistor is further reduced, thereby reducing the insertion loss of the switch as a whole.
[0096] The first control voltage source 4 and the second control voltage source 5 include direct current voltage sources V1 and V2.
[0097] The first parallel module A1 and the first series module B1 in the transmitting channel circuit 1 are controlled by the first control voltage source 4 and the second control voltage source 5, respectively. When the direct current voltage source V1 outputs a high level and the direct current voltage source V1 outputs a low level, the transmitting channel circuit is in an on state, the receiving channel circuit is in an off state, and the radio frequency signal is input from the first radio frequency input / output terminal Port1 and output from the second radio frequency input / output terminal Port2.
[0098] The second parallel module A2 and the second series module B2 in the receiving channel circuit 3 are controlled by the first control voltage source 4 and the second control voltage source 5, respectively. When the direct current voltage source V1 outputs a low level and the direct current voltage source V1 outputs a high level, the transmitting channel circuit is in an off state, the receiving channel circuit is in an on state, and the radio frequency signal is input from the second radio frequency input / output terminal Port2 and output from the third radio frequency input / output terminal Port3.
[0099] The first control voltage source 4 and the second control voltage source 5 do not output high levels or low levels at the same time.
[0100] As an important application of the X-band asymmetric single-pole double-throw switch, the embodiment also provides an 8-12GHz asymmetric single-pole double-throw switch embodiment, which has the same circuit structure as the X-band asymmetric single-pole double-throw switch described above. The chip fully utilizes the beneficial effects and effects of the asymmetric single-pole double-throw switch described above.
[0101] Figure 3 The insertion loss simulation curves of the transmitting channel circuit and the receiving channel circuit of the 8-12GHz asymmetric single-pole double-throw switch when they are turned on, respectively. Figure 3 The Tx graph line is an insertion loss curve input from the first radio frequency input / output terminal Port1 and output from the second radio frequency input / output terminal Port2. The Rx graph line is an insertion loss curve input from the second radio frequency input / output terminal Port2 and output from the third radio frequency input / output terminal Port3. Figure 3The simulation curve shows that the insertion loss of the transmitting channel Tx is stabilized at about -0.4 dB when the transmitting channel is turned on, and the insertion loss of the receiving channel Rx is stabilized at about -0.43 dB when the receiving channel is turned on, indicating that the asymmetric single-pole double-throw switch circuit has low insertion loss in the transmitting and receiving channels.
[0102] Figure 4 Figure 8 is a simulation curve of the isolation of the transmitting channel circuit and the receiving channel circuit of the asymmetric single-pole double-throw switch in the 8-12 GHz band when the circuits are turned off. Figure 4 The Tx curve is the isolation curve when the signal is input from the second radio frequency input / output port Port2 and output from the third radio frequency input / output port Port3, and the transmitting channel is turned off; and the Rx curve is the isolation curve when the signal is input from the first radio frequency input / output port Port1 and output from the second radio frequency input / output port Port2, and the receiving channel is turned off. Figure 4 The simulation curve shows that the isolation of the transmitting channel Tx is about -37 dB when the transmitting channel is turned off, and the insertion loss of the receiving channel Rx is stabilized at about -55 dB when the receiving channel is turned off. Generally, the isolation parameter is negative, and the greater the value of the isolation parameter, the better the isolation of the switch. The isolation of the receiving channel turned off in the 8-12 GHz band is more than 40 dB, indicating that the series-stacked transistor can improve the isolation of the millimeter wave switch in the off state. Due to the effect of the second inductor L2 connected in parallel to the transistor, the isolation value is more than 55 dB in the 9-12 GHz band, indicating that the parallel inductor can further improve the isolation of the switch in the off state.
[0103] Referring to Figure 5 Figure 9 is a simulation curve of the input / output port voltage standing wave ratio of the transmitting channel of the asymmetric single-pole double-throw switch in the 8-12 GHz band when the transmitting channel is turned on. Figure 5 The VSWR11 and VSWR22 curves are the voltage standing wave ratio curves of the two ports when the signal is input from the first radio frequency input / output port Port1 and output from the second radio frequency input / output port Port2. The voltage standing wave ratio is used to represent the matching degree of the device port impedance to 50 Ω, and a value of 1 represents complete impedance matching, without radio frequency signal reflected back from the port. Figure 5 The simulation curve shows that the voltage standing wave ratio of the two ports is about 1.2 when the transmitting channel is turned on, and the matching is good.
[0104] Referring to Figure 6 Figure 10 is a simulation curve of the input / output port voltage standing wave ratio of the receiving channel of the asymmetric single-pole double-throw switch in the 8-12 GHz band when the receiving channel is turned on. Figure 6The VSWR22 and VSWR33 curves shown are the voltage standing wave ratio curves of the two ports when the signal is input by the second radio frequency input and output port Port2 and output by the third radio frequency input and output port Port3. Figure 5 The simulation curve shows that the voltage standing wave ratio of the two ports is about 1.2 when the receiving channel is turned on, and the matching is good.
[0105] In summary, the X-band asymmetric single-pole double-throw switch of the present application adopts an asymmetric circuit topology and differentiates the design of the transmit Tx and receive Rx paths. First, the transmit Tx channel circuit adopts a design of double-parallel stacked high electron mobility transistors HEMT, which divides the high voltage swing among the stacked transistors, solves the problem of insufficient power capacity caused by the breakdown voltage limitation of a single transistor, and improves the power capacity of the switch transmit channel circuit without significantly increasing the complexity of the topology. Second, the receive Rx channel circuit adopts a design of two high electron mobility transistors HEMT stacked in series, which makes the off-state capacitances (C off ) of the two transistors in series, thereby presenting a smaller off-state capacitance overall, reducing the signal leakage to the receiving channel when the transmitting channel is turned on, and effectively improving the off-state isolation of the receiving channel. Third, the source and drain electrodes of the high electron mobility transistors HEMT in the transmit Tx channel and the receive Rx channel are connected in parallel with a resonant inductor, which forms an LC resonant circuit with the off-state parasitic capacitance (C off ) of the transistor, cancels out the capacitance effect at the target frequency band such as the X-band, improves the isolation, and reduces the loss. Finally, a small capacitor is connected in series with the off-state capacitance (C off ) of the transistor at the end farthest from the second radio frequency input and output port Port2, thereby presenting a smaller off-state capacitance overall, reducing the signal leakage when the switch is turned on, and further reducing the on-state loss. The present embodiment has a significant practical application significance for modern radio frequency wireless communication systems.
[0106] The above is only a preferred embodiment of the present embodiment and is not intended to limit the present embodiment. For those skilled in the art, the present embodiment can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present embodiment shall be included in the protection scope of the present embodiment.
Claims
1. An X-band asymmetric single-pole double-throw switch, characterized in that: It includes a first radio frequency input / output terminal, a second radio frequency input / output terminal, a third radio frequency input / output terminal, a transmitting channel circuit, a matching circuit, a receiving channel circuit, a first control voltage source, and a second control voltage source; The transmitting channel circuit is used to receive a high-power radio frequency signal input from the first radio frequency input / output terminal and output it from the second radio frequency input / output terminal; the transmitting channel circuit includes a first parallel module and a first series module; The matching circuit is used to achieve impedance matching between the second RF input / output terminal and the transmitting channel circuit and the receiving channel circuit. The receiving channel circuit is used to receive the radio frequency signal input from the second radio frequency input / output terminal and output it from the third radio frequency input / output terminal; the receiving channel circuit includes a second series module and a second parallel module; The first control voltage source is connected to the first series module of the transmitting channel circuit and to the second parallel module of the receiving channel circuit; the second control voltage source is connected to the first parallel module of the transmitting channel circuit and to the second series module of the receiving channel circuit. The transmitting channel circuit is controlled by a first control voltage source and a second control voltage source. When the first control voltage source is at a high level and the second control voltage source is at a low level, the transmitting channel circuit is in a conducting state; otherwise, it is in a turning-off state. The receiving channel circuit is also controlled by a first control voltage source and a second control voltage source. When the first control voltage source is at a low level and the second control voltage source is at a high level, the receiving channel circuit is in a conducting state; otherwise, it is in a turning-off state. The transmission channel circuit includes a first parallel module and a first series module; The input terminal of the first parallel module is connected to the first radio frequency input / output terminal, and the output terminal is connected to the input terminal of the first series module; the input terminal of the first series module is connected to the first parallel module, and the output terminal is connected to one end of the matching circuit. The first parallel module includes a first transistor to a fourth transistor, a first resistor to a fourth resistor, a first transmission line to a third transmission line, and a first capacitor; One end of the first transmission line is connected to the first RF input / output terminal, and the other end is connected to the drain of the first transistor and the second transmission line; the gate of the first transistor is connected to the first resistor, and the source is connected to the drain of the second transistor; the gate of the second transistor is connected to the second resistor, and the source is connected to one end of the first capacitor; the other ends of the first and second resistors are connected to the second control voltage source; the other end of the first capacitor is grounded; the other end of the second transmission line is connected to the drain of the third transistor and the third transmission line; the gate of the third transistor is connected to the third resistor, and the source is connected to the drain of the fourth transistor; the gate of the fourth transistor is connected to the fourth resistor, and the source is grounded; the other ends of the third and fourth resistors are connected to the second control voltage source; the other end of the third transmission line is connected to the input terminal of the first series module; the first to fourth transistors are high electron mobility transistors; the first, second, third, and fourth transistors are stacked in parallel; the first capacitor is connected in series with the source of the second transistor, which is furthest from the second RF input / output terminal. The first series module includes a fifth transistor, a fifth resistor, and a first inductor; the first inductor connected in parallel across the source and drain terminals of the fifth transistor and the off-state parasitic capacitance of the fifth transistor form an LC resonant circuit. The receiving channel circuit includes a second series module and a second parallel module; The input terminal of the second series module is connected to the matching circuit, and the output terminal is connected to the input terminal of the second parallel module; the input terminal of the second parallel module is connected to the output terminal of the second series module, and the output terminal is connected to the third RF input / output terminal. The second series module includes a sixth transistor, a seventh transistor, a sixth resistor, a seventh resistor, and a second inductor; the second inductor connected in parallel with the drain of the sixth transistor and the source of the seventh transistor forms an LC resonant circuit with the off-state parasitic capacitance of the transistor. The second parallel module includes an eighth transistor, a ninth transistor, an eighth resistor, a ninth resistor, a third capacitor, a seventh transmission line, an eighth transmission line, and a ninth transmission line; One end of the seventh transmission line is connected to the output terminal of the second series module, and the other end is connected to the drain of the eighth transistor and the eighth transmission line; the gate of the eighth transistor is connected to the eighth resistor, and the source is grounded; the other end of the eighth transmission line is connected to the drain of the ninth transistor and the ninth transmission line; the gate of the ninth transistor is connected to the ninth resistor, and the source is connected to one end of the third capacitor; the other ends of the eighth and ninth resistors are connected to the first control voltage source; the other end of the third capacitor is grounded; the other end of the ninth transmission line is connected to the third RF input / output terminal; the eighth and ninth transistors are high electron mobility transistors; the sixth and seventh transistors are stacked in series; the third capacitor is connected in series with the source of the ninth transistor, which is furthest from the second RF input / output terminal.
2. The X-band asymmetric single-pole double-throw switch according to claim 1, characterized in that: The drain of the fifth transistor is connected to the output terminal of the first parallel module, and the gate is connected to the fifth resistor; the first inductor is connected in parallel with the fifth transistor, and its two ends are respectively connected to the drain and source of the fifth transistor; the other end of the fifth resistor is connected to the first control voltage source; the fifth transistor is a high electron mobility transistor.
3. The X-band asymmetric single-pole double-throw switch according to claim 1, characterized in that: The matching circuit includes a second capacitor and fourth to sixth transmission lines; One end of the second capacitor is connected to the second RF input / output terminal, and the other end is connected to the fifth transmission line; the other end of the fifth transmission line is connected to one end of the fourth transmission line and the sixth transmission line respectively; the other end of the fourth transmission line is connected to the output terminal of the transmitting channel circuit; and the other end of the sixth transmission line is connected to the input terminal of the receiving channel circuit.
4. The X-band asymmetric single-pole double-throw switch according to claim 1, characterized in that: The drain of the sixth transistor is connected to the right end of the matching circuit, the source is connected to the drain of the seventh transistor, and the gate is connected to one end of the sixth resistor; the drain of the seventh transistor is connected to the source of the sixth transistor, the source is connected to the input end of the second parallel module, and the gate is connected to one end of the seventh resistor; the drain of the sixth transistor is connected to one end of the first inductor, and the other end is connected to the source of the seventh transistor. The other end of the sixth and seventh resistors is connected to the second control voltage source; the sixth and seventh transistors are high electron mobility transistors.
5. The X-band asymmetric single-pole double-throw switch according to claim 1, characterized in that: The first control voltage source and the second control voltage source include a first DC voltage source and a second DC voltage source.
Citation Information
Patent Citations
Low distortion switch
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High frequency switch
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