Ring oscillator and manufacturing method thereof

Abstract

The invention discloses a ring oscillator and a manufacturing method thereof, relates to the technical field of microelectronics, and is used for reducing the power consumption of the ring oscillator. The ring oscillator includes a plurality of inverters. The plurality of phase inverters are divided into a first phase inverter group, a second phase inverter group and a third phase inverter group. The switching speed of the inverters included in the first inverter group is greater than the switching speed of the inverters included in the second inverter group. The power consumption of the inverters included in the second inverter group is less than the power consumption of the inverters included in the first inverter group and the third inverter group. And the third inverter group is used for outputting signals. And the transistors in at least one phase inverter included in the first phase inverter group and the third phase inverter are ring gate transistors. And the transistor in at least one phase inverter included in the second phase inverter group is an oxide thin film transistor. The oxide thin film transistor is disposed over the gate-all-around transistor. The manufacturing method of the ring oscillator is used for manufacturing the ring oscillator.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, and in particular to a ring oscillator and a manufacturing method thereof. Background Art

[0002] Ring oscillators are widely used as clock signal generators due to their simple structure and no need for external oscillation sources.

[0003] With the development of microelectronics technology, it is necessary to further reduce the power consumption of ring oscillators to meet the requirements of low-power scenarios. However, in the prior art, due to the high power consumption of silicon-based transistors and / or germanium-based transistors, it is difficult to further reduce the power consumption of ring oscillators based on silicon-based transistors and / or germanium-based transistors. Summary of the invention

[0004] An object of the present invention is to provide a ring oscillator and a manufacturing method thereof, so as to reduce the power consumption of the ring oscillator.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a ring oscillator, which includes: a plurality of inverters; the plurality of inverters are divided into a first inverter group, a second inverter group and a third inverter group. The first inverter group, the second inverter group and the third inverter group each include at least one inverter. Among them, the switching speed of the inverter included in the first inverter group is greater than the switching speed of the inverter included in the second inverter group. The power consumption of the inverter included in the second inverter group is less than the power consumption of the inverter included in the first inverter group and the third inverter group; the third inverter group is used to output signals. The transistor in at least one inverter included in the first inverter group and the third inverter is a ring-gate transistor, and the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor. The oxide thin film transistor is arranged above the ring-gate transistor.

[0006] In the case of adopting the above technical solution, the switching speed of the inverter included in the first inverter group is greater than the switching speed of the inverter included in the second inverter group, and the third inverter group is used to output the signal. At the same time, the ring-gate transistor has a high switching speed and driving capability. Based on this, in the ring oscillator provided by the present invention, the transistor in at least one inverter of the first inverter group is a ring-gate transistor, which is conducive to the first inverter group having a faster switching speed, thereby ensuring efficient processing of data, so that the output result of the ring oscillator is more accurate, and is conducive to improving the working performance of the ring oscillator. In addition, the transistor in at least one inverter included in the third inverter is a ring-gate transistor, which is conducive to improving the driving capability of the third inverter, thereby facilitating improving the maximum driving capability of the ring oscillator provided by the present invention. In addition, the ring-gate transistor can occupy a smaller area than the traditional planar transistor or fin field effect transistor under the same performance, thereby reducing the area occupied by the first inverter group and the second inverter group, and effectively improving the integration of the ring oscillator provided by the present invention. The leakage of the oxide thin film transistor has lower power consumption. Based on this, in the ring oscillator provided by the present invention, the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor, which can be beneficial to the second inverter group having lower power consumption. Since the oxide thin film transistor is arranged above the ring gate transistor, the ring oscillator provided by the present invention adopts a monolithic heterogeneous integrated device, which effectively improves the integration of the ring oscillator provided by the present invention. Furthermore, the oxide thin film transistor can be formed by a low temperature process to avoid high temperature damage to the lower ring gate transistor in the process of manufacturing the upper device on the ring gate transistor, which is beneficial to the structural integrity of the ring gate transistor and the function of the ring gate transistor in accordance with the design expectations, thereby facilitating the improvement of the yield of the manufacturing process of the ring oscillator provided by the present invention. Furthermore, the first inverter group, the second inverter group and the third inverter group form a ring oscillator, and the power consumption of the ring oscillator can be reduced by selecting the second inverter group of oxide thin film transistors, and the switching speed and driving capability of the ring oscillator can be improved by the ring gate transistors selected by the first inverter group and the second inverter group, so that the ring oscillator provided by the present invention can take into account both low power consumption and high performance.

[0007] As a possible implementation, at least one oxide thin film transistor is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor or a titanium oxide thin film transistor.

[0008] When the above technical solution is adopted, in the ring oscillator provided by the present invention, at least one oxide thin film transistor is selected as the above type of transistor, which can make the range of device types that can be selected for the oxide thin film transistor larger, thereby meeting the switching speed, power consumption, conductivity type, operating voltage and other parameter requirements of at least one inverter included in the second inverter group, thereby expanding the application scope of the ring oscillator provided by the present invention.

[0009] As a possible implementation scheme, the plurality of inverters include: a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter. The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are sequentially connected in series. The input end of the first inverter is connected to the output end of the fifth inverter. The output end of the fifth inverter and the output end of the eighth inverter are used to output a signal.

[0010] In the case of adopting the above technical solution, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter enable the ring oscillator to generate an oscillation signal, and the sixth inverter, the seventh inverter and the eighth inverter receive the oscillation signal output by the first five inverters, process it and output the signal, play a buffering role, and are used to improve the output capacity of the ring oscillator, and are used for output amplification, thereby improving the output capacity of the ring oscillator. In addition, the output end of the fifth inverter and the output end of the eighth inverter can both output signals. When a higher output capacity is not required, the sixth inverter, the seventh inverter and the eighth inverter can be turned off to output a signal from the output end of the fifth inverter, thereby saving the power consumption occupied by the sixth inverter, the seventh inverter and the eighth inverter, thereby reducing the power consumption of the ring oscillator provided by the present invention.

[0011] As a possible implementation, the first inverter group includes: a first inverter and a fifth inverter. The second inverter group includes: a second inverter, a third inverter and a fourth inverter. The third inverter group includes a sixth inverter, a seventh inverter and an eighth inverter.

[0012] In the case of adopting the above technical solution, the transistor in at least one inverter included in the first inverter group is a ring-gate transistor, so that the first inverter and the fifth inverter have a higher switching frequency so that the ring oscillator provided by the present invention can output a high-frequency signal. Moreover, when the ring oscillator outputs via the output end of the fifth inverter, it can be beneficial to improve the output capacity of the ring oscillator provided by the present invention. Furthermore, the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor, so that the second inverter, the third inverter and the fourth inverter as the intermediate stage of the ring oscillator have lower power consumption than the first inverter group and the third inverter group, thereby reducing the power consumption of the ring oscillator provided by the present invention. In addition, the transistor in at least one inverter included in the third inverter group is a ring-gate transistor, so that the sixth inverter, the seventh inverter and the eighth inverter have a stronger driving capability, so that when outputting via the output end of the eighth inverter, it can be beneficial to improve the output capacity of the ring oscillator provided by the present invention.

[0013] As a possible implementation, the oxide thin film transistor has a back gate structure.

[0014] When the above technical solution is adopted, the oxide thin film transistor is arranged above the ring gate transistor, and the oxide thin film transistor with a back gate structure can be directly connected when its gate is interconnected with the ring gate transistor below, thereby reducing the wiring difficulty of the ring oscillator, thereby reducing the design cost of the ring oscillator manufactured by the embodiment of the present invention.

[0015] As a possible implementation, the ring oscillator includes an isolation layer disposed between a ring-gate transistor and an oxide thin film transistor, and an interconnection structure disposed in the isolation layer. The interconnection structure is used to lead out a first source region and a first drain region included in the ring-gate transistor, and to interconnect a first gate included in the ring-gate transistor and a second gate included in the oxide thin film transistor.

[0016] In the case of adopting the above technical solution, the isolation layer can be used as an insulating layer between the ring-gate transistor and the oxide thin film transistor to electrically isolate the two. Furthermore, the interconnection structure is arranged in the isolation layer, and the source and drain of the ring-gate transistor are led out, and the gate of the ring-gate transistor and the gate of the oxide thin film transistor are interconnected, so that the isolation layer has the function of a wiring layer, making the wiring of the ring-gate transistor and the oxide thin film transistor and their interconnection simpler, thereby reducing the wiring difficulty of manufacturing the ring oscillator provided by the present invention, thereby reducing the design cost of the ring oscillator manufactured by the present invention.

[0017] As a possible implementation, along the distribution direction of the all-around gate transistors and the oxide thin film transistors, the size of the interconnect structure is greater than or equal to 10 nm and less than or equal to 2000 nm.

[0018] When the above technical solution is adopted, the size of the interconnection structure is within the above range, which can avoid the increase of interconnection delay due to the large size of the interconnection structure, resulting in a large deviation of the output signal frequency from the design value, thereby improving the accuracy of the ring oscillator provided by the present invention. When the size of the interconnection structure is within the above range, it can also avoid the increase of the difficulty of interconnection structure wiring due to the small size of the interconnection structure, thereby reducing the wiring difficulty of the ring oscillator provided by the present invention, thereby reducing the design cost of the ring oscillator manufactured by the present invention.

[0019] In a second aspect, the present invention provides a method for manufacturing a ring oscillator, the method for manufacturing a ring oscillator comprising: providing a semiconductor substrate. Forming a plurality of inverters on the semiconductor substrate. The plurality of inverters are divided into a first inverter group, a second inverter group and a third inverter group. The first inverter group, the second inverter group and the third inverter group each include at least one inverter. Among them, the switching speed of the inverter included in the first inverter group is greater than the switching speed of the inverter included in the second inverter group; the power consumption of the inverter included in the second inverter group is less than the power consumption of the inverter included in the first inverter group and the third inverter group. The third inverter group is used to output a signal. The transistor in at least one inverter included in the first inverter group and the second inverter is a ring-gate transistor, and the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor; the oxide thin film transistor is arranged above the ring-gate transistor.

[0020] As a possible implementation, forming a ring-gate transistor on a semiconductor substrate includes: forming a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes alternating sacrificial layers and channel layers; in the alternating sacrificial layers and channel layers, the film layer located at the bottom is a sacrificial layer. Next, a mask structure is formed across the fin structure. Next, the portion of the fin structure exposed outside the mask structure is removed. Next, a first source region and a first drain region included in the ring-gate transistor are formed on both sides of the remaining fin structure. Next, at least a portion of the mask structure is removed, and the remaining sacrificial layer is removed so that the remaining channel layer forms a first channel region included in the ring-gate transistor. Next, a first gate dielectric layer and a first gate are sequentially formed on the periphery of the first channel region.

[0021] As a possible implementation, forming an oxide thin film transistor above the ring-gate transistor includes: forming an isolation layer on the ring-gate transistor. Next, forming a second gate included in the oxide thin film transistor on the isolation layer. Next, forming a second gate dielectric layer on the gate included in the oxide thin film transistor. Next, forming an active region on the second gate dielectric layer included in the oxide thin film transistor. The active region includes a second source region, a second drain region, and a second channel region located between the second source region and the second drain region. The second channel region is in contact with the second source region and the second drain region, respectively.

[0022] When the above technical solution is adopted, compared with the prior art, the beneficial effects of the method for manufacturing a ring oscillator provided by the present invention can be referred to the relevant description about the oxide thin film transistor in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 A schematic diagram of a gate-all-around transistor and an oxide thin-film transistor provided in an embodiment of the present invention;

[0025] Figure 2 A circuit logic diagram of a ring oscillator provided by an embodiment of the present invention;

[0026] Figure 3 is a process flow chart of forming a gate-all-around transistor on a semiconductor substrate in an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of forming a stacking structure in an embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of forming a fin-shaped structure in an embodiment of the present invention;

[0029] Figure 6 is a schematic diagram of forming a mask structure in an embodiment of the present invention;

[0030] Figure 7 is a schematic diagram of removing the portion of the fin structure exposed outside the mask structure in an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of etching a sacrificial layer to form a recess in an embodiment of the present invention;

[0032] Fig. 9 is a schematic diagram of forming an inner side wall in an embodiment of the present invention;

[0033] Fig.10 is a schematic diagram of forming a first source region and a first drain region in an embodiment of the present invention;

[0034] Fig.11 It is a schematic diagram of forming an isolation layer and planarizing it in an embodiment of the present invention;

[0035] Fig.12 is a schematic diagram of forming a first channel region in an embodiment of the present invention;

[0036] Fig.13 is a schematic diagram of forming a first gate dielectric layer and a first gate in an embodiment of the present invention;

[0037] Fig.14 is a process flow chart of forming an oxide thin film transistor above a gate-all-around transistor in an embodiment of the present invention;

[0038] Fig.15 is a schematic diagram of forming an isolation layer in an embodiment of the present invention;

[0039] Fig.16 is a schematic diagram of forming an interconnection structure in an embodiment of the present invention;

[0040] Fig.17 A schematic diagram of forming a gate electrode of an oxide thin film transistor in an embodiment of the present invention;

[0041] Fig.18 is a schematic diagram of forming a second gate dielectric layer in an embodiment of the present invention;

[0042] Fig.19 is a schematic diagram of forming an active region in an embodiment of the present invention;

[0043] Fig. 20 is a schematic diagram of forming a first electrode and a second electrode in an embodiment of the present invention;

[0044] Fig.21 is a schematic diagram of forming an isolation layer on an oxide thin film transistor in an embodiment of the present invention;

[0045] Fig. 22 FIG. 4 is a schematic diagram of forming a second interconnection portion in an embodiment of the present invention.

[0046] Reference numerals:

[0047] 100-semiconductor substrate, 200-gate-all-around transistor,

[0048] 211 - first source region, 212 - first drain region,

[0049] 220 - first gate dielectric layer, 221 - gate sidewall,

[0050] 222- inner side wall, 230- first gate,

[0051] 240-nanostructure, 310-first interconnection,

[0052] 320 - second interconnection, 330 - third interconnection,

[0053] 400 - oxide thin film transistor, 411 - first electrode,

[0054] 412 - second electrode, 420 - second gate dielectric layer,

[0055] 430 - second gate, 440 - active region,

[0056] 500-isolation layer, 231-sacrificial layer,

[0057] 232-gate oxide layer, 233-sacrificial gate,

[0058] 241-channel layer,

[0059] 260-fin structure, 270-mask structure,

[0060] 601-first inverter, 602-second inverter,

[0061] 603- third inverter, 604- fourth inverter,

[0062] 605 - fifth inverter, 606 - sixth inverter,

[0063] 607-seventh inverter, 608-eighth inverter. DETAILED DESCRIPTION

[0064] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.

[0065] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0066] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0067] In the description of the embodiments of the present invention, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the embodiments of the present invention.

[0068] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0069] Ring oscillators are widely used as clock signal generators due to their simple structure and no need for external oscillation sources.

[0070] With the development of microelectronics technology, it is necessary to further reduce the power consumption of ring oscillators to meet the requirements of low-power scenarios. However, in the prior art, due to the high power consumption of silicon-based transistors and / or germanium-based transistors, it is difficult to further reduce the power consumption of ring oscillators based on silicon-based transistors and / or germanium-based transistors.

[0071] The subthreshold swing of oxide thin-film transistors is usually smaller than that of traditional transistors, which means that under the same current control requirements, oxide thin-film transistors can operate at a lower voltage, effectively reducing the operating voltage and thus reducing dynamic power consumption. In addition, oxide thin-film transistors have near-threshold operating characteristics, which allow them to operate in a voltage range close to the threshold voltage of oxide thin-film transistors. The current of oxide thin-film transistors is small, but they can still maintain good switching characteristics, thereby reducing the power consumption of oxide thin-film transistors. Furthermore, oxide thin-film transistors have extremely low off-state leakage current, and their off-state power consumption is lower than that of traditional transistors.

[0072] To reduce the power consumption of the ring oscillator, refer to Figure 1 and Figure 2In a first aspect, an embodiment of the present invention provides a ring oscillator, which includes: a plurality of inverters; the plurality of inverters are divided into a first inverter group, a second inverter group, and a third inverter group. The first inverter group, the second inverter group, and the third inverter group each include at least one inverter. Among them, the switching speed of the inverter included in the first inverter group is greater than the switching speed of the inverter included in the second inverter group. The power consumption of the inverter included in the second inverter group is less than the power consumption of the inverter included in the first inverter group and the third inverter group. The third inverter group is used to output a signal. The transistor in at least one inverter included in the first inverter group and the third inverter is a ring-gate transistor 200, and the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor 400. The oxide thin film transistor 400 is arranged above the ring-gate transistor 200.

[0073] In the case of adopting the above technical solution, the switching speed of the inverter included in the first inverter group is greater than the switching speed of the inverter included in the second inverter group, and the third inverter group is used to output the signal. At the same time, the ring-gate transistor has a high switching speed and driving capability. Based on this, in the ring oscillator provided by the embodiment of the present invention, the transistor in at least one inverter of the first inverter group is a ring-gate transistor, which is conducive to the first inverter group having a faster switching speed, thereby ensuring efficient processing of data, so that the output result of the ring oscillator is more accurate, and is conducive to improving the working performance of the ring oscillator. In addition, the transistor in at least one inverter included in the third inverter is a ring-gate transistor, which is conducive to improving the driving capability of the third inverter, thereby facilitating the improvement of the maximum driving capability of the ring oscillator provided by the embodiment of the present invention. In addition, the ring-gate transistor can occupy a smaller area than the traditional planar transistor or fin field effect transistor under the same performance, thereby reducing the area occupied by the first inverter group and the second inverter group, and effectively improving the integration of the ring oscillator provided by the embodiment of the present invention. The leakage of the oxide thin film transistor has lower power consumption. Based on this, in the ring oscillator provided by the embodiment of the present invention, the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor, which can be beneficial to the second inverter group having lower power consumption. Since the oxide thin film transistor is arranged above the ring gate transistor, the ring oscillator provided by the embodiment of the present invention adopts a monolithic heterogeneous integrated device, which effectively improves the integration of the ring oscillator provided by the embodiment of the present invention. Further, the oxide thin film transistor can be formed by a low temperature process to avoid high temperature damage to the lower ring gate transistor in the process of manufacturing the upper device on the ring gate transistor, which is beneficial to the structural integrity of the ring gate transistor and the function of the ring gate transistor in accordance with the design expectations, thereby facilitating the improvement of the yield of the manufacturing process of the ring oscillator provided by the embodiment of the present invention. Furthermore, the first inverter group, the second inverter group and the third inverter group form a ring oscillator, and the power consumption of the ring oscillator can be reduced by selecting the second inverter group of oxide thin film transistors, and the switching speed and driving capability of the ring oscillator can be improved by the ring gate transistors selected by the first inverter group and the second inverter group, so that the ring oscillator provided by the embodiment of the present invention can take into account both low power consumption and high performance.

[0074] Regarding the multiple inverters included in the ring oscillator provided in the above embodiment of the present invention, it can be understood that the ring oscillator can include 3 inverters, 4 inverters, 5 inverters, 6 inverters or more inverters. The number of inverters included in the multiple inverters can be determined according to the period of the oscillation signal output to the ring oscillator.

[0075] For example, please refer to Figure 2The ring oscillator provided in the embodiment of the present invention includes a plurality of inverters including: a first inverter 601, a second inverter 602, a third inverter 603, a fourth inverter 604, a fifth inverter 605, a sixth inverter 606, a seventh inverter 607 and an eighth inverter 608. The first inverter 601, the second inverter 602, the third inverter 603, the fourth inverter 604, the fifth inverter 605, the sixth inverter 606, the seventh inverter 607 and the eighth inverter 608 are connected in series in sequence. The input end of the first inverter 601 is connected to the output end of the fifth inverter 605. The output end of the fifth inverter 605 and the output end of the eighth inverter 608 are used to output signals. Among them, the first inverter 601, the second inverter 602, the third inverter 603, the fourth inverter 604 and the fifth inverter 605 form an oscillation loop and function as an oscillator, and the sixth inverter 606, the seventh inverter 607 and the eighth inverter 608 play a buffering role for output amplification.

[0076] It can be understood that the multiple inverters included in the ring oscillator are connected in series in sequence, which means that the output end of the previous inverter is connected to the input end of the next inverter in the order of the first inverter to the eighth inverter.

[0077] In the case of adopting the above technical solution, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter form an oscillation loop, so that the ring oscillator generates an oscillation signal. The sixth inverter, the seventh inverter and the eighth inverter play a buffering role, and receive the oscillation signal output by the first five inverters, process and output the signal for output amplification, thereby improving the output capacity of the ring oscillator, which is conducive to improving the output capacity of the ring oscillator. In addition, the output end of the fifth inverter and the output end of the eighth inverter can both output signals. When a higher output capacity is not required, the sixth inverter, the seventh inverter and the eighth inverter can be turned off, and the signal is output from the output end of the fifth inverter, thereby saving the power consumption occupied by the sixth inverter, the seventh inverter and the eighth inverter, thereby reducing the power consumption of the ring oscillator provided by the embodiment of the present invention.

[0078] Furthermore, in the ring oscillator, multiple inverters included in the ring oscillator can be grouped according to different functional requirements, so that different inverter groups have different functions, and the types of transistors included in the inverter groups are determined according to the functions of the different inverter groups.

[0079] Exemplarily, multiple inverters are divided into a first inverter group that enables the ring oscillator to output a high-frequency signal, a second inverter group that increases the period of the ring oscillator output signal, and a third inverter group as the main output terminal. The first inverter group includes: a first inverter and a fifth inverter. The second inverter group includes: a second inverter, a third inverter and a fourth inverter. The third inverter group includes a sixth inverter, a seventh inverter and an eighth inverter. In addition, the switching speed of the first inverter and the fifth inverter is greater than the switching speed of the second inverter, the third inverter and the fourth inverter. The power consumption of the second inverter, the third inverter and the fourth inverter is greater than the power consumption of the other five inverters. The first inverter group and the second inverter group constitute an oscillation loop of the ring oscillator. The third inverter group is used to output a signal.

[0080] In order to meet the power consumption and switching speed requirements of the above-mentioned multiple inverters and each inverter group, in the ring oscillator provided in an embodiment of the present invention, the transistors in at least one inverter included in the first inverter group and the third inverter group are ring-gate transistors, and the transistors in at least one inverter included in the second inverter group are oxide thin film transistors.

[0081] In the case of adopting the above technical solution, the transistor in at least one inverter included in the first inverter group is a ring-gate transistor, so that the first inverter and the fifth inverter have a higher switching frequency so that the ring oscillator provided by the embodiment of the present invention can output a high-frequency signal, thereby ensuring efficient processing of data, so that the output result of the ring oscillator is more accurate, which is conducive to improving the working performance of the ring oscillator. In addition, when the ring oscillator outputs via the output end of the fifth inverter, it can be beneficial to the output capacity of the ring oscillator provided by the embodiment of the present invention. Furthermore, the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor, so that the second inverter, the third inverter and the fourth inverter as the intermediate stage of the ring oscillator have lower power consumption than the first inverter group and the third inverter group, thereby reducing the power consumption of the ring oscillator provided by the embodiment of the present invention. In addition, the transistor in at least one inverter included in the third inverter group is a ring-gate transistor, so that the sixth inverter, the seventh inverter and the eighth inverter have a stronger driving capability, so that when outputting via the output end of the eighth inverter, it can be beneficial to the output capability of the ring oscillator provided by the embodiment of the present invention.

[0082] In the ring oscillator provided in the embodiment of the present invention, it can be understood that the above-mentioned ring-gate transistor is arranged on a semiconductor substrate.

[0083] The embodiment of the present invention does not specifically limit the material of the semiconductor substrate, and it can be determined according to actual needs. For example, the semiconductor substrate includes at least one of silicon on insulator, silicon, germanium, germanium silicon, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Optionally, the material of the semiconductor substrate is silicon.

[0084] The embodiment of the present invention does not specifically limit the doping condition of the semiconductor substrate, and can be determined according to actual needs and the material of the semiconductor substrate. For example, when silicon is selected as the material of the semiconductor substrate, the semiconductor substrate can be appropriately doped to reduce the leakage of the first source region and the first drain region to the semiconductor substrate, thereby further reducing the power consumption of the ring-gate transistor, thereby reducing the power consumption of the ring oscillator.

[0085] The embodiment of the present invention does not specifically limit the structure of the ring-gate transistor in at least one inverter included in the first inverter group and the third inverter group, and can be determined according to the performance requirements of the first inverter group and the third inverter group.

[0086] As a possible implementation, please refer to Figure 1 The structure of the gate-all-around transistor 200 includes: a first source region 211, a first drain region 212, a first channel region, a first gate dielectric layer 220 and a first gate 230. The first source region 211, the first drain region 212 and the first channel region are formed on the semiconductor substrate 100. The first channel region is located between the first source region 211 and the first drain region 212, and the first channel region includes at least one layer of nanostructures 240 stacked along the thickness direction of the substrate. The first gate dielectric layer 220 surrounds the periphery of each layer of nanostructures 240, and the first gate 230 is arranged on the first gate dielectric layer 220. The first source region 211 and the first drain region 212 are arranged on the semiconductor substrate 100 and connected to the first channel region.

[0087] When the above technical solution is adopted, since the ring-gate transistor has the above structure, the ring-gate transistor adopts a surrounding gate design, so that the ring-gate transistor has better gate control capability, which is beneficial to suppress the short channel effect. Furthermore, the switching speed of the ring-gate transistor is faster, which enables the first inverter group using the ring-gate transistor to be applied to the generation of relatively high-frequency signals, thereby increasing the upper limit of the frequency range of the output signal of the ring oscillator provided in the embodiment of the present invention. In addition, the three-dimensional structure design of the ring-gate transistor allows it to integrate more transistors in a smaller chip area, effectively reducing the size of the transistor and improving the integration of the ring oscillator provided in the embodiment of the present invention.

[0088] It is understandable that the positions of the first source region and the first drain region can be exchanged, and the embodiment of the present invention does not make any specific limitation thereto, and can be determined according to the conductivity type of the nanostructure and the wiring requirements of the ring oscillator.

[0089] Optional, in the above technical solution, please refer to Figure 1 Inner sidewalls 222 may be further provided between the first gate 230 and the first source region 211 and between the first gate 230 and the first drain region 212 .

[0090] Optional, in the above technical solution, please refer to Figure 1 , along the thickness direction of the substrate, the first gate 230 is also arranged on the side of the nanostructure 240 farthest from the semiconductor substrate 100 away from the semiconductor substrate; and the all-around gate transistor further includes a first gate spacer 221. The first gate spacer 221 is at least located on both sides of the first gate 230 along the length direction to suppress leakage between the first gate 230 and other conductive structures. The first gate spacer 221 spans over the edge portions of both sides of the at least one layer of nanostructure 240 included in the first channel region along the length direction.

[0091] When using the above technical solution, please refer to Figure 1 The first gate sidewall 221 and the inner sidewall 222 can be used as an effective isolation medium to limit the length of the first gate 230 formed later on the inner side of the first gate sidewall 221 and the inner sidewall 222; the parasitic capacitance between the first gate and the first source region 211 and between the first gate 230 and the first drain region 212 can also be reduced, thereby increasing the switching speed of the ring-gate transistor 200, thereby increasing the upper limit of the frequency range of the output signal of the ring oscillator provided by the embodiment of the present invention. In addition, the first gate sidewall 221 and the inner sidewall 222 can optimize the electric field distribution inside the ring-gate transistor 200, so that the electric field is more concentrated on at least one layer of nanosheets, enhance the control ability of the gate over the channel, and improve the switching speed and current driving ability of the transistor. Furthermore, please refer to the description of the manufacturing method in the second aspect, the first gate sidewall 221 and the inner sidewall 222 can improve the process yield of manufacturing the ring oscillator.

[0092] The material of the first source region and the material of the first drain region are not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, the material of the first source region and the material of the first drain region include silicon, germanium or germanium silicon. Optionally, the material of the first source region and the material of the first drain region are silicon.

[0093] It is understandable that the doping type and concentration of the first source region and the first drain region need to be determined according to the conductivity type of the nanostructure to form a reasonable all-around gate transistor structure.

[0094] The material of the first gate is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, the material of the first gate includes: copper, aluminum, chromium, silver, gold or other possible materials.

[0095] The material of the at least one layer of nanostructure included in the first channel region is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, the material of the nanostructure includes silicon, germanium or germanium silicon.

[0096] The material of the first gate dielectric layer is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, the material of the first gate dielectric layer can be selected from traditional materials such as silicon dioxide to reduce the difficulty of manufacturing the first gate dielectric layer. The material of the first gate dielectric layer can also be selected from high dielectric constant materials such as hafnium-based oxides, aluminum oxides, zirconium oxides, and tantalum oxides to reduce the thickness of the first gate dielectric layer, thereby reducing the volume of the all-around gate transistor and improving the integration.

[0097] The material of the first gate sidewall and the inner sidewall is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, the material of the first gate sidewall and the inner sidewall includes silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride.

[0098] In addition, the first gate sidewall and the inner sidewall may be made of the same material or different materials, which is not specifically limited in the embodiment of the present invention and may be determined according to actual needs.

[0099] Secondly, please refer to Figure 1 and Fig. 22 An isolation layer 500 is further provided between the ring-gate transistor 200 and the oxide thin film transistor 400, and an interconnection structure is further provided in the isolation layer 500. The interconnection structure is used to lead out the first source region 211 and the first drain region 212 included in the ring-gate transistor 200, and to interconnect the first gate 230 included in the ring-gate transistor 200 and the second gate included in the oxide thin film transistor 400. Specifically, the interconnection structure includes a first interconnection portion 310 and a second interconnection portion 320, the first interconnection portion 310 is used to interconnect the first source region 211 and the first drain region 212, and the second interconnection portion 320 is used to interconnect the first gate 230 and the second gate 430.

[0100] When using the above technical solution, please refer to Figure 1 and Fig. 22, the isolation layer 500 can be used as an insulating layer between the ring-gate transistor 200 and the oxide thin film transistor 400 to electrically isolate the two. Furthermore, the interconnection structure is arranged in the isolation layer 500, and the first source region 211 and the first drain region 212 are led out, and the first gate 230 and the second gate 430 are interconnected, so that the isolation layer has the function of a wiring layer, making the wiring of the ring-gate transistor 200 and the oxide thin film transistor 400 and their interconnection simpler, thereby reducing the wiring difficulty of manufacturing the ring oscillator provided by the embodiment of the present invention, thereby reducing the design cost of the ring oscillator manufactured by the embodiment of the present invention.

[0101] Regarding the material of the interconnect structure, it may include copper, aluminum, chromium, silver, gold or other possible materials.

[0102] The embodiment of the present invention does not specifically limit the size of the interconnect structure, and the size may be determined according to the performance requirements and wiring requirements of the ring oscillator.

[0103] As a possible implementation, please refer to Figure 1 and Fig. 22 Along the distribution direction of the ring-gate transistor 200 and the oxide thin film transistor 400 , the size of the interconnect structure is greater than or equal to 10 nm and less than or equal to 2000 nm.

[0104] When the above technical solution is adopted, the size of the interconnection structure is within the above range, which can avoid the increase of interconnection delay due to the large size of the interconnection structure, resulting in a large deviation of the output signal frequency from the design value, thereby improving the accuracy of the ring oscillator provided by the embodiment of the present invention. When the size of the interconnection structure is within the above range, it can also avoid the increase of the difficulty of interconnection structure wiring due to the small size of the interconnection structure, thereby reducing the wiring difficulty of the ring oscillator provided by the embodiment of the present invention, thereby reducing the design cost of the ring oscillator manufactured by the embodiment of the present invention.

[0105] It can be understood that the thickness of the isolation layer between the all-around gate transistor and the oxide thin film transistor is the same as the size of the above-mentioned interconnect structure along the distribution direction of the all-around gate transistor and the oxide thin film transistor.

[0106] Secondly, the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor, and the oxide thin film transistor is arranged above the ring-gate transistor.

[0107] The embodiment of the present invention does not specifically limit the type of the above-mentioned oxide thin film transistor, which can be determined according to actual needs.

[0108] As a possible implementation, at least one oxide thin film transistor is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor or a titanium oxide thin film transistor.

[0109] When the above technical solution is adopted, in the ring oscillator provided in the embodiment of the present invention, at least one oxide thin film transistor is selected as the above type of transistor, which can make the range of device types that can be selected for the oxide thin film transistor larger. Different oxide thin film transistors can be selected according to the actual needs when applying the ring-gate transistor provided in the embodiment of the present invention, thereby meeting the switching speed, power consumption, conductivity type, operating voltage and other parameter requirements of at least one inverter included in the second inverter group, thereby expanding the application scope of the ring oscillator provided in the embodiment of the present invention.

[0110] Regarding the structure of the above-mentioned oxide thin film transistor, it can be a forward gate structure, or it can also be a back gate structure.

[0111] Specifically, in the case where the oxide thin film transistor is a back-gate structure, please refer to Figure 1 , the oxide thin film transistor 400 is arranged on the isolation layer 500, and the oxide thin film transistor 400 includes: a first electrode 411, a second electrode 412, a second gate dielectric layer 420, a second gate 430 and an active area 440. The second gate 430 is arranged on the isolation layer 500. The second gate dielectric layer 420 is arranged on the active area 440. The active area 440 is arranged on the second gate dielectric layer 420. The active area 440 includes a second source area, a second drain area, and a second channel area between the second source area and the second drain area. The second channel area included in the oxide thin film transistor 400 is in contact with the second source area and the second drain area, respectively. The first electrode 411 is arranged on the second source area as the source electrode of the oxide thin film transistor 400. The second electrode 412 is arranged on the second drain area as the drain electrode of the oxide thin film transistor 400. The second gate 430 is the gate included in the oxide thin film transistor.

[0112] When the above technical solution is adopted, the oxide thin film transistor is arranged above the ring-gate transistor, and the oxide thin film transistor with a back-gate structure can be directly connected when its gate is interconnected with the ring-gate transistor below, thereby reducing the wiring difficulty of the ring oscillator and thus reducing the design cost of the ring oscillator manufactured by the embodiment of the present invention.

[0113] Understandably, please refer to Figure 1 The second gate dielectric layer 420 , the active region 440 , the first electrode 411 , and the second electrode 412 may all extend onto the isolation layer 500 in a direction parallel to the semiconductor substrate 100 .

[0114] Regarding the material of the second gate, please refer to the material of the second gate and related descriptions, which will not be repeated here.

[0115] Regarding the material of the second gate dielectric layer, please refer to the material and related description of the first gate dielectric layer, which will not be repeated here.

[0116] Regarding the materials of the first electrode and the second electrode, please refer to the material of the second gate and related descriptions, which will not be repeated here.

[0117] In addition, please refer to Figure 1 , the isolation layer 500 can also extend onto the oxide thin film transistor 400, so as to isolate the first electrode 411 and the second electrode 412 to reduce leakage, and isolate the oxide thin film transistor 400 from the outside to prevent the oxide thin film transistor 400 from being affected or polluted by the outside environment. In addition, in the portion where the isolation layer 500 extends onto the oxide thin film transistor 400, a third interconnection portion 330 can also be provided to lead out the first electrode 411 and the second electrode 412, and connect the oxide thin film transistor 400 with other transistors in the ring oscillator according to the circuit logic of the ring oscillator.

[0118] Regarding the material of the third interconnection part, please refer to the related description of the material of the above interconnection structure, which will not be repeated here.

[0119] It can be understood that the interconnection structure and the specific structure of the third interconnection portion can be determined according to the detailed circuit logic of the ring oscillator provided by the above-mentioned embodiment of the present invention.

[0120] In a second aspect, an embodiment of the present invention provides a method for manufacturing a ring oscillator, which is used to manufacture the ring oscillator provided in the first aspect. The method for manufacturing the ring oscillator includes: first, providing a semiconductor substrate. Next, forming a plurality of inverters on the semiconductor substrate. The plurality of inverters are divided into a first inverter group, a second inverter group and a third inverter group. The first inverter group, the second inverter group and the third inverter group each include at least one inverter. Among them, the switching speed of the inverter included in the first inverter group is greater than the switching speed of the inverter included in the second inverter group. The power consumption of the inverter included in the second inverter group is less than the power consumption of the inverter included in the first inverter group and the third inverter group. The third inverter group is used to output a signal. The transistor in at least one inverter included in the first inverter group and the second inverter is a ring gate transistor, and the transistor in at least one inverter included in the second inverter group is an oxide thin film transistor. The oxide thin film transistor is arranged above the ring gate transistor.

[0121] When the above technical solution is adopted, the beneficial effects of the method for manufacturing a ring oscillator provided by the embodiment of the present invention can be referred to the relevant description of the first aspect, and will not be repeated here.

[0122] First, please refer to Figure 4 , a semiconductor substrate 100 is provided.

[0123] Regarding the material and doping conditions of the semiconductor substrate, please refer to the relevant description of the first aspect and will not be repeated here.

[0124] Please refer to Figures 4 to 13 The process of forming the gate-all-around transistor 200 on the semiconductor substrate 100 is described below. Exemplarily, the process of forming the gate-all-around transistor 200 on the semiconductor substrate 100 includes the following steps:

[0125] Please refer to Figure 5 , a fin structure 260 is formed on the semiconductor substrate 100. Along the thickness direction of the semiconductor substrate 100, the fin structure 260 includes a sacrificial layer 231 and a channel layer 241 that are alternately arranged. Among the sacrificial layers 231 and the channel layers 241 that are alternately arranged, the film layer located at the bottom is the sacrificial layer 231. It should be noted that, for the convenience of description and display, Figure 4 and Figure 5 The ring oscillator is perpendicular to Figure 1 Schematic diagram of the paper orientation.

[0126] Specifically, the channel layer is used to form at least one layer of nanostructure included in the subsequent first channel region. The thickness of the channel layer can be determined according to the performance requirements of the all-around gate transistor, and the embodiment of the present invention does not specifically limit it.

[0127] The sacrificial layer serves as a placeholder layer for the first gate and the first gate dielectric layer to be formed subsequently. Its material may include silicon oxide, silicon nitride, polysilicon, etc., and its thickness needs to be determined according to the thickness of the first gate and the first gate dielectric layer.

[0128] In the fin structure, the film layer at the bottom is a sacrificial layer, and the film layer at the top can be a channel layer or a sacrificial layer.

[0129] In the actual manufacturing process, please refer to Figure 4 , epitaxy or other processes may be used to form a stacked sacrificial layer 231 and a channel layer 241 on a semiconductor substrate according to the distribution of the film layers in the fin structure 260 described above. Then, as Figure 5As shown, dry etching or wet etching processes can be used, and under the protection of the first mask, at least the stacked sacrificial layer 231 and the channel layer 241 are selectively etched to form a fin on the semiconductor substrate 100. Among them, the above-mentioned first mask can include any mask layer with mask protection function such as a silicon nitride mask, a silicon oxide mask, a photoresist mask, etc., as long as it can be applied to the manufacturing method provided in the embodiment of the present invention. In addition, if the semiconductor substrate 100 used is a semiconductor substrate with a buried oxide layer such as a silicon-on-insulator substrate, it is only necessary to selectively etch the stacked sacrificial layer 231 and the channel layer 241 to obtain the fin structure 260 (the fin is the fin structure at this time). If the semiconductor substrate 100 used does not include a buried oxide layer, when performing the above-mentioned selective etching, it is also necessary to etch part of the semiconductor substrate 100; and after the fin is formed, a shallow trench isolation structure (STI) is formed on the semiconductor substrate 100 by using deposition and etching processes. The top height of the shallow trench isolation structure is less than or equal to the bottom height of the sacrificial layer located at the bottom layer. The part of the fin exposed outside the shallow trench isolation structure is a fin-shaped structure.

[0130] Next, please refer to Figure 6 , forming a mask structure 270 straddling the fin structure 260 .

[0131] Specifically, the embodiment of the present invention does not impose any specific limitation on the structure and material of the mask structure, as long as it can protect the portion of the fin structure used to manufacture the channel region when the fin structure is selectively etched later.

[0132] Exemplarily, the mask structure may include only the sacrificial gate; or, the mask structure may include the sacrificial gate and the first gate spacers 1 disposed on both sides of the sacrificial gate along the length direction; or, please refer to Figure 6 The mask structure 270 may further include a gate oxide layer 232 and a sacrificial gate 233 stacked in sequence along the thickness direction of the semiconductor substrate 100 , and a first gate spacer 221 disposed on both sides of the sacrificial gate along the length direction.

[0133] The material of the sacrificial gate may include amorphous silicon or silicon germanium or other easily etched materials. Furthermore, the material of the gate oxide layer may include silicon oxide, germanium oxide, or a mixture of silicon oxide and germanium oxide.

[0134] When the above technical solution is adopted, the first gate sidewall is a sidewall of the first gate formed subsequently, which electrically isolates the first gate from structures such as the first source region and the second source region.

[0135] In the actual manufacturing process, please refer to Figure 6, epitaxy or deposition and other processes may be used to form a mask structure 270 on the fin structure 260 according to the distribution of each film layer in the mask structure 270 described above. If the mask structure 270 only includes the sacrificial gate 233, epitaxy or deposition and other processes may be used to form the sacrificial gate 233 on the fin structure 260, and then, dry etching or wet etching and other processes may be used, and under the protection of the second mask, the sacrificial gate 233 may be selectively etched to form the mask structure 270 on the semiconductor substrate 100. The above-mentioned second mask may include any mask layer with mask protection function, such as a silicon nitride mask, a silicon oxide mask, a photoresist mask, etc., as long as it can be applied to the manufacturing method provided in the embodiment of the present invention. In addition, if the mask structure 270 also includes a first gate sidewall 221 disposed on both sides of the sacrificial gate 233 along the length direction, after etching the sacrificial gate 233, it is also necessary to deposit a first gate sidewall layer on the fin structure 260 and the sacrificial gate 233, and then use an etching process to make the first gate sidewall layer form the first gate sidewall 221. If the mask structure 270 also includes a gate oxide layer 232 formed by stacking with the sacrificial gate 233 in sequence along the thickness direction of the semiconductor substrate 100, epitaxy or deposition processes can be used to form a stacked gate oxide layer 232 and a sacrificial gate 233 on the semiconductor substrate according to the distribution of each film layer in the mask structure 270 described above, and then the gate oxide layer 232 and the sacrificial gate 233 are etched, and then the first gate sidewall 221 is formed on both sides of the gate oxide layer 232 and the sacrificial gate 233.

[0136] Next, please refer to Figure 7 , a dry etching process or a wet etching process may be used to remove the portion of the fin structure 260 exposed outside the mask structure 270 .

[0137] For example, please refer to Fig. 9 In the case where the manufactured semiconductor device also includes an inner sidewall, after removing the portion of the fin structure 260 exposed outside the mask structure 270, an inner sidewall 222 may be formed in the fin structure 260. Specifically, the steps of forming the inner sidewall include: Figure 8 , using wet etching or other etching processes, the edge portion of the sacrificial layer 231 is etched to form a notch. Next, please refer to Fig. 9 An inner sidewall layer is formed on the mask structure 270 and the fin structure 260 by epitaxial growth or other processes, and the inner sidewall layer is etched to form an inner sidewall 222 in the above-mentioned recess.

[0138] Next, please refer to Fig.10 , epitaxial growth or other processes may be used to form a first source region 211 and a first drain region 212 of the gate-all-around transistor on both sides of the remaining fin structure 260 .

[0139] Next, please refer to Fig.12 , using a process such as dry etching or wet etching to remove at least a portion of the mask structure 270 and remove the remaining sacrificial layer 231, so that the remaining channel layer 241 forms the nanostructure 240 included in the all-around gate transistor.

[0140] The following takes the case where the mask structure includes an oxide layer, a sacrificial gate, a second mask, and a first gate sidewall as an example to illustrate the process of removing at least part of the mask structure and the remaining sacrificial layer. Fig.11 , an isolation layer 500 is formed on the first source region 211 and the first drain region 212. Next, the isolation layer 500 is planarized, and the gate oxide layer 232 is partially removed. Next, please refer to Fig.12 , remove the sacrificial gate 233 , the second mask 234 and the remaining sacrificial layer 231 , and make the remaining channel layer 241 form at least one layer of nanostructure 240 included in the first channel region.

[0141] When using the above technical solution, please refer to Fig.11 The isolation layer 500 serves as an interlayer dielectric (ILD) to protect the first source region 211 and the first drain region 212 from being affected by subsequent processes, which is beneficial to the structural integrity of the first source region 211 and the first drain region 212 and to prevent contamination, thereby facilitating the normal function of the ring oscillator manufactured by the embodiment of the present invention. In addition, the planarization treatment of the isolation layer 500 can improve the flatness of the surface of the isolation layer 500 away from the semiconductor substrate 100, providing a good foundation for subsequent processes. It can be understood that the isolation layer 500 formed in this step can extend to the semiconductor substrate 100.

[0142] Next, if Fig.12 and Fig.13 As shown, a first gate dielectric layer 220 and a first gate 230 may be sequentially formed on the periphery of the first channel region by using processes such as atomic layer deposition.

[0143] Regarding the contents and beneficial effects of the structure of the above-mentioned ring-gate transistor that are not described, such as materials, etc., please refer to the relevant description of the first aspect and will not be repeated here.

[0144] It should be noted that the above-mentioned ring-gate transistor can be formed in a variety of ways. How to form the above-mentioned ring-gate transistor is not the main feature of the embodiment of the present invention, so in this specification, only a brief introduction is given to it so that ordinary technicians in this field can easily implement the embodiment of the present invention. Ordinary technicians in this field can completely imagine other ways to make the above-mentioned ring-gate transistor.

[0145] Please refer to Figures 14 to 21The process of forming the oxide thin film transistor 400 above the ring-gate transistor 200 is described below. Exemplarily, the process of forming the oxide thin film transistor 400 above the ring-gate transistor 200 includes the following steps:

[0146] Please refer to Fig.15 , an isolation layer 500 may be formed on the gate-all-around transistor 200 by using processes such as chemical vapor deposition or atomic layer deposition.

[0147] When using the above technical solution, please refer to Fig.15 The isolation layer 500 is used to isolate the ring-gate transistor 200 and the oxide thin film transistor 400 to avoid leakage and short circuit between the ring-gate transistor 200 and the oxide thin film transistor 400. The isolation layer 500 also serves as the basis for the subsequent formation of various structures included in the oxide thin film transistor 400. The isolation layer 500 also serves as the basis for the subsequent formation of the first interconnection part 310 and the second interconnection part 320 included in the interconnection structure, so as to facilitate the wiring of the ring oscillator manufactured by the embodiment of the present invention, thereby reducing the design cost of the ring oscillator manufactured by the embodiment of the present invention.

[0148] Next, please refer to Fig.16 The above-mentioned forming of the isolation layer 500 on the ring-gate transistor 200 further includes: forming a first interconnection portion 310 including an interconnection structure in the isolation layer 500; please refer to Fig. 22 , and the connection of the first inverter group, the second inverter group and the third inverter group included in the ring oscillator manufactured according to the embodiment of the present invention forms a second interconnection portion 320 included in the interconnection structure in the isolation layer 500.

[0149] In the actual manufacturing process, please refer to Fig.16 and Fig. 22 , an interconnection through hole is formed in the isolation layer 500 according to the distribution of the interconnection structure described above by an etching process. Then, in the interconnection through hole, a process such as chemical vapor deposition is used to form the first interconnection 310 and the second interconnection 320 respectively. If the first interconnection 310 includes a structure parallel to the semiconductor substrate 100, after the structure included in the first interconnection 310 and arranged along the thickness direction of the substrate is partially formed, the structure in the first interconnection 310 parallel to the semiconductor substrate 100 can be formed on the isolation layer 500 by combining a deposition process and an etching process, and then the isolation layer 500 is continuously formed on the first interconnection 310.

[0150] Next, please refer to Fig.17 , a second gate 430 of the oxide thin film transistor is formed on the isolation layer 500 .

[0151] In the actual manufacturing process, please refer to Fig.17A second gate forming layer may be formed on the isolation layer 500 by using a process such as atomic layer deposition, and then the second gate forming layer may be selectively etched by using a process such as dry etching or wet etching to form a second gate 430 on the isolation layer 500 .

[0152] Next, please refer to Fig.18 , a second gate dielectric layer 420 is deposited on the second gate 430 .

[0153] In the actual manufacturing process, please refer to Fig.18 , a second gate dielectric layer forming layer can be formed on the isolation layer 500 and the second gate 430 by using processes such as atomic layer deposition, and then the second gate dielectric layer forming layer can be selectively etched by using processes such as dry etching or wet etching to form a second gate dielectric layer 420 on the isolation layer 500.

[0154] Next, please refer to Fig.19 , an active area 440 is formed on the second gate dielectric layer 420 included in the oxide thin film transistor. The active area 440 includes a second source area, a second drain area, and a second channel area located between the second source area and the second drain area, and the second channel area is in contact with the second source area and the second drain area, respectively. The second channel area included in the oxide thin film transistor is in contact with the second source area and the second drain area, respectively. Specifically, an active area formation layer is formed on the second gate dielectric layer 420 and the isolation layer 500, and then the active area formation layer is patterned by wet etching to form the active area 440.

[0155] Next, please refer to Fig. 20 After forming an active region 440 on the second gate dielectric layer 420 included in the oxide thin film transistor, forming the oxide thin film transistor 400 above the ring-gate transistor 200 further includes:

[0156] Please refer to Fig. 20 , forming a first electrode 411 and a second electrode 412, wherein the first electrode 411 is used as a source electrode of the oxide thin film transistor 400 and is disposed on the second source region. The second electrode 412 is used as a drain electrode of the oxide thin film transistor 400 and is disposed on the second drain region.

[0157] In the actual manufacturing process, please refer to Fig. 20 A metal layer may be formed on the isolation layer 500 and the second gate 430 by using processes such as atomic layer deposition. Then, according to the distribution of the first electrode 411 and the second electrode 412 described above, the metal layer may be selectively etched by using processes such as dry etching or wet etching to form the first electrode 411 and the second electrode 412.

[0158] Next, please refer to Fig.21 and Figure 1 , an isolation layer 500 is formed on the oxide thin film transistor, and a third interconnection 330 including an interconnection structure is formed in the isolation layer 500. The third interconnection 330 is used to lead out the first electrode 411 and the second electrode 412, and connect the oxide thin film transistor 400 with other transistors in the ring oscillator according to the circuit logic of the ring oscillator.

[0159] In the actual manufacturing process, the third interconnection may be formed by using the same process as the first interconnection and the second interconnection.

[0160] Regarding the contents and beneficial effects of the structure of the above-mentioned oxide thin film transistor that have not been described, such as materials, etc., please refer to the relevant description of the first aspect and will not be repeated here.

[0161] It should be noted that the oxide thin film transistor can be formed in a variety of ways. How to form the oxide thin film transistor is not the main feature of the embodiment of the present invention, so in this specification, only a brief introduction is given so that ordinary technicians in the field can easily implement the embodiment of the present invention. Ordinary technicians in the field can completely imagine other ways to make the oxide thin film transistor.

[0162] Next, according to the circuit logic of the ring oscillator provided in the first aspect, a plurality of ring-gate transistors and oxide thin film transistors included in the ring-gate transistor can be interconnected through an interconnection structure and a third interconnection part, for example, by using a back-end of line (BEOL) process to form a ring oscillator composed of multiple inverters and multiple inverters.

[0163] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0164] The above is only a specific implementation of the embodiment of the present invention, but the protection scope of the embodiment of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the embodiment of the present invention, which should be included in the protection scope of the embodiment of the present invention. Therefore, the protection scope of the embodiment of the present invention should be based on the protection scope of the claims.

Claims

1. A ring oscillator, characterized in that: The inverter comprises a plurality of inverters; the plurality of inverters are divided into a first inverter group, a second inverter group and a third inverter group; the first inverter group, the second inverter group and the third inverter group each comprise at least one inverter; Wherein, the switching speed of the inverters included in the first inverter group is greater than the switching speed of the inverters included in the second inverter group; the power consumption of the inverters included in the second inverter group is less than the power consumption of the inverters included in the first inverter group and the third inverter group; the third inverter group is used to output signals; The transistor in at least one of the inverters included in the first inverter group and the third inverter is a ring-gate transistor, and the transistor in at least one of the inverters included in the second inverter group is an oxide thin film transistor; the oxide thin film transistor is arranged above the ring-gate transistor.

2. The ring oscillator according to claim 1, characterized in that At least one of the oxide thin film transistors is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor or a titanium oxide thin film transistor.

3. The ring oscillator according to claim 1, characterized in that: The plurality of inverters include: a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter; The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are connected in series in sequence; the input end of the first inverter is connected to the output end of the fifth inverter; the output end of the fifth inverter and the output end of the eighth inverter are used to output signals.

4. The ring oscillator according to claim 3, characterized in that: The first inverter group includes: a first inverter and a fifth inverter; The second inverter group includes: a second inverter, a third inverter and a fourth inverter; The third inverter group includes a sixth inverter, a seventh inverter and an eighth inverter.

5. The ring oscillator according to claim 1, characterized in that: The oxide thin film transistor has a back gate structure.

6. The ring oscillator according to claim 1, characterized in that: The ring oscillator includes an isolation layer arranged between the ring-gate transistor and the oxide thin film transistor, and an interconnection structure arranged in the isolation layer; the interconnection structure is used to lead out a first source region and a first drain region included in the ring-gate transistor, and to interconnect a first gate included in the ring-gate transistor and a second gate included in the oxide thin film transistor.

7. The ring oscillator according to claim 1, characterized in that: Along the distribution direction of the ring-gate transistor and the oxide thin film transistor, the size of the interconnect structure is greater than or equal to 10 nm and less than or equal to 2000 nm.

8. A method for manufacturing a ring oscillator, characterized in that: include: Providing a semiconductor substrate; forming a plurality of inverters on the semiconductor substrate; The plurality of inverters are divided into a first inverter group, a second inverter group and a third inverter group; The first inverter group, the second inverter group and the third inverter group each include at least one inverter; wherein the switching speed of the inverter included in the first inverter group is greater than the switching speed of the inverter included in the second inverter group; the power consumption of the inverter included in the second inverter group is less than the power consumption of the inverter included in the first inverter group and the third inverter group; the third inverter group is used to output signals; the transistor in at least one of the inverters included in the first inverter group and the second inverter is a ring-gate transistor, and the transistor in at least one of the inverters included in the second inverter group is an oxide thin film transistor; the oxide thin film transistor is arranged above the ring-gate transistor.

9. The ring oscillator according to claim 8, characterized in that: Forming the gate-all-around transistor on the semiconductor substrate comprises: A fin-shaped structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the fin-shaped structure includes sacrificial layers and channel layers that are alternately arranged; among the sacrificial layers and channel layers that are alternately arranged, the film layer located at the bottom is the sacrificial layer; forming a mask structure spanning over the fin-shaped structure; removing a portion of the fin structure exposed outside the mask structure; forming a first source region and a first drain region included in the gate-all-around transistor on both sides of the remaining fin structure; removing at least a portion of the mask structure and removing the remaining sacrificial layer, so that the remaining channel layer forms a first channel region included in the gate-all-around transistor; A first gate dielectric layer and a first gate are sequentially formed around the first channel region.

10. The ring oscillator according to claim 8, characterized in that Forming the oxide thin film transistor above the gate-all-around transistor includes: forming an isolation layer on the gate-all-around transistor; forming a second gate of the oxide thin film transistor on the isolation layer; forming a second gate dielectric layer on the second gate; An active region is formed on the second gate dielectric layer; the active region includes a second source region, a second drain region, and a second channel region located between the second source region and the second drain region; the second channel region is in contact with the second source region and the second drain region respectively.

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