A method for optimizing the spurs of a phase-locked loop based on a mixing architecture

Abstract

The present invention discloses a method for optimizing the spurs of a phase-locked loop based on a mixing architecture. The method includes: first, determining a frequency division ratio set of a first phase-locked loop based on a set output frequency and a frequency range of a synthesized reference signal, where the synthesized reference signal is specifically a signal obtained by mixing the output signal of a second phase-locked loop with a fixed reference local oscillator signal; then determining a set of spur values corresponding to each frequency division ratio in the frequency division ratio set, and extracting the worst spur value from each group of spur values to obtain a set of worst spur values; finally, determining an optimal spur value based on the set of worst spur values, and using the frequency division ratio corresponding to the optimal spur value as the final frequency division ratio, which can effectively reduce the spurs in a multi-loop phase-locked loop and reduce costs, thereby improving the performance of the multi-loop phase-locked loop.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and particularly relates to a method for optimizing the spurs of a phase-locked loop based on a mixing architecture. Background Art

[0002] The local oscillator phase noise refers to the phenomenon of signal quality degradation in radio frequency transmitters and receivers due to the phase noise of the fixed reference local oscillator signal. The fixed reference local oscillator signal plays a key role in the up-conversion and down-conversion processes, and its phase noise will have a significant impact on the quality of the transmitted and received signals. With the rapid development of electronic technology, the requirements for local oscillator phase noise are getting higher and higher.

[0003] In the prior art, a circuit with a mixing architecture is provided to meet the requirements for local oscillator phase noise. The mixing architecture in the prior art is a multi-loop technology, mainly including a main loop and a bias loop. Its application core mainly includes two schemes. Scheme one is to mix the main loop signal and the bias loop signal to a lower intermediate frequency signal through mixing, and then lock the intermediate frequency signal to the fractional loop frequency reference to achieve. Scheme two is to increase the output signal frequency of the bias loop as the phase comparison signal of the main loop, thereby reducing the main loop division ratio to achieve. However, the multi-loop based on the former mixing scheme in the prior art is relatively complex, with larger power consumption and area, and higher cost. The multi-loop based on the latter mixing scheme is relatively simple and has lower cost and power consumption, but there are spur problems, which affect the performance.

[0004] Therefore, how to reduce the spurs in the multi-loop phase-locked loop and reduce the cost while ensuring that the cost of the mixing architecture is not high, so as to improve the performance of the multi-loop phase-locked loop, is a technical problem to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to solve the technical problem of more spurs in the mixing scheme with lower cost in the prior art, so as to reduce the spurs based on a simpler design, lower power consumption, cost, and area.

[0006] To achieve the above technical purpose, on the one hand, the present invention provides a method for optimizing the spurs of a phase-locked loop based on a mixing architecture, and the method includes:

[0007] Determine the division ratio set of the first phase-locked loop based on the set output frequency and the frequency range of the synthesized reference signal, where the synthesized reference signal is specifically the signal after mixing the output signal of the second phase-locked loop and the fixed reference local oscillator signal;

[0008] Determine the spur value group corresponding to each division ratio in the division ratio set, and extract the worst spur value in each group of spur values to obtain the worst spur value group;

[0009] Determine the optimal spurious value based on the worst spurious value group, and use the frequency division ratio corresponding to the optimal spurious value as the final frequency division ratio.

[0010] Further, the worst spurious value is the value with the smallest absolute value in each group of spurious values.

[0011] Further, or extract the worst spurious value through the following process:

[0012] Divide the spurious values corresponding to the finite high-order harmonics of the same fixed reference local oscillator signal in the spurious value group into different subgroups, take the spurious value with the smallest absolute value in each subgroup as the spurious value to be extracted, and group all the spurious values to be extracted and their related parameters into a first list;

[0013] Determine the worst spurious value based on the first list.

[0014] Further, the determination of the worst spurious value based on the first list specifically includes:

[0015] Traverse the first list, and take the current spurious value to be extracted in the traversal as the spurious value to be processed;

[0016] If the spurious value to be processed is less than 1, group all the spurious values corresponding to the minimum high-order harmonic of the fixed reference local oscillator signal in the first list into a second list, and normalize all the spurious values in the second list. When there are two or more spurious values in the second list, take the spurious value corresponding to the smallest absolute value as the spurious value to be determined as the worst spurious value; if the spurious value to be processed is not less than 1, extract a third list from the first list, and normalize all the spurious values in the third list. When there are two or more spurious values in the third list, take the spurious value with the smallest absolute value as the spurious value to be determined as the worst spurious value. Any spurious value in the third list corresponds to the fixed reference local oscillator signal with the smallest high-order harmonic and the actual spurious difference is less than the expected spurious difference. The actual spurious difference is equal to the spurious value to be processed minus the corresponding spurious value in the third list, and the expected spurious difference is equal to the difference between the high-order harmonic of the fixed reference local oscillator signal corresponding to the spurious value to be processed and the high-order harmonic of the fixed reference local oscillator signal corresponding to the corresponding spurious value in the third list multiplied by 5;

[0017] After normalizing all the spurious values to be determined as the worst spurious value, take the spurious value with the smallest absolute value after normalization as the worst spurious value.

[0018] Further, the determination of the optimal spurious value based on the worst spurious value group specifically includes:

[0019] Arrange the spurious values in the worst spurious value group in descending order to form a sequence;

[0020] Take the first spurious value in the sequence as the current spurious value, and start from the second spurious value as the spurious value to be compared, and compare the spurious effects with the current spurious value in turn. Among them, when the spurious effect of a certain spurious value is better than the current spurious value, update the corresponding spurious value to the current spurious value.

[0021] Further, the process of comparing the spurious effects specifically includes:

[0022] S60. Determine whether the value obtained by subtracting the high-order harmonic corresponding to the fixed reference local oscillator signal of the to-be-compared spurious value from the high-order harmonic corresponding to the fixed reference local oscillator signal of the current spurious value is not less than 2. If so, perform the next comparison; if not, execute S61.

[0023] S61. Determine whether the current spurious value is not less than 1 and the to-be-compared spurious value is less than 1. If so, perform the next comparison; if not, execute S62.

[0024] S62. Determine whether the value obtained by subtracting the high-order harmonic corresponding to the fixed reference local oscillator signal of the to-be-compared spurious value from the high-order harmonic corresponding to the fixed reference local oscillator signal of the current spurious value is equal to 1 and the value obtained by subtracting the current spurious value from the to-be-compared spurious value is not greater than 5. If so, perform the next comparison; if not, execute S63.

[0025] S63. If the high-order harmonic corresponding to the fixed reference local oscillator signal of the current spurious value is the same as the high-order harmonic corresponding to the fixed reference local oscillator signal of the to-be-compared spurious value, and the value obtained by subtracting the current spurious value from the to-be-compared spurious value is greater than 2, then update the current spurious value. If the high-order harmonic corresponding to the fixed reference local oscillator signal of the current spurious value is the same as the high-order harmonic corresponding to the fixed reference local oscillator signal of the to-be-compared spurious value, and the value obtained by subtracting the current spurious value from the to-be-compared spurious value is less than 2, and the value obtained by subtracting the high-order harmonic corresponding to the second phase-locked loop output signal of the to-be-compared spurious value from the high-order harmonic corresponding to the second phase-locked loop output signal of the current spurious value is greater than 3, then update the to-be-compared spurious value to the current spurious value and then perform the next comparison. If the high-order harmonic corresponding to the fixed reference local oscillator signal of the current spurious value is the same as the high-order harmonic corresponding to the fixed reference local oscillator signal of the to-be-compared spurious value, and the value obtained by subtracting the current spurious value from the to-be-compared spurious value is less than 2, and the value obtained by subtracting the high-order harmonic corresponding to the second phase-locked loop output signal of the to-be-compared spurious value from the high-order harmonic corresponding to the second phase-locked loop output signal of the current spurious value is not greater than 3, then execute S64.

[0026] S64. Determine whether the first actual spurious difference is less than the first predicted spurious difference. If so, execute S65. If not and the first actual spurious difference is less than 3.5, update the spurious value to be compared with the current item spurious value. Wherein, the first actual spurious difference is specifically the difference between the current item spurious value and the spurious value to be compared, and the first predicted spurious difference is equal to the difference between the higher harmonics of the fixed reference local oscillator signal corresponding to the current item spurious value and the higher harmonics of the fixed reference local oscillator signal corresponding to the spurious value to be compared, multiplied by 5;

[0027] S65. Determine whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current item spurious value is not less than 2 and the higher harmonics of the fixed reference local oscillator signal corresponding to the spurious value to be compared is not less than 2. If so, execute S66. If not, execute the next comparison;

[0028] S66. Determine whether the absolute value of the current item spurious value is greater than or equal to 4.5 and the absolute value of the spurious value to be compared is less than 5. If so, execute the next comparison. If not, execute S67;

[0029] S67. Determine whether the difference obtained by subtracting the absolute value of the spurious value to be compared from the absolute value of the current item spurious value is less than 1.5 and the absolute values of the current item spurious value and the spurious value to be compared are both less than or equal to 3. If so, execute S68. If not, execute the next comparison;

[0030] S68. Determine whether the higher harmonics of the fixed reference local oscillator signal corresponding to the current item spurious value is greater than the higher harmonics of the fixed reference local oscillator signal corresponding to the spurious value to be compared, and the higher harmonics of the fixed reference local oscillator signal corresponding to the current item spurious value is equal to 1. If so, execute the next comparison. If not, execute S69;

[0031] S69. Determine whether the current item spurious value is greater than the spurious value to be compared and the current item spurious value is not 1. If so, update the spurious value to be compared with the current item spurious value and then execute the next comparison. If not, execute the next comparison.

[0032] Further, after frequency doubling the fixed reference signal of the second phase-locked loop, a fixed reference local oscillator signal is obtained.

[0033] A method for optimizing spurs of a phase-locked loop based on a mixing architecture provided by the present invention, compared with the prior art, first determines a frequency division ratio set of a first phase-locked loop based on a set output frequency and a frequency range of a synthesized reference signal, where the synthesized reference signal is specifically a signal obtained by mixing an output signal of a second phase-locked loop with a fixed reference local oscillator signal; then determines a spurious value group corresponding to each frequency division ratio in the frequency division ratio set, and extracts the worst spurious value from each group of spurious values to obtain a worst spurious value group; finally determines an optimal spurious value based on the worst spurious value group, and uses the frequency division ratio corresponding to the optimal spurious value as the final frequency division ratio, which can effectively reduce spurs in a multi-loop phase-locked loop and reduce costs, thereby improving the performance of the multi-loop phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments described in this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1 The figure shows a schematic flow chart of a method for optimizing spurs of a phase-locked loop based on a mixing architecture provided by an embodiment of this specification;

[0036] Figure 2 The figure shows a schematic structural diagram of a mixing architecture in an embodiment of this specification. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] In order to enable those of ordinary skill in the art to better understand the technical solutions in this specification, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0038] As Figure 1The following is a schematic flowchart of the method for optimizing the spurious of a phase-locked loop based on a mixing architecture provided by the embodiments of the present specification. Although the present specification provides the method operation steps or device structures shown in the following embodiments or drawings, more or fewer operation steps or module units may be included in the method or device based on routine or non-creative labor. In steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure shown in the embodiments or drawings of the present specification. When the method or module structure is applied to an actual device, server, or terminal product, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or drawings.

[0039] The method for optimizing the spurious of a phase-locked loop based on a mixing architecture provided by the embodiments of the present specification can be applied to various mixing architectures, such as Figure 1 As shown, the method specifically includes the following steps:

[0040] Step S101: Determine the division ratio set of the first phase-locked loop based on the set output frequency and the frequency range of the synthesized reference signal. The synthesized reference signal is specifically the signal after mixing the output signal of the second phase-locked loop and the fixed reference local oscillator signal.

[0041] First, refer to Figure 2 This is a schematic structural diagram of a mixing architecture, including a second phase-locked loop and a first phase-locked loop. The first phase-locked loop is the main loop that outputs the required frequency. Its input is the synthesized reference signal after mixing the output signal of the second phase-locked loop and the fixed reference local oscillator signal. The structures of the first phase-locked loop and the second phase-locked loop can be seen Figure 2As shown, the phase-locked loop structure is the same as that in the prior art, and the multi-loop mixing architecture is not adjusted in the solution of this application. The mixing architecture mainly includes a second phase-locked loop or a signal generator, a mixing module, and a first phase-locked loop. The fractional loop, that is, the second phase-locked loop or the DDS module, that is, the signal generator, is responsible for providing a variable reference signal for fine frequency tuning within a certain range; the reference frequency multiplication and mixing module is responsible for multiplying the fixed time-base reference frequency, then extracting the high-order harmonics of the fixed time-base reference, and mixing them with the aforementioned variable reference signal. After mixing, the intermediate-frequency signal also changes within a certain range following the variable reference signal. This intermediate-frequency signal is used as the synthesized reference signal and provided to the main loop, that is, the first phase-locked loop, for phase discrimination. The main loop locks onto the intermediate-frequency signal. When this intermediate-frequency signal changes within a certain designed range, the main loop can track and seamlessly lock onto the intermediate-frequency signal through the continuously variable division ratio D, thereby achieving full-band frequency coverage output. It is described as follows in the order from top to bottom and from left to right: The fractional loop module consists of an input fixed time-base reference fREF, a phase detector PFD, a broadband VCO, a frequency divider, a fractional controller, and a loop filter. The output of the VCO is dynamically divided by the frequency divider operated by the fractional controller and then sent to the phase detector to perform phase discrimination with another input fixed time-base reference fREF. The output error voltage is sent to the loop filter, and the final negative feedback tuning voltage tunes the VCO, thereby finally achieving loop locking. Since this module is a fractional loop, it can provide an output for fine frequency tuning, and the same applies to DDS. After dividing the output of this fractional loop by a fixed frequency divider, a continuously tunable frequency output reference signal within a limited range is obtained, that is, the output signal of the second phase-locked loop. The reference frequency multiplication and mixing module is mainly responsible for extracting the high-order harmonics after multiplying the fixed time-base reference frequency, and then mixing the extracted high-order time-base harmonics with the aforementioned continuously tunable frequency output reference signal. After passing through a band-pass filter, the corresponding synthesized reference signal is obtained. The main loop module is mainly responsible for finally outputting the frequency signal, which is usually a broadband loop or an integrated loop. When the aforementioned corresponding reference signal is obtained, by controlling and setting the corresponding division ratio D of the main loop, the main loop frequency divider divides the broadband VCO signal and then sends it to the main loop phase detector to perform phase discrimination with the intermediate frequency, that is, the corresponding reference signal, obtained after mixing. After external loop filtering, the broadband VCO is tuned and locked, and finally a broadband output frequency is obtained.

[0042] Among them, the division ratio set of the first phase-locked loop is determined according to the set output frequency and the frequency range of the synthesized reference signal. The division ratio D = the frequency of the output signal of the main phase-locked loop, that is, the first phase-locked loop / the synthesized reference frequency, where the synthesized reference frequency, that is, the frequency of the synthesized reference signal, is obtained by mixing the variable range reference signal output by the FN loop or DDS with the harmonics of the fixed-frequency time-base reference signal. Each available division value D is calculated to obtain the corresponding synthesized reference frequency (synthesized reference frequency = K * fixed-frequency time-base reference signal + / - variable range reference signal output by the FN loop or DDS, where K is a positive integer).

[0043] For each synthesized reference frequency, there is a corresponding unique FN loop or DDS reference frequency. If the harmonic number of the FN loop or DDS reference frequency is set to M and the harmonic frequency of the fixed reference local oscillator signal is N, the intermediate frequency signal based on the mixing architecture will generate M*N spurs. Therefore, a limited-range M*N spur calculation is performed for each FN loop or DDS reference frequency based on the actual spur attenuation performance (that is, for the mixer input, there are RF input and LO terminals, and non-linear products will be generated at both ends of the signal when the mixer is working, namely M*RF and N*LO. Then, the N*LO + / - M*RF products will be obtained at the final intermediate frequency output. Among these non-linear products, except for the fundamental product which is the intermediate frequency we need, other high-order products are unwanted frequency points that may generate spurs).

[0044] Step S102: Determine the spur value group corresponding to each division ratio in the division ratio set, and extract the worst spur value from each group of spur values to obtain the worst spur value group.

[0045] Specifically, the worst spur value is the value with the smallest absolute value in each group of spur values. After determining the spur value group corresponding to each division ratio in the division ratio set, the method further includes normalizing each spur value based on weights.

[0046] After successively obtaining the spur delta values generated by different M combinations corresponding to the finite range N respectively (the high-order non-linear products N*LO + / - M*RF of the mixer will generate various different frequencies, and this frequency will be modulated onto the intermediate frequency signal to generate spurs, and this spur value represents the frequency difference between it and the main spectrum, that is, the delta value), similarly, the delta values are normalized according to the weights.

[0047] According to the loop bandwidth and the roll-off suppression curve, the in-band and out-of-band up to 10 MHz are divided into multiple segments. Corresponding priority numbers are assigned according to their different suppression degrees. (The loop filter design is divided into in-band and out-of-band. Among them, the in-band will not have any suppression on spurs; the out-of-band is further divided into a standard suppression band and an additional suppression band according to the loop design, etc. Each suppression band has a different low-pass suppression rate or roll-off rate according to the specific design differences. Therefore, different suppression bands and suppression degrees can be obtained through calculation.) Theoretically, more segments will bring better selectivity, but at the same time, it will bring the complexity of M*N weight discrimination. Therefore, the number of segments needs to comprehensively consider feasibility, accuracy, and complexity. The loop is divided into in-band and out-of-band, and the out-of-band can be further divided into a standard suppression band and an additional suppression band according to different loop designs, etc. Therefore, segmentation can be carried out according to the roll-off rates of different suppression bands. In this example, a total of 6 suppression bands are designed and divided according to different roll-off rates, namely in-band, in-band to 1 MHz, 1 MHz to 3 MHz, 3 MHz to 5 MHz, 5 MHz to 10 MHz, and beyond 10 MHz. Each suppression band has a different weight.

[0048] In some embodiments, the worst spurious value is extracted through the following process:

[0049] Divide the spurious values corresponding to the finite high-order harmonics of the same fixed reference local oscillator signal in the spurious value group into different subgroups. Take the spurious value with the smallest absolute value in each subgroup as the spurious value to be extracted, and group all the spurious values to be extracted and their related parameters into a first list;

[0050] Determine the worst spurious value based on the first list.

[0051] The determining the worst spurious value based on the first list specifically includes:

[0052] Traverse the first list and take the spurious value to be extracted in the current item during the traversal as the spurious value to be processed;

[0053] If the stray value to be processed is less than 1, all stray value groups corresponding to the minimum high-order harmonic of the fixed reference local oscillator signal in the first list are grouped into the second list. At the same time, all stray values in the second list are normalized. When there are two or more stray values in the second list, the stray value corresponding to the smallest absolute value is used as the worst stray value to be determined. If the stray value to be processed is not less than 1, a third list is extracted from the first list. At the same time, all stray values in the third list are normalized. When there are two or more stray values in the third list, the stray value with the smallest absolute value is used as the worst stray value to be determined. For any stray value in the third list, the high-order harmonic of the corresponding fixed reference local oscillator signal is the smallest and the actual stray difference is less than the predicted stray difference. The actual stray difference is equal to the stray value to be processed minus the corresponding stray value in the third list. The predicted stray difference is equal to the difference between the high-order harmonic of the fixed reference local oscillator signal corresponding to the stray value to be processed and the high-order harmonic of the fixed reference local oscillator signal corresponding to the corresponding stray value in the third list multiplied by 5;

[0054] After normalizing all the worst stray values to be determined, the worst stray value is the one with the smallest absolute value after normalization.

[0055] Step S103: Determine the optimal stray value based on the worst stray value group, and use the frequency division ratio corresponding to the optimal stray value as the final frequency division ratio.

[0056] In the embodiment of the present application, the determining the optimal stray value based on the worst stray value group specifically includes:

[0057] Arrange the stray values in the worst stray value group in descending order to form a sequence;

[0058] Take the first stray value in the sequence as the current stray value, and start from the second stray value as the stray value to be compared and compare the stray effects with the current stray value in turn. Among them, when the stray effect of a certain stray value is better than the current stray value, the corresponding stray value is updated to the current stray value.

[0059] In the embodiment of the present application, the process of comparing the stray effects specifically includes:

[0060] S60: Determine whether the value obtained by subtracting the high-order harmonic of the fixed reference local oscillator signal corresponding to the current stray value from the high-order harmonic of the fixed reference local oscillator signal corresponding to the stray value to be compared is not less than 2. If so, perform the next comparison. If not, execute S61;

[0061] S61: Determine whether the current stray value is not less than 1 and the stray value to be compared is less than 1. If so, perform the next comparison. If not, execute S62;

[0062] S62. Determine whether the value obtained by subtracting the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value from the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared is equal to 1 and the value obtained by subtracting the current item spurious value from the spurious value to be compared is not greater than 5. If so, perform the next comparison; otherwise, execute S63.

[0063] S63. If the high-order harmonics corresponding to the fixed reference local oscillator signals of the current item spurious value and the spurious value to be compared are the same, and the value obtained by subtracting the current item spurious value from the spurious value to be compared is greater than 2, update the current item spurious value. If the high-order harmonics corresponding to the fixed reference local oscillator signals of the current item spurious value and the spurious value to be compared are the same, and the value obtained by subtracting the current item spurious value from the spurious value to be compared is less than 2, and the value obtained by subtracting the high-order harmonic corresponding to the second phase-locked loop output signal of the spurious value to be compared from the high-order harmonic corresponding to the second phase-locked loop output signal of the current item spurious value is greater than 3, update the spurious value to be compared to the current item spurious value and then perform the next comparison. If the high-order harmonics corresponding to the fixed reference local oscillator signals of the current item spurious value and the spurious value to be compared are the same, and the value obtained by subtracting the current item spurious value from the spurious value to be compared is less than 2, and the value obtained by subtracting the high-order harmonic corresponding to the second phase-locked loop output signal of the spurious value to be compared from the high-order harmonic corresponding to the second phase-locked loop output signal of the current item spurious value is not greater than 3, execute S64.

[0064] S64. Determine whether the first actual spurious difference is less than the first expected spurious difference. If so, execute S65; if not and the first actual spurious difference is less than 3.5, update the spurious value to be compared to the current item spurious value, where the first actual spurious difference is specifically the difference between the current item spurious value and the spurious value to be compared, and the first expected spurious difference is equal to the difference between the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value and the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared multiplied by 5.

[0065] S65. Determine whether the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value is not less than 2 and the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared is not less than 2. If so, execute S66; if not, perform the next comparison.

[0066] S66. Determine whether the absolute value of the current item spurious value is greater than or equal to 4.5 and the absolute value of the spurious value to be compared is less than 5. If so, perform the next comparison; if not, execute S67.

[0067] S67. Determine whether the difference obtained by subtracting the absolute value of the stray value of the comparison target from the absolute value of the stray value of the current item is less than 1.5 and the absolute values of the stray value of the current item and the stray value of the comparison target are both less than or equal to 3. If so, execute S68; otherwise, execute the next comparison.

[0068] S68. Determine whether the higher harmonic of the fixed reference local oscillator signal corresponding to the stray value of the current item is greater than the higher harmonic of the fixed reference local oscillator signal corresponding to the stray value of the comparison target, and the higher harmonic of the fixed reference local oscillator signal corresponding to the stray value of the current item is equal to 1. If so, execute the next comparison; otherwise, execute S69.

[0069] S69. Determine whether the stray value of the current item is greater than the stray value of the comparison target and the stray value of the current item is not equal to 1. If so, update the comparison target to the stray value of the current item and then execute the next comparison; otherwise, execute the next comparison.

[0070] Specifically, the solution of this application actually first determines all the stray values corresponding to each frequency division ratio, and then determines the worst stray value in the stray value group corresponding to each frequency division ratio. The worst stray value is also the stray value that has the greatest impact on the main frequency signal. Then, find the stray value that has the smallest impact on the main frequency signal among all the worst stray values and use it as the optimal stray value. This is because the loop has an inhibitory effect, and only the stray within a certain range from the main frequency will have a greater impact on the main frequency signal. Therefore, the conventional method of finding the optimal stray value in the stray value group corresponding to the frequency division ratio has an unsatisfactory effect. Therefore, first determine the worst stray value corresponding to each frequency division ratio, and then determine the optimal stray value from them, so as to determine the optimal frequency division ratio, and finally determine the input signal of the second phase-locked loop.

[0071] Based on the above-mentioned method for optimizing the stray of the phase-locked loop based on the mixing architecture, one or more embodiments of this specification also provide a platform and a terminal for optimizing the stray of the phase-locked loop based on the mixing architecture. The platform or terminal may include devices, software, modules, plugins, servers, clients, etc. that use the method described in the embodiments of this specification, and devices that combine the necessary implementation hardware. Based on the same innovative concept, the systems in one or more embodiments provided by the embodiments of this specification are as described in the following embodiments. Since the implementation solutions of the systems for solving problems are similar to the methods, the implementation of the specific systems in the embodiments of this specification may refer to the implementation of the foregoing methods, and the repeated parts will not be elaborated. The term "unit" or "module" used below may be a combination of software and / or hardware that can implement a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, hardware and a combination of software and hardware implementations are also possible and contemplated.

[0072] The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or plugins can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed among each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0073] These computer program instructions can also be loaded onto a computer or other programmable resource data update device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one process or multiple processes and / or Figure 1 the steps of the functions specified in one block or multiple blocks.

[0074] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple. The relevant parts can refer to the description of the method embodiment. In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0075] Those of ordinary skill in the art will realize that the embodiments described here are to help the reader understand the principles of the present invention. It should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of the present invention according to the technical revelations disclosed in the present invention, and these deformations and combinations are still within the protection scope of the present invention.

Claims

1. A method for optimizing the spurs of a phase-locked loop based on a mixing architecture, characterized in that The method includes: Determining a frequency division ratio set of a first phase-locked loop based on a set output frequency and a frequency range of a synthesized reference signal, where the synthesized reference signal is specifically a signal obtained by mixing an output signal of a second phase-locked loop with a fixed reference local oscillator signal, and the fixed reference local oscillator signal is obtained by multiplying the fixed reference signal of the second phase-locked loop by a frequency; Determining a set of spurious values corresponding to each frequency division ratio in the frequency division ratio set, and performing normalization processing on all spurious values, and then extracting the worst spurious value in each set of spurious values to obtain a worst spurious value set; Determining an optimal spurious value based on the worst spurious value set, and using the frequency division ratio corresponding to the optimal spurious value as the final frequency division ratio.

2. The method for optimizing the spurs of a phase-locked loop based on a mixing architecture according to claim 1, wherein The worst spurious value is the value with the smallest absolute value in each set of spurious values.

3. The method for optimizing the spurs of a phase-locked loop based on a mixing architecture according to claim 2, wherein, Or the worst spurious value is extracted through the following process: Dividing the spurious values corresponding to the finite high-order harmonics of the same fixed reference local oscillator signal in the set of spurious values into different subgroups, taking the spurious value with the smallest absolute value in each subgroup as the spurious value to be extracted, and grouping all the spurious values to be extracted and their related parameters into a first list; Determining the worst spurious value based on the first list.

4. The method for optimizing the spurs of a phase-locked loop based on a mixing architecture according to claim 3, wherein, The determining the worst spurious value based on the first list specifically includes: Traversing the first list, and using the current spurious value to be extracted in the traversal as the spurious value to be processed; If the spurious value to be processed is less than 1, grouping all the spurious values corresponding to the minimum high-order harmonics of the fixed reference local oscillator signal in the first list into a second list, and performing normalization processing on all the spurious values in the second list, and when there are two or more spurious values in the second list, taking the spurious value corresponding to the smallest absolute value as the spurious value to be determined as the worst spurious value; if the spurious value to be processed is not less than 1, extracting a third list from the first list, and performing normalization processing on all the spurious values in the third list, and when there are two or more spurious values in the third list, taking the spurious value with the smallest absolute value as the spurious value to be determined as the worst spurious value, where any spurious value in the third list corresponds to the minimum high-order harmonics of the fixed reference local oscillator signal and the actual spurious difference is less than the expected spurious difference, the actual spurious difference is equal to the spurious value to be processed minus the corresponding spurious value in the third list, and the expected spurious difference is equal to the difference between the high-order harmonics of the fixed reference local oscillator signal corresponding to the spurious value to be processed and the high-order harmonics of the fixed reference local oscillator signal corresponding to the corresponding spurious value in the third list multiplied by 5; After performing normalization processing on all the spurious values to be determined as the worst spurious value, taking the spurious value to be determined as the worst spurious value with the smallest absolute value after normalization processing as the worst spurious value.

5. The method for optimizing the spurs of a phase-locked loop based on a mixing architecture according to claim 1, wherein The determining the optimal spurious value based on the worst spurious value set specifically includes: Arranging the spurious values in the worst spurious value set from largest to smallest in sequence; Taking the first spurious value in the sequence as the current spurious value, and starting from the second spurious value as the spurious value to be compared, comparing the spurious effects with the current spurious value in turn, where when the spurious effect of a certain spurious value is better than the current spurious value, updating the corresponding spurious value to the current spurious value.

6. The method for optimizing the spurs of a phase-locked loop based on a mixing architecture according to claim 5, wherein The process of comparing the spurious effects specifically includes: S60. Determine whether the value obtained by subtracting the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value from the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared is not less than 2. If so, perform the next comparison. If not, execute S61; S61. Determine whether the current item spurious value is not less than 1 and the spurious value to be compared is less than 1. If so, perform the next comparison. If not, execute S62; S62. Determine whether the value obtained by subtracting the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared from the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value is equal to 1 and the value obtained by subtracting the current item spurious value from the spurious value to be compared is not greater than 5. If so, perform the next comparison. If not, execute S63; S63. If the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value is the same as the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared, and the value obtained by subtracting the current item spurious value from the spurious value to be compared is greater than 2, then update the current item spurious value. If the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value is the same as the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared, and the value obtained by subtracting the current item spurious value from the spurious value to be compared is less than 2, and the value obtained by subtracting the high-order harmonic corresponding to the second phase-locked loop output signal of the spurious value to be compared from the high-order harmonic corresponding to the second phase-locked loop output signal of the current item spurious value is greater than 3, then update the spurious value to be compared to the current item spurious value and then perform the next comparison. If the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value is the same as the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared, and the value obtained by subtracting the current item spurious value from the spurious value to be compared is less than 2, and the value obtained by subtracting the high-order harmonic corresponding to the second phase-locked loop output signal of the spurious value to be compared from the high-order harmonic corresponding to the second phase-locked loop output signal of the current item spurious value is not greater than 3, then execute S64; S64. Determine whether the first actual spurious difference is less than the first expected spurious difference. If so, execute S65. If not and the first actual spurious difference is less than 3.5, then update the spurious value to be compared to the current item spurious value, where the first actual spurious difference is specifically the difference between the current item spurious value and the spurious value to be compared, and the first expected spurious difference is equal to the difference between the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value and the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared multiplied by 5; S65. Determine whether the high-order harmonic corresponding to the fixed reference local oscillator signal of the current item spurious value is not less than 2 and the high-order harmonic corresponding to the fixed reference local oscillator signal of the spurious value to be compared is not less than 2. If so, execute S66. If not, perform the next comparison; S66. Determine whether the absolute value of the current item spurious value is greater than or equal to 4.5 and the absolute value of the spurious value to be compared is less than 5. If so, perform the next comparison. If not, execute S67; S67. Determine whether the difference obtained by subtracting the absolute value of the stray value to be compared from the absolute value of the current item's stray value is less than 1.5 and the absolute values of the current item's stray value and the stray value to be compared are both less than or equal to 3. If so, execute S68; if not, execute the next comparison. S68. Determine whether the higher harmonic of the fixed reference local oscillator signal corresponding to the current item's stray value is greater than the higher harmonic of the fixed reference local oscillator signal corresponding to the stray value to be compared, and the higher harmonic of the fixed reference local oscillator signal corresponding to the current item's stray value is equal to 1. If so, execute the next comparison; if not, execute S69. S69. Determine whether the current item's stray value is greater than the stray value to be compared and the current item's stray value is not 1. If so, update the stray value to be compared with the current item's stray value and then execute the next comparison; if not, execute the next comparison.

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