Adaptive common-mode hybrid structure successive approximation analog-to-digital converter

Abstract

The invention discloses an adaptive common-mode hybrid structure successive approximation analog-to-digital converter, which comprises two single-ended m-bit FLASH ADCs, a fully differential n-bit SAR ADC and an encoder, and the fully differential SAR ADC comprises two groups of binary capacitor arrays including a P end and an N end and corresponding switch control logic circuits. The two m-bit single-ended input FLASH ADCs quantize input signals of the P end and the N end respectively, and quantization results control a high m-bit capacitor switch in the fully differential SAR ADC. A pair of preceding-stage FLASH ADCs are added on the basis of a traditional SAR ADC to convert differential signals respectively, converted digital codes serve as DAC input in the SAR ADC, so that common-mode signals and differential-mode signals corresponding to high-order codes are subtracted in the DAC, a comparator in the SAR ADC only needs to process low-order signals, the common mode is constant, the amplitude of the differential-mode signals is small, and the differential-mode signals can be converted into the low-order signals. And the problems of signal overload and common-mode interference are avoided.

Description

Technical Field

[0001] The invention relates to an adaptive common-mode hybrid structure successive approximation analog-to-digital converter, belonging to the technical field of high-precision analog-to-digital converters in integrated circuits. Background Art

[0002] In the field of successive approximation analog-to-digital converters (SAR ADCs), the comparator is one of the core circuits, and the performance of the comparator will directly affect the accuracy of the analog-to-digital converter. The factors that restrict the accuracy of the comparator mainly include noise, offset, bandwidth, gain, and common-mode rejection. For traditional SAR ADCs, the common mode of the input signal will be directly reflected to the comparator input, so the common-mode rejection capability of the comparator directly determines the common-mode rejection capability of the ADC.

[0003] In addition, for traditional SAR ADC, when there is a large common-mode disturbance in the input signal, the bias current of the comparator input pair tube will change greatly, which will cause the transconductance coefficient to change and thus change the small signal gain, and on the other hand, it will cause the output common-mode level to shift and thus limit the maximum allowable output swing. This limits the application of traditional SAR ADC in systems with large common-mode signal changes. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an adaptive common-mode hybrid structure successive approximation analog-to-digital converter, which solves the problem that when the input common-mode level of the traditional SAR ADC changes greatly, the internal switch leaks or the comparator works abnormally, thereby causing the ADC performance to deteriorate. The present invention can significantly improve the common-mode voltage operating range of the input signal and has a higher common-mode rejection ratio.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] An adaptive common-mode hybrid structure successive approximation analog-to-digital converter, comprising a P-end flash memory analog-to-digital converter, an N-end flash memory analog-to-digital converter, a fully differential successive approximation analog-to-digital converter and an encoder, wherein the P-end flash memory analog-to-digital converter and the N-end flash memory analog-to-digital converter are both m-bit flash memory analog-to-digital converters, the fully differential successive approximation analog-to-digital converter is an n-bit fully differential successive approximation analog-to-digital converter, and m<n, and m and n are both positive integers;

[0007] The fully differential successive approximation analog-to-digital converter includes a P-terminal fully differential digital-to-analog conversion capacitor array, an N-terminal fully differential digital-to-analog conversion capacitor array, a fully differential comparator, and a successive approximation logic and a low-bit segment switch control circuit;

[0008] The input end of the P-end flash analog-to-digital converter and the input end of the P-end fully differential digital-to-analog conversion capacitor array simultaneously sample the fully differential analog input signal Vip, and the input end of the N-end flash analog-to-digital converter and the input end of the N-end fully differential digital-to-analog conversion capacitor array simultaneously sample the fully differential analog input signal Vin; the P-end flash analog-to-digital converter converts the input signal Vip into a digital code DFp <m:1>The N-end flash analog-to-digital converter converts the input signal Vin into a digital code DFn <m:1>; Digital code DFp <m:1>Control the high m-bit capacitor array in the fully differential digital-to-analog conversion capacitor array at the P end, digital code DFn <m:1>The high m-bit capacitor array in the fully differential fractional analog conversion capacitor array at the N end is controlled. The low-bit segment capacitor arrays of the fully differential fractional analog conversion capacitor arrays at the P end and the N end are controlled by a successive approximation logic and a low-bit segment switch control circuit. The successive approximation logic and the low-bit segment switch control circuit output a digital code DS. <n-m:1>, digital code DFp <m:1>、DFn <m:1>and DS <n-m:1>After passing through the encoder, the final digital code D is output <n:1>.

[0009] As a preferred solution of the present invention, when the P-end flash analog-to-digital converter and the N-end flash analog-to-digital converter are sampling, the upper plates of all capacitors of the P-end and N-end fully differential digital-to-analog conversion capacitor arrays are connected to the reference voltage Vcm0, and the input voltages of the in-phase input terminal and the inverting input terminal of the fully differential comparator are both Vcm0; the lower plates of all capacitors of the P-end fully differential digital-to-analog conversion capacitor array are connected to the input signal Vip, and the lower plates of all capacitors of the N-end fully differential digital-to-analog conversion capacitor array are connected to the input signal Vin;

[0010] The P-end flash analog-to-digital converter and the N-end flash analog-to-digital converter convert their respective input signals into digital codes at the same timing. During the conversion process, the upper plates of all capacitors in the P-end and N-end fully differential digital-to-analog conversion capacitor arrays are disconnected from the external reference voltage Vcm0, and the digital code DFp of the P-end flash analog-to-digital converter is <m:1>Control the high m-bit capacitor switch of the fully differential digital-to-analog conversion capacitor array at the P end to connect to the external reference voltage Vref 2 or GND, and the digital code DFn of the flash analog-to-digital converter at the N end <m:1>The high m-bit capacitor switches of the fully differential fractional analog conversion capacitor array at the N end are controlled to be connected to the external reference voltage Vref 2 or GND; the remaining low nm-bit capacitor switches of the fully differential fractional analog conversion capacitor array at the P end and the N end are switched in sequence by the successive approximation logic and the low-bit segment switch control circuit.

[0011] As a preferred solution of the present invention, the P-end fully differential digital-to-analog conversion capacitor array includes n+1 capacitors in parallel, the upper plates of all capacitors are connected to the in-phase input terminal of the fully differential comparator, the lower plates of all capacitors are connected to Vip when sampling the fully differential analog input signal, and when converting the input signal Vip into a digital code, the high m-bit capacitor switch is connected to an external reference voltage Vref 2 or GND; when the i-th bit output code DFp(i) of the P-end flash analog-to-digital converter is 1, the corresponding n-m+i-th bit capacitor lower plate in the P-end fully differential digital-to-analog conversion capacitor array is connected to Vref 2, otherwise it is connected to GND; the low nm-bit capacitor switches are switched in sequence by successive approximation logic and a low-bit segment switch control circuit;

[0012] The N-terminal fully differential digital-to-analog conversion capacitor array includes n+1 capacitors connected in parallel, the upper plates of all the capacitors are connected to the inverting input terminal of the fully differential comparator, the lower plates of all the capacitors are connected to Vin when sampling the fully differential analog input signal, and when converting the input signal Vin into a digital code, the high m-bit capacitor switch is connected to the external reference voltage Vref 2 or GND; when the i-bit output code DFn(i) of the N-terminal flash analog-to-digital converter is 1, the corresponding n-m+i-bit capacitor lower plate in the N-terminal fully differential digital-to-analog conversion capacitor array is connected to Vref 2, otherwise it is connected to GND; the low nm-bit capacitor switches are switched in sequence by the successive approximation logic and the low-bit segment switch control circuit.

[0013] As a preferred solution of the present invention, the P-end flash analog-to-digital converter and the N-end flash analog-to-digital converter have the same structure, both comprising 2 m resistors, 2 m -1 comparator and an encoding circuit, 2 m The remaining end of the first resistor is grounded, and the second m The remaining end of the resistor is connected to the external reference voltage Vref 1, and the connection point of the two adjacent resistors is connected to the non-inverting input terminal of a comparator through a switch. m -1 The inverting input of each comparator is connected to the fully differential analog input signal Vip or Vin, 2 m The output ends of -1 comparators are connected to the input ends of the encoding circuit, and the output ends of the encoding circuit are connected to the input ends of the P-end or N-end fully differential digital-to-analog conversion capacitor array.

[0014] As a preferred solution of the present invention, the digital code output by the P-end flash analog-to-digital converter is assigned to the digital code of the high m-bit capacitor of the P-end fully differential digital-to-analog conversion capacitor array, and the digital code output by the N-end flash analog-to-digital converter is assigned to the digital code of the high m-bit capacitor of the N-end fully differential digital-to-analog conversion capacitor array. The corresponding relationship is:

[0015]

[0016] Among them, D n-m+i , DB n-m+i They represent the control words of the n-m+i-th capacitors at the P-end and N-end in an n-bit fully differential successive approximation analog-to-digital converter, respectively. The minimum value of n-m+i is 1. DFp(i) and DFn(i) represent the i-th output codes of the flash analog-to-digital converter at the P-end and the flash analog-to-digital converter at the N-end, respectively.

[0017] The residual voltage at the non-inverting and inverting inputs of the fully differential comparator is:

[0018]

[0019] Wherein, Vxp and Vxn respectively represent the output voltages of the fully differential digital-to-analog conversion capacitor arrays at the P and N ends of the fully differential successive approximation analog-to-digital converter, that is, the input voltages of the non-inverting input and the inverting input of the fully differential comparator, Vcm0 represents the common-mode voltage of the upper plate of the capacitor array during sampling, Vref1 represents the reference voltage of the flash analog-to-digital converter, CP_tot and CN_tot represent the total capacitance values ​​of the fully differential digital-to-analog conversion capacitor arrays at the P and N ends of the fully differential successive approximation analog-to-digital converter, and CP_tot=CN_tot, CP(n-m+i) and CN(n-m+i) respectively represent the capacitance values ​​of the n-m+ith positions in the fully differential digital-to-analog conversion capacitor arrays at the P and N ends of the fully differential successive approximation analog-to-digital converter;

[0020] Then the common mode voltage Vcmx at the input of the fully differential comparator is:

[0021]

[0022] in, C(n-m+i)=CP(n-m+i)=CN(n-m+i).

[0023] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0024] 1. The present invention processes the traditional SAR ADC in segments, introduces FLASH ADC as the high-m-bit sub-ADC in the high-bit segment, and uses the high-speed characteristics of FLASH ADC to quickly obtain the high-bit segment digital code of the SAR ADC. Compared with the traditional single-structure SAR ADC, it can save up to m-1 working clocks and improve the conversion speed of the SAR ADC.

[0025] 2. The present invention uses two independent single-ended FLASH ADCs at the front end of the traditional fully differential SAR ADC to convert both the input common-mode signal and the differential-mode signal, and then sends them to the low-order segment of the SAR ADC as the residual voltage for the next conversion, so that the input common-mode signal decreases in proportion to the input differential-mode signal, thereby suppressing the common-mode signal interference entering the SAR ADC comparator and improving the common-mode rejection ratio of the overall circuit.

[0026] 3. In a traditional fully differential ADC, the input common-mode signal offset amplitude cannot be too large, otherwise it will cause the comparator to work abnormally, thus causing ADC to lose code. Based on the adaptive common-mode circuit proposed in the present invention, while ensuring a high common-mode rejection ratio, the common-mode offset range of the input signal is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural schematic diagram of an adaptive common-mode hybrid structure successive approximation analog-to-digital converter of the present invention;

[0028] Figure 2 It is a schematic diagram of the FLASH ADC (Flash Analog-to-Digital Converter) structure;

[0029] Figure 3 It is a schematic diagram of the structure of a fully differential SAR ADC;

[0030] Figure 4 It is a schematic diagram of the corresponding relationship between the fully differential SAR ADC switch coding and the capacitor bottom plate switch;

[0031] Figure 5 This is the voltage transfer curve of Vxp and Vxn in SAR ADC after 3-bit FLASH ADC is completed. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0033] Figure 1 The figure shows the overall structure of the hybrid structure successive approximation analog-to-digital converter with adaptive common mode, which mainly includes two single-ended m-bit FLASH ADCs (FLASH_P and FLASH_N), a fully differential n-bit SAR ADC and an encoder. The structure of the FLASH ADC is shown in Figure 1. Figure 2 As shown. Compared with the traditional fully differential SAR ADC, two single-ended FLASH ADCs are added, which sample the differential input signal simultaneously with the SAR ADC. The input fully differential analog signals are Vip and Vin, which are composed of the input common mode signal Vcm and the input differential mode signal Vdm. During sampling, the input signal Vip is sampled simultaneously by FLASH_P and the P terminal of the SAR ADC, and the input signal Vin is sampled simultaneously by FLASH_N and the N terminal of the SAR ADC. After sampling, FLASH_P converts the input signal Vip into a digital code DFp <m:1>, FLASH_N converts the input signal Vin into a digital code DFn <m:1>These two sets of digital codes directly control the high m-bit capacitor switches in the SAR ADC, so that the SAR ADC only needs to convert the remaining nm-bit digital codes DS <n-m:1>The three sets of digital codes are output by the encoder as the final digital code D <n:1>During the FLASH ADC conversion process, the SAR ADC does not work, and the lower plate switch of the capacitor array is suspended to prevent the DAC output voltage from exceeding the maximum tolerable voltage of the upper plate switch and the comparator input circuit.

[0034] Figure 3 The internal structure of the fully differential SAR ADC is shown, which mainly includes the fully differential DAC capacitor array (DAC_P and DAC_N), the fully differential comparator, the SAR logic circuit and the low-segment switch control circuit. During sampling, the upper plates of all capacitors in the capacitor array are connected to the reference voltage Vcm0, so that the comparator differential input signals Vxp and Vxn are both Vcm0; the lower plates of all capacitors in DAC_P are connected to Vip, and the lower plates of all capacitors in DAC_N are connected to Vin. During conversion, the upper plates of all capacitors in the capacitor array are disconnected from the reference voltage Vcm0. Unlike traditional SAR ADCs, the capacitor switches of the upper m bits are not switched in sequence by the SAR logic control, but are directly controlled by the digital code of the FLASH ADC: the digital code DFp of FLASH_P <m:1>Control the high m-bit capacitor switch of DAC_P to connect Vref 2 or GND, and the digital code DFn of FLASH_N <m:1>The high m-bit capacitor switches of DAC_N are controlled to connect to Vref 2 or GND. The remaining low nm-bit capacitor switches are switched in sequence by SAR logic control. Compared with the traditional single-structure SAR ADC, it can save up to m-1 working clocks.

[0035] Figure 3 Indicates the correspondence between the digital codeword in the SAR ADC and the controlled capacitor switch. Taking the lowest bit Dummy capacitor C0 as the unit capacitor, the capacitance of the jth bit is expressed as:

[0036] C j =2 j-1 C0 j=1~n

[0037] The digital code output by the FLASH ADC is directly assigned to the digital code of the high m bits of the SAR ADC, and the corresponding relationship is:

[0038]

[0039] The key to the circuit implementation is that although the SAR ADC and the two FLASH ADCs simultaneously sample the input signals Vip and Vin, the SAR ADC does not directly convert the input signals. The analog voltage actually converted by the SAR ADC is a residual voltage, which can be expressed as:

[0040]

[0041] Among them, VFp is the equivalent voltage of the digital code of FLASH_P to the upper m-bit capacitor of DAC_P, and VFn is the equivalent voltage of the digital code of FLASH_N to the upper m-bit capacitor of DAC_N.

[0042] After the LASH ADC conversion is completed, the output code DFp of FLASH_P ADC and FLASH_N ADC is <m:1>and DFn <m:1>It is directly used to control the lower plate switch of the high m-bit capacitor array in the fully differential SAR ADC. The corresponding relationship between the fully differential SAR ADC switch code and the capacitor lower plate switch is as follows: Figure 4 Taking the P terminal as an example, when DFp(i) is 1, the corresponding bit capacitance Cp in the SAR ADC is<n-m+i> The lower plate switch of the SAR ADC is connected to Vref 2, otherwise it is connected to GND. At the same time, the P-end and N-end low-segment capacitor array CP of the SAR ADC are connected to Vref 2. <n-m:1>、CN <n-m:1>The lower plates are connected to GND. Therefore, the output voltages Vxp and Vxn of the P-side and N-side DACs in the SAR ADC can be calculated as follows:

[0043]

[0044] When the internal capacitor array of the SAR ADC is binary, the output voltages Vxp and Vxn of the P-end and N-end DACs are:

[0045]

[0046] in, Typically, the capacitance of the corresponding capacitors at the P and N terminals is the same, so CP_tot = CN_tot = C tot .

[0047] The common-mode voltage at the SAR ADC comparator input is:

[0048]

[0049] in,

[0050] It can be seen from the formula that when the common mode of the input signal changes greatly, the common mode signal at the input of the SAR ADC comparator changes very little. Therefore, the input common mode interference can be adaptively suppressed to improve the common mode rejection ratio.

[0051] For the traditional fully differential SAR ADC, the output voltages of the phase capacitor DAC P and N are:

[0052]

[0053] The common-mode voltage at the SAR ADC comparator input is:

[0054]

[0055] The comparator input common-mode voltage changes with the input signal common-mode voltage.

[0056] The present invention takes FLASH ADC+fully differential SAR ADC as an example, and is also applicable to other ADC structures. The first-stage FLASH ADC may also be replaced by SAR ADC, folded interpolation and other structures.

[0057] The reference voltage of FLASH ADC and the reference voltage of SAR ADC can be designed independently. In order to adapt to a wider range of input signal common-mode changes, the reference voltage of FLASH ADC can be greater than the reference voltage of SAR ADC. The common-mode adaptability range of the entire ADC is determined by the reference voltage of FLASH ADC. The different reference voltages of FLASH ADC and SAR ADC mean that there are different weight coefficients, and the DAC and data recovery circuit in the SAR ADC need to be redundant and weighted, which will not affect the performance of the ADC.

[0058] Without considering the conversion error of FLASH ADC, the voltage transfer curve of Vxp and Vxn is as follows: Figure 5 As shown in the figure, taking 3-bit FLASH ADC as an example, after the FLASH ADC conversion is completed, the DAC output voltage ranges of the P and N terminals in the SAR ADC are This voltage is also the holding phase voltage of the SAR ADC. Vcm0 is to make the comparator in the SAR ADC work in a suitable voltage range. Here we take a 3-bit FLASH ADC as an example. If Vref 1 is larger than Vref 2, a higher-bit FLASH ADC can be selected, such as m bits. Then the holding voltage range of the SAR ADC is The equivalent input range of each end of the SAR ADC is Just need SAR ADC can convert normally. At this time, the equivalent signal range of the fully differential SAR ADC is much smaller than the full scale.

[0059] The common-mode component in the ADC input signal is quantized by the FLASH ADC at the P and N ends respectively, and is subtracted in the SAR ADC sampling and holding circuit. Therefore, the SAR ADC only quantizes the reduced differential-mode signal, reducing the common-mode offset at the comparator input in the SAR ADC and improving the common-mode applicability range and common-mode rejection ratio of the entire ADC.

[0060] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. An adaptive common-mode hybrid structure successive approximation analog-to-digital converter, characterized in that: It includes a P-end flash memory analog-to-digital converter, an N-end flash memory analog-to-digital converter, a fully differential successive approximation analog-to-digital converter and an encoder, the P-end flash memory analog-to-digital converter and the N-end flash memory analog-to-digital converter are both m-bit flash memory analog-to-digital converters, the fully differential successive approximation analog-to-digital converter is an n-bit fully differential successive approximation analog-to-digital converter, and m<n, m and n are both positive integers; The fully differential successive approximation analog-to-digital converter includes a P-terminal fully differential digital-to-analog conversion capacitor array, an N-terminal fully differential digital-to-analog conversion capacitor array, a fully differential comparator, and a successive approximation logic and a low-bit segment switch control circuit; The input end of the P-end flash analog-to-digital converter and the input end of the P-end fully differential digital-to-analog conversion capacitor array simultaneously sample the fully differential analog input signal Vip, and the input end of the N-end flash analog-to-digital converter and the input end of the N-end fully differential digital-to-analog conversion capacitor array simultaneously sample the fully differential analog input signal Vin; the P-end flash analog-to-digital converter converts the input signal Vip into a digital code DFp <m:1>The N-end flash analog-to-digital converter converts the input signal Vin into a digital code DFn <m:1>; Digital code DFp <m:1>Control the high m-bit capacitor array in the fully differential digital-to-analog conversion capacitor array at the P end, digital code DFn <m:1>The high m-bit capacitor array in the fully differential fractional analog conversion capacitor array at the N end is controlled. The low-bit segment capacitor arrays of the fully differential fractional analog conversion capacitor arrays at the P end and the N end are controlled by a successive approximation logic and a low-bit segment switch control circuit. The successive approximation logic and the low-bit segment switch control circuit output a digital code DS. <n-m:1>, digital code DFp <m:1>、DFn <m:1>and DS <n-m:1>After passing through the encoder, the final digital code D is output <n:1> 。< / n:1> 2. The adaptive common-mode hybrid structure successive approximation analog-to-digital converter according to claim 1, characterized in that: When the P-end flash analog-to-digital converter and the N-end flash analog-to-digital converter are sampling, the upper plates of all capacitors of the P-end and N-end fully differential digital-to-analog conversion capacitor arrays are connected to the reference voltage Vcm0, and the input voltages of the in-phase input terminal and the inverting input terminal of the fully differential comparator are both Vcm0; the lower plates of all capacitors of the P-end fully differential digital-to-analog conversion capacitor array are connected to the input signal Vip, and the lower plates of all capacitors of the N-end fully differential digital-to-analog conversion capacitor array are connected to the input signal Vin; The P-end flash analog-to-digital converter and the N-end flash analog-to-digital converter convert their respective input signals into digital codes at the same timing. During the conversion process, the upper plates of all capacitors in the P-end and N-end fully differential digital-to-analog conversion capacitor arrays are disconnected from the external reference voltage Vcm0, and the digital code DFp of the P-end flash analog-to-digital converter is <m:1>Control the high m-bit capacitor switch of the fully differential digital-to-analog conversion capacitor array at the P end to connect to the external reference voltage Vref 2 or GND, and the digital code DFn of the flash analog-to-digital converter at the N end <m:1> The high m-bit capacitor switches of the fully differential fractional analog conversion capacitor array at the N end are controlled to be connected to the external reference voltage Vref 2 or GND; the remaining low nm-bit capacitor switches of the fully differential fractional analog conversion capacitor array at the P end and the N end are switched in sequence by the successive approximation logic and the low-bit segment switch control circuit.

3. The adaptive common-mode hybrid structure successive approximation analog-to-digital converter according to claim 2, characterized in that: The P-end fully differential digital-to-analog conversion capacitor array includes n+1 capacitors connected in parallel, the upper plates of all the capacitors are connected to the in-phase input terminal of the fully differential comparator, the lower plates of all the capacitors are connected to Vip when sampling the fully differential analog input signal, and when converting the input signal Vip into a digital code, the high m-bit capacitor switch is connected to an external reference voltage Vref 2 or GND; when the i-th bit output code DFp(i) of the P-end flash analog-to-digital converter is 1, the corresponding n-m+i-th bit capacitor lower plate in the P-end fully differential digital-to-analog conversion capacitor array is connected to Vref 2, otherwise it is connected to GND; the low nm-bit capacitor switches are switched in sequence by successive approximation logic and a low-bit segment switch control circuit; The N-terminal fully differential digital-to-analog conversion capacitor array includes n+1 capacitors connected in parallel, the upper plates of all the capacitors are connected to the inverting input terminal of the fully differential comparator, the lower plates of all the capacitors are connected to Vin when sampling the fully differential analog input signal, and when converting the input signal Vin into a digital code, the high m-bit capacitor switch is connected to the external reference voltage Vref 2 or GND; when the i-bit output code DFn(i) of the N-terminal flash analog-to-digital converter is 1, the corresponding n-m+i-bit capacitor lower plate in the N-terminal fully differential digital-to-analog conversion capacitor array is connected to Vref 2, otherwise it is connected to GND; the low nm-bit capacitor switches are switched in sequence by the successive approximation logic and the low-bit segment switch control circuit.

4. The adaptive common-mode hybrid structure successive approximation analog-to-digital converter according to claim 1, characterized in that: The P-end flash analog-to-digital converter and the N-end flash analog-to-digital converter have the same structure, both of which include 2 m resistors, 2 m -1 comparator and an encoding circuit, 2 m The remaining end of the first resistor is grounded, and the second m The remaining end of the resistor is connected to the external reference voltage Vref 1, and the connection point of the two adjacent resistors is connected to the non-inverting input terminal of a comparator through a switch. m -1 The inverting input of each comparator is connected to the fully differential analog input signal Vip or Vin, 2 m The output ends of -1 comparators are connected to the input ends of the encoding circuit, and the output ends of the encoding circuit are connected to the input ends of the P-end or N-end fully differential digital-to-analog conversion capacitor array.

5. The adaptive common-mode hybrid structure successive approximation analog-to-digital converter according to claim 1, characterized in that: The digital code output by the P-end flash analog-to-digital converter is assigned to the digital code of the high m-bit capacitor of the P-end fully differential digital-to-analog conversion capacitor array, and the digital code output by the N-end flash analog-to-digital converter is assigned to the digital code of the high m-bit capacitor of the N-end fully differential digital-to-analog conversion capacitor array. The corresponding relationship is: Among them, D n-m+i , DB n-m+i They represent the control words of the n-m+i-th capacitors at the P-end and N-end in an n-bit fully differential successive approximation analog-to-digital converter, respectively. The minimum value of n-m+i is 1. DFp(i) and DFn(i) represent the i-th output codes of the flash analog-to-digital converter at the P-end and the flash analog-to-digital converter at the N-end, respectively. The residual voltage at the non-inverting and inverting inputs of the fully differential comparator is: Wherein, Vxp and Vxn respectively represent the output voltages of the fully differential digital-to-analog conversion capacitor arrays at the P and N ends of the fully differential successive approximation analog-to-digital converter, that is, the input voltages of the non-inverting input and the inverting input of the fully differential comparator, Vcm0 represents the common-mode voltage of the upper plate of the capacitor array during sampling, Vref1 represents the reference voltage of the flash analog-to-digital converter, CP_tot and CN_tot represent the total capacitance values ​​of the fully differential digital-to-analog conversion capacitor arrays at the P and N ends of the fully differential successive approximation analog-to-digital converter, and CP_tot=CN_tot, CP(n-m+i) and CN(n-m+i) respectively represent the capacitance values ​​of the n-m+ith positions in the fully differential digital-to-analog conversion capacitor arrays at the P and N ends of the fully differential successive approximation analog-to-digital converter; Then the common mode voltage Vcmx at the input of the fully differential comparator is: Among them, C(n - m + i) = CP(n - m + i) = CN(n - m + i).

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