Continuous-time high-precision analog-to-digital converter and implementation method

Abstract

The application discloses a continuous-time high-precision analog-digital converter and an implementation method, and is characterized in that the analog-digital converter comprises a first side differential circuit and a second side differential circuit; the first side differential circuit and the second side differential circuit are of the same structure; the first side differential circuit comprises a digital-analog converter array channel A, a digital-analog converter array channel B, a comparator, a register 11 and a register 12; the digital-analog converter array channel A and the digital-analog converter array channel B are of the same structure; in the technical scheme, two-channel digital-analog converter arrays are used, two operations of successive approximation quantization and residual voltage integration can be alternately completed in two adjacent clock periods, two stages of parallel integration and quantization in the same clock period are realized, the conversion efficiency is greatly improved, and high-precision application can be realized.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital converter architecture design, specifically relating to a continuous-time high-precision analog-to-digital converter and its implementation method. Background Technology

[0002] The Continuous-Time Noise-Shaping Successive-Approximation Register Analog-to-Digital Converter (CT NS-SAR ADC) combines noise shaping technology with a successive-approximation register ADC, overcoming the limitations of SAR (Successive-Approximation Register) in high-resolution and low-power applications. It also eliminates the need for anti-aliasing filters, saving power and area. Traditional CT NS-SAR ADCs use a duty-cycle-controlled integrator to complete SAR quantization and residual integration within one clock cycle. However, the successive-approximation quantization phase interrupts continuous-time integration, leading to inaccurate integration. This architecture achieves an approximately ideal noise transfer function (NTF) by reducing the proportion of the quantization phase within the entire clock cycle. However, this approach limits the available time for quantization to less than 5% of the entire clock cycle, and the NTF approximation performance deteriorates further at higher orders, thus limiting the application range of this architecture. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention provides a continuous-time high-precision analog-to-digital converter and its implementation method.

[0004] The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, the present invention provides a continuous-time high-precision analog-to-digital converter, the analog-to-digital converter comprising: a first-side differential circuit and a second-side differential circuit; the first-side differential circuit and the second-side differential circuit have the same structure; the first-side differential circuit comprises: a digital-to-analog converter array channel A, a digital-to-analog converter array channel B, a comparator, register 11, and register 12; the digital-to-analog converter array channel A and the digital-to-analog converter array channel B have the same structure;

[0006] The digital-to-analog converter array channel A is used for clock signal Φ RST When the rising edge of the signal arrives, the input signal VIN is processed to obtain the first signal;

[0007] The digital-to-analog converter array channel B is used in the clock signal Φ RST When the rising edge arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain the first integrated signal;

[0008] The comparator is used to control the register 11 to switch the capacitor array of the digital-to-analog converter array channel A according to the first integral signal and the first signal, so as to complete SAR quantization;

[0009] The digital-to-analog converter array channel A is also used for clock signal Φ RST When the next rising edge arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain the second integrated signal;

[0010] The digital-to-analog converter array channel B is also used in the clock signal Φ RST When the next rising edge arrives, the input signal VIN is processed to obtain the second signal;

[0011] The comparator is used to control the register 12 to switch the capacitor array of the digital-to-analog converter array channel B according to the second integral signal and the second signal, so as to complete the SAR quantization.

[0012] Optionally, the first-side differential circuit further includes: capacitor C1, capacitor C2, resistor R1, resistor R2, a first single-pole three-throw switch, and a second single-pole three-throw switch; the upper plate of the digital-to-analog converter array channel A is connected to the lower plate of capacitor C1, the upper plate of the digital-to-analog converter array channel A is connected to the first terminal of resistor R1, the upper plate of capacitor C1 is connected to the input signal VIN, the second terminal of resistor R1 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel A is connected to the first terminal of the first single-pole three-throw switch, and the second terminals of the first single-pole three-throw switch are respectively connected to the reference level. VREFN, reference level VREFP, and reference level VCM; the upper plate of the digital-to-analog converter array channel B is connected to the lower plate of the capacitor C2, the upper plate of the digital-to-analog converter array channel B is connected to the first terminal of the resistor R2, the upper plate of the capacitor C2 is connected to the input signal VIN, the second terminal of the resistor R2 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel B is connected to the first terminal of the second single-pole three-throw switch, and the second terminal of the second single-pole three-throw switch is connected to the reference level VREFN, the reference level VREFP, and the reference level VCM respectively.

[0013] Optionally, the digital-to-analog converter array channel A is used for the clock signal Φ RSTThe lower plate of the digital-to-analog converter array channel A is connected to the reference level VCM before the first rising edge arrives;

[0014] The digital-to-analog converter array channel B is used in the clock signal Φ RST The lower plate of the digital-to-analog converter array channel B is connected to the reference level VCM before the first rising edge arrives.

[0015] Optionally, the first-side differential circuit further includes: switches S1, S2, S3, S4, S5, S6, S7, and S8; integrator 11; integrator 12; voltage amplifier 11; voltage amplifier 12; voltage amplifier 13; voltage amplifier 14; and adder; the first terminal of switch S1 is connected to the upper plate of the digital-to-analog converter array channel A; the second terminal of switch S1 is connected to the first input terminal of voltage amplifier 12; and the first terminal of switch S2 is connected to the upper plate of the digital-to-analog converter array channel B. The second terminal of switch S2 is connected to the second input terminal of voltage amplifier 12; the first terminal of switch S3 is connected to the upper plate of digital-to-analog converter array channel A; the second terminal of switch S3 is connected to the first input terminal of integrator 11; the first terminal of switch S4 is connected to the upper plate of digital-to-analog converter array channel B; the second terminal of switch S4 is connected to the second input terminal of integrator 11; the first terminal of switch S5 is connected to the upper plate of digital-to-analog converter array channel B; and the second terminal of switch S5 is connected to the first input terminal of voltage amplifier 11. The input terminals are connected as follows: the first terminal of switch S6 is connected to the upper plate of channel A of the digital-to-analog converter array; the second terminal of switch S6 is connected to the second input terminal of voltage amplifier 11; the output terminal of voltage amplifier 11 is connected to the first input terminal of the adder; the output terminal of voltage amplifier 12 is connected to the second input terminal of the adder; the first output terminal of integrator 11 is connected to the input terminal of integrator 12; the second output terminal of integrator 11 is connected to the input terminal of voltage amplifier 13; the output terminal of voltage amplifier 13 is connected to the third input terminal of the adder; the output terminal of integrator 12 is connected to the input terminal of voltage amplifier 14; the output terminal of voltage amplifier 14 is connected to the fourth input terminal of the adder; the output terminal of the adder is connected to the non-inverting input terminal of the comparator; the inverting input terminal of the comparator is grounded; the first terminal of switch S7 is connected to the first output terminal of the comparator; the first terminal of switch S8 is connected to the second output terminal of the comparator; the second terminal of switch S7 is connected to register 12; and the second terminal of switch S8 is connected to register 11.

[0016] Optionally, the switches S1, S3, S5, and S7 are connected via a clock signal. Controlled by a clock signal, switches S2, S4, S6, and S8 are connected via a clock signal. control.

[0017] Optionally, both the digital-to-analog converter array channel A and the digital-to-analog converter array channel B include multiple capacitors connected in parallel; the multiple capacitors connected in parallel are arranged in order of their capacitance values.

[0018] Optionally, the amplification factors of voltage amplifier 12, voltage amplifier 13, and voltage amplifier 14 are obtained according to the following formula:

[0019]

[0020] in, This is the amplification factor of the voltage amplifier 14. The amplification factor of the voltage amplifier 13 is... Let k0 be the amplification factor of the voltage amplifier 12, k1 be the first ideal factor, and k2 be the third ideal factor. N represents the number of SAR conversions.

[0021] In a second aspect, the present invention provides a method for implementing a continuous-time high-precision analog-to-digital converter, for implementation by any continuous-time high-precision analog-to-digital converter as described in the first aspect, comprising the following steps:

[0022] Through digital-to-analog converter array channel A at clock signal Φ RST When the rising edge of the signal arrives, the input signal VIN is processed to obtain the first signal;

[0023] The clock signal Φ is transmitted through the digital-to-analog converter array channel B. RST When the rising edge arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain the first integrated signal;

[0024] The register 11 is controlled by a comparator, the first integral signal, and the first signal to switch the capacitor array of the digital-to-analog converter array channel A to complete SAR quantization.

[0025] Through the digital-to-analog converter array channel A, at clock signal Φ RST When the next rising edge arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain the second integrated signal;

[0026] The clock signal Φ is transmitted through the digital-to-analog converter array channel B. RSTWhen the next rising edge arrives, the input signal VIN is processed to obtain the second signal;

[0027] The comparator, the second integral signal, and the second signal control the register 12 to switch the capacitor array of the digital-to-analog converter array channel B to complete the SAR quantization.

[0028] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0029] In the above technical solution, a two-channel digital-to-analog converter array is used to alternately complete the successive approximation quantization and residual voltage integration operations in two adjacent clock cycles, realizing the parallel integration and quantization stages in the same clock cycle, thereby greatly improving the conversion efficiency and enabling high-precision applications.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the first-side differential circuit of a continuous-time high-precision analog-to-digital converter provided in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of a clock signal provided in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the structure of a digital-to-analog converter array channel provided in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of a spectrum diagram provided in an embodiment of the present invention;

[0035] Figure 5 This is a flowchart of an implementation method for a continuous-time high-precision analog-to-digital converter provided by an embodiment of the present invention. Detailed Implementation

[0036] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0037] The analog-to-digital converter includes: a first-side differential circuit and a second-side differential circuit, the first-side differential circuit and the second-side differential circuit have the same structure; Figure 1 This is a schematic diagram of the first-side differential circuit of a continuous-time high-precision analog-to-digital converter provided in an embodiment of the present invention, as shown below. Figure 1As shown, the first-side differential circuit includes: digital-to-analog converter array channel A (channel A), digital-to-analog converter array channel B (channel B), comparator, register 11 and register 12; digital-to-analog converter array channel A and digital-to-analog converter array channel B have the same structure.

[0038] Optionally, refer to Figure 1 The first-side differential circuit also includes: capacitor C1, capacitor C2, resistors R1 and R2, a first single-pole three-throw switch, and a second single-pole three-throw switch; the upper plate of the digital-to-analog converter array channel A is connected to the lower plate of capacitor C1, the upper plate of the digital-to-analog converter array channel A is connected to the first terminal of resistor R1, the upper plate of capacitor C1 is connected to the input signal VIN, the second terminal of resistor R1 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel A is connected to the first terminal of the first single-pole three-throw switch, and the second terminal of the first single-pole three-throw switch is connected to the reference level VCM. The upper plate of the digital-to-analog converter array channel B is connected to the lower plate of capacitor C2, the upper plate of the digital-to-analog converter array channel B is connected to the first terminal of resistor R2, the upper plate of capacitor C2 is connected to the input signal VIN, the second terminal of resistor R2 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel B is connected to the first terminal of the second single-pole three-throw switch, and the second terminal of the second single-pole three-throw switch is connected to the reference level VREFN, the reference level VREFP, and the reference level VCM respectively.

[0039] Optionally, refer to Figure 1The first-side differential circuit also includes: switches S1, S2, S3, S4, S5, S6, S7, and S8; integrator 11; integrator 12; voltage amplifier 11; voltage amplifier 12; voltage amplifier 13; voltage amplifier 14; and an adder. The first terminal of switch S1 is connected to the upper plate of digital-to-analog converter array channel A; the second terminal of switch S1 is connected to the first input terminal of voltage amplifier 12; the first terminal of switch S2 is connected to the upper plate of digital-to-analog converter array channel B; the second terminal of switch S2 is connected to the second input terminal of voltage amplifier 12; the first terminal of switch S3 is connected to the upper plate of digital-to-analog converter array channel A; the second terminal of switch S3 is connected to the first input terminal of integrator 11; the first terminal of switch S4 is connected to the upper plate of digital-to-analog converter array channel B; the second terminal of switch S4 is connected to the second input terminal of integrator 11; the first terminal of switch S5 is connected to the upper plate of digital-to-analog converter array channel B; and the second terminal of switch S5 is connected to the voltage amplifier 14. The first input terminal of 11 is connected; the first terminal of switch S6 is connected to the upper plate of channel A of the digital-to-analog converter array; the second terminal of switch S6 is connected to the second input terminal of voltage amplifier 11; the output terminal of voltage amplifier 11 is connected to the first input terminal of adder; the output terminal of voltage amplifier 12 is connected to the second input terminal of adder; the first output terminal of integrator 11 is connected to the input terminal of integrator 12; the second output terminal of integrator 11 is connected to the input terminal of voltage amplifier 13; the output terminal of voltage amplifier 13 is connected to the third input terminal of adder; the output terminal of integrator 12 is connected to the input terminal of voltage amplifier 14; the output terminal of voltage amplifier 14 is connected to the fourth input terminal of adder; the output terminal of adder is connected to the non-inverting input terminal of comparator; the inverting input terminal of comparator is grounded; the first terminal of switch S7 is connected to the first output terminal of comparator; the first terminal of switch S8 is connected to the second output terminal of comparator; the second terminal of switch S7 is connected to register 12; and the second terminal of switch S8 is connected to register 11.

[0040] Understandably, the process for determining the amplification factor of a voltage amplifier can be referenced as follows: First, estimate the time T required for each SAR conversion based on the manufacturing process. sar Given an expected input signal bandwidth of BW, the number of SAR transformations N required for effective quantization can be obtained:

[0041] N≤log 0.5 (2π·BW·T sar );

[0042] N is taken as the largest integer satisfying the above formula. After determining N, N·T is used to... sarThe sampling clock period is estimated to obtain the sampling rate, and the oversampling rate is determined. Next, the noise shaping order and maximum out-of-band gain are determined based on the desired signal-to-noise ratio. Then, the required noise transfer function NTF is generated using MATLAB's SynthesizeNTF function. Finally, the discrete-domain loop filter function H(z) is determined according to the following formula:

[0043]

[0044] Next, the d2c function in Matlab is used to convert H(z) into a continuous-time domain function H(s), thereby determining the ideal coefficients k0, k1, and k2. Then, the excessive loop delay t in the system is determined. d In this design, other non-ideal factors are not considered. The coefficients after loop compensation are determined using the following formula:

[0045]

[0046] in, This refers to the amplification factor of voltage amplifier 14. This represents the amplification factor of voltage amplifier 13. denoted as the amplification factor of voltage amplifier 12, k0 as the first ideal factor, k1 as the second ideal factor, k2 as the third ideal factor, and N as the number of conversions used for SAR.

[0047] Optionally, Figure 2 This is a schematic diagram of a clock signal provided in an embodiment of the present invention, such as... Figure 2 As shown, switches S1, S3, S5, and S7 are connected via clock signal Φ. CLK Control is achieved through a clock signal for switches S2, S4, S6, and S8. Control; Clock signal Φ CLK and clock signal It is a two-phase non-overlapping clock signal.

[0048] Specifically, clock signal Φ CLK When the signal is high, switches S1, S3, S5, and S7 are closed; clock signal Φ CLK When the signal is low, switches S1, S3, S5, and S7 are disconnected; clock signal When the signal is high, switches S2, S4, S6, and S8 are closed; clock signal. When the voltage is low, switches S2, S4, S6, and S8 are disconnected.

[0049] Optionally, both digital-to-analog converter array channel A and digital-to-analog converter array channel B include multiple capacitors connected in parallel; the multiple capacitors connected in parallel are arranged in order of their capacitance values.

[0050] Understandable, Figure 3 This is a schematic diagram of the structure of a digital-to-analog converter array channel provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the capacitance values ​​of the capacitors in the digital-to-analog converter array channels are arranged in powers of 2, namely 16C, 8C, 4C, 2C, and C. CMSB is the capacitor with the largest capacitance value, and CLSB is the capacitor with the smallest capacitance value.

[0051] In one implementation, digital-to-analog converter array channel A is used for clock signal Φ RST When the rising edge of the signal arrives, the input signal VIN is processed to obtain the first signal;

[0052] Digital-to-analog converter array channel B, used for clock signal Φ RST When the rising edge arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain the first integrated signal;

[0053] A comparator is used to switch the capacitor array of digital-to-analog converter array channel A according to the first integral signal and the first signal control register 11 to complete SAR quantization;

[0054] Digital-to-analog converter array channel A is also used for clock signal Φ RST When the next rising edge arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain the second integrated signal;

[0055] Digital-to-analog converter array channel B is also used for clock signal Φ RST When the next rising edge arrives, the input signal VIN is processed to obtain the second signal;

[0056] A comparator is used to switch the capacitor array of digital-to-analog converter array channel B according to the second integral signal and the second signal control register 12 to complete SAR quantization.

[0057] It is understandable that the aforementioned SAR quantization process is the ping-pong operation stage of the first-side differential circuit of the continuous-time high-precision analog-to-digital converter. During the ping-pong operation stage, such as... Figure 1 As shown, since the structures of channel A and channel B are exactly the same, channel A and channel B alternately perform integration and quantization operations.

[0058] Furthermore, in this invention, from the clock signal Φ RST Before the rising edge to Φ RST One clock cycle precedes the next rising edge of the clock signal. Clock signal ΦRST During the ping-pong operation phase, such as Figure 1 As shown, since channel A and channel B have identical structures, they alternately perform integration and quantization operations. Here, we take the case where channel A performs SAR quantization on the input signal VIN and channel B performs integration as an example. The first Φ in the initial stage... RST After the clock cycle ends, a first residual voltage is generated on the upper plate of channel B. This first residual voltage is carried over into the ping-pong operation phase; during the ping-pong operation phase, Φ RST Before the rising edge of the clock arrives, Φ CLK Become low level, Φ CLK The signal becomes high, thus disconnecting S1, S3, S5, and S7, and closing S2, S4, S6, and S8. At this time, the upper plate of channel A is connected to voltage amplifier 11 and input to the adder to form the signal on the VRES path. The upper plate of channel B is connected to integrator 11, and after passing through integrator 12 and voltage amplifier 14, the signal on the VINT2 path is formed, and after passing through voltage amplifier 13, the signal on the VINT1 path is formed. The signal on the upper plate of channel B is also input to voltage amplifier 12 to form the signal on the VELD path. The signals on the VRES path, VINT1 path, VINT2 path, and VELD path are input to the adder to obtain the final signal. The comparator is then connected to the clock signal Φ. RST When the signal is high, a reset is performed first. Then, the final signal is compared, and the comparison result is sent to register 11 to control the switching of the DAC switch array in channel A of the digital-to-analog converter array. The lower plate of channel B of the digital-to-analog converter array remains unchanged from the previous cycle through register 12. The voltage residual generated on the upper plate of channel B at the end of this clock cycle will be carried over to the next clock signal Φ. RST The clock cycle, and the functions of channels A and B will also be in the clock signal Φ RST The swap is achieved within the next clock cycle. In each clock signal Φ RST At the end of the clock cycle, the clock signal Φ CLK Before the falling edge, the reference voltage connected to the lower plate of the capacitor array of the output digital-to-analog converter array channel responsible for successive approximation quantization is used as the quantization output digital code of that channel. The digital codes of the digital-to-analog converter array channel responsible for successive approximation quantization in the first-side differential circuit and the digital codes of the digital-to-analog converter array channel responsible for successive approximation quantization in the second-side differential circuit are added in the time domain to obtain the digital code of the continuous-time high-precision analog-to-digital converter.

[0059] Optionally, prior to the ping-pong operation phase, the invention further includes an initial state phase, in which the digital-to-analog converter array channel A is configured to operate on clock signal Φ. RSTConnect the lower plate of the digital-to-analog converter array channel A to the reference level VCM before the first rising edge arrives;

[0060] Digital-to-analog converter array channel B, used for clock signal Φ RST Connect the lower plate of the digital-to-analog converter array channel B to the reference level VCM before the first rising edge arrives.

[0061] It is understandable that the initial state phase only includes the clock signal Φ. RST One clock cycle, in clock signal Φ RST Before the first rising edge of the clock arrives, the lower plates of both digital-to-analog converter array channels are reset to the reference level VCM. At the clock signal Φ CLK High level, clock signal Φ CLK When the signal is low, S1, S3, S5, and S7 are closed, while S2, S4, S6, and S8 are open. The signal on the upper plate of channel B is amplified by 1 times by voltage amplifier 11 and connected to the adder; this signal is the signal on the VRES path. The upper plate of channel A is connected to integrator 11, and the resulting integrated signal is amplified by k1 times by voltage amplifier 13 to obtain the signal on the VINT1 path, which is then connected to the adder. Simultaneously, the output signal of integrator 11 is also connected to integrator 12 and amplified by k2 times by voltage amplifier 14 to obtain the signal on the VINT2 path, which is then connected to the adder. The residual voltage on the upper plate of channel A is also amplified by k0 times by voltage amplifier 12 and then connected to the adder to obtain the signal on the VELD path. The adder sums the signals on the four paths VELD, VINT1, VINT2, and VRES and then inputs the sum to the comparator. The comparator operates on clock signal Φ. RST When the signal is high, the device is in a reset state until the clock signal Φ is received. RST The voltage level drops back to low, at which point the comparator begins comparison. The comparison result is stored in register 12, and the lower plate of the capacitor array in channel B of the digital-to-analog converter array is switched. The switching process is as follows: Figure 3 During this clock cycle, the lower plate of channel A remains connected to the VCM reference voltage.

[0062] It is worth mentioning that, based on the comparator's comparison result, the lower-level board of the capacitor array for each digital-to-analog converter array channel is controlled by a single-pole triple-throw switch to determine its connection to the reference level: during the reset phase, all capacitors are connected to the reference level VCM; after the Nth comparison, the comparator outputs the comparison result and the control signal Φ. CMP If the comparator outputs a high level, the control signal Φ CMP Control 2 via register 11 at the corresponding falling edge. 5-N Capacitor C (1≤N≤5) is connected to the reference level VREFN. If the comparator outputs a low level, it controls 2.5-N Capacitor C is connected to the reference level VREFP.

[0063] In one embodiment, the continuous-time high-precision analog-to-digital converter designed in this invention is circuit-designed using a 65nm standard CMOS process. The entire circuit operates at a 1.2V power supply voltage, a sampling frequency of 600MS / s, an input signal amplitude of 1.2-V Vpp, and a power consumption of 8.5mW at an input signal frequency of 3.698MHz. Figure 4 This is a schematic diagram of a spectrum diagram provided in an embodiment of the present invention, such as... Figure 4 As shown. By analyzing... Figure 4 According to calculations, the continuous-time high-precision analog-to-digital converter designed in this invention has a signal harmonic noise ratio of 76.8 dB, an effective accuracy of 12.5 bits, and a quality factor of 49.8 fJ / conv.-step. Figure 4 As can be seen, compared with the traditional architecture, the signal bandwidth achieved by the architecture of this invention is increased by more than 10 times, while maintaining the signal harmonic noise ratio at more than 75dB.

[0064] Figure 5 This is a flowchart illustrating an implementation method for a continuous-time high-precision analog-to-digital converter provided by an embodiment of the present invention, as shown below. Figure 5 As shown, the method may include the following steps:

[0065] S501, via digital-to-analog converter array channel A, in clock signal Φ RST When the rising edge of the signal arrives, the input signal VIN is processed to obtain the first signal;

[0066] S502, via digital-to-analog converter array channel B, in clock signal Φ RST When the rising edge arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain the first integrated signal;

[0067] S503. The capacitor array of the digital-to-analog converter array channel A is switched by the comparator, the first integration signal and the first signal control register 11 to complete SAR quantization;

[0068] S504, via digital-to-analog converter array channel A, in clock signal Φ RST When the next rising edge arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain the second integrated signal;

[0069] S505, via digital-to-analog converter array channel B, in clock signal Φ RST When the next rising edge arrives, the input signal VIN is processed to obtain the second signal;

[0070] S506. The capacitor array of the digital-to-analog converter array channel B is switched through the comparator, the second integral signal and the second signal control register 12 to complete SAR quantization.

[0071] In the above technical solution, a two-channel digital-to-analog converter array is used to alternately complete the successive approximation quantization and residual voltage integration operations in two adjacent clock cycles, realizing the parallel integration and quantization stages in the same clock cycle, thereby greatly improving the conversion efficiency and enabling high-precision applications.

[0072] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0074] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0075] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0076] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A continuous-time high-precision analog-to-digital converter, characterized in that, The analog-to-digital converter (ADC) includes: a first-side differential circuit and a second-side differential circuit; the first-side differential circuit and the second-side differential circuit have the same structure; the first-side differential circuit includes: ADC array channel A, ADC array channel B, a comparator, register 11, and register 12; ADC array channel A and ADC array channel B have the same structure; the first-side differential circuit further includes: capacitor C1, capacitor C2, resistor R1, resistor R2, a first single-pole three-throw switch, and a second single-pole three-throw switch; the upper plate of ADC array channel A is connected to the lower plate of capacitor C1, the upper plate of ADC array channel A is connected to the first terminal of resistor R1, the upper plate of capacitor C1 is connected to the input signal VIN, the second terminal of resistor R1 is connected to the reference level VCM, the lower plate of ADC array channel A is connected to the first terminal of the first single-pole three-throw switch, and the first single-pole three-throw switch... The two terminals are respectively connected to reference level VREFN, reference level VREFP, and reference level VCM; the upper plate of the digital-to-analog converter array channel B is connected to the lower plate of the capacitor C2, the upper plate of the digital-to-analog converter array channel B is connected to the first terminal of the resistor R2, the upper plate of the capacitor C2 is connected to the input signal VIN, the second terminal of the resistor R2 is connected to the reference level VCM, the lower plate of the digital-to-analog converter array channel B is connected to the first terminal of the second single-pole triple-throw switch, and the second terminal of the second single-pole triple-throw switch is respectively connected to the reference level VREFN, the reference level VREFP, and the reference level VCM; the first-side differential circuit also includes: switches S1, S2, S3, S4, S5, S6, S7, and S8, integrator 11, integrator 12, voltage amplifier 11, voltage amplifier 12, voltage amplifier 13, voltage amplifier 14, and adder;The first end of switch S1 is connected to the upper plate of the digital-to-analog converter array channel A, and the second end of switch S1 is connected to the first input terminal of voltage amplifier 12. The first end of switch S2 is connected to the upper plate of the digital-to-analog converter array channel B, and the second end of switch S2 is connected to the second input terminal of voltage amplifier 12. The first end of switch S3 is connected to the upper plate of the digital-to-analog converter array channel A, and the second end of switch S3 is connected to the first input terminal of integrator 11. The first end of switch S4 is connected to the upper plate of the digital-to-analog converter array channel B, and the second end of switch S4 is connected to the second input terminal of integrator 11. The first end of switch S5 is connected to the upper plate of the digital-to-analog converter array channel B, and the second end of switch S5 is connected to the first input terminal of voltage amplifier 11. The first end of switch S6 is connected to the upper plate of the digital-to-analog converter array channel A, and the second end of switch S6 is connected to the voltage amplifier... The second input terminal of voltage amplifier 11 is connected to the first input terminal of the adder, the output terminal of voltage amplifier 12 is connected to the second input terminal of the adder, the first output terminal of integrator 11 is connected to the input terminal of integrator 12, the second output terminal of integrator 11 is connected to the input terminal of voltage amplifier 13, the output terminal of voltage amplifier 13 is connected to the third input terminal of the adder, the output terminal of integrator 12 is connected to the input terminal of voltage amplifier 14, the output terminal of voltage amplifier 14 is connected to the fourth input terminal of the adder, the output terminal of the adder is connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is grounded, the first terminal of switch S7 is connected to the first output terminal of the comparator, the first terminal of switch S8 is connected to the second output terminal of the comparator; the second terminal of switch S7 is connected to register 12, and the second terminal of switch S8 is connected to register 11. The digital-to-analog converter array channel A is used for clock signals. When the rising edge of the signal arrives, the input signal VIN is processed to obtain the first signal; The digital-to-analog converter array channel B is used in the clock signal When the rising edge arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain the first integrated signal; The comparator is used to control the register 11 to switch the capacitor array of the digital-to-analog converter array channel A according to the first integral signal and the first signal, so as to complete SAR quantization; The digital-to-analog converter array channel A is also used for clock signals. When the next rising edge arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain the second integrated signal; The digital-to-analog converter array channel B is also used in the clock signal When the next rising edge arrives, the input signal VIN is processed to obtain the second signal; The comparator is used to control the register 12 to switch the capacitor array of the digital-to-analog converter array channel B according to the second integral signal and the second signal, so as to complete the SAR quantization.

2. The continuous-time high-precision analog-to-digital converter according to claim 1, characterized in that, The digital-to-analog converter array channel A is used for the clock signal The lower plate of the digital-to-analog converter array channel A is connected to the reference level VCM before the first rising edge arrives; The digital-to-analog converter array channel B is used in the clock signal The lower plate of the digital-to-analog converter array channel B is connected to the reference level VCM before the first rising edge arrives.

3. The continuous-time high-precision analog-to-digital converter according to claim 1, characterized in that, The switches S1, S3, S5, and S7 are connected via a clock signal. Controlled by a clock signal, switches S2, S4, S6, and S8 are connected via a clock signal. Control; the clock signal and the clock signal It is a two-phase non-overlapping clock signal.

4. The continuous-time high-precision analog-to-digital converter according to claim 1, characterized in that, Both the digital-to-analog converter array channel A and the digital-to-analog converter array channel B include multiple capacitors connected in parallel; the multiple capacitors connected in parallel are arranged in order of their capacitance values.

5. The continuous-time high-precision analog-to-digital converter according to claim 1, characterized in that, The amplification factors of voltage amplifier 12, voltage amplifier 13 and voltage amplifier 14 are obtained according to the following formula: ； in, This is the amplification factor of the voltage amplifier 14. The amplification factor of the voltage amplifier 13 is... The amplification factor of the voltage amplifier 12 is... The first ideal coefficient, The second ideal coefficient, The third ideal coefficient, , Indicates the number of SAR conversions.

6. A method for implementing a continuous-time high-precision analog-to-digital converter, used by means of a continuous-time high-precision analog-to-digital converter as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Through digital-to-analog converter array channel A, the clock signal When the rising edge of the signal arrives, the input signal VIN is processed to obtain the first signal; The clock signal is transmitted through the digital-to-analog converter array channel B. When the rising edge arrives, the first residual voltage of the digital-to-analog converter array channel B is integrated to obtain the first integrated signal; The register 11 is controlled by a comparator, the first integral signal, and the first signal to switch the capacitor array of the digital-to-analog converter array channel A to complete SAR quantization. Through the digital-to-analog converter array channel A, the clock signal When the next rising edge arrives, the second residual voltage of the digital-to-analog converter array channel A is integrated to obtain the second integrated signal; The clock signal is transmitted through the digital-to-analog converter array channel B. When the next rising edge arrives, the input signal VIN is processed to obtain the second signal; The comparator, the second integral signal, and the second signal control the register 12 to switch the capacitor array of the digital-to-analog converter array channel B to complete the SAR quantization.

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