Digitally assisted adaptive zero-crossing detection circuit

Abstract

The application relates to the technical field of integrated circuits, and discloses a digital auxiliary adaptive zero-crossing detection circuit. The circuit comprises a digital auxiliary comparator module, a digital logic module, a detection discrimination module and a counter module. The digital auxiliary comparator module compares a switch node voltage signal with a power ground signal to generate a first output signal; the digital logic module processes the first output signal to generate a zero-crossing detection signal and control the turn-off of a power tube; the detection discrimination module receives a second output signal of the digital logic module and the zero-crossing detection signal to generate a digital tuning signal; and the counter module receives the digital tuning signal to generate a six-digit digital signal, dynamically adjusts a resistance array in the digital auxiliary comparator module, adaptively adjusts the flip offset of the comparator by changing the resistance value of the resistance array, and thus changes the turn-off timing of the power tube. The application can accurately control the turn-off timing of a synchronous rectification power tube, reduce the reverse current and reduce the dynamic power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a zero-crossing detection circuit technology for DC-DC switching power supply converters. Background Technology

[0002] With the continuous development of electronic technology, DC-DC converters have been widely used in various fields such as communications, computers, and consumer electronics. As a common topology of DC-DC converters, the Buck converter is widely favored for its simple structure and high efficiency. However, in practical applications, the Buck converter also faces some technical problems that urgently need to be solved.

[0003] Firstly, when operating under light load, BUCK converters typically employ DCM (Discontinuous Conduction Mode) control to reduce switching losses. However, in DCM mode, the inductor current drops to zero in each switching cycle, accompanied by ringing. If the turn-off timing of the synchronous rectifier is not properly controlled, it may remain in a conducting state even when the current reverses, causing current to flow back from the output to the input, resulting in power loss.

[0004] Secondly, ideally, the synchronous rectifier should turn off immediately when the inductor current crosses zero to minimize conduction losses. However, differences in device characteristics, circuit board layout, and control signal delays in actual circuits make accurate prediction and control of the zero-crossing moment extremely difficult. Traditional zero-crossing detection circuits rely solely on comparators with fixed thresholds, making it difficult to adapt to the optimal turn-off timing under different operating conditions.

[0005] Third, the magnitude of inductor current ripple is closely related to the load conditions. When the load changes abruptly, a large current ripple may cause a brief reverse current, which in turn causes additional losses in the power transistor. Achieving smooth mode transitions and suppressing reverse current spikes are key to improving system robustness.

[0006] Therefore, it is necessary to design an adaptive zero-crossing detection circuit to achieve efficient and accurate synchronous rectifier control, suppress current backflow, and improve the operating efficiency of the BUCK converter in DCM mode. Summary of the Invention

[0007] The purpose of this application is to provide a digitally assisted adaptive zero-crossing detection circuit to solve the problems mentioned in the background art.

[0008] This application discloses a digitally assisted adaptive zero-crossing detection circuit, comprising:

[0009] A digital auxiliary comparator module, including a resistor array, is configured to sample and compare a switching node voltage signal Vsw with a power ground signal pvss when the power transistor in the power stage of the buck converter is turned on, and generate a first output signal Vcp.

[0010] The digital logic module, electrically connected to the digital auxiliary comparator module, is used to receive the first output signal Vcp and the upper power transistor control signal HS and the lower power transistor control signal LS in the power stage of the buck converter. After logic processing, it generates the dynamic bias signal Vdb, the second output signal Vcmp and the zero-crossing detection signal ZCD, respectively.

[0011] The detection and discrimination module is electrically connected to the digital logic module and is used to receive the second output signal Vcmp and the zero-crossing detection signal ZCD, and generate a digital tuning signal UP / DN after logic processing.

[0012] The counter module, electrically connected to the detection and discrimination module, is used to receive the digital tuning signal UP / DN, and generate a six-bit digital control signal Q<5:0> after counting processing. The six-bit digital control signal Q<5:0> is connected to the resistor array of the digital auxiliary comparator module. By dynamically changing the resistance value of the resistor array, the adaptive adjustment of the flip offset of the digital auxiliary comparator module is realized.

[0013] In a preferred embodiment, the digital auxiliary comparator module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal, and an output signal terminal. The power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the first input terminal receives a switching node voltage signal Vsw, the second input terminal receives a power ground signal pvss, the third input terminal receives a dynamic bias signal Vdb, the six-bit digital input terminal sequentially receives a six-bit digital control signal Q<5:0> from the counter module, and the output signal terminal outputs a first output signal Vcp.

[0014] In a preferred embodiment, the resistor array includes a first group of resistors R5 to R0 and a second group of resistors R5b to R0b; the six-bit digital control signal Q<5:0> is inverterized to generate a corresponding inverted signal Qb<5:0>; wherein Q<5:0> controls the first group of resistors R5 to R0, and Qb<5:0> controls the second group of resistors R5b to R0b; when Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited; when Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit; when the dynamic bias signal Vdb is high, the digital auxiliary comparator module compares the magnitude of the input switch node voltage signal Vsw with the power ground signal pvss; when the switch node voltage signal Vsw is greater than the power ground signal pvss, the first output signal Vcp is output.

[0015] In a preferred embodiment, the digital logic module includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, and a third output terminal. The power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal Vcp from the digital auxiliary comparator module, the second input terminal receives an upper power transistor control signal HS in the power stage of the buck converter, the third input terminal receives a lower power transistor control signal LS in the power stage of the buck converter, the first output terminal outputs a dynamic bias signal Vdb, the second output terminal outputs a second output signal Vcmp, and the third output terminal outputs a zero-crossing detection signal ZCD.

[0016] In a preferred embodiment, when the received first output signal Vcp flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD output by the digital logic module successively flip to a high level; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the received upper power transistor control signal HS flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the received lower power transistor control signal LS flips to a high level, the dynamic bias signal Vdb flips to a high level, and the falling edge of the lower power transistor control signal LS, after being delayed, triggers the dynamic bias signal Vdb to flip to a low level.

[0017] In a preferred embodiment, the detection and discrimination module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, and an output signal terminal. The power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the first input terminal receives a second output signal Vcmp from the digital logic module, the second input terminal receives a zero-crossing detection signal ZCD from the digital logic module, and the output signal terminal outputs the digital tuning signal UP / DN.

[0018] In a preferred embodiment, the detection and discrimination module generates a clock signal CLKD for the D flip-flop after delaying the zero-crossing detection signal ZCD. When the rising edge of the clock signal CLKD arrives, the level of the second output signal Vcmp is sampled. When the sampled second output signal Vcmp is high, it indicates that the lower power transistor is delayed and turned off, and the detection and discrimination module outputs a low digital tuning signal UP / DN. When the sampled second output signal Vcmp is low, it indicates that the lower power transistor is turned off prematurely, and the detection and discrimination module outputs a high digital tuning signal UP / DN.

[0019] In a preferred embodiment, the counter module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, and a six-bit digital signal output terminal. The power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the first input terminal receives a digital tuning signal UP / DN from the detection and discrimination module, the second input terminal receives a set signal SET, the third input terminal receives a clock signal CLK, and the six-bit digital signal output terminal outputs the six-bit digital control signal Q<5:0>.

[0020] In a preferred embodiment, when the set signal SET is low, the six-bit digital signal output terminal of the counter module outputs low level, high level, high level, high level, high level, high level sequentially from the high bit to the low bit; when the digital tuning signal UP / DN is low, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module is decreased by one when the rising edge of the clock signal CLK arrives; when the digital tuning signal UP / DN is high, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module is increased by one when the rising edge of the clock signal CLK arrives.

[0021] The digitally assisted adaptive zero-crossing detection circuit provided in this application achieves the following technical effects through the coordinated operation of a digitally assisted comparator, a digital logic module, a detection and discrimination module, and a counter module:

[0022] First, the quiescent current of this circuit can be precisely controlled at the nanoampere level, significantly reducing power consumption compared to traditional solutions. This makes it particularly suitable for ultra-low-power applications with stringent power requirements, such as portable electronic devices and IoT terminals. This low-power characteristic is due to the circuit's simplified design; complex adaptive loop control can be achieved with only a comparator and a small amount of basic digital logic circuitry.

[0023] Secondly, the digital auxiliary comparator of this application is multifunctional. It can not only accurately detect the zero-crossing point of the inductor current, but its output signal can also provide crucial information for the detection and discrimination module to accurately determine the timing of the power transistor's turn-off. This integrated design reduces the need for additional comparators while improving detection accuracy and system consistency.

[0024] Third, during the initial startup phase of the circuit, the digital auxiliary comparator can directly detect and quickly turn off the power transistor, significantly reducing initial errors. This rapid convergence characteristic avoids the problem of severe deviation in the initial turn-off timing that may occur in traditional solutions, ensuring the rapid stabilization of the system.

[0025] Furthermore, the six-bit digital control adaptive feedback mechanism employed in this application enables the digital auxiliary comparator to gradually approach the optimal turn-off time of the lower power transistor through up to 64 levels of fine adjustments under the regulation of the feedback loop. This refined control achieves precise optimization of the circuit's operating state, effectively improving the conversion efficiency of the DC-DC converter in DCM operating mode, while reducing ringing at the switching nodes.

[0026] The aforementioned technical effects are achieved thanks to the unique mixed-signal architecture and adaptive control method of this application, which provides an innovative solution for zero-crossing detection in DC-DC converters while taking into account both accuracy and power consumption.

[0027] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the overall architecture of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of the circuit structure of a digitally assisted comparator module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the circuit structure of a digital logic module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of the operating waveforms of the digital logic module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the circuit structure of the detection and discrimination module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the working waveform of the detection and discrimination module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of the circuit structure of a counter module of a digitally assisted adaptive zero-crossing detection circuit according to an embodiment of this application. Detailed Implementation

[0035] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Explanation of some concepts:

[0037] BUCK converter: a switching power supply circuit that converts input voltage into a lower output voltage. In this application, it is used as the application carrier of a zero-crossing detection circuit, and is also referred to as a "buck converter" in this document.

[0038] DCM mode (Discontinuous Conduction Mode): refers to the working mode in which the inductor current in the buck converter drops to zero and remains at a certain time during each switching cycle. At this time, it is necessary to precisely control the turn-off time of the synchronous rectifier to avoid current backflow.

[0039] Switch node voltage signal (Vsw): The voltage signal obtained by sampling at the switch node of the BUCK converter.

[0040] Power ground signal (PVSS): The power ground potential signal used as a comparison reference.

[0041] First output signal (Vcp): The signal output by the digital auxiliary comparator module after comparison, which serves as the basis for subsequent digital logic processing.

[0042] Dynamic bias signal (Vdb): A signal generated by the digital logic module to dynamically control the bias of the digital auxiliary comparator module.

[0043] The second output signal (Vcmp) is a signal generated by the digital logic module. It exhibits a double-pulse characteristic when the current power transistor is turned off early and a single-pulse characteristic when it is turned off late. It is used to determine the timing of the synchronous rectifier transistor's turn-off.

[0044] Zero-crossing detection signal (ZCD): A signal output by the digital logic module that detects the moment when the current crosses zero and is used to control the power transistor to turn off.

[0045] Digital tuning signal (UP / DN): A signal generated by the detection and discrimination module based on the sampling results, used to indicate the counting operation of the counter module.

[0046] Six-bit digital control signal (Q<5:0>): A digital signal generated by the counter module, used to dynamically adjust the resistance value of the resistor array in the digital auxiliary comparator module to achieve adaptive adjustment of the flip offset.

[0047] Resistor array: A resistor network set inside the digital auxiliary comparator module, including two sets of resistors R5 to R0 and R5b to R0b. Its connection state is dynamically controlled by a six-bit digital control signal Q<5:0> and its inverted signal Qb<5:0>, thereby realizing precise adjustment of the comparator flip offset.

[0048] Upper power transistor control signal (HS) and lower power transistor control signal (LS): These are control signals that control the upper power transistor and the lower power transistor in the buck converter to turn on or off, respectively.

[0049] The following is a brief summary of some of the innovative aspects of this application:

[0050] In summary, this application addresses the current backflow problem caused by the control error in the turn-off timing of the synchronous rectifier in DCM mode of a BUCK switching power supply, proposing a hybrid analog-digital dynamic adaptive closed-loop control scheme. Within the range where the inductor current is close to zero, high-speed real-time sampling and comparison of the switching node voltage signal are employed, combined with the control signal for logical combination and discrimination, forming an iterative optimization closed loop. This enables dynamic adjustment of the comparison offset threshold, thereby achieving precise control of the synchronous rectifier turn-off timing. Its main technical contributions are:

[0051] First, to address the problems of large turn-off timing errors and low conversion efficiency caused by traditional fixed threshold comparison schemes, this application adopts a hybrid analog-digital dynamic closed-loop control architecture. By adjusting the offset of the analog comparator through a programmable digital resistor array, the combination of digital feedback and analog comparison is achieved, improving the adaptability of turn-off control.

[0052] Furthermore, this application utilizes the LC resonance characteristics of the switching node voltage waveform to determine the turn-off timing using the pulse characteristics of the second output signal Vcmp. Specifically, when the current power transistor turns off prematurely, the switching node voltage is pulled down to a negative value due to the forward voltage drop of the body diode, and then rises again under the action of LC resonance, resulting in Vcmp exhibiting a double-pulse characteristic; when the current power transistor turns off with a delay, the current has already crossed zero, and the switching node voltage remains positive, resulting in Vcmp exhibiting a single-pulse characteristic. Based on this pattern, a feedback path of sampling comparison - feature extraction - logic discrimination - digital tuning is constructed.

[0053] Furthermore, in the digital feedback path, this application employs a six-bit programmable counter, in conjunction with a latching trigger circuit for the digital tuning signals UP / DN, to convert the lead / lag information at the turn-off moment into an addition / subtraction operation of the resistor array. Through iterative adjustment, the continuity of the comparison threshold adjustment is ensured, reducing the impact of unstable factors such as drift and offset of the analog circuit.

[0054] Furthermore, this application combines digital assistance, adaptive closed-loop control, and mixed-signal processing technologies to improve the accuracy and stability of turn-off control. Dynamic closed-loop control eliminates the influence of device deviations, achieving superior control performance.

[0055] Furthermore, this application introduces dynamic bias control technology, which uses the dynamic bias signal Vdb to control the enabling and disabling of the circuit module. Within one cycle, the digital auxiliary comparator is enabled for only a short period of time, which greatly reduces the overall static power consumption of the circuit.

[0056] This application upgrades zero-crossing current detection into a closed-loop system with signal sampling, feature extraction-logic discrimination, and parameter optimization functions by combining digital control and analog comparison. Simultaneously, through the design and matching of digital and analog circuits, precise control of the turn-off time is achieved while maintaining the static current of the control circuit at the nanoampere level. This hybrid digital-analog technology offers improvements in accuracy and power consumption compared to existing technologies, providing a new implementation method for zero-crossing detection control in switching power supplies.

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] In this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as the corresponding technical features represented by their Chinese names plus letter codes. For example, "Vsw" and "switching node voltage signal Vsw" refer to the same technical feature, and "ZCD" and "zero-crossing detection signal ZCD" refer to the same technical feature. Other similar technical features represented by English letter codes are also equivalent to their corresponding technical features represented by their Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding technical features represented by their Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to:

[0059] Switch node voltage signal Vsw;

[0060] Power ground signal PVSS;

[0061] First output signal Vcp;

[0062] Dynamic bias signal Vdb;

[0063] Second output signal Vcmp;

[0064] Zero-crossing detection signal ZCD;

[0065] Digital tuning signal UP / DN;

[0066] Six-bit digital control signal Q<5:0>;

[0067] The six-bit digital control signal is inverted by the signal Qb<5:0>.

[0068] Upper power transistor control signal HS;

[0069] Lower power transistor control signal LS;

[0070] Clock signal CLK;

[0071] The clock signal CLKD for the D flip-flop;

[0072] Set signal;

[0073] Power supply potential VDD;

[0074] Inductor current IL;

[0075] Input voltage VIN;

[0076] The preamplifier outputs Vp in-phase.

[0077] The preamplifier outputs Vn inverted.

[0078] The current source Ip of the preamplifier;

[0079] Buck converter;

[0080] Discontinuous conduction mode (DCM).

[0081] Furthermore, in all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0082] 100: Zero-crossing detection circuit

[0083] 110: Digital Auxiliary Comparator Module

[0084] 120: Digital Logic Module

[0085] 130: Detection and discrimination module

[0086] 140: Counter modulus.

[0087] The first embodiment of this application relates to a digitally assisted adaptive zero-crossing detection circuit 100, such as... Figure 1 As shown, it includes:

[0088] A digital auxiliary comparator module 110, including a resistor array, is configured to sample and compare a switching node voltage signal Vsw with a power ground signal pvss when the power transistor in the power stage of the buck converter is turned on, and generate a first output signal Vcp.

[0089] Digital logic module 120, electrically connected to digital auxiliary comparator module 110, is used to receive the first output signal Vcp and the upper power transistor control signal HS and the lower power transistor control signal LS in the power stage of the buck converter, and after logic processing, respectively generate dynamic bias signal Vdb, second output signal Vcmp and zero-crossing detection signal ZCD.

[0090] The detection and discrimination module 130 is electrically connected to the digital logic module 120 and is used to receive the second output signal Vcmp and the zero-crossing detection signal ZCD, and generate a digital tuning signal UP / DN after logic processing.

[0091] The counter module 140 is electrically connected to the detection and discrimination module 130 and is used to receive the digital tuning signal UP / DN, and generate a six-bit digital control signal Q<5:0> after counting processing.

[0092] The six-bit digital control signal Q<5:0> is connected to the resistor array of the digital auxiliary comparator module 110. By dynamically changing the resistance value of the resistor array, the adaptive adjustment of the flip offset of the digital auxiliary comparator module 110 is achieved.

[0093] Optionally, the digital auxiliary comparator module 110 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal, and an output signal terminal. The power supply terminal receives the power supply potential VDD, the reference ground terminal receives the reference ground potential, the first input terminal receives the switching node voltage signal Vsw, the second input terminal receives the power ground signal pvss, the third input terminal receives the dynamic bias signal Vdb, the six-bit digital input terminal sequentially receives the six-bit digital control signal Q<5:0> from the counter module 140, and the output signal terminal outputs the first output signal Vcp.

[0094] Furthermore, the resistor array includes a first group of resistors R5 to R0 and a second group of resistors R5b to R0b; the six-bit digital control signal Q<5:0> is inverterized to generate a corresponding inverted signal Qb<5:0>; wherein Q<5:0> controls the first group of resistors R5 to R0, and Qb<5:0> controls the second group of resistors R5b to R0b; when Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited; when Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit; when the dynamic bias signal Vdb is high, the digital auxiliary comparator module 110 compares the magnitude of the input switch node voltage signal Vsw with the power ground signal pvss; when the switch node voltage signal Vsw is greater than the power ground signal pvss, the first output signal Vcp is output.

[0095] Optionally, the digital logic module 120 includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, and a third output terminal. The power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal Vcp from the digital auxiliary comparator module 110, the second input terminal receives an upper power transistor control signal HS in the power stage of the buck converter, the third input terminal receives a lower power transistor control signal LS in the power stage of the buck converter, the first output terminal outputs a dynamic bias signal Vdb, the second output terminal outputs a second output signal Vcmp, and the third output terminal outputs a zero-crossing detection signal ZCD.

[0096] Furthermore, when the received first output signal Vcp flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD output by the digital logic module 120 successively flip to a high level; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the received upper power transistor control signal HS flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the received lower power transistor control signal LS flips to a high level, the dynamic bias signal Vdb flips to a high level, and the falling edge of the lower power transistor control signal LS, after being delayed, triggers the dynamic bias signal Vdb to flip to a low level.

[0097] Optionally, the detection and discrimination module 130 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, and an output signal terminal. The power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the first input terminal receives a second output signal Vcmp from the digital logic module 120, the second input terminal receives a zero-crossing detection signal ZCD from the digital logic module 120, and the output signal terminal outputs the digital tuning signal UP / DN.

[0098] Furthermore, the detection and discrimination module 130 generates a clock signal CLKD for the D flip-flop after delaying the zero-crossing detection signal ZCD; when the rising edge of the clock signal CLKD arrives, the level of the second output signal Vcmp is sampled; when the sampled second output signal Vcmp is high, it indicates that the lower power transistor is delayed and turned off, and the detection and discrimination module 130 outputs a low digital tuning signal UP / DN; when the sampled second output signal Vcmp is low, it indicates that the lower power transistor is turned off prematurely, and the detection and discrimination module 130 outputs a high digital tuning signal UP / DN.

[0099] Optionally, the counter module 140 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, and a six-bit digital signal output terminal. The power supply terminal receives a power supply potential VDD, the reference ground terminal receives a reference ground potential, the first input terminal receives a digital tuning signal UP / DN from the detection and discrimination module 130, the second input terminal receives a set signal SET, the third input terminal receives a clock signal CLK, and the six-bit digital signal output terminal outputs the six-bit digital control signal Q<5:0>.

[0100] Furthermore, when the set signal SET is low, the six-bit digital signal output terminal of the counter module 140 outputs low level, high level, high level, high level, high level, high level sequentially from high bit to low bit; when the digital tuning signal UP / DN is low, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module 140 is decreased by one when the rising edge of the clock signal CLK arrives; when the digital tuning signal UP / DN is high, the decimal value of the six-bit digital control signal Q<5:0> output by the counter module 140 is increased by one when the rising edge of the clock signal CLK arrives.

[0101] To make the technical solution of the present invention clearer and more understandable, it is now combined with Figures 1 to 7 Preferred embodiments of the present invention will be described in detail, but it should be understood that the described embodiments are merely exemplary and not restrictive.

[0102] Reference Figure 1 The digitally assisted adaptive zero-crossing detection circuit 100 of this application includes four main functional modules: a digitally assisted comparator module 110, a digital logic module 120, a detection and discrimination module 130, and a counter module 140.

[0103] The digital auxiliary comparator module 110 receives the switching node voltage signal Vsw and the power ground signal pvss as inputs. This module outputs a first output signal Vcp to the digital logic module 120, and simultaneously receives a six-bit digital control signal Q<5:0> from the counter module 140 and a dynamic bias signal Vdb from the digital logic module 120.

[0104] Digital logic module 120 receives the first output signal Vcp from digital auxiliary comparator module 110, as well as the upper power transistor control signal HS and the lower power transistor control signal LS from the power stage of the buck converter. This module generates three output signals: a dynamic bias signal Vdb fed back to digital auxiliary comparator module 110, a second output signal Vcmp passed to detection and discrimination module 130, and a zero-crossing detection signal ZCD.

[0105] The detection and discrimination module 130 receives the second output signal Vcmp and the zero-crossing detection signal ZCD from the digital logic module 120, generates a digital tuning signal UP / DN after logic discrimination, and transmits it to the counter module 140.

[0106] The counter module 140 receives the digital tuning signal UP / DN from the detection and discrimination module 130, as well as the externally input set signal SET and clock signal CLK. This module generates a six-bit digital control signal Q<5:0> based on changes in the input signal, which is used to dynamically adjust the resistor array inside the digital auxiliary comparator module 110 to achieve adaptive optimization of the comparison threshold.

[0107] Figure 1 The diagram also schematically illustrates a simplified structure of the power stage of a Buck converter, including the input voltage VIN, upper and lower power transistors, output inductor L0, output capacitor C0, and load. The zero-crossing detection circuit in this application is primarily used to detect in real time whether the current flowing through the output inductor L0 crosses zero, and accordingly turn off the synchronous rectifier transistor in a timely manner to prevent current backflow.

[0108] Reference Figure 2 The digital auxiliary comparator module 110 mainly consists of a preamplifier, a dynamic bias adjustment circuit, a comparator, and a resistor array.

[0109] The preamplifier includes two differential inputs and two differential outputs. Its non-inverting input receives the switching node voltage signal Vsw, its negative input receives the power ground signal pvss, its non-inverting output outputs the signal Vp, and its inverting output outputs the signal Vn.

[0110] The dynamic bias adjustment circuit provides dynamic bias to the preamplifier and includes three PMOS transistors, MP0, MP1, and MP2. The sources of MP0 and MP1 are connected to the power supply voltage VDD, and their drains are connected to the non-inverting output Vp and inverting output Vn of the preamplifier, respectively. The source of MP2 is connected to the power supply voltage VDD, and its gate and drain receive the dynamic bias signal Vdb and the current source Ip of the preamplifier, respectively. When the dynamic bias signal Vdb is high, the current source Ip of the preamplifier is activated, MP0 and MP1 are turned on, establishing a voltage difference between the non-inverting output Vp and the inverting output Vn of the preamplifier.

[0111] The non-inverting and inverting inputs of the comparator are connected to the non-inverting output Vp and the inverting output Vn of the preamplifier, respectively. When the non-inverting output Vp is greater than the inverting output Vn, the comparator outputs a high level, resulting in the first output signal Vcp; otherwise, it outputs a low level.

[0112] The resistor array is divided into two groups: the first group of resistors R5 to R0 and the second group of resistors R5b to R0b. R5 to R0 are connected sequentially between the non-inverting output Vp of the preamplifier and ground, while R5b to R0b are connected sequentially between the inverting output Vn of the preamplifier and ground. The six-bit digital control signal Q<5:0> and its inverted signal Qb<5:0> output by the counter module 140 control the connection state of the first and second groups of resistors, respectively: a high-level signal in Q<5:0> shorts the corresponding resistor, and a low-level signal connects the corresponding resistor to the circuit; the control effect of Qb<5:0> is exactly the opposite of Q<5:0>. By adjusting the connection combination of resistors in the resistor array, a certain initial voltage difference can be formed between the outputs Vp and Vn of the preamplifier, thereby affecting the input voltage of the comparator and ultimately achieving dynamic optimization of the zero-crossing detection threshold.

[0113] Reference Figure 3 The digital logic module 120 includes a first logic unit, a second logic unit, and a delay unit.

[0114] The first logic unit receives the first output signal Vcp from the digital auxiliary comparator module 110 and the upper power transistor control signal HS from the power stage of the buck converter. When the upper power transistor control signal HS is low, the first logic unit outputs a zero-crossing detection signal ZCD controlled by the first output signal Vcp; when the upper power transistor control signal HS is high, the zero-crossing detection signal ZCD is forcibly pulled low, indicating that zero-crossing detection is not required during the conduction of the upper power transistor.

[0115] The second logic unit receives the first output signal Vcp and the dynamic bias signal Vdb. When both are high, the second logic unit outputs a high-level second output signal Vcmp; otherwise, it outputs a low-level signal. This signal will be used for feature sampling in the subsequent detection and discrimination module.

[0116] The delay unit receives the lower power transistor control signal LS from the power stage of the buck converter. When the lower power transistor control signal LS is high, the delay unit outputs a high-level dynamic bias signal Vdb, initiating the sampling and comparison function of the digital auxiliary comparator module. After the falling edge of the lower power transistor control signal LS arrives, the delay unit will switch the dynamic bias signal Vdb low after a preset delay time. This delay mechanism ensures that the digital auxiliary comparator module 110 has sufficient time to complete the sampling and comparison of the switching node voltage, avoiding transient interference during power transistor switching from affecting detection accuracy.

[0117] Reference Figure 4The figure shows the main operating waveforms of the digital logic module 120. From top to bottom, the waveforms represent the changes of the upper power transistor control signal HS, the lower power transistor control signal LS, the first output signal Vcp, the second output signal Vcmp, the zero-crossing detection signal ZCD, and the dynamic bias signal Vdb over time t. The period T marked in the figure represents one complete cycle of these signal changes.

[0118] Regarding the dynamic bias signal Vdb, when the current power transistor control signal LS flips to a high level, Vdb also flips to a high level; when LS flips to a low level, Vdb flips to a low level after a certain delay.

[0119] Regarding the processing of the first output signal Vcp, when Vcp flips to a high level, if the dynamic bias signal Vdb is high (i.e., during the conduction of the lower power transistor), the second output signal Vcmp and the zero-crossing detection signal ZCD successively flip to a high level. When Vcp flips to a low level, Vcmp also flips to a low level.

[0120] The zero-crossing detection signal ZCD is controlled not only by Vcp, but also by the upper power transistor control signal HS: when HS is low, ZCD is controlled by Vcp; when HS flips to high, ZCD will be forcibly pulled low, indicating that zero-crossing detection is not performed during the conduction of the upper power transistor.

[0121] The timing and logical dependencies between the signals can be clearly seen from the waveform. The changes in these signals work together to achieve accurate detection of the zero-crossing point of the inductor current.

[0122] Reference Figure 5 The detection and discrimination module 130 mainly consists of a D flip-flop and a delay unit.

[0123] The data input terminal D of the D flip-flop is connected to the second output signal Vcmp from the digital logic module 120, and the clock input terminal CLK is connected to the signal CLKD processed by the delay unit. The zero-crossing detection signal ZCD generates the clock signal CLKD after passing through the delay unit.

[0124] When the rising edge of the clock signal CLKD arrives, the D flip-flop samples the instantaneous level of the second output signal Vcmp. When sampling occurs, the second output signal Vcmp is high, and the output digital tuning signal UP / DN is low; when sampling occurs, the second output signal Vcmp is low, and the output digital tuning signal UP / DN is high.

[0125] The delay unit's processing of the zero-crossing detection signal ZCD ensures signal stability when sampling the second output signal Vcmp. The digital tuning signal UP / DN output by this module indicates the offset of the actual turn-off time of the power transistor relative to the ideal zero-crossing point.

[0126] Reference Figure 6 The figure shows the waveform changes of the detection and discrimination module 130 under two operating states. The figure shows the two cases of delayed turn-off and early turn-off of the lower power transistor. For each case, the timing relationship of the switching node voltage signal Vsw, inductor current IL, second output signal Vcmp, zero-crossing detection signal ZCD, clock signal CLKD, and digital tuning signal UP / DN is given.

[0127] The zero-crossing detection signal ZCD is delayed to generate the clock signal CLKD for the D flip-flop. When the rising edge of the clock signal CLKD arrives, the D flip-flop samples the level of the second output signal Vcmp.

[0128] With the lower power transistor delayed turn-off, the current has already crossed zero, the switching node voltage Vsw remains at a high level, and the second output signal Vcmp exhibits single-pulse characteristics. At this time, the D flip-flop samples the high level of Vcmp on the rising edge of the clock signal CLKD and outputs a low-level digital tuning signal UP / DN.

[0129] When the lower power transistor is turned off early, the switching node voltage Vsw is pulled to a negative value and then rises again due to the conduction of the body diode, causing the second output signal Vcmp to exhibit a double-pulse characteristic. At this time, the D flip-flop samples the low level of Vcmp on the rising edge of the clock signal CLKD and outputs a high-level digital tuning signal UP / DN.

[0130] In this way, the detection and discrimination module 130 can determine the deviation of the actual turn-off time of the lower power transistor from the ideal zero-crossing point, and transmit this information to the counter module 140 through the level state of the digital tuning signal UP / DN for subsequent compensation and adjustment.

[0131] Reference Figure 7 The counter module 140 mainly consists of a six-bit binary increment / decrement counter and a six-bit digital signal output terminal.

[0132] The counter module 140 has three input signals: a set signal SET, a digital tuning signal UP / DN, and a clock signal CLK. The set signal SET is active low. When the set signal is low, the six-bit digital signal output terminal of the counter module 140 outputs low level, high level, high level, high level, high level, and high level sequentially from the most significant bit to the least significant bit.

[0133] Under normal operating conditions, when the digital tuning signal UP / DN from the detection and discrimination module 130 is low, the decimal representation of the six-bit digital control signal Q<5:0> output by the counter module 140 is decremented by one on the rising edge of the clock signal CLK. When the digital tuning signal UP / DN is high, the decimal representation of the six-bit digital control signal Q<5:0> output is incremented by one on the rising edge of the clock signal CLK.

[0134] By using this incrementing or decrementing counting method, the counter module 140 can dynamically adjust the output six-bit digital control signal Q<5:0> according to the indication of the digital tuning signal UP / DN, thereby controlling the connection state of the resistor array in the digital auxiliary comparator module 110 and realizing adaptive optimization of the comparison threshold.

[0135] Working principle:

[0136] The working principle of the digitally assisted adaptive zero-crossing detection circuit in this embodiment is explained in detail below.

[0137] This application addresses the efficiency and electromagnetic compatibility issues of buck DC-DC converters in DCM mode by proposing a hybrid analog-digital adaptive control scheme. This scheme achieves accurate detection of the inductor current zero-crossing point and optimal turn-off control of the synchronous rectifier diodes by dynamically adjusting the comparator's switching threshold.

[0138] The entire system's workflow can be divided into the following key steps:

[0139] First, during the conduction of the lower power transistor, the digital auxiliary comparator module 110 monitors the switching node voltage signal Vsw and the power ground signal pvss in real time. When Vsw is greater than pvss, the comparator outputs a high-level first output signal Vcp, indicating that the inductor current may be about to cross zero.

[0140] Next, the digital logic module 120 performs logic operations on the first output signal Vcp and the power transistor control signals HS and LS to generate three key signals: the dynamic bias signal Vdb for feedback control comparator bias, the second output signal Vcmp indicating the zero-crossing characteristic of the current, and the zero-crossing detection signal ZCD for controlling the power transistor to turn off.

[0141] It is worth noting that the actual turn-off time may deviate from the ideal zero-crossing point. For example... Figure 6 As shown, when the current power transistor is turned off early, the forward voltage drop of the acceptor diode causes Vsw to be pulled to a negative value first and then rise, resulting in Vcmp exhibiting a double-pulse characteristic; when the current power transistor is turned off late, the current has already crossed zero, Vsw remains at a high level, and Vcmp only exhibits a single-pulse characteristic.

[0142] The detection and discrimination module 130 utilizes this difference feature to sample the second output signal Vcmp at the rising edge of the clock signal CLKD generated by the zero-crossing detection signal ZCD delay. When the sample is high (corresponding to the delayed turn-off of the lower power transistor), a low-level digital tuning signal UP / DN is output; when the sample is low (corresponding to the early turn-off of the lower power transistor), a high-level digital tuning signal UP / DN is output.

[0143] The counter module 140 dynamically adjusts the value of the six-bit digital control signal Q<5:0> on the rising edge of the clock signal CLK based on the level of the digital tuning signal UP / DN, thereby changing the connection state of the internal resistor array of the digital auxiliary comparator module 110. For example... Figure 2 As shown, the combination of resistor arrays R5 to R0 and R5b to R0b controlled by Q<5:0> and its inverting signal Qb<5:0> affects the output voltage difference of the preamplifier, ultimately adjusting the flip offset of the comparator.

[0144] During system operation, if the lower power transistor is detected to turn off later than the zero-crossing point, the counter module 140 will decrease the value of Q<5:0>, causing the comparator to flip earlier in the next cycle; conversely, if the lower power transistor turns off earlier than the zero-crossing point, the value of Q<5:0> will be increased, delaying the comparator flipping. After several cycles of adaptive iteration, the system will converge to the optimal turn-off time.

[0145] In summary, this application ingeniously combines analog-digital circuits and adaptive control algorithms. Through a closed-loop feedback mechanism of sampling comparison, feature extraction, logic discrimination, and digital tuning, it achieves dynamic optimization of the turn-off time of the synchronous rectifier tube, effectively improving the efficiency performance of the DC-DC converter in DCM mode and suppressing the ringing phenomenon of the switching node. It has significant technical effects and application value.

[0146] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0147] In summary, this example is characterized by the following: the digital auxiliary comparator module compares the switching node voltage signal Vsw with the power ground signal pvss and generates a first output signal Vcp; the digital logic module processes the first output signal Vcp to generate a zero-crossing detection signal ZCD, and generates a power transistor control signal through the logic driver module to control the power transistor to turn off; the detection and discrimination module receives the second output signal Vcmp and the zero-crossing detection signal ZCD from the digital logic module and generates a digital tuning signal UP / DN; the counter module receives the digital tuning signal UP / DN from the detection and discrimination module and generates a six-bit digital signal Q<5:0>, dynamically adjusts the resistor array in the digital auxiliary comparator module, and adaptively adjusts the comparator's flip-flop offset by changing the resistance value of the resistor array, thereby precisely controlling the power transistor's turn-off timing.

[0148] Furthermore, the purpose of this example is to provide a digitally assisted adaptive zero-crossing detection circuit. It generates a zero-crossing detection signal ZCD by comparing the switching node voltage signal Vsw with the power ground signal pvss, thereby controlling the turn-off of the power transistor. This example achieves high-precision zero-crossing detection in different application scenarios, while also improving the chip's conversion efficiency in DCM operating mode and reducing ringing at the switching node.

[0149] The digitally assisted adaptive zero-crossing detection circuit in this example includes: a digitally assisted comparator module 110, a digital logic module 120, a detection and discrimination module 130, and a counter module 140. The digitally assisted comparator module 110 is configured to sample the switching node voltage signal Vsw and the power ground signal pvss when the lower power transistor in the buck converter power stage is turned on, compare them, and generate a first output signal Vcp. The digital logic module 120 is configured to receive the first output signal Vcp from the digitally assisted comparator module 110, as well as the upper power transistor control signal HS and the lower power transistor control signal HS in the buck converter power stage, when the lower power transistor in the buck converter power stage is turned on. After logical processing, the digital logic module 120 generates a dynamic bias signal Vdb, a second output signal Vcmp, and a zero-crossing detection signal ZCD. The detection and discrimination module 130 is configured to receive the second output signal Vcmp and the zero-crossing detection signal ZCD from the digital logic module 120, and after logical processing, generate a digital tuning signal UP / DN. The counter module 140 is configured to receive the digital tuning signal UP / DN from the detection and discrimination module 130, and after counting processing, generate a six-bit digital control signal Q<5:0>, dynamically adjusting the resistor array in the digital auxiliary comparator module 110. By changing the resistance value of the resistor array, the flip-flop offset of the comparator is adaptively adjusted.

[0150] In this example, optionally, the digital auxiliary comparator module 110 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal, and an output signal terminal. The power supply terminal receives the power supply potential, the reference ground terminal receives the reference ground potential, the first input terminal receives the switching node voltage signal Vsw, the second input terminal receives the power ground signal pvss, the third input terminal receives the dynamic bias signal Vdb, the six-bit digital input terminal sequentially receives the six-bit digital control signal Q<5:0> from the counter module 140, and the output signal terminal outputs the first output signal Vcp. Furthermore, the digital auxiliary comparator module 110 is configured to compare the input switch node voltage signal Vsw with the power ground signal pvss when the dynamic bias signal Vdb is high, and output the first output signal Vcp when the switch node voltage signal Vsw is greater than the power ground signal pvss. The received six-bit digital control signal Q<5:0> is used to control the resistance value of the internal resistor array of the module, and the offset of the comparator flipping is changed by changing the resistance value of the resistor array.

[0151] In this example, optionally, the digital logic module 120 includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, and a third output terminal. The power supply terminal receives a power supply potential, the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal Vcp from the digital auxiliary comparator module 110, the second input terminal receives an upper power transistor control signal HS from the power stage of the buck converter, the third input terminal receives a lower power transistor control signal LS from the power stage of the buck converter, the first output terminal outputs a dynamic bias signal Vdb, the second output terminal outputs a second output signal Vcmp, and the third output terminal outputs a zero-crossing detection signal ZCD. Furthermore, the digital logic module 120 is configured such that when the first output signal Vcp received from the digital auxiliary comparator module 110 flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD flip to a high level; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the upper power transistor control signal HS received from the power stage of the buck converter flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the lower power transistor control signal LS received from the power stage of the buck converter flips to a high level, the dynamic bias signal Vdb flips to a high level; and the falling edge of the lower power transistor control signal LS triggers the dynamic bias signal Vdb to flip to a low level after a certain delay.

[0152] In this example, optionally, the detection and discrimination module 130 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, and an output signal terminal. The power supply terminal receives a power supply potential, the reference ground terminal receives a reference ground potential, the first input terminal receives a second output signal Vcmp from the digital logic module 120, the second input terminal receives a zero-crossing detection signal ZCD from the digital logic module 120, and the output signal terminal outputs a digital tuning signal UP / DN. Further, the detection and discrimination module 130 is configured to sample the second output signal Vcmp at the rising edge of the delayed zero-crossing detection signal ZCD. When sampling, the second output signal Vcmp is high, and the output digital tuning signal UP / DN is low; conversely, when sampling, the second output signal Vcmp is low, and the output digital tuning signal UP / DN is high.

[0153] In this example, optionally, the counter module 140 includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, and a six-bit digital signal output terminal. The power supply terminal receives the power supply potential, the reference ground terminal receives the reference ground potential, the first input terminal receives the digital tuning signal UP / DN from the detection and discrimination module 130, the second input terminal receives the set signal SET, the third input terminal receives the clock signal CLK, and the six-bit digital signal output terminal outputs a six-bit digital control signal Q<5:0>. Furthermore, the counter module 140 is configured to receive a set signal SET that is active low. When the set signal SET is low, the six-bit digital signal output terminal of the counter module 140 outputs low level, high level, high level, high level, high level, high level, and high level respectively from the high bit to the low bit. When the received digital tuning signal UP / DN is low, the decimal representation of the output six-bit digital control signal Q<5:0> is decremented by one at the rising edge of the received clock signal CLK. When the received digital tuning signal UP / DN is high, the decimal representation of the output six-bit digital control signal Q<5:0> is incremented by one at the rising edge of the received clock signal CLK.

[0154] In this example, the quiescent current can be controlled at the nanoampere level, making it suitable for ultra-low power applications. Only one comparator and a small amount of basic digital logic circuitry are needed to efficiently achieve adaptive loop control. The digital auxiliary comparator is multifunctional, not only accurately detecting the current zero-crossing point but also providing crucial information for the detection and discrimination module through its output signal Vcp, thereby accurately determining the timing of the turn-off. During the initial circuit startup, the initial error is significantly reduced because the digital auxiliary comparator can directly detect and quickly turn off the power transistor.

[0155] Furthermore, such as Figure 1As shown. The zero-crossing detection circuit 100 includes: a digital auxiliary comparator module 110, a digital logic module 120, a detection and discrimination module 130, and a counter module 140. The digital auxiliary comparator module 110 is configured to sample the switching node voltage signal Vsw and the power ground signal pvss when the lower power transistor in the buck converter power stage is turned on, compare them, and generate a first output signal Vcp. The digital logic module 120 is configured to receive the first output signal Vcp from the digital auxiliary comparator module 110 and the upper power transistor control signal H from the upper power transistor in the buck converter power stage when the lower power transistor in the buck converter power stage is turned on. After logical processing of the S and the lower power transistor control signal LS, a dynamic bias signal Vdb, a second output signal Vcmp, and a zero-crossing detection signal ZCD are generated. The detection and discrimination module 130 is configured to receive the second output signal Vcmp and the zero-crossing detection signal ZCD from the digital logic module 120, perform logical processing, and then generate a digital tuning signal UP / DN. The counter module 140 is configured to receive the digital tuning signal UP / DN from the detection and discrimination module 130, perform counting processing, and then generate a six-bit digital control signal Q<5:0> to control the toggle offset of the digital auxiliary comparator module 110.

[0156] Digital Auxiliary Comparator Module 110 Figure 2 As shown, when the dynamic bias signal Vdb is high, the module compares the input switch node voltage signal Vsw with the power ground signal pvss. When the switch node voltage signal Vsw is greater than the power ground signal pvss, it outputs the first output signal Vcp. This module receives a six-bit digital control signal Q<5:0> from the counter module 140, which is then passed through an inverter to generate a logically opposite six-bit digital control signal Qb<5:0>. The six-bit digital control signals Q<5:0> and Qb<5:0> control resistors R5 to R0 and R5b to R0b in the resistor array, respectively. When the six-bit digital control signals Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited; when the six-bit digital control signals Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit. In the initial state of the circuit, Q<5:0> from high to low level are low level, high level, high level, high level, high level, high level. At this time, only R5 is connected to the circuit from R5 to R0. Qb<5:0> from high to low level are high level, low level, low level, low level, low level, low level. At this time, R4b, R3b, R2b, R1b and R0b from R5b to R0b are connected to the circuit.

[0157] Digital Logic Module 120, etc. Figure 3 As shown, the working waveform is as follows Figure 4As shown. When the first output signal Vcp received from the digital auxiliary comparator module 110 flips to a high level, the second output signal Vcmp and the zero-crossing detection signal ZCD flip to a high level; when the first output signal Vcp flips to a low level, the second output signal Vcmp flips to a low level; when the upper power transistor control signal HS received from the power stage of the buck converter flips to a high level, the zero-crossing detection signal ZCD flips to a low level; when the lower power transistor control signal LS received from the power stage of the buck converter flips to a high level, the dynamic bias signal Vdb flips to a high level, and the falling edge of the lower power transistor control signal LS triggers the dynamic bias signal Vdb to flip to a low level after a certain delay.

[0158] Detection and discrimination module 130, etc. Figure 5 As shown, the working waveform is as follows Figure 6 As shown in the diagram, during the operation of the circuit, when the lower power transistor is turned off prematurely, the current will freewheel through the body diode of the lower power transistor. Due to the certain forward voltage drop of the body diode, the switching node voltage signal Vsw will be pulled down to approximately negative several hundred millivolts. This voltage value is significantly lower than the Vsw voltage threshold when the comparator flips, so the second output signal Vcmp will flip to a low level. However, with the resonance effect of the LC circuit, Vsw will gradually rise and, after a period of time, trigger the comparator to flip to a high level again until the comparator is finally turned off. Therefore, in this case, the second output signal Vcmp will exhibit the characteristics of two pulse signals. Conversely, when the lower power transistor is delayed in turning off, the current has already passed zero, and the switching node voltage signal Vsw has become positive and remains greater than zero for a period of time until the comparator is finally turned off. Therefore, in this case, the second output signal Vcmp will exhibit a single pulse signal.

[0159] The detection and discrimination module 130 generates a clock signal CLKD for the D flip-flop after delaying the zero-crossing detection signal ZCD from the digital logic module 120. The second output signal Vcmp is sampled on the rising edge of the clock signal CLKD. When sampling, the second output signal Vcmp is high, and the output digital tuning signal UP / DN is low; when sampling, the second output signal Vcmp is low, and the output digital tuning signal UP / DN is high.

[0160] Counter module 140, etc. Figure 7As shown, the received set signal SET is active low. When the set signal SET is low, the six-bit digital signal output terminal Q<5:0> of the counter module 140 outputs low level, high level, high level, high level, high level, high level respectively from high bit to low bit. When the received digital tuning signal UP / DN is low, the decimal representation of the output six-bit digital control signal Q<5:0> is decremented by one at the rising edge of the received clock signal CLK. When the received digital tuning signal UP / DN is high, the decimal representation of the output six-bit digital control signal Q<5:0> is incremented by one at the rising edge of the received clock signal CLK.

[0161] Taking the case of delayed turn-off of the lower power transistor as an example, at this time, the digital tuning signal UP / DN is at a low level, and the counter module 140 performs a subtraction operation, updating its output six-bit digital control signal Q<5:0> from the initial value 011111 in binary representation to 011110. Correspondingly, the six-bit digital control signal Qb<5:0> is updated from the initial value 100000 in binary representation to 100001. At this time, R5 and R0 in the resistor array R5 to R0 are connected to the circuit, and their resistance increases, while R4b, R3b, R2b, and R1b in the resistor array R5b to R0b are connected to the circuit, and their resistance decreases. The adjustment of the resistor array further affects the output voltage of the preamplifier: the voltage signal Vp at the non-inverting output terminal increases, while the voltage signal Vn at the inverting output terminal decreases. This voltage change causes the comparator to flip earlier in the next working cycle, thereby prompting the lower power transistor to turn off earlier.

[0162] Conversely, when the lower power transistor is turned off prematurely, the digital tuning signal UP / DN is high, and the counter module 140 performs an addition operation. This updates the six-bit digital control signal Q<5:0> output from its initial binary value of 011111 to 100000. Correspondingly, the six-bit digital control signal Qb<5:0> is updated from its initial binary value of 100000 to 011111. At this time, resistors R4, R3, R2, R1, and R0 in the resistor array R5 to R0 are connected to the circuit, and their resistance decreases, while R5b in the resistor array R5b to R0b is connected to the circuit, and its resistance increases. The adjustment of the resistor array further affects the output voltage of the preamplifier: the voltage signal Vp at the non-inverting output terminal decreases, while the voltage signal Vn at the inverting output terminal increases. This voltage change causes the comparator to delay its flip in the next operating cycle, thereby causing the lower power transistor to turn off delayed.

[0163] Through an adaptive feedback mechanism, after several cycles of tuning, the digital auxiliary comparator module 110 can gradually approach the optimal turn-off time of the lower power transistor under the adjustment of the feedback loop, thereby achieving precise control and optimization of the circuit's operating state.

[0164] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0165] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A digitally assisted adaptive zero-crossing detection circuit, characterized in that, include: A digital auxiliary comparator module, including a resistor array, is configured to sample and compare a switching node voltage signal (Vsw) with a power ground signal (pvss) when the power transistor in the power stage of the buck converter is turned on, and generate a first output signal (Vcp). The digital logic module, electrically connected to the digital auxiliary comparator module, is used to receive the first output signal (Vcp) and the upper power transistor control signal (HS) and lower power transistor control signal (LS) in the power stage of the buck converter, and generate the dynamic bias signal (Vdb), the second output signal (Vcmp) and the zero-crossing detection signal (ZCD) respectively after logic processing. The detection and discrimination module is electrically connected to the digital logic module and is used to receive the second output signal (Vcmp) and the zero-crossing detection signal (ZCD), and generate a digital tuning signal (UP / DN) after logic processing. The counter module, electrically connected to the detection and discrimination module, is used to receive the digital tuning signal (UP / DN), and generate a six-bit digital control signal (Q<5:0>) after counting processing. The six-bit digital control signal (Q<5:0>) is connected to the resistor array of the digital auxiliary comparator module. By dynamically changing the resistance value of the resistor array, the adaptive adjustment of the flip offset of the digital auxiliary comparator module is realized. The digital auxiliary comparator module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, a six-bit digital input terminal, and an output signal terminal. The power supply terminal receives the power supply potential (VDD), the reference ground terminal receives the reference ground potential, the first input terminal receives the switching node voltage signal (Vsw), the second input terminal receives the power ground signal (pvss), the third input terminal receives the dynamic bias signal (Vdb), the six-bit digital input terminal sequentially receives the six-bit digital control signal (Q<5:0>) from the counter module, and the output signal terminal outputs the first output signal (Vcp). The digital logic module includes: a power supply terminal, a reference ground terminal, an enable terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, and a third output terminal. The power supply terminal receives a power supply potential (VDD), the reference ground terminal receives a reference ground potential, the enable terminal receives an enable signal, the first input terminal receives a first output signal (Vcp) from the digital auxiliary comparator module, the second input terminal receives an upper power transistor control signal (HS) in the buck converter power stage, the third input terminal receives a lower power transistor control signal (LS) in the buck converter power stage, the first output terminal outputs a dynamic bias signal (Vdb), the second output terminal outputs a second output signal (Vcmp), and the third output terminal outputs a zero-crossing detection signal (ZCD). The detection and discrimination module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, and an output signal terminal. The power supply terminal receives the power supply potential (VDD), the reference ground terminal receives the reference ground potential, the first input terminal receives the second output signal (Vcmp) from the digital logic module, the second input terminal receives the zero-crossing detection signal (ZCD) from the digital logic module, and the output signal terminal outputs the digital tuning signal (UP / DN). The counter module includes: a power supply terminal, a reference ground terminal, a first input terminal, a second input terminal, a third input terminal, and a six-bit digital signal output terminal. The power supply terminal receives the power supply potential (VDD), the reference ground terminal receives the reference ground potential, the first input terminal receives the digital tuning signal (UP / DN) from the detection and discrimination module, the second input terminal receives the set signal (SET), the third input terminal receives the clock signal (CLK), and the six-bit digital signal output terminal outputs the six-bit digital control signal (Q<5:0>).

2. The digitally assisted adaptive zero-crossing detection circuit according to claim 1, characterized in that, The resistor array includes a first group of resistors (R5 to R0) and a second group of resistors (R5b to R0b); the six-bit digital control signal (Q<5:0>) is inverterized to generate a corresponding inverted signal (Qb<5:0>); where Q<5:0> controls the first group of resistors (R5 to R0), and Qb<5:0> controls the second group of resistors (R5b to R0b); when Q<5:0> and Qb<5:0> are high, the corresponding resistors are short-circuited; when Q<5:0> and Qb<5:0> are low, the corresponding resistors are connected to the circuit; when the dynamic bias signal (Vdb) is high, the digital auxiliary comparator module compares the magnitude of the input switch node voltage signal (Vsw) with the power ground signal (pvss); when the switch node voltage signal (Vsw) is greater than the power ground signal (pvss), the first output signal (Vcp) is output.

3. The digitally assisted adaptive zero-crossing detection circuit according to claim 1, characterized in that, When the received first output signal (Vcp) flips to a high level, the second output signal (Vcmp) and the zero-crossing detection signal (ZCD) output by the digital logic module successively flip to a high level; when the first output signal (Vcp) flips to a low level, the second output signal (Vcmp) flips to a low level; when the received upper power transistor control signal (HS) flips to a high level, the zero-crossing detection signal (ZCD) flips to a low level; when the received lower power transistor control signal (LS) flips to a high level, the dynamic bias signal (Vdb) flips to a high level, and the falling edge of the lower power transistor control signal (LS) triggers the dynamic bias signal (Vdb) to flip to a low level after a delay.

4. The digitally assisted adaptive zero-crossing detection circuit according to claim 1, characterized in that, The detection and discrimination module generates a clock signal (CLKD) for the D flip-flop after delaying the zero-crossing detection signal (ZCD); when the rising edge of the clock signal (CLKD) arrives, the level state of the second output signal (Vcmp) is sampled. When the sampled second output signal (Vcmp) is high, it indicates that the lower power transistor is delayed in turning off, and the detection and discrimination module outputs a low digital tuning signal (UP / DN); when the sampled second output signal (Vcmp) is low, it indicates that the lower power transistor is turned off prematurely, and the detection and discrimination module outputs a high digital tuning signal (UP / DN).

5. The digitally assisted adaptive zero-crossing detection circuit according to claim 1, characterized in that, When the set signal (SET) is low, the six-bit digital signal output terminal of the counter module outputs low level, high level, high level, high level, high level, high level sequentially from the high bit to the low bit; when the digital tuning signal (UP / DN) is low, the decimal value of the six-bit digital control signal (Q<5:0>) output by the counter module is decreased by one when the rising edge of the clock signal (CLK) arrives; when the digital tuning signal (UP / DN) is high, the decimal value of the six-bit digital control signal (Q<5:0>) output by the counter module is increased by one when the rising edge of the clock signal (CLK) arrives.

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