Data processing method, semiconductor test board card and semiconductor test equipment

Abstract

The invention is suitable for the technical field of communication, and provides a data processing method, a semiconductor test board card and semiconductor test equipment, the method is applied to a host end in ATE equipment, the method comprises the steps that calling operation of an application side on a plurality of interfaces is acquired, and the calling operation carries an instruction; in response to the calling operation, on the basis of the calling time of each calling operation, the incidence relation between the instructions of two adjacent calling times and the byte length of each instruction, carrying out merging and packaging operation on one or more instructions to obtain a target data packet; and transmitting the target data packet to the slave end. The overhead of network communication can be reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor testing, and in particular to a data processing method, a semiconductor testing board and a semiconductor testing device. Background Art

[0002] With the rapid development of the semiconductor industry and the continuous improvement of chip integration, semiconductor automatic test equipment (ATE) plays an increasingly critical role in the field of testers. In the test process, the internal mechanism of ATE relies on the host to send instructions to the slave to drive the slave to test the target chip. In this process, the communication between the master and the slave is particularly important.

[0003] However, the traditional master-slave communication mode, that is, the question-and-answer method, has obvious limitations. In this mode, the execution of each instruction must go through the complete process of establishing a connection, sending instructions, waiting for responses, and closing the connection. This not only increases the network burden, but also consumes a lot of network resources in scenarios with frequent communications, resulting in reduced efficiency. Summary of the invention

[0004] The embodiments of the present application provide a data processing method, a semiconductor test board and a semiconductor test device, which can reduce the overhead of network communication.

[0005] In a first aspect, an embodiment of the present application provides a data processing method, which is applied to a host side in an ATE device, and the method includes: obtaining a calling operation of an application side on multiple interfaces, the calling operation carrying instructions; in response to the calling operation, based on the calling time of each calling operation, the association relationship between instructions of two adjacent calling times, and the byte length of each instruction, merging and packaging one or more instructions to obtain a target data packet; and transmitting the target data packet to a slave side.

[0006] In a possible implementation of the first aspect, based on the calling time of each calling operation, the association relationship between instructions of two adjacent calling times, and the byte length of the instructions, one or more instructions are merged and packaged to obtain a target data packet, including: according to the calling time of the calling operation, determining in sequence that the idle byte length of the data packet is greater than or equal to the byte length occupied by one or more instructions, and when there is no association relationship between two instructions of two adjacent calling times in one or more instructions, the one or more instructions are merged and packaged to obtain the target data packet.

[0007] In a possible implementation of the first aspect, based on the calling time of each calling operation, the association relationship between instructions of two adjacent calling times, and the byte length of the instructions, one or more instructions are merged and packaged to obtain a target data packet, including: according to the calling time of the calling operation, determining in sequence that the idle byte length of the data packet is greater than or equal to the byte length occupied by one or more instructions, and when there is no association relationship between two instructions of two adjacent calling times in one or more instructions, the one or more instructions are merged and packaged to obtain the target data packet.

[0008] In a possible implementation of the first aspect, among two instructions at two adjacent calling times, if the execution of the instruction at the later calling time depends on the completion of the instruction at the earlier calling time, it is determined that there is an association relationship between the two instructions at the two adjacent calling times; otherwise, it is determined that there is no association relationship between the two instructions at the two adjacent calling times.

[0009] In a possible implementation of the first aspect, if the instruction type with a later calling time is a preset type, it is determined that the execution of the instruction with a later calling time depends on the completion of the instruction with an earlier calling time; the preset types include: waiting type, measurement type, judgment type, and monitoring type.

[0010] In a possible implementation of the first aspect, one or more instructions are merged and packaged to obtain a target data packet, including: filling one or more instructions byte by byte starting from the header position of the data packet in order of calling time, and filling a first preset function code at the preset byte of the last instruction, and filling a second preset function code in the preset bytes of other instructions except the last instruction to obtain the target data packet; the first preset function code is used to indicate that the data packet will no longer merge new instructions, and the second preset function code is used to indicate that the data packet can merge new instructions.

[0011] In a possible implementation of the first aspect, a second preset function code is filled in the preset bytes of other instructions except the last instruction, including: for any instruction other than the last instruction, obtaining the original value in the preset byte of the instruction; performing a bitwise OR operation on the original value and 0x0800 to obtain the second preset function code of the instruction.

[0012] In a possible implementation manner of the first aspect, the preset byte is located at the second byte of the instruction.

[0013] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to a slave end in an ATE device, and the method includes: receiving a target data packet, the target data packet being obtained based on the first aspect; identifying one or more instructions based on a function code in the target data packet, and determining the position of each instruction in the data packet; and executing one or more instructions in sequence based on the position of each instruction in the data packet.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor test board, the semiconductor test board comprising:

[0015] The acquisition module is used to receive the calling operation of multiple interfaces from the application side, where the calling operation carries instructions.

[0016] The merging module is used to respond to the calling operation, and based on the calling time of each calling operation, the association relationship between the instructions of two adjacent calling times and the byte length of each instruction, merge and pack one or more instructions to obtain a target data packet.

[0017] The transmission module is used to transmit the target data packet to the underlying processor.

[0018] In a fourth aspect, an embodiment of the present application provides a semiconductor test board, the semiconductor test board comprising:

[0019] The receiving module is used to receive the target data packet.

[0020] The identification module is used to identify one or more instructions based on the function code in the target data packet and determine the position of each instruction in the data packet.

[0021] The execution module is used to execute one or more instructions in sequence based on the position of each instruction in the data packet.

[0022] In a fifth aspect, an embodiment of the present application provides a semiconductor testing device, which includes: the semiconductor testing board of the third aspect and the semiconductor testing board of the fourth aspect.

[0023] In the sixth aspect, an embodiment of the present application provides a terminal device, including: the terminal device is a host end, the host end includes a processor and a memory and a data interface coupled to the processor; wherein the data interface is used for data communication with the slave end, the memory is used for program data, and the program data, when executed by the processor, is used to implement the above-mentioned method applied to the first aspect.

[0024] In the seventh aspect, an embodiment of the present application provides a terminal device, including: the terminal device is a slave end, the slave end includes a processor and a memory and a data interface coupled to the processor; wherein the data interface is used to communicate data with the host end, the memory is used for program data, and the program data, when executed by the processor, is used to implement the above-mentioned method provided for application in the first aspect.

[0025] In an eighth aspect, an embodiment of the present application provides an ATE device, which includes a host end and a slave end that can be connected to communicate with each other; wherein the host end is the host end in the terminal device of the fifth aspect above, and / or the slave end is the slave end in the terminal device of the sixth aspect above.

[0026] In the ninth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program / instructions. When the computer program / instructions are executed on an electronic device, the electronic device executes the above-mentioned first aspect and any possible implementation method thereof or the method in the second aspect.

[0027] In the tenth aspect, an embodiment of the present application provides a computer program product, including a computer program / instructions, which, when executed by a processor, enables an electronic device to execute the above-mentioned first aspect and any possible implementation thereof or the method in the second aspect.

[0028] Compared with the prior art, the embodiments of the present application have the following beneficial effects: when the application side performs a call operation on multiple interfaces, based on the call time of each call operation, the correlation between the instructions of two adjacent call times, and the byte length of the instructions carried by each call operation, one or more instructions are combined and packaged to be transmitted to the slave end as a data packet, which can not only reduce the number and overhead of communications between the host end and the slave end, thereby improving communication efficiency, especially in the case of large data volume or frequent communication, the effect of improving communication efficiency is more significant. Moreover, it can also reduce the number and transmission volume of data packets, save the use of bandwidth resources, reduce the load and pressure of the system, and help improve the overall performance and response speed of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 It is a schematic diagram of the architecture of an ATE device provided in one embodiment of the present application;

[0031] Figure 2 It is a flowchart of a data processing method provided by an embodiment of the present application;

[0032] Figure 3 It is a schematic diagram of the structure of a data packet provided in an embodiment of the present application;

[0033] Figure 4 It is a structural diagram of data merging provided in an embodiment of the present application;

[0034] Figure 5 is a flowchart of a data processing method provided by another embodiment of the present application;

[0035] Figure 6 is a schematic diagram of the structure of a semiconductor test board provided in an embodiment of the present application;

[0036] Figure 7 is a structural schematic diagram of a semiconductor testing device provided by another embodiment of the present application;

[0037] Figure 8 It is a schematic diagram of the structure of the terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0039] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0040] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0041] As used in the specification and appended claims of this application, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]", depending on the context.

[0042] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0043] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0044] ATE equipment mainly adopts the master-slave mode, also known as the master-servant mode, abbreviated in English as (Master-Slave), which consists of two parties: the host side and the slave side. The host side distributes work (i.e. sends instructions) to the same slave side and calculates the final results, which are returned by the slave side.

[0045] In the communication between the host and slave ends of ATE equipment, the traditional communication solution adopts a question-and-answer mode, and the next instruction can only be executed after one instruction is executed. In the question-and-answer mode, a series of processes such as establishing a connection, sending instructions, waiting for responses, and closing connections are required every time an instruction is executed, which invisibly increases the network overhead, especially in the scenario of frequent communication, which consumes a lot of network resources.

[0046] Based on the above defects, the embodiment of the present application provides a data processing method, a semiconductor test board and a semiconductor test device. The technical principle of the present application is: when the application side performs a call operation on multiple interfaces, based on the call time of each call operation, the correlation between the instructions of two adjacent call times and the byte length of the instructions carried by each call operation, one or more instructions are merged and packaged as a data packet and transmitted to the slave end. The slave end unpacks the received data packet, identifies one or more instructions based on the function code in the data packet, and determines the position of each instruction in the data packet so as to divide the merged instructions in the data packet into one or more instructions. Through this application, not only the number and overhead of communications can be reduced, but also the communication efficiency can be improved.

[0047] See also Figure 1 , Figure 1 1 is an implementation environment architecture diagram of a data processing method provided in an embodiment of the present application. The implementation environment architecture includes an ATE device 10; the ATE device 10 includes a host end 11 and a slave end 12; there can be one or more host ends 11, and similarly, there can be one or more slave ends 12, and one host end 11 can be used to control one or more slave ends 12.

[0048] Optionally, the host end 11 is connected to the slave end 12 via a bus, and the host end 11 and the slave end 12 can communicate with each other, but multiple slave ends 12 cannot communicate with each other.

[0049] Optionally, the communication technology between the host side 11 and the slave side 12 can be: extended direct memory access (eXtended Direct Memory Access, XDMA), transmission control protocol (Transmission Control Protocol, TCP), user datagram protocol (User Datagram Protocol, UDP), serial port, memory mapped I / O (Memory-Mapped I / O, MMIO), remote direct memory access (Remote Direct Memory Access, RDMA), etc.

[0050] As an example, taking MMIO communication technology as an example, in ATE equipment 10, MMIO (memory mapped I / O) is a technology for accessing I / O devices. In this system, the main processor (i.e., the host end 11, such as a semiconductor test board) communicates with the slave device (i.e., the slave end 12, such as other processors, such as a microcontroller unit (MCU), such as a semiconductor test board, etc.) through memory mapping. The main processor maps the registers of the I / O device to a specific address space of the system memory. By reading and writing these memory addresses, the main processor can directly control and transmit data to the slave device without passing specific I / O instructions. This direct memory access method can improve the efficiency and performance of data transmission. In ATE equipment 10, MMIO can be used to access various peripherals, such as graphics cards, network adapters, storage controllers, etc. The main processor can configure and control these peripherals and transmit data by reading and writing corresponding memory addresses.

[0051] As another example, taking XDMA communication technology as an example, in the ATE device 10, XDMA (Extended Direct Memory Access) is a technology for high-performance data transmission. Allow the main processor, i.e., the host end 11, usually the CPU) to directly access the memory of the slave device (i.e., the slave end 12, such as other processors, such as MCU) to achieve fast data transmission. XDMA implements data transmission by using a DMA (Direct Memory Access) engine. The DMA engine is a hardware module that can directly read data from the memory of the device or write data to the memory of the device under the intervention of the main processor without the active participation of the main processor. In the ATE device 10, XDMA can be used for high-speed data transmission, such as in the fields of high-performance computing, data centers, network communications, etc. The main processor can use XDMA to directly access the memory of the slave device to achieve fast data transmission and processing.

[0052] Optionally, the ATE device 10 of the embodiment of the present application can be applied to the energy management industry, such as smart grids, energy monitoring and control systems; the transportation industry, such as traffic signal control, intelligent traffic management and vehicle tracking systems; the medical industry, such as medical equipment and monitoring systems; the Internet of Things industry, such as connecting and controlling various devices and sensors to achieve data collection, remote monitoring and intelligent control, etc.

[0053] As an example, the ATE device 10 can be a management system applied to the medical industry, the host end 11 is the main control end, and the slave end 12 may include medical equipment with different functions, such as scanning equipment, blood sample detectors, particle detectors, etc. After the host end 11 establishes communication with each device of the slave end 12, the host end 11 can issue control commands to the slave end 12 to control the operation of the slave end 12. In addition, the slave end 12 can also send working data to the host end 11.

[0054] The following will be combined Figure 1 The technical solution of the present application and how the technical solution of the present application solves the above technical problems are described in detail with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0055] like Figure 2 As shown, the embodiment of the present application provides a data processing method, which is applied to the host side of the above-mentioned ATE device 10, and the method specifically includes the following steps:

[0056] 201. Obtain calling operations of multiple interfaces on the application side, where the calling operations carry instructions.

[0057] The instructions may be used to instruct the slave to perform a specific operation or configuration.

[0058] For example, the RelayOn and RelayOff instructions (turn on or off the relay): are used to turn on or off the relay on the pin to connect or disconnect the circuit. The SetLevelN and Levels instructions (set the level or current): are used to set the level or current value of the pin for testing or simulating specific signal conditions. The Raten instruction (set the rate): is used to indicate the cycle of the digital signal Pattern operation. The Markern instruction (generates a marker or waveform): is used to generate a marker or a specific waveform on the pin for synchronization or identification of specific events during testing. The ForceN instruction (set to high-impedance state): is used to put the chip into a high-impedance safe state when powered off.

[0059] The communication transmission mode between the host end and the slave end can be any one of parallel transmission, serial transmission and asynchronous transmission.

[0060] In a possible implementation, before the host transmits the target data packet to the slave, it is also necessary to establish a communication connection with the slave. Specifically, after powering on, the slave performs configuration based on preset configuration parameters, generates configuration data and configuration completion instructions after the configuration is completed, and sends the configuration data and configuration completion instructions to the host.

[0061] The host side detects whether the execution of the slave side is completed by judging whether the configuration data is the same as the preset data. If they are the same, it is determined that the configuration of the slave side is completed and the communication connection with the slave side is confirmed; if they are not the same, it is determined that the configuration of the slave side is not completed and the communication between the host side and the slave side is not established. In addition, if the communication between the host side and the slave side is not established, the slave side can report an error or the host side can report an error to remind the user that the configuration of the slave side is incorrect.

[0062] The preset data may be data pre-saved in the host side, which is the configuration data of the slave side when the host side and the slave side can communicate normally. For example, in one embodiment, when the host side and the slave side can communicate normally, the host side can be controlled to read and save the configuration data of the slave side, and the saved configuration data can be used as the preset data when the next detection is performed.

[0063] Optionally, in one embodiment, the host side calculates the configuration data based on a set algorithm. For example, the preset data is calculated to obtain a first check value, and the configuration data obtained from the slave side is calculated using the same algorithm to obtain a second check value, and then it is determined whether the first check value and the second check value are equal. If they are the same, it is determined that the preset data and the configuration data are the same.

[0064] 202. In response to the calling operation, based on the calling time of each calling operation, the association relationship between instructions at two adjacent calling times, and the byte length of each instruction, one or more instructions are combined and packaged to obtain a target data packet.

[0065] Optionally, the association relationship between instructions at two adjacent call times can be used to characterize the dependency relationship between instructions at two adjacent call times; the association relationship is used to characterize whether the execution of a later instruction is conditional on the completion of the execution of a previous instruction.

[0066] For example, assume that the previous instruction (recorded as instruction A) is used to instruct the generation of a mark or a specific waveform on the pin, and the latter instruction (recorded as instruction B) is used to instruct the measurement of the voltage or current of the pin. Normally, the execution of instruction B is based on the completion of instruction A. Therefore, it can be understood that there is an association and dependency relationship between instruction A and instruction B.

[0067] Based on the above, if instruction A and instruction B are combined and packaged, instruction B may be executed at an incorrect time, thereby affecting the execution result of instruction B. Therefore, it can be understood that there must be no correlation between the instructions that can be combined and packaged.

[0068] Optionally, one or more instructions are spliced ​​according to the calling time of one or more instructions to obtain a target data packet. Further, multiple instructions are spliced ​​according to a preset format to form a packaged instruction.

[0069] For example, the data of multiple instructions are concatenated in JSON (JavaScript Object Notation) format to form a JSON object or string, which can be applicable to the transmission of structured data and complex instructions.

[0070] Optionally, according to the calling time of one or more instructions, data compression is performed on one or more instructions and then data splicing is performed to obtain a target data packet, so as to reduce the size of the data and thus the amount of data transmitted and the transmission time.

[0071] 203. Transmit the target data packet to the slave end.

[0072] Optionally, the target data packet is transmitted to the slave end according to a preset communication protocol (a communication protocol generated based on the aforementioned communication technology) and hardware equipment.

[0073] When the data processing method provided in the embodiment of the present application performs a call operation on multiple interfaces on the application side, based on the call time of each call operation, the correlation between the instructions of two adjacent call times, and the byte length of the instructions carried by each call operation, one or more instructions are combined and packaged to be transmitted to the slave end as a data packet, which can not only reduce the number and overhead of communications between the host end and the slave end, thereby improving communication efficiency, especially in the case of large data volume or frequent communication, the effect of improving communication efficiency is more significant. Moreover, it can also reduce the number and transmission volume of data packets, save the use of bandwidth resources, reduce the load and pressure of the system, and help improve the overall performance and response speed of the system.

[0074] In one embodiment of the present application, based on the calling time of each calling operation, the association relationship between instructions of two adjacent calling times and the byte length of the instructions, one or more instructions are merged and packaged to obtain a target data packet, including: according to the calling time of the calling operation, determining in sequence that the idle byte length of the data packet is greater than or equal to the byte length occupied by one or more instructions, and when there is no association relationship between two instructions of two adjacent calling times in one or more instructions, one or more instructions are merged and packaged to obtain the target data packet.

[0075] As an example, according to the call time, assume that instruction A (byte length is assumed to be 160 bytes), instruction B (byte length is assumed to be 30 bytes), and instruction C (byte length is assumed to be 80 bytes) are received in sequence; the length of the data packet is 256 bytes, and in the process of packing the instructions, the total available space bytes are 255 bytes. After packing instruction A, the remaining free bytes of the data packet are 95 bytes; after packing instruction B, the remaining free bytes of the data packet are 65 bytes; and instruction C requires 80 bytes, and the remaining 65 free bytes of the data packet cannot accommodate instruction C. Therefore, there are two ways to pack instruction C:

[0076] Method 1: perform data compression processing on instruction C. If the byte length occupied by the compressed instruction C is less than or equal to 65 bytes, the compressed instruction C is combined with instruction A and instruction B for packaging.

[0077] It is understandable that since instruction C is compressed, a compression identifier can be carried in the compressed instruction C, so that the slave end can recognize that instruction C is compressed data, so as to decompress the compressed instruction C and restore instruction C.

[0078] Method 2: Use instruction C as instruction data in the next data packet.

[0079] Based on the above content, determine that the idle byte length of the data packet is greater than or equal to the byte length occupied by one or more instructions, including determining that the sum of the byte lengths of other instructions except the last instruction in one or more instructions and the byte length of the last instruction after compression is less than or equal to the idle byte length of the data packet, and if there is no correlation between two instructions at two adjacent call times in one or more instructions, then merge and package the one or more instructions to obtain a target data packet.

[0080] In one embodiment of the present application, among two instructions at two adjacent calling times, if the execution of the instruction at the later calling time depends on the completion of the instruction at the earlier calling time, it is determined that there is an association relationship between the two instructions at the two adjacent calling times; otherwise, it is determined that there is no association relationship between the two instructions at the two adjacent calling times.

[0081] Optionally, if the instruction type with a later calling time is a preset type, it is determined that the execution of the instruction with a later calling time depends on the completion of the instruction with an earlier calling time; the preset types include: waiting type, measurement type, judgment type, and monitoring type.

[0082] Exemplarily, the wait type instruction may include a sleep function. In the instruction, sleep is used to control the command or function of program execution pause, and is used to pause the execution of the program for a specified period of time to achieve a delay or timing effect. The parameter of the sleep instruction can be a unit of time, such as seconds, milliseconds, or microseconds. For example, sleep(2) means that the program will pause execution for 2 seconds.

[0083] Measurement instructions may include a Measure function, in which Measure is used to perform a measurement operation, such as measuring voltage, current, temperature, pressure, and other physical quantities. The specific implementation may involve sensors, measuring instruments, or related API calls.

[0084] The judgment type of instructions may include a JudgePat (judgment mode) function. In the instruction, JudgePat is used to determine whether a device or system is in a certain mode or state. According to different conditions or rules, the judgment mode instruction can be used to determine the subsequent operation or process.

[0085] The monitoring instructions may include BPMU (Board Power Measurement Unit) functions. BPMU is the abbreviation of Board PowerMeasure Unit. In the instructions, BPMU is used to measure and output the power supply voltage and current.

[0086] In one embodiment of the present application, one or more instructions are merged and packaged to obtain a target data packet, including: filling one or more instructions byte by byte starting from the header position of the data packet in order of calling time, and filling a first preset function code at the preset byte of the last instruction, and filling a second preset function code in the preset bytes of other instructions except the last instruction to obtain the target data packet; the first preset function code is used to indicate that the data packet will no longer merge new instructions, and the second preset function code is used to indicate that the data packet can merge new instructions.

[0087] For example, assume that there are three commands, namely the first package command, the second package command and the third package command; the order of the command calling time is the first package command, the second package command and the third package command; the byte length of the first package command is 9 bytes, the byte length of the second package command is 9 bytes, and the byte length of the third package command is 7 bytes; according to the order of calling time, one or more instructions are filled byte by byte starting from the header position of the data packet. Figure 3 The packet format is shown.

[0088] During the packaging process, in order to identify whether the data packet stops receiving new instructions, the first preset function code (such as Figure 3 The second byte of the third packet command shown in FIG. 1 is filled with "00"), and the second preset function code (such as Figure 3 The second byte of the first packet command and the second packet command shown in FIG.

[0089] In one possible implementation, a second preset function code is filled in the preset bytes of instructions other than the last instruction, including: for any instruction other than the last instruction, obtaining the original value in the preset byte of the instruction; performing a bitwise OR operation on the original value and 0x0800 to obtain the second preset function code of the instruction.

[0090] It is understandable that when combining commands, for commands other than the last one, the frame function code needs to be added to 0x0800, but the function code of the last command does not need to be added to indicate that the combined command ends with this command.

[0091] Optionally, the preset byte is located at the second byte of the instruction.

[0092] For example, refer to Figure 4 , assuming that the application side calls the following interfaces in sequence (sorted from A to Z):

[0093] A:RelayOn(ALL_Pin,PPMU,10*mS).

[0094] B:SetLevelN(1,ALL_Pin,0*V,1.2*V,0.3*V,0.8*V,0*mA,0*mA,0*V,true).

[0095] C:Raten(1,50*nS).

[0096] D:Markern(1,ALL_Pin,0*nS,0*nS,0*nS,0*nS,0*nS,25*nS,45*nS,Waveform_NRZ,true); / / STB 0.7*rate1.

[0097] E:Levels(1,1*mS).

[0098] F: ForceN(ALL_Pin,PPMU,10*mS).

[0099] G:RelayOff(ALL_Pin,PPMU,10*mS).

[0100] The corresponding single instruction messages of instructions A to G are:

[0101] Instruction A: 07 0001 03 02 00 00 00 01 00 00 00 00 00 00 00 05 00 00 00 0024f449 94........86.

[0102] Instruction B: 01 0002 00 01 00 00 00 00 00 00 00 28 6b ee 4e 5e d0 b2 4f 20bcbe4b 20bc be 4b 00 24f4 49 05 00 00 00 00 00 00 00 59........57.

[0103] Instruction C: 03 0003 03 02 00 00 00 01 00 00 00 00 00......34.

[0104] Instruction D; 04 0004 00 01 00 00 00 00 00 00 00 28 6b ee 4e 5e d0 b2 4f 20bcbe4b 20bc be 4b 00 24f4 49 05 00 00 00 00 00 00 00 59........23.

[0105] Instruction E: 02 0005 03 02 00 00 00 01 00 00 00 00 00......33.

[0106] Instruction F: 18 0006 00 01 00 00 00 00 00 00 00 28 6b ee 4e 5e d0 b2 4f20........47.

[0107] Instruction G: 08 0007 03 02 00 00 00 01 00 00 00 00 00 00 00 05 00 00 00 0024f449 94........89.

[0108] After combining instructions A to G, the target data packet obtained is referenced Figure 4 shown. Figure 4 The underlined bytes in the target data packet shown in the figure represent the corresponding function codes in each instruction. It can be understood that the byte data of the target data packet does not carry underlines. The underlines here are only used to identify the position of the corresponding function code and the specific data, where the first preset function code is 00 and the second preset function code is 08.

[0109] In another embodiment of the present application, refer to Figure 5 , and also provides a data processing method, which is applied to a slave end in an ATE device, the method comprising:

[0110] 501. Receive target data packet.

[0111] The target data packet is obtained based on the above data processing method.

[0112] 502. Identify one or more instructions based on the function code in the target data packet, and determine the location of each instruction in the data packet.

[0113] Exemplarily, taking the case where the function code is set at the second byte of each instruction, when identifying the target data packet, first confirm the location of the function code of each instruction, and divide the merged instructions based on the function code to obtain one or more instructions.

[0114] In one possible implementation, when the target data packet is an encrypted data packet, one or more instructions are identified based on a function code in the target data packet, and the location of each instruction in the data packet is determined, including: decrypting the target data packet to obtain a merged instruction, and identifying one or more instructions based on a function code in the merged instruction, and determining the location of each instruction in the data packet.

[0115] Optionally, according to the target data packet structure, the header information of the target data packet is read, including the data packet length, data type, verification method, etc. This information is usually located in a fixed position or a specific field of the data packet. Afterwards, the data field is parsed according to the data packet structure and header information of the target data packet. Specifically, it includes data decoding, conversion or extraction operations to obtain valid data content. Finally, a verification operation is performed based on the verification field to ensure the integrity and accuracy of the data. The verification method can be executed according to a specific verification method, such as calculating a checksum, using a CRC algorithm, etc. After the verification is completed, the merged instructions in the target data are used to identify one or more instructions using the function code therein.

[0116] 503. Execute one or more instructions in sequence based on the location of each instruction in the data packet.

[0117] Optionally, after step 502, the slave end may send the execution result of the instruction to the host end.

[0118] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0119] Corresponding to the data processing method described in the above embodiment, Figure 6A structural block diagram of a semiconductor test board provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0120] Reference Figure 6 The semiconductor test board includes: an acquisition module 601, a merging module 602 and a transmission module 603, wherein:

[0121] The acquisition module 601 is used to receive the calling operation of the application side on multiple interfaces, and the calling operation carries instructions;

[0122] A merging module 602 is used to, in response to a call operation, merge and pack one or more instructions based on the call time of each call operation, the association relationship between instructions at two adjacent call times, and the byte length of each instruction to obtain a target data packet;

[0123] The transmission module 603 is used to transmit the target data packet to the bottom layer processor.

[0124] In one possible implementation, the merging module is specifically used to determine, in accordance with the calling time of the calling operation, that the idle byte length of the data packet is greater than or equal to the byte length occupied by one or more instructions, and if there is no correlation between two instructions with two adjacent calling times in the one or more instructions, then merge and package the one or more instructions to obtain a target data packet.

[0125] In one possible implementation, the merging module 602 is specifically used to determine, in accordance with the calling time of the calling operation, that the idle byte length of the data packet is greater than or equal to the byte length occupied by one or more instructions, and if there is no correlation between two instructions with two adjacent calling times in one or more instructions, then merge and pack the one or more instructions to obtain a target data packet.

[0126] In one possible implementation, among two instructions at two adjacent call times, if the execution of the instruction at the later call time depends on the completion of the instruction at the earlier call time, it is determined that there is an association relationship between the two instructions at the two adjacent call times; otherwise, it is determined that there is no association relationship between the two instructions at the two adjacent call times.

[0127] In a possible implementation, if the instruction type with a later calling time is a preset type, the execution of the instruction with a later calling time is determined to depend on the completion of the instruction with an earlier calling time; the preset types include: waiting type, measurement type, judgment type, and monitoring type.

[0128] In one possible implementation, the merging module 602 is specifically used to fill one or more instructions byte by byte starting from the header position of the data packet in the order of calling time, and fill the first preset function code at the preset byte of the last instruction, and fill the second preset function code in the preset bytes of other instructions except the last instruction, so as to obtain the target data packet; the first preset function code is used to indicate that the data packet no longer merges new instructions, and the second preset function code is used to indicate that the data packet can merge new instructions.

[0129] In a possible implementation, the merging module 602 is specifically used to obtain the original value in the preset byte of the instruction for any instruction other than the last instruction; perform a bitwise OR operation on the original value and 0x0800 to obtain the second preset function code of the instruction.

[0130] In a possible implementation, the preset byte is located at the second byte of the instruction.

[0131] It should be understood that the units recorded in the semiconductor test board are similar to those in the reference Figure 2 The various steps in the described method correspond to each other. Therefore, the operations and features described above for the method are also applicable to the semiconductor test board and the units contained therein, and will not be repeated here. The semiconductor test board can be pre-implemented in the browser or other security applications of the terminal device, and can also be loaded into the browser or its security application of the terminal device by downloading or the like. The corresponding units in the semiconductor test board can cooperate with the units in the terminal device to implement the solution of the embodiment of the present application.

[0132] Corresponding to the data processing method described in the above embodiment, Figure 7 A structural block diagram of the device provided in an embodiment of the present application is shown. For the sake of convenience of explanation, only the parts related to the embodiment of the present application are shown.

[0133] Reference Figure 7 The semiconductor test board includes: a receiving module 701, an identification module 702 and an execution module 703, wherein:

[0134] Receiving module 701, used for receiving target data packet;

[0135] An identification module 702, for identifying one or more instructions based on a function code in a target data packet, and determining a location of each instruction in the data packet;

[0136] The execution module 703 is used to execute one or more instructions in sequence based on the position of each instruction in the data packet.

[0137] It should be understood that the units recorded in the semiconductor test board are similar to those in the reference Figure 7The various steps in the described method correspond to each other. Therefore, the operations and features described above for the method are also applicable to the semiconductor test board and the units contained therein, and will not be repeated here. The semiconductor test board can be pre-implemented in the browser or other security applications of the terminal device, and can also be loaded into the browser or its security application of the terminal device by downloading or the like. The corresponding units in the semiconductor test board can cooperate with the units in the terminal device to implement the solution of the embodiment of the present application.

[0138] The several modules or units mentioned in the above detailed description are not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0139] It should be noted that for details not disclosed in the semiconductor test board of the embodiment of the present application, please refer to the details disclosed in the above embodiment of the present application, which will not be repeated here.

[0140] In one embodiment of the present application, a semiconductor testing device is also provided, comprising the above Figure 6 and Figure 7 Semiconductor test board.

[0141] Reference below Figure 8 , Figure 8 A schematic diagram of the structure of a terminal device suitable for implementing an embodiment of the present application is shown. Figure 8 As shown, computer system 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage part 808 into a random access memory (RAM) 803. In RAM 803, various programs and data required for the operation instructions of the system are also stored. CPU 801, ROM 802 and RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to bus 804.

[0142] The following components are connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed, so that a computer program read therefrom is installed into the storage section 808 as needed.

[0143] In particular, according to an embodiment of the present application, the above reference flow chart Figure 2 or Figure 5 The described process can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer readable medium, and the computer program includes a program code for executing the method shown in the flow chart. In such an embodiment, the computer program includes a program code for executing the method shown in the flow chart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 809, and / or installed from the removable medium 811. When the computer program is executed by the central processing unit (CPU) 801, the above-mentioned functions defined in the system of the present application are executed.

[0144] It should be noted that the computer-readable medium shown in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium such as a computer-readable storage medium that can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0145] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operating instructions of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the aforementioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operating instruction, or can be implemented with a combination of dedicated hardware and computer instructions.

[0146] The units or modules involved in the embodiments described in the present application may be implemented by software or by hardware. The units or modules described may also be arranged in a processor, for example, it may be described as follows: a processor includes an acquisition module, a merging module, and a transmission module. The names of these units or modules do not, in some cases, constitute limitations on the units or modules themselves.

[0147] As another aspect, the present application further provides a computer-readable storage medium, which may be included in the terminal device described in the above embodiment, or may exist independently without being installed in the terminal device. The above computer-readable storage medium stores one or more programs, and when the above programs are used by one or more processors to execute the data processing method described in the present application or. For example, it can be executed Figure 2 The steps of the data processing method shown in FIG. Figure 5 The various steps of the data processing method shown.

[0148] The present application embodiment provides a computer program product, which includes instructions. When the instructions are executed, the method described in the present application embodiment is executed. For example, Figure 2 The steps of the data processing method shown in FIG. Figure 5 The various steps of the data processing method shown.

[0149] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the aforementioned disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A data processing method, characterized in that: The host side used in ATE equipment includes: Acquire the calling operations of the application side on multiple interfaces, wherein the calling operations carry instructions; In response to the calling operation, based on the calling time of each calling operation, the correlation relationship between instructions at two adjacent calling times, and the byte length of each instruction, one or more instructions are combined and packaged to obtain a target data packet; The target data packet is transmitted to the slave end.

2. The data processing method according to claim 1, characterized in that: The step of combining and packaging one or more instructions based on the calling time of each calling operation, the correlation between instructions at two adjacent calling times, and the byte length of the instructions to obtain a target data packet includes: According to the calling time of the calling operation, it is determined in turn that the idle byte length of the data packet is greater than or equal to the byte length occupied by one or more instructions, and if there is no correlation between two instructions with two adjacent calling times in the one or more instructions, then the one or more instructions are merged and packaged to obtain the target data packet.

3. The data processing method according to claim 2, characterized in that: Among two instructions at two adjacent calling times, if the execution of the instruction at the later calling time depends on the completion of the instruction at the earlier calling time, it is determined that there is an association relationship between the two instructions at the two adjacent calling times; otherwise, it is determined that there is no association relationship between the two instructions at the two adjacent calling times.

4. The data processing method according to claim 3, characterized in that: If the instruction type with a later calling time is a preset type, it is determined that the execution of the instruction with a later calling time depends on the completion of the instruction with an earlier calling time; the preset types include: waiting type, measurement type, judgment type, and monitoring type.

5. The data processing method according to any one of claims 2 to 4, characterized in that: The step of merging and packaging one or more instructions to obtain the target data packet includes: According to the order of calling time, the one or more instructions are filled byte by byte starting from the header position of the data packet, and the first preset function code is filled in the preset byte of the last instruction, and the second preset function code is filled in the preset bytes of other instructions except the last instruction, so as to obtain the target data packet; the first preset function code is used to indicate that the data packet will no longer merge new instructions, and the second preset function code is used to indicate that the data packet can merge new instructions.

6. The data processing method according to claim 5, characterized in that: Fill the second preset function code in the preset bytes of other instructions except the last instruction, including: For any instruction other than the last instruction, obtaining the original value in the preset byte of the instruction; Perform a bitwise OR operation on the original value and 0x0800 to obtain the second preset function code of the instruction.

7. A data processing method, characterized in that: Applied to the slave end of ATE equipment, the method comprises: Receive a target data packet, wherein the target data packet is obtained based on any one of claims 1 to 6; Identify one or more instructions based on the function code in the target data packet, and determine the location of each instruction in the data packet; The one or more instructions are executed sequentially based on the location of each instruction in the data packet.

8. A semiconductor test board, characterized in that: include: An acquisition module, used to receive a call operation on multiple interfaces from the application side, wherein the call operation carries instructions; A merging module, configured to, in response to the calling operation, merge and pack one or more instructions based on the calling time of each calling operation, the association relationship between instructions at two adjacent calling times, and the byte length of each instruction to obtain a target data packet; The transmission module is used to transmit the target data packet to the bottom layer processor.

9. A semiconductor test board, characterized in that: include: A receiving module, used for receiving a target data packet; An identification module, used for identifying one or more instructions based on the function code in the target data packet, and determining the position of each instruction in the data packet; The execution module is used to execute the one or more instructions in sequence based on the position of each instruction in the data packet.

10. A semiconductor testing device, characterized in that: include: The semiconductor test board as claimed in claim 8 and the semiconductor test board as claimed in claim 9.

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